M29W008AT M29W008AB 8 Mbit (1Mb x8, Boot Block) Low Voltage Single Supply Flash Memory ■ 2.7V to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ■ ACCESS TIME: 80ns ■ PROGRAMMING TIME: 10µs typical ■ PROGRAM/ERASE CONTROLLER (P/E.C.) – Program Byte-by-Byte – Status Register bits and Ready/Busy Output ■ SECURITY PROTECTION MEMORY AREA ■ INSTRUCTIONS ADDRESS CODING: 3 digits ■ MEMORY BLOCKS TSOP40 (N) 10 x 20mm – Boot Block (Top or Bottom location) – Parameter and Main blocks ■ BLOCK, MULTI-BLOCK and CHIP ERASE ■ MULTI BLOCK PROTECTION/TEMPORARY UNPROTECTION MODES ■ ERASE SUSPEND and RESUME MODES Figure 1. Logic Diagram – Read and Program another Block during Erase Suspend ■ VCC LOW POWER CONSUMPTION – Stand-by and Automatic Stand-by ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK ■ 20 YEARS DATA RETENTION – Defectivity below 1ppm/year ■ ELECTRONIC SIGNATURE 20 A0-A19 – Bottom Device Code, M29W008AB: DCh DQ0-DQ7 W E – Manufacturer Code: 20h – Top Device Code, M29W008AT: D2h 8 M29W008AT M29W008AB RB G RP VSS AI02716 March 2000 1/30 M29W008AT, M29W008AB Figure 2. TSOP Connections A16 A15 A14 A13 A12 A11 A9 A8 W RP NC RB A18 A7 A6 A5 A4 A3 A2 A1 1 Table 1. Signal Names 40 10 M29W008AT 31 11 M29W008AB 30 20 21 A17 VSS NC A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 G VSS E A0 AI02717 DESCRIPTION The M29W008A is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte basis using only a single 2.7V to 3.6V VCC supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against programing and erase on programming equipment, and temporarily unprotected to make changes in the application. Each block can be programmed and erased over 100,000 cycles. Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commands to a Command Interface using standard microprocessor write timings. The device is offered in TSOP40 (10 x 20mm) package. 2/30 A0-A19 Address Inputs DQ0-DQ7 Data Input/Outputs, Command Inputs E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output VCC Supply Voltage VSS Ground NC Not Connected Internally Organisation The M29W008A is organised as 1Mb x8. The memory uses the address inputs A0-A19 and the Data Input/Outputs DQ0-DQ7. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. A Reset/Block Temporary Unprotection RP tri-level input provides a hardware reset when pulled Low, and when held High (at VID) temporarily unprotects blocks previously protected allowing them to be programed and erased. Erase and Program operations are controlled by an internal Program/ Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicate the state of the P/E.C operations. A Ready/Busy RB output indicates the completion of the internal algorithms. Memory Blocks The devices feature asymmetrically blocked architecture providing system memory integration. Both M29W008AT and M29W008AB devices have an array of 19 blocks, one Boot Block of 16 Kbytes, two Parameter Blocks of 8 Kbytes, one Main Block of 32 Kbytes and fifteen Main Blocks of 64 Kbytes. The M29W008AT has the Boot Block at the top of the memory address space and the M29W008AB locates the Boot Block starting at the bottom. The memory maps are showed in Tables 3, 4. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations are managed automatically by the P/E.C. M29W008AT, M29W008AB Table 2. Absolute Maximum Ratings (1) Symbol Value Unit Ambient Operating Temperature (3) –40 to 85 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltage –0.6 to 5 V Supply Voltage –0.6 to 5 V –0.6 to 13.5 V TA VCC V(A9, E, G, RP) (2) Parameter A9, E, G, RP Voltage Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions. 3. Depends on range. The block erase operation can be suspended in order to read from or program to any block not being erased, and then resumed. Block protection provides additional data security. Each block can be separately protected or unprotected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprotected in the application. Bus Operations The following operations can be performed using the appropriate bus cycles: Read (Array, Electronic Signature, Block Protection Status), Write command, Output Disable, Stand-by, Reset, Block Protection, Unprotection, Protection Verify, Unprotection Verify and Block Temporary Unprotection. See Tables 5 and 6. Command Interface Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller through a Command Interface (C.I.). For added data protection, program or erase execution starts after 4 or 6 cycles. The first, second, fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all Program/Erase Controller instructions. The ’Command’ itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. Any incorrect command or any improper command sequence will reset the device to Read Array mode. Instructions Seven instructions are defined to perform Read Array, Auto Select (to read the Electronic Signature or Block Protection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling, Toggle, Error bits and the RB output may be read at any time, during programming or erase, to monitor the progress of the operation. Instructions are composed of up to six cycles. The first two cycles input a Coded sequence to the Command Interface which is common to all instructions (see Table 9). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature or Block Protection Status for Read operations. In order to give additional data protection, the instructions for Program and Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied or if VCC falls below VLKO, the command interface is reset to Read Array. 3/30 M29W008AT, M29W008AB Table 3. Top Boot Block Addresses, M29W008AT Table 4. Bottom Boot Block Addresses, M29W008AB # Size (Kbytes) Address Range # Size (Kbytes) Address Range 18 16 FC000h-FFFFFh 18 64 F0000h-FFFFFh 17 8 FA000h-FBFFFh 17 64 E0000h-EFFFFh 16 8 F8000h-F9FFFh 16 64 D0000h-DFFFFh 15 32 F0000h-F7FFFh 15 64 C0000h-CFFFFh 14 64 E0000h-EFFFFh 14 64 B0000h-BFFFFh 13 64 D0000h-DFFFFh 13 64 A0000h-AFFFFh 12 64 C0000h-CFFFFh 12 64 90000h-9FFFFh 11 64 B0000h-BFFFFh 11 64 80000h-8FFFFh 10 64 A0000h-AFFFFh 10 64 70000h-7FFFFh 9 64 90000h-9FFFFh 9 64 60000h-6FFFFh 8 64 80000h-8FFFFh 8 64 50000h-5FFFFh 7 64 70000h-7FFFFh 7 64 40000h-4FFFFh 6 64 60000h-6FFFFh 6 64 30000h-3FFFFh 5 64 50000h-5FFFFh 5 64 20000h-2FFFFh 4 64 40000h-4FFFFh 4 64 10000h-1FFFFh 3 64 30000h-3FFFFh 3 32 08000h-0FFFFh 2 64 20000h-2FFFFh 2 8 06000h-07FFFh 1 64 10000h-1FFFFh 1 8 04000h-05FFFh 0 64 00000h-0FFFFh 0 16 00000h-03FFFh 4/30 M29W008AT, M29W008AB SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A19). The address inputs for the memory array are latched during a write operation on the falling edge of Chip Enable E or Write Enable W. When A9 is raised to V ID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combination of levels on A0, A1 A6, A12 and A15. Data Input/Outputs (DQ0-DQ7). The input is data to be programmed in the memory array or a command to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled and when RP is at a Low level. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects the memory and reduces the power consumption to the stand-by level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. The Chip Enable must be forced to V ID during the Block Unprotection operation. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is High the outputs are High impedance. G must be forced to VID level during Block Protection and Unprotection operations. Write Enable (W). This input controls writing to the Command Register and Address and Data latches. Ready/Busy Output (RB). Ready/Busy is an open-drain output and gives the internal state of the P/E.C. of the device. When RB is Low, the device is Busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend instruction. When RB is High, the device is ready for any Read, Program or Erase operation. The RB will also be High when the memory is put in Erase Suspend or Stand-by modes. Reset/Block Temporary Unprotect Input (RP). The RP Input provides hardware reset and protected block(s) temporary unprotection functions. Reset of the memory is achieved by pulling RP to VIL for at least tPLPX. When the reset pulse is given, if the memory is in Read or Stand-by modes, it will be available for new operations in tPHEL after the rising edge of RP. If the memory is in Erase, Erase Suspend or Program modes the reset will take t PLYH during which the RB signal will be held at VIL. The end of the memory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Program operation will corrupt the data being programmed or the sector(s) being erased. See Tables 15, 16 and Figure 8. Temporary block unprotection is made by holding RP at VID. In this condition previously protected blocks can be programmed or erased. The transition of RP from VIH to V ID must slower than tPHPHH . (See Tables 17, 18 and Figure 8). When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected. VCC Supply Voltage. The power supply for all operations (Read, Program and Erase). VSS Ground. VSS is the reference for all voltage measurements. 5/30 M29W008AT, M29W008AB DEVICE OPERATIONS See Tables 5, 6 and 7. Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register or the Block Protection Status. Both Chip Enable E and Output Enable G must be low in order to read the output of the memory. A new read operation is initiated either on the falling edge of Chip, Enable E, or on any address transition with E at V IL. Write. Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed. A write operation is initiated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High. Addresses are latched on the falling edge of W or E whichever occurs last. Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Output Disable. The data outputs are high impedance when the Output Enable G is High with Write Enable W High. Stand-by. The memory is in stand-by when Chip Enable E is High and the P/E.C. is idle. The power consumption is reduced to the stand-by level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Automatic Stand-by. After 150ns of bus inactivity (no address transition, E = V IL) and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-stand-by mode where consumption is reduced to the CMOS stand-by value, while outputs still drive the bus (if G = V IL). Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memory. The manufacturer’s code for STMicroelectronics is 20h, the device code is D2h for the M29W008AT (Top Boot) and DCh for the M29W008AB (Bottom Boot). These codes allow programming equipment or applications to automatically match their interface to the characteristics of the M29W008A. The Electronic Signature is output by a Read operation when the voltage applied to A9 is at VID and address inputs A1 is Low. The manufacturer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The Electronic Signature can also be read, without raising A9 to VID, by giving the memory the Instruction AS. 6/30 Block Protection. Each block can be separately protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or erase operations. This mode is activated when both A9 and G are raised to VID and an address in the block is applied on A13-A19. Block protection is initiated on the edge of W falling to V IL. Then after a delay of 100µs, the edge of W rising to VIH ends the protection operations. Block protection verify is achieved by bringing G, E, A0 and A6 to VIL and A1 to VIH, while W is at VIH and A9 at VID. Under these conditions, reading the data output will yield 01h if the block defined by the inputs on A13-A19 is protected. Any attempt to program or erase a protected block will be ignored by the device. Block Temporary Unprotection. Any previously protected block can be temporarily unprotected in order to change stored data. The temporary unprotection mode is activated by bringing RP to VID. During the temporary unprotection mode the previously protected blocks are unprotected. A block can be selected and data can be modified by executing the Erase or Program instruction with the RP signal held at VID. When RP is returned to VIH, all the previously protected blocks are again protected. Block Unprotection. All protected blocks can be unprotected on programming equipment to allow updating of bit contents. All blocks must first be protected before the unprotection operation. Block unprotection is activated when A9, G and E are at VID and A12, A15 at V IH. Unprotection is initiated by the edge of W falling to V IL. After a delay of 10ms, the unprotection operation will end. Unprotection verify is achieved by bringing G and E to VIL while A0 is at VIL, A6 and A1 are at VIH and A9 remains at VID. In these conditions, reading the output data will yield 00h if the block defined by the inputs A13-A19 has been successfully unprotected. Each block must be separately verified by giving its address in order to ensure that it has been unprotected. M29W008AT, M29W008AB Table 5. User Bus Operations (1) Operation E G W RP A0 A1 A6 A9 A12 A15 DQ0-DQ7 Read Byte VIL VIL VIH VIH A0 A1 A6 A9 A12 A15 Data Output Write Byte VIL VIH VIL VIH A0 A1 A6 A9 A12 A15 Data Input Output Disable VIL VIH VIH VIH X X X X X X Hi-Z Stand-by VIH X X VIH X X X X X X Hi-Z X X X VIL X X X X X X Hi-Z Block Protection (2,4) VIL VID VIL Pulse VIH X X X VID X X X Blocks Unprotection (4) VID VID VIL Pulse VIH X X X VID VIH VIH X Block Protection Verify (2,4) VIL VIL VIH VIH VIL VIH VIL VID A12 A15 Block Protect Status(3) Block Unprotection Verify (2,4) VIL VIL VIH VIH VIL VIH VIH VID A12 A15 Block Protect Status(3) Block Temporary Unprotection X X X VID X X X X X X X Reset Note: 1. 2. 3. 4. X = VIL or VIH. Block Address must be given an A13-A19 bits. See Table 7. Operation performed on programming equipment. Table 6. Read Electronic Signature (following AS instruction or with A9 = VID) Code Device Manufact. Code E G W A0 A1 Other Addresses DQ0-DQ7 VIL VIL VIH VIL VIL Don’t Care 20h Table 7. Read Block Protection with AS Instruction E G W A0 A1 A13-A19 Other Addresses DQ0-DQ7 Protected Block VIL VIL VIH VIL VIH Block Address Don’t Care 01h Unprotected Block VIL VIL VIH VIL VIH Block Address Don’t Care 00h Code 7/30 M29W008AT, M29W008AB INSTRUCTIONS AND COMMANDS The Command Interface latches commands written to the memory. Instructions are made up from one or more commands to perform Read Memory Array, Read Electronic Signature, Read Block Protection, Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made of address and data sequences. The instructions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the instruction. They are followed by either further write cycles to confirm the first command or execute the command immediately. Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to assure maximum data security. Instructions are initialised by two initial Coded cycles which unlock the Command Interface. In addition, for Erase, instruction confirmation is again preceded by the two Coded cycles. Status Register Bits P/E.C. status is indicated during execution by Data Polling on DQ7, detection of Toggle on DQ6 and DQ2, or Error on DQ5 and Erase Timer DQ3 bits. Any read attempt during Program or Erase command execution will automatically output these five Status Register bits. The P/E.C. automatically sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked. See Tables 10 and 11. Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7. During Erase operation, it outputs a ’0’. After completion of the operation, DQ7 will output the bit last programmed or a ’1’ after erasing. Data Polling is valid and only effective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for erase. It must be performed at the address being programmed or at an address within the block being erased. If all the blocks selected for erasure are protected, DQ7 will be set to '0' for about 100µs, and then return to the previous addressed memory data value. See Figure 10 for the Data Polling flowchart and Figure 9 for the Data Polling waveforms. DQ7 will also flag the Erase Suspend mode by switching from '0' to 8/30 '1' at the start of the Erase Suspend. In order to monitor DQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Erase Suspend mode, DQ7 will output '1' if the read is attempted on a block being erased and the data value on other blocks. During Program operation in Erase Suspend Mode, DQ7 will have the same behavior as in the normal program execution outside of the suspend mode. Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following toggling of either G, or E when G is low. The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmed or a '1' after erasing. The toggle bit DQ6 is valid only during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. If the blocks selected for erasure are protected, DQ6 will toggle for about 100µs and then return back to Read. DQ6 will be set to '1' if a Read operation is attempted on an Erase Suspend block. When erase is suspended DQ6 will toggle during programming operations in a block different to the block in Erase Suspend. Either E or G toggling will cause DQ6 to toggle. See Figure 11 for Toggle Bit flowchart and Figure 12 for Toggle Bit waveforms. Table 8. Commands Hex Code Command 00h Invalid/Reserved 10h Chip Erase Confirm 20h Reserved 30h Block Erase Resume/Confirm 80h Set-up Erase 90h Read Electronic Signature/ Block Protection Status A0h Program B0h Erase Suspend F0h Read Array/Reset M29W008AT, M29W008AB Table 9. Instructions (1) Mne. Instr. Cyc. 1+ RD (2,4) Read/Reset Memory Array 1st Cyc. Addr. (3,7) 2nd Cyc. 3rd Cyc. PG Auto Select Program 3+ ES (10) Read Memory Array until a new write cycle is initiated. Addr. (3,7) 555h 2AAh 555h Data AAh 55h F0h Addr. (3,7) 555h 2AAh 555h Data AAh 55h 90h Addr. (3,7) 555h 2AAh 555h Program Address Read Data Polling or Toggle Bit until Data AAh 55h A0h Program Program completes. Data Addr. (3,7) 555h 2AAh 555h 555h 2AAh Block Address Additional Block (8) Data AAh 55h 80h AAh 55h 30h 30h Addr. (3,7) 555h 2AAh 555h 555h 2AAh 555h Data AAh 55h 80h AAh 55h 10h Read Electronic Signature or Block Protection Status until a new write cycle is initiated. See Note 5 and 6. Note 9 1 Addr. (3,7) Data ER Read Memory Array until a new write cycle is initiated. Chip Erase Erase Suspend Erase Resume 7th Cyc. F0h Block Erase 6 CE 6th Cyc. Data 4 6 BE 5th Cyc. X 3+ AS (4) 4th Cyc. 1 Addr. Data X B0h (3,7) X 30h Read until Toggle stops, then read all the data needed from any Block(s) not being erased then Resume Erase. Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time. Note: 1. Commands not interpreted in this table will default to read array mode. 2. A wait of t PLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new operation (see Tables 15, 16 and Figure 9). 3. X = Don’t Care. 4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles. 5. Signature Address bits A0, A1, at V IL will output Manufacturer code (20h). Address bits A0 at V IH and A1, at VIL will output Device code. 6. Block Protection Address: A0, at V IL, A1 at VIH and A13-A19 within the Block will output the Block Protection status. 7. For Coded cycles address inputs A15-A19 are don’t care. 8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout statuscan be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended. 9. Read Data Polling, Toggle bits or RB until Erase completes. 10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. 9/30 M29W008AT, M29W008AB Table 10. Status Register Bits DQ 7 Name Logic Level Definition ’1’ Erase Complete or erase block in Erase Suspend ’0’ Erase On-going DQ Program Complete or data of non erase block during Erase Suspend DQ Program On-going Data Polling ’-1-0-1-0-1-0-1-’ DQ 6 Toggle Bit ’-1-1-1-1-1-1-1-’ 5 4 3 2 Erase Complete or Erase Suspend on currently addressed block Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for program or Erase Success. Successive reads output complementary data on DQ6 while Programming or Erase operations are on-going. DQ6 remains at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged. ’1’ Program or Erase Error ’0’ Program or Erase On-going ’1’ Erase Timeout Period Expired P/E.C. Erase operation has started. Only possible command entry is Erase Suspend (ES). ’0’ Erase Timeout Period On-going An additional block to be erased in parallel can be entered to the P/E.C. ’-1-0-1-0-1-0-1-’ Chip Erase, Erase or Erase Suspend on the currently addressed block. Erase Error due to the currently addressed block (when DQ5 = ‘1’). This bit is set to ‘1’ in the case of Programming or Erase failure. Reserved Erase Time Bit Toggle Bit Reserved 0 Reserved 10/30 Program Complete Error Bit 1 Note: Erase or Program On-going Note 1 Program on-going, Erase ongoing on another block or Erase Complete DQ Erase Suspend read on non Erase Suspend block Indicates the erase status and allows to identify the erased block. Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. M29W008AT, M29W008AB Table 11. Polling and Toggle Bits Mode DQ7 DQ6 DQ2 DQ7 Toggle 1 Erase 0 Toggle Note 1 Erase Suspend Read (in Erase Suspend block) 1 1 Toggle Erase Suspend Read (outside Erase Suspend block) DQ7 DQ6 DQ2 Erase Suspend Program DQ7 Toggle N/A Program Note: 1. Toggle if the address is within a block being erased. ’1’ if the address is within a block not being erased. Toggle Bit (DQ2). This toggle bit, together with DQ6, can be used to determine the device status during the Erase operations. It can also be used to identify the block being erased. During Erase or Erase Suspend a read from a block being erased will cause DQ2 to toggle. A read from a block not being erased will set DQ2 to '1' during erase and to DQ2 during Erase Suspend. During Chip Erase a read operation will cause DQ2 to toggle as all blocks are being erased. DQ2 will be set to '1' during program operation and when erase is complete. After erase completion and if the error bit DQ5 is set to '1', DQ2 will toggle if the faulty block is addressed. Error Bit (DQ5). This bit is set to '1' by the P/E.C. when there is a failure of programming, block erase, or chip erase that results in invalid data in the memory block. In case of an error in block erase or program, the block in which the error occurred or to which the programmed data belongs, must be discarded. The DQ5 failure condition will also appear if a user tries to program a '1' to a location that is previously programmed to '0'. Other Blocks may still be used. The error bit resets after a Read/Reset (RD) instruction. In case of success of Program or Erase, the error bit will be set to '0'. Erase Timer Bit (DQ3). This bit is set to '0' by the P/E.C. when the last block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the erase timeout period is finished, after 50µs to 90µs, DQ3 returns to '1'. Coded Cycles The two Coded cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The Coded cycles consist of writing the data AAh at address 555h during the first cycle. During the second cycle the Coded cycles consist of writing the data 55h at address 2AAh. A0 to A11 are valid, other address lines are ’don’t care’. The Coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. Instructions See Table 9. Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded cycles. Subsequent read operations will read the memory array addressed and output the data read. A wait state of 10µs is necessary after Read/Reset prior to any valid read if the memory was in an Erase mode when the RD instruction is given. The Read/Reset command is not accepted during Erase and Erase Suspend. Auto Select (AS) Instruction. This instruction uses the two Coded cycles followed by one write cycle giving the command 90h to address 555h for command set-up. A subsequent read will output the manufacturer code and the device code or the block protection status depending on the levels of A0 and A1. The manufacturer code, 20h, is output when the addresses lines A0 and A1 are Low, the device code, EAh for Top Boot, EBh for Bottom Boot is output when A0 is High with A1 Low. The AS instruction also allows access to the block protection status. After giving the AS instruction, A0 and A6 are set to VIL with A1 at VIH, while A13A19 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. Program (PG) Instruction. This instruction uses four write cycles. The Program command A0h is written to address 555h on the third cycle after two Coded cycles. A fourth write operation latches the Address on the falling edge of W or E and the Data to be written on the rising edge and starts the P/ E.C. Read operations output the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Programming at an address not in blocks being erased is also possible during erase suspend. In this case, DQ2 will toggle at the address being programmed. 11/30 M29W008AT, M29W008AB Table 12. AC Measurement Conditions Figure 4. AC Testing Load Circuit Input Rise and Fall Times ≤10ns Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 0.8V 1.5V 1N914 Figure 3. AC Testing Input Output Waveform 3.3kΩ DEVICE UNDER TEST 3V OUT CL = 30pF or 100pF 1.5V 0V AI01417 CL includes JIG capacitance AI01968 Table 13. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol CIN Parameter Input Capacitance COUT Output Capacitance Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: Sampled only, not 100% tested. Table 14. DC Characteristics (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2.7V to 3.6V) Symbol Parameter Test Condition ILI Input Leakage Current ILO Output Leakage Current ICC1 Supply Current (Read) E = VIL, G = VIH, f = 6MHz ICC2 Supply Current (Read) ICC3 Supply Current (Stand-by) ICC4 (1) Supply Current (Program or Erase) Min Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA 3 10 mA E = VIL, G = VIL, f = 6MHz 4.5 100 mA E = VCC ±0.2V 30 100 µA 20 mA Typ. Byte program, Block or Chip Erase in progress VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 VCC VCC + 0.3 V VOL Output Low Voltage 0.45 V VOH Output High Voltage CMOS VID A9 Voltage (Electronic Signature) IID A9 Current (Electronic Signature) VLKO (1) Supply Voltage (Erase and Program lock-out) Note: 1. Sampled only, not 100% tested. 12/30 IOL = 1.8mA IOH = –100µA VCC –0.4V V 11.5 A9 = VID 30 2.0 12.5 V 100 µA 2.3 V M29W008AT, M29W008AB Table 15. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W008AT / M29W008AB Symbol Alt Parameter 80 Test Condition VCC = 3.0V to 3.6V CL = 30pF Min Max 90 VCC = 3.0V to 3.6V CL = 30pF Min Unit Max tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 0 tEHQX tOH Chip Enable High to Output Transition G = VIL 0 0 tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 30 30 ns tELQV (2) tCE Chip Enable Low to Output Valid G = VIL 80 90 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL 0 0 ns tGHQX tOH Output Enable High to Output Transition E = VIL 0 0 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 30 30 ns tGLQV (2) tOE Output Enable Low to Output Valid E = VIL 35 35 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL tPHEL tRH RP High to Chip Enable Low tPLYH(1,3) tRRB tREADY tPLPX tRP 80 80 ns 90 ns ns ns 0 0 ns 50 50 ns RP Low to Read Mode RP Pulse Width 90 10 500 10 500 µs ns Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV . 3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode. 13/30 M29W008AT, M29W008AB Table 16. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W008AT / M29W008AB Symbol Alt Parameter 100 Test Condition VCC = 2.7V to 3.6V CL = 30pF Min Max 120 VCC = 2.7V to 3.6V CL = 30pF Min Unit Max tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 0 tEHQX tOH Chip Enable High to Output Transition G = VIL 0 0 tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 30 30 ns tELQV (2) tCE Chip Enable Low to Output Valid G = VIL 100 120 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL 0 0 ns tGHQX tOH Output Enable High to Output Transition E = VIL 0 0 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 30 30 ns tGLQV (2) tOE Output Enable Low to Output Valid E = VIL 40 50 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL tPHEL tRH RP High to Chip Enable Low tPLYH(1,3) tRRB tREADY tPLPX tRP 100 100 120 ns ns ns 0 ns 50 50 ns 10 500 Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV . 3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode. 14/30 ns 0 RP Low to Read Mode RP Pulse Width 120 10 500 µs ns Note: Write Enable (W) = High. DQ0-DQ7 G E A0-A19 ADDRESS VALID AND CHIP ENABLE tAVQV tGLQV OUTPUT ENABLE tGLQX tELQX tELQV VALID tAVAV DATA VALID VALID tGHQZ tGHQX tEHQX tEHQZ tAXQX AI02191 M29W008AT, M29W008AB Figure 5. Read Mode AC Waveforms 15/30 M29W008AT, M29W008AB Table 17. Write AC Characteristics, W Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W008AT / M29W008AB Symbol Alt Parameter 80 90 VCC = 3.0V to 3.6V CL = 30pF VCC = 3.0V to 3.6V CL = 30pF Min Max Min Unit Max tAVAV tWC Address Valid to Next Address Valid 80 90 ns tAVWL tAS Address Valid to Write Enable Low 0 0 ns tDVWH tDS Input Valid to Write Enable High 35 45 ns tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns Output Enable High to Write Enable Low 0 0 ns 500 500 ns 4 4 µs tGHWL tPHPHH (1, 2) tVIDR RP Rise Time to VID tPHWL (1) tRSP RP High to Write Enable Low tPLPX tRP RP Pulse Width 500 500 ns tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns tWHRL (1) tBUSY Program Erase Valid to RB Delay tWHWL tWPH Write Enable High to Write Enable Low 30 30 ns tWLAX tAH Write Enable Low to Address Transition 45 45 ns tWLWH tWP Write Enable Low to Write Enable High 35 35 ns 90 90 ns Note: 1. Sampled only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles. During the input of the second command an address within the block to be erased is given and latched into the memory. Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Coded cycles. The erase will start after the erase timeout period (see Erase Timer Bit DQ3 description). Thus, additional Erase Confirm commands for other blocks must 16/30 be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is ’0’ the Block Erase Command has been given and the timeout is running, if DQ3 is ’1’, the timeout has expired and the P/E.C. is erasing the Block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before to erasing to FFh. Read operations after the sixth rising edge of W or E output the status register status bits. M29W008AT, M29W008AB Table 18. Write AC Characteristics, W Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W008AT / M29W008AB Symbol Alt Parameter 100 120 VCC = 2.7V to 3.6V CL = 30pF VCC = 2.7V to 3.6V CL = 30pF Min tAVAV tWC Address Valid to Next Address Valid tAVWL tAS tDVWH tELWL Max Min Unit Max 100 120 ns Address Valid to Write Enable Low 0 0 ns tDS Input Valid to Write Enable High 45 50 ns tCS Chip Enable Low to Write Enable Low 0 0 ns Output Enable High to Write Enable Low 0 0 ns 500 500 ns 4 4 µs tGHWL tPHPHH (1, 2) tVIDR RP Rise Time to VID tPHWL (1) tRSP RP High to Write Enable Low tPLPX tRP RP Pulse Width 500 500 ns tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns tWHRL (1) tBUSY Program Erase Valid to RB Delay tWHWL tWPH Write Enable High to Write Enable Low 30 30 ns tWLAX tAH Write Enable Low to Address Transition 45 50 ns tWLWH tWP Write Enable Low to Write Enable High 35 50 ns 90 90 ns Note: 1. Sampled only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. During the execution of the erase by the P/E.C., the memory accepts only the Erase Suspend ES and Read/Reset RD instructions. Data Polling bit DQ7 returns ’0’ while the erasure is in progress and ’1’ when it has completed. The Toggle bit DQ2 and DQ6 toggle during the erase operation. They stop when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C. Chip Erase (CE) Instruction. This instruction uses six write cycles. The Erase Set-up command 80h is written to address 555h on the third cycle af- ter the two Coded cycles. The Chip Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/ E.C. will automatically do this before erasing it to FFh. Read operations after the sixth rising edge of W or E output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The Toggle bits DQ2 and DQ6 toggle during erase operation and stop when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure. 17/30 M29W008AT, M29W008AB Figure 6. Write AC Waveforms, W Controlled tAVAV A0-A19 VALID tWLAX tAVWL tWHEH E tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH DQ0-DQ7 tWHDX VALID VCC tVCHEL RB tWHRL AI02192 Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W. Erase Suspend (ES) Instruction. The Block Erase operation may be suspended by this instruction which consists of writing the command B0h without any specific address. No Coded cycles are required. It permits reading of data from another block and programming in another block while an erase operation is in progress. Erase suspend is accepted only during the Block Erase instruction execution. Writing this command during Erase timeout will, in addition to suspending the erase, terminate the timeout. The Toggle bit DQ6 stops toggling when the P/E.C. is suspended. The Toggle bits will stop toggling between 0.1µs and 15µs after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is 18/30 suspended, a Read from blocks being erased will output DQ2 toggling and DQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume ER and the Program PG instructions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in both DQ2 and DQ6 toggling when the data is being programmed. A Read/Reset command will definitively abort erasure and result in invalid data in the blocks being erased. Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any Coded cycles. M29W008AT, M29W008AB Table 19. Write AC Characteristics, E Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W008AT / M29W008AB Symbol Alt Parameter 80 90 VCC = 3.0V to 3.6V CL = 30pF VCC = 3.0V to 3.6V CL = 30pF Min Max Min Unit Max tAVAV tWC Address Valid to Next Address Valid 80 90 ns tAVEL tAS Address Valid to Chip Enable Low 0 0 ns tDVEH tDS Input Valid to Chip Enable High 35 45 ns tEHDX tDH Chip Enable High to Input Transition 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 30 30 ns tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns tEHRL (1) tBUSY Program Erase Valid to RB Delay tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tELAX tAH Chip Enable Low to Address Transition 45 45 ns tELEH tCP Chip Enable Low to Chip Enable High 35 35 ns Output Enable High Chip Enable Low 0 0 ns 500 500 ns 4 4 µs tGHEL 90 90 ns tPHPHH (1, 2) tVIDR RP Rise TIme to VID tPHWL (1) tRSP RP High to Write Enable Low tPLPX tRP RP Pulse Width 500 500 ns tVCHWL tVCS VCC High to Write Enable Low 50 50 µs tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns Note: 1. Sampled only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. POWER SUPPLY Power Up The memory Command Interface is reset on power up to Read Array. The device does not accept commands on the first rising edge of W, if both W and E are at VIL with G at V IH during power-up. Any write cycle initiation is blocked when VCC is below VLKO . Supply Rails Normal precautions must be taken for supply voltage decoupling; each device in a system should have the VCC rail decoupled with a 0.1µF capacitor close to the V CC and VSS pins. The PCB trace widths should be sufficient to carry the VCC program and erase currents required. 19/30 M29W008AT, M29W008AB Table 20. Write AC Characteristics, E Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W008AT / M29W008AB Symbol Alt Parameter 100 120 VCC = 2.7V to 3.6V CL = 30pF VCC = 2.7V to 3.6V CL = 30pF Min tAVAV tWC Address Valid to Next Address Valid tAVEL tAS tDVEH Max Min Unit Max 100 120 ns Address Valid to Chip Enable Low 0 0 ns tDS Input Valid to Chip Enable High 45 50 ns tEHDX tDH Chip Enable High to Input Transition 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 30 20 ns tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns tEHRL (1) tBUSY Program Erase Valid to RB Delay tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tELAX tAH Chip Enable Low to Address Transition 45 50 ns tELEH tCP Chip Enable Low to Chip Enable High 35 50 ns Output Enable High Chip Enable Low 0 0 ns 500 500 ns 4 4 µs tGHEL 90 90 ns tPHPHH (1, 2) tVIDR RP Rise TIme to VID tPHWL (1) tRSP RP High to Write Enable Low tPLPX tRP RP Pulse Width 500 500 ns tVCHWL tVCS VCC High to Write Enable Low 50 50 µs tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns Note: 1. Sampled only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. 20/30 M29W008AT, M29W008AB Figure 7. Write AC Waveforms, E Controlled tAVAV VALID A0-A19 tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL tELEH E tEHEL tDVEH DQ0-DQ7 tEHDX VALID VCC tVCHWL RB tEHRL AI02193 Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E. Figure 8. Read and Write AC Characteristics, RP Related E tPHEL W tPHWL RB RP tPLPX tPHPHH tPLYH AI02091 21/30 M29W008AT, M29W008AB Table 21. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W008AT / M29W008AB Symbol tEHQ7V tEHQV tQ7VQV tWHQ7V tWHQV Parameter 80 90 VCC = 3.0V to 3.6V CL = 30pF VCC = 3.0V to 3.6V CL = 30pF Unit Min Max Min Max Chip Enable High to DQ7 Valid (Program, E Controlled) 10 2400 10 2400 µs Chip Enable High to DQ7 Valid (Chip Erase, E Controlled) 1.0 60 1.0 60 sec Chip Enable High to Output Valid (Program) 10 2400 10 2400 µs Chip Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec 35 ns Q7 Valid to Output Valid (Data Polling) 35 Write Enable High to DQ7 Valid (Program, W Controlled) 10 2400 10 2400 ms Write Enable High to DQ7 Valid (Chip Erase, W Controlled) 1.0 60 1.0 60 sec Write Enable High to Output Valid (Program) 10 2400 10 2400 µs Write Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec Note: 1. All other timings are defined in Read AC Characteristics table. Table 22. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W008AT / M29W008AB Symbol tEHQ7V tEHQV tQ7VQV tWHQ7V tWHQV Parameter 120 VCC = 2.7V to 3.6V CL = 30pF VCC = 2.7V to 3.6V CL = 30pF Unit Min Max Min Max Chip Enable High to DQ7 Valid (Program, E Controlled) 10 2400 10 2400 µs Chip Enable High to DQ7 Valid (Chip Erase, E Controlled) 1.0 60 1.0 60 sec Chip Enable High to Output Valid (Program) 10 2400 10 2400 µs Chip Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec 50 ns Q7 Valid to Output Valid (Data Polling) 40 Write Enable High to DQ7 Valid (Program, W Controlled) 10 2400 10 2400 ms Write Enable High to DQ7 Valid (Chip Erase, W Controlled) 1.0 60 1.0 60 sec Write Enable High to Output Valid (Program) 10 2400 10 2400 µs Write Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec Note: 1. All other timings are defined in Read AC Characteristics table. 22/30 100 DQ0-DQ6 DQ7 W G E A0-A19 LAST WRITE CYCLE OF PROGRAM OR ERASE INSTRUCTION DATA POLLING READ CYCLES tWHQ7V tEHQ7V tELQV tAVQV tQ7VQV IGNORE DQ7 DATA POLLING (LAST) CYCLE tGLQV ADDRESS (WITHIN BLOCKS) VALID VALID DATA OUTPUT VALID AI02194 MEMORY ARRAY READ CYCLE M29W008AT, M29W008AB Figure 9. Data Polling DQ7 AC Waveforms 23/30 M29W008AT, M29W008AB Figure 10. Data Polling Flowchart Figure 11. Data Toggle Flowchart START START READ DQ2, DQ5 & DQ6 READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA NO NO YES NO DQ5 =1 DQ5 =1 YES YES READ DQ7 DQ7 = DATA NO DQ2, DQ6 = TOGGLE YES READ DQ2, DQ6 YES DQ2, DQ6 = TOGGLE NO FAIL NO YES PASS FAIL PASS AI01369 AI01873 Table 23. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70°C; VCC = 2.7V to 3.6V) M29W008AT / M29W008AB Parameter Unit Typ Typical after 100k W/E Cycles Chip Erase (Preprogrammed, VCC = 2.7V) 10 10 sec Chip Erase (VCC = 2.7V) 15 15 sec Main Block Erase (VCC = 2.7V) 1.5 Min Max 15 sec Chip Program (Byte) (1) 5 5 sec Byte Program 10 10 µs Program/Erase Cycles (per Block) 100,000 Note: 1. Excluded the time required to execute bus cycles sequence for program operation. 24/30 cycles DATA TOGGLE READ CYCLE Note: All other timings are as a normal Read cycle. LAST WRITE CYCLE OF PROGRAM OF ERASE INSTRUCTION DQ0-DQ1,DQ3-DQ5,DQ7 DQ6,DQ2 W G E A0-A19 DATA TOGGLE READ CYCLE IGNORE STOP TOGGLE tWHQV tEHQV tAVQV MEMORY ARRAY READ CYCLE VALID VALID tGLQV tELQV VALID AI02195 M29W008AT, M29W008AB Figure 12. Data Toggle DQ6, DQ2 AC Waveforms 25/30 M29W008AT, M29W008AB SECURITY PROTECTION MEMORY AREA The M29W008A features a security protection memory area. It consists of a memory block of 256 bytes which is programmed in the ST factory to store a unique code that uniquely identifies the part. This memory block can be read by using the Read Security Data instruction (RDS) as shown in Table 24. Read Security Data (RDS) Instruction. This RDS uses a single write cycle instruction: the command B8h is written to the address AAh. This sets the memory to the Read Security mode. Any successive read attempt will output the addressed Security byte until a new write cycle is initiated. Table 24. Security Block Instruction Unlock Cycle Mne. Instr. Cyc. 2nd Cyc. 1st Cyc. RDS Read Security Data Addr. (1) AAh Data (2) B8h Read OTP Data until a new write cycle is initiated. 1 Note: 1. Address bits A10-A19 are don’t care for coded address inputs. 2. Data bits DQ8-DQ15 are don’t care for coded address inputs. Figure 13. Security Block Address Table TOP BOOT BLOCK BOTTOM BOOT BLOCK Security Memory Block Security Memory Block 000FFh 00000h 0E0FFh 0E000h AI02740 26/30 M29W008AT, M29W008AB Table 25. Ordering Information Scheme Example: M29W008AT 80 N 1 T Device Type M29 Operating Voltage W = 2.7 to 3.6V Device Function 008A = 8 Mbit (1Mb x8), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 80 = 80 ns 90 = 90 ns 100 = 100 ns 120 = 120 ns Package N = TSOP40: 10 x 20 mm Temperature Range 1 = 0 to 70 °C 5 = –20 to 85°C 6 = –40 to 85 °C Option T = Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 27/30 M29W008AT, M29W008AB Table 26. Revision History Date Description November 1998 First issue 02/09/00 New document template Document type: from Preliminary Data to Data Sheet 03/06/00 Program Erase Times change (Table 23) 28/30 M29W008AT, M29W008AB Table 27. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data mm Symbol Typ inches Min Max A Typ Min 1.20 Max 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413 B 0.17 0.27 0.0067 0.0106 C 0.10 0.21 0.0039 0.0083 D 19.80 20.20 0.7795 0.7953 D1 18.30 18.50 0.7205 0.7283 9.90 10.10 0.3898 0.3976 – – – – L 0.50 0.70 0.0197 0.0276 α 0° 5° 0° 5° N 40 E e 0.50 0.0197 40 CP 0.10 0.0039 Figure 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a A1 α L Drawing is not to scale. 29/30 M29W008AT, M29W008AB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. 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