Mitsubishi M34551 Single-chip 4-bit cmos microcomputer for infrared remote control transmitter Datasheet

MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
DESCRIPTION
● LCD control circuit
Segment output ................................................................... 20
Common output .................................................................... 4
● Carrier wave frequency switch function
System clock, system clock/2, system clock/8,
system clock/12, system clock/16, system clock/24, “H” fixed
● Timers
Timer 1 ................................ 8-bit timer with a reload register
Timer 2 ............... 14-bit timer also used as a watchdog timer
Timer LC ............................. 4-bit timer with a reload register
● Interrupt ................................................................... 3 sources
● Voltage drop detection circuit ............................................... 1
● Clock generating circuit (ceramic resonance and quartz-crystal
oscillation)
The 4551 Group is a 4-bit single-chip microcomputer designed
with CMOS technology. Its CPU is that of the 4500 series using
a simple, high-speed instruction set. The computer is equipped
with an 8-bit timer with a reload register, a 14-bit timer which is
also used as a watchdog timer, a 4-bit timer with a reload register,
a carrier wave output circuit and an LCD control circuit.
The mask ROM version and built-in PROM version of 4551 Group
are produced as shown in the table below.
FEATURES
● Minimum instruction execution time ............................. 3.0 µs
(f(XIN)=4.0 MHz, VDD=3.0 V, system clock = f(XIN)/4)
● Supply voltage
............................. 2.5 V to 5.5 V (One Time PROM version)
....................................... 2.2 V to 5.5 V (Mask ROM version)
● System clock switch function
........................................... Clock divided by 4 or not divided
ROM (PROM) size
(✕ 10 bits)
Product
Remote control transmitter
RAM size
4096 words
M34551M4-XXXFP
APPLICATION
8192 words
M34551E8-XXXFP
(Note)
Note: Shipped after writing (shipped in blank: M34551E8FP)
Package
ROM type
(✕ 4 bits)
280 words
48P6S-A
Mask ROM
280 words
48P6S-A
One Time PROM
RESET
COM1
COM0
COM 2
COM3
SEG1
SEG0
SEG3
SEG2
SEG5
SEG4
SEG 6
SEG 8
M34551M4-XXXFP
SEG 7
PIN CONFIGURATION (TOP VIEW)
38 37 36 35 34 33 32 31 30 29 28 27 26 25
SEG9
39
24
D7/XCOUT
SEG10
40
23
D6/XCIN
SEG11
41
22
CNVSS
SEG12
42
21
XOUT
VSS
43
20
XIN
SEG13
44
19
VSS
SEG14
45
18
VDD
SEG15
46
17
CARR
P20 / SEG 16
47
16
D5 / INT
P21 / SEG 17
48
15
D4
Outline 48P6S-A
D3
9 10 11 12 13 14
D2
P02
8
D1
P00
P01
7
D0
P22 / SEG18
6
P13
5
P11
4
P12
3
P10
2
P03
1
P23 / SEG 19
M34551M4-XXXFP
2
Port P0
Port P1
4
4
Port P2
20
Segment output
4
Common output
LCD drive control circuit
(max. 20 segments ✕ 4 common)
Register B (4 bits)
Register A (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack registers SKs (8 levels)
Interrupt stack register SDP(1 level)
ALU(4 bits)
4500 Series
CPU core
Remote control carrier wave output
Note: PROM 8192 words ✕ 10 bits
280 words ✕ 4 bits
(LCD RAM
20 words ✕ 4 bits included)
RAM
4096 to 8192 words ✕ 10 bits
ROM (Note)
Memory
XIN –XOUT
(Main clock)
XCIN –XCOUT
(Sub-clock)
Timer 1 (8 bits)
Timer 2 (14 bits)
Timer LC (4 bits)
System clock generating circuit
Port D
8
Timers
Internal peripheral functions
I/O port
4
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
BLOCK DIAGRAM
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
PERFORMANCE OVERVIEW
Parameter
Function
Number of basic instructions
92
Minimum instruction execution time 1.5 µs (f(XIN) = 8.0 MHz:system clock = f(XIN)/4: VDD = 5.0 V)
Memory sizes ROM
M34551M4 4096 words ✕ 10 bits
Input/Output
ports
RAM
D0–D7
M34551E8 8192 words ✕ 10 bits
280 words ✕ 4 bits (LCD RAM 20 words ✕ 4 bits included)
Eight independent output ports
Output
P00–P03 I/O
P10–P13 I/O
P20–P23 Input
Output
CARR
Timers
Interrupt
4-bit I/O port; each pin is equipped with a pull-up function.
4-bit input port
1-bit output port (CMOS output)
Timer 1
Timer 2/
8-bit timer with a reload register
14-bit timer/
Watchdog timer
Fixed dividing frequency timer
Timer LC
Sources
4-bit timer with a reload register
3 (one for external and two for timer)
Nesting
Subroutine nesting
LCD
4-bit I/O port; each pin is equipped with a pull-up function.
1 level
8 levels (however, only 7 levels can be used when an interrupt is used or the TABP p instruction
is executed)
Selective bias value 1/2, 1/3 bias
Selective duty value 2, 3, 4 duty
4
Common output
20
Segment output
Internal resistor for 200 kΩ ✕ 3
power supply
Device structure
Package
CMOS silicon gate
48-pin plastic molded QFP
Operating temperature range
–20 °C to 70 °C
Supply voltage
Power
at active
dissipation
at clock operating
2.2 V to 5.5 V (One Time PROM version: 2.5 V to 5.5 V)
2.5 mA (f(XIN) = 8.0 MHz system clock = f(XIN)/4, VDD=5 V)
(typical value) at RAM back-up
0.1 µA (at main clock oscillation stop, sub-clock oscillation stop, Ta=25 °C, VDD=5V)
27.5 µA (at main clock oscillation stop, sub-clock oscillation frequency: 32.0 kHz, VDD=5 V)
DEFINITION OF CLOCK AND CYCLE
● System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock can be selected by bits 0 and 3 of the clock
control register MR as shown in the table below.
Table Selection of system clock
Register MR
System clock (STCK)
MR3 MR0
f(XIN)
0
0
0
1
1
● Instruction clock (INSTK)
The instruction clock is the standard clock for controlling CPU.
The instruction clock is a signal derived from dividing the
system clock by 3. The one cycle of the instruction clock is
equivalent to the one machine cycle.
● Machine cycle
The machine cycle is the standard cycle required to execute
the instruction.
f(XCIN)
f(XIN)/4
0
f(XCIN)/4
1
1
Note: f(XIN)/4 is selected immediately after system is released
from reset.
3
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
PIN DESCRIPTION
VDD
Name
Power supply
VSS
Ground
CNVSS
CNVSS
Reset input
Pin
RESET
Input/Output
Function
—
Connected to a plus power supply.
—
Connected to a 0 V power supply.
Input
I/O
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
An N-channel open-drain I/O pin for a system reset. A pull-up resistor is built-in
this pin. When the watchdog timer causes the system to be reset or the lowsupply voltage is detected, the RESET pin outputs “L” level.
XIN
Main clock input
Input
I/O pins of the main clock generating circuit. A ceramic resonator can be connected
XOUT
Main clock output
Output
D0–D4
Output port D
Output
between XIN pin and XOUT pin. A feedback resistor is built-in between them.
Each pin of port D has an independent 1-bit wide output function. The output
D5/INT
Output port D
I/O
D6/XCIN
Output port D
I/O
D7/XCOUT
Output port D
Output
P00–P03
I/O port P0
structure is N-channel open-drain.
1-bit output port. Port D5 is also used as an INT input pin. When D5/INT pin is
used as the INT input pin, set the output latch to “1.” The output structure is Nchannel open-drain.
I/O
Each pin of port D has an independent 1-bit output function. Ports D6 and D7 are
also used as pins XCIN and XCOUT for the sub-clock generating circuit, respectively.
When pins D6/XCIN and D7/XCOUT are used as the pins for the sub-clock generating
circuit, a 32.0 kHz quartz-crystal oscillator can be connected between XCIN pin
and XCOUT pin. A feedback resistor is built-in between them.
4-bit I/O port. It can be used as an input port when the output latch is set to “1.”
The output structure is N-channel open-drain. Every pin of the ports has a key-on
wakeup function and a pull-up function.
P10–P13
I/O port P1
I/O
4-bit I/O port. It can be used as an input port when the output latch is set to “1.”
The output structure is N-channel open-drain. Every pin of the ports has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
I/O
4-bit input port. Ports P20–P23 are also used as the segment output pins SEG16–
SEG19, respectively.
Output
Carrier wave output pin for remote control transmit. The output structure is the
for remote control
SEG0–SEG15 Segment output
Output
CMOS circuit.
LCD segment output pins.
COM0–COM3 Common output
Output
P20/SEG16– Input port P2
P23/SEG19
CARR
Carrier wave output
LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0–
COM2 are used at 1/3 duty and pins COM0–COM3 are used at 1/4 duty.
4
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
MULTIFUNCTION
Pin
Multifunction
Pin
Multifunction
D5
INT
INT
D5
D6
XCIN
D7
P20
XCOUT
SEG16
XCIN
XCOUT
D6
D7
SEG16
P20
P21
SEG17
SEG17
P22
SEG18
SEG18
P23
SEG19
SEG19
Notes 1: Pins except above have just single function.
2: The port D5 is the output port and ports P20–P23 are the input ports.
P21
P22
P23
CONNECTIONS OF UNUSED PINS
Pin
Connection
Pin
Connect to VSS, or set the output latch to CARR
“0” and open.
SEG0–SEG15
Select ports D6 and D7 and connect to VSS, COM0–COM3
or set the output latch to “0” and open.
P00–P03
D0–D4
D5/INT
D6/XCIN
D7/XCOUT
P 2 0 / S E G 1 6 – P 2 3 / Select port P2 and connect to VSS, or select P10–P13
SEG19
the segment output function and open.
Connection
Open
Open
Open
Set the output latch to “1” and open.
Open or connect to VSS (Note)
Note: In order to connect ports P10–P13 to VSS, turn off their pull-up transistors (Pull-up control register PU0i=“0”) by software. In
order to make these pins open, turn on their pull-up transistors (register PU0 i=“1”) by software, or turn off their pull-up
transistors (register PU0i=“0”) and set the output latch to “0” (i = 0, 1, 2, or 3).
Be sure to select the key-on wakeup function and the pull-up function with every one port.
(Note in order to set the output latch to “0” and make pins open)
• After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “0” by software.
Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away
(caused by noise).
(Note in order to connect unused pins to VSS or VDD)
• To avoid noise, connect the unused pins to VSS or VDD at the shortest distance using a thick wire.
PORT FUNCTION
Port
Port D
Pin
D0–D4, D5/INT,
D6/XCIN,
Input/
Output
Output structure
Output
N-channel open-drain
Control
bits
1
(8)
Control
Control
instructions registers
SD
MR
Remark
RD
D7/XCOUT
Port P0
P00–P03
I/O
N-channel open-drain
4
Port P1
P10–P13
(4)
I/O
N-channel open-drain
4
CLD
OP0A
Pull-up functions
IAP0
(4)
OP1A
IAP1
PU0
Key-on wakeup functions
Pull-up functions
(programmable)
Key-on wakeup functions
(programmable)
Port P2
P20/SEG16–
P23/SEG19
Input
4
IAP2
(4)
5
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
PORT BLOCK DIAGRAMS
Pull-up
transistor
Key-on wakeup
input
(Note 1)
IAP0 instruction
Register A
P00–P03
Ai
Ai
D Q
OP0A instruction
T
Pull-up
transistor
PU0i
Key-on wakeup
input
(Note 1)
IAP1 instruction
Register A
P10–P13
Ai
Ai
D Q
OP1A instruction
T
(Note 1)
LCD power supply
LCD control signal
Connected to
when selecting SEG
P20/SEG16–P23/SEG19
L2i
LCD
power
supply
IAP2 instruction
Register A
Register Y
Decoder
(Note 1)
CLD
instruction
S
SD instruction
D0–D4
R Q
RD instruction
(Note 1)
Register Y
Decoder
INT input
D5/INT
CLD instruction
S
SD instruction
R Q
RD instruction
Register Y
(Note 1)
Decoder
MR2
CLD
instruction
S
0
R Q
1
D6/XCIN
SD instruction
RD instruction
MR2
MR2
XCIN clock
Register Y
(Note 1)
Decoder
MR2
CLD
instruction
SD instruction
RD instruction
S
R Q
Notes 1:
This symbol represents a parasitic diode.
2: i represents bit 0, 1, 2 or 3.
6
0
1
D7/XCOUT
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
PORT BLOCK DIAGRAMS (continued)
To timer 1
TC1A instruction
CR flag
STCR instruction
S Q
SPCR instruction
R
CARRY
Register C1
(Note)
Carrier wave
output circuit
Timer LC underflow signal
CARR
W31
F/F
W30
Timer 1 underflow signal
F/F
C20
W20
LCD power supply
LCD control signal
Pch
SEG0–SEG15
LCD control signal
Nch
LCD power supply
LCD power supply
LCD control signal
Pch
COM0–COM3
LCD control signal
Pch
LCD power supply
LCD power supply
LCD control signal
LCD control signal
Nch
Nch
Note:
This symbol represents a parasitic diode.
7
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such
as 4-bit data addition, comparison, AND operation, OR
operation, and bit manipulation.
(2) Register A and carry flag (CY)
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction.
The value of A0 is stored in carry flag CY with the RAR
instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4bit data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and
register A as the low-order 4 bits (Figure 3).
(M(DP))
Addition
ALU
(A)
<Result>
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
A3 A2 A1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register
A and is used as a pointer within the specified page when the
TABP p, BLA p, or BMLA p instruction is executed (Figure 4).
Register B TAB instruction Register A
B3 B2 B1 B0
A3 A2 A1 A0
TEAB instruction
Register E E7 E6 E5 E4 E3 E2 E1 E0
TABE instruction
B3 B2 B1 B0
Register B
A3 A2 A1 A0
TBA instruction
Register A
Fig. 3 Registers A, B and register E
ROM
TABP p instruction
Specifying address
p6 p5
PCH
p4 p3 p2 p1 p0
PCL
DR2 DR1 DR0 A3 A2 A1 A0
8
4
0
Low-order 4 bits
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field
value p
The contents of The contents of
register D
register A
Fig. 4 TABP p instruction execution example
8
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the
contents of program counter (PC) just before branching until
returning to the original routine when;
• branching to an interrupt service routine (referred to as
an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that
subroutines can be nested up to 8 levels. However, one of
stack registers is used when using an interrupt service routine
or when executing a table reference instruction. Accordingly,
be careful not to stack over when performing these operations
together. The contents of registers SKs are destroyed when
8 levels are exceeded.
The register SK nesting level is pointed automatically by 3bit stack pointer (SP). The contents of the stack pointer (SP)
can be transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an
interrupt occurs, this register (SDP) is used to temporarily
store the contents of data pointer, carry flag, skip flag, register
A, and register B just before an interrupt until returning to the
original routine.
Unlike the stack registers (SKs), this register (SDP) is not
used when executing the subroutine call instruction and the
table reference instruction.
Program counter (PC)
Executing the subroutine
Executing the return or
call or table reference
table reference instruction
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
SK4
(SP) = 4
SK5
(SP) = 5
SK6
(SP) = 6
SK7
(SP) = 7
Stack pointer (SP) points “7” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after eight
stack registers are used ((SP) = 7), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP)
(SK0)
(PC)
0
000116
SUB1
Subroutine
Main program
(7) Skip flag
Skip flag controls skip decision for the conditional skip
instructions and continuous described skip instructions. When
an interrupt occurs, the contents of skip flag is stored
automatically in the interrupt stack register (SDP) and the
skip condition is retained.
Address
SUB1 :
000016 NOP
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC)
(SP)
(SK0)
7
Note: Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction is equivalent to the NOP instruction.
Fig. 6 Example of operation at subroutine call
9
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
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(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page
and address). It determines a sequence in which instructions
stored in ROM are read. It is a binary counter that increments
the number of instruction bytes each time an instruction is
executed. However, the value changes to a specified address
when branch instructions, subroutine call instructions, return
instructions, or the table reference instruction (TABP p) is
executed.
Program counter consists of PCH (most significant bit to bit
7) which specifies to a ROM page and PCL (bits 6 to 0) which
specifies an address within a page. After it reaches the last
address (address 127) of a page, it specifies address 0 of the
next page (Figure 7).
Make sure that the PCH does not specify after the last page
of the built-in ROM.
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and
consists of registers Z, X, and Y. Register Z specifies a RAM
file group, register X specifies a file, and register Y specifies
a RAM digit (Figure 8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y
certainly and execute the SD, RD, or SZD instruction (Figure
9).
Program counter (PC)
p6 p5 p4 p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
PCH
Specifying page
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
Register Y (4)
Register X (4)
Register Z (2)
Specifying
RAM digit
Specifying RAM file
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D7
0
1
0
1
Register Y (4)
D6
D5
Port D output latch
Fig. 9 SD instruction execution example
10
D4
1
D0
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
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PROGRAM MEMORY (ROM)
1 word of ROM is composed of 10 bits. ROM is separated every
128 words by the unit of page (addresses 0 to 127). Table 1
shows the ROM size and pages. Figure 10 shows the ROM map
of M34551E8.
Table 1 ROM size and pages
Product
ROM size
Pages
M34551M4
(✕ 10 bits)
4096 words
32 (0 to 31)
M34551E8
8192 words
64 (0 to 63)
A top part of page 1 (addresses 008016 to 00FF16) is reserved
for interrupt addresses (Figure 11). When an interrupt occurs,
the address (interrupt address) corresponding to each interrupt
is set in the program counter, and the instruction at the interrupt
address is executed. When using an interrupt service routine,
write the instruction generating the branch to that routine at an
interrupt address.
Page 2 (addresses 010016 to 017F 16) is the special page for
subroutine calls. Subroutines written in this page can be called
from any page with the 1-word instruction (BM). Subroutines
extending from page 2 to another page can also be called with
the BM instruction when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data
areas with the TABP p instruction.
9 8
000016
007F16
008016
00FF16
010016
017F16
018016
7
6
5
4
3 2
1 0
Page 0
Interrupt address page
Page 1
Subroutine special page
Page 2
Page 3
0FFF16
Page 31
1FFF16
Page 63
Fig. 10 ROM map of M34551E8
008016
9 8 7 6 5 4 3 2 1 0
External 0 interrupt address
008416
Timer 1 interrupt address
008616
Timer 2 interrupt address
00FF16
Fig. 11 Interrupt address page (addresses 008016 to 00FF16) structure
11
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
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DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation
(with the SB j, RB j, and SZB j instructions) is enabled for the
entire memory area. A RAM address is specified by a data
pointer. The data pointer consists of registers Z, X, and Y. Set a
value to the data pointer certainly when executing an instruction
to access RAM.
RAM includes the area corresponding to the LCD. A segment is
turned on automatically when “1” is written in the bit
corresponding to the segment.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
Table 2 RAM size
Product
M34551M4
RAM size
280 words ✕ 4 bits (1120 bits)
M34551E8
RAM 280 words ✕ 4 bits (1120 bits)
Register Z
0
Register X 0 1 2 3 ••• 6 7 •••••• 15
0
1
0
1
1
2
6
7
8
9
0
1
8
9
16
17
10
11
12
13
2
3
4
5
10
11
12
13
18
19
14
15
6
7
14
15
Register Y
2
3
4
5
280 words
Notes 1: The area marked “–” (Z = 1, X = 0 to 2, Y = 0 to 7) is not a memory area.
2: The numbers in the shaded area indicate the corresponding segment output pin numbers.
Fig. 12 RAM map
12
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INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source.
An interrupt occurs when the following 3 conditions are satisfied.
• Interrupt enable flag (INTE) = “1” (Interrupt enabled)
• Interrupt enable bit = “1” (Interrupt request occurrence enabled)
• An interrupt activated condition is satisfied
(request flag = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every
interrupt enable/disable. Interrupts are enabled when INTE
flag is set to “1” with the EI instruction and disabled when
INTE flag is cleared to “0” with the DI instruction. When any
interrupt occurs, the INTE flag is automatically cleared to “0,”
so that other interrupts are disabled until the EI instruction is
executed.
(2) Interrupt enable bits (V10–V13)
Use an interrupt enable bit of interrupt control register V1 to
select the corresponding interrupt request or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit
and skip instruction.
Table 5 shows the interrupt enable bit function.
Table 3 Interrupt sources
Interrupt
Priority
Activated condition
Interrupt name
address
level
Address 0
1
External 0 interrupt Level change of
in page 1
INT pin
2
Timer 1 underflow Address 4
Timer 1 interrupt
in page 1
3
Timer 2 interrupt
Timer 2 underflow
Address 6
in page 1
Table 4 Interrupt request flag, interrupt enable bit and skip
instruction
Request flag Enable bit Skip instruction
Interrupt name
EXF0
V10
SNZ0
External 0 interrupt
Timer 1 interrupt
T1F
V12
SNZT1
Timer 2 interrupt
T2F
V13
SNZT2
Table 5 Interrupt enable bit function
Occurrence of
Interrupt enable bit
interrupt request
1
0
Enabled
Disabled
Skip instruction
Invalid
Valid
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied,
the corresponding interrupt request flag is set to “1.” Each
interrupt request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition
is satisfied even if the interrupt is disabled by the INTE flag or
its interrupt enable bit. Once set, the interrupt request flag
retains set until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable
state is released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt
disable state is released, the interrupt priority level is as follows
shown in Table 3.
13
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(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is
as follows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The
address to be executed when returning to the main routine
is automatically stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is
cleared to “0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored
automatically in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address
is executed after a branch to a sequence for storing data into
stack register is performed. Write the branch instruction to
an interrupt service routine at an interrupt address.
Use the RTI instruction to return to main routine.
Interrupt enabled by executing the EI instruction is performed
after executing 1 instruction (just after the next instruction is
executed). Accordingly, when the EI instruction is executed
just before the RTI instruction, interrupts are enabled after
returning to the main routine. (Refer to Figure 13)
Main
routine
•Program counter (PC)
..................................................... Each interrupt address
•Stack register (SK)
........... The address of main routine to be executed when returning
•Interrupt enable flag (INTE)
........................................................ 0 (Interrupt disabled)
•Interrupt request flag (only the flag for the current interrupt source)
........................................................................................ 0
•Data pointer, carry flag, registers A and B, skip flag
............... Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
INT pin
(L → H or
H → L input)
V10
Timer 1
underflow
T1F
V12
Timer 2
underflow
T2F
V13
INTE
Activated
condition
Request
flag
(state retained)
Enable
bit
Enable
flag
Interrupt
service routine
Interrupt
occurs
Interrupt
is enabled
Fig. 15 Interrupt system diagram
EI
RTI
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
14
Address 0 in
page 1
EXF0
Address 4 in
page 1
Address 6 in
page 1
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(6) Interrupt control register
● Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are
assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1
instruction can be used to transfer the contents of register
V1 to register A.
Table 6 Interrupt control register
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
at power down : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
1
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
0
R/W
This bit has no function, but read/write is enabled.
1
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
Note: “R” represents read enabled, and “W” represents write enabled.
(7) Interrupt sequence
Interrupts occur only when the respective INTE flag, interrupt
enable bits (V10–V13), and interrupt request flags (EXF0, T1F,
T2F) are “1.” The interrupt actually occurs 2 to 3 machine
cycles after the cycle in which all three conditions are satisfied.
The interrupt occurs after 3 machine cycles only when the
three interrupt conditions are satisfied on execution of other
than one-cycle instructions (Refer to Figure 16).
● When an interrupt request flag is set after its interrupt is enabled
1 machine cycle
System clock (STCK)
Interrupt enable
flag (INTE)
INT pin
External
interrupt
EXF0
flag
“1”
“0”
EI instruction
execution cycle
Interrupt disabled state
Interrupt enabled state
“H”
“L”
Retaining level for 4 cycles or
more of STCK is necessary.
“1”
“0”
Interrupt activated
condition is satisfied.
Timer 1
and
Timer 2
interrupts
“1”
T1F, T2F “0”
flags
Flag cleared
Software starts from the
interrupt address.
2 to 3 machine cycles
(Note 1, 2)
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time when each interrupt activated
condition is satisfied.
Fig. 16 Interrupt sequence
15
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EXTERNAL INTERRUPTS
An external interrupt request occurs when a valid waveform (=
waveform causing the external 0 interrupt) is input to an interrupt
input pin (edge detection).
The external 0 interrupt can be controlled with the interrupt control
register I1.
Table 7 External interrupt activated condition
Name
External 0 interrupt
D5/INT
Valid waveform
Valid waveform
Input pin
selection bit (I12)
0
1
Falling waveform (“H”→“L”)
Rising waveform (“L”→“H”)
I12
Falling
0
One-sided edge
detection circuit
D5/INT
EXF0
1
Rising
Fig. 17 External interrupt circuit structure
16
SNZI0
instruction
Skip
External 0
interrupt
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(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to “1” when a
valid waveform is input to D5/INT pin.
The valid waveforms causing the interrupt must be retained
at their level for 4 cycles or more of the system clock (Refer
to Figure 16).
The state of EXF0 flag can be examined with the skip
instruction (SNZ0). Use the interrupt control register V1 to
select the interrupt or the skip instruction. The EXF0 flag is
cleared to “0” when an interrupt occurs or when the next
instruction is skipped with the skip instruction.
The D5/INT pin need not be selected the external interrupt
input INT function or the normal output port D5 function.
However, the EXF0 flag is set to “1” when a valid waveform
output from port D5 is input to INT pin even if it is used as an
output port D5.
(2) External interrupt control register
● Interrupt control register I1
Register I1 controls the valid waveform for the external 0
interrupt. Set the contents of this register through register A
with the TI1A instruction. The TAI1 instruction can be used
to transfer the contents of register I1 to register A.
● External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a
valid waveform is input to D5/INT pin.
The valid waveform can be selected from rising waveform or
falling waveform. An example of how to use the external 0
interrupt is as follows.
➀ Select the valid waveform with the bit 2 of register I1.
➁ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➂ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➃ Set both the external 0 interrupt enable bit (V10 ) and the
INTE flag to “1.”
The external 0 interrupt is now enabled. Now when a valid
waveform is input to the D5/INT pin, the EXF0 flag is set to
“1” and the external 0 interrupt occurs.
Table 8 External interrupt control register
Interrupt control register I1
I13
Not used
I12
Interrupt valid waveform for INT pin
selection bit (Note 2)
at reset : 00002
0
1
at power down : state retained
R/W
This bit has no function, but read/write is enabled.
0
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)
1
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)
I11
Not used
I10
Not used
0
1
This bit has no function, but read/write is enabled.
0
This bit has no function, but read/write is enabled.
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Depending on the input state of D 5/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents of
I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after
executing at least one instruction.
17
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TIMERS
The 4551 Group has the programmable timers.
● Programmable timer
The programmable timer has a reload register and enables
the frequency dividing ratio to be set. It is decremented from a
set value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload
register, and count continues (auto-reload function).
● Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency
dividing ratio (n). An interrupt request flag is set to “1” every n
count of a count pulse.
FF16
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
Timer 1 interrupt “1”
request flag
“0”
An interrupt occurs or
a skip instruction is executed.
Fig. 18 Auto-reload function
The 4551 Group timer consists of the following circuits.
• Prescaler : frequency divider
• Timer 1 : 8-bit programmable timer
• Timer 2 : 14-bit fixed dividing frequency timer
• Timer LC : 4-bit programmable timer
(Timers 1 and 2 have the interrupt function, respectively)
Prescaler, timer 1, timer 2 and timer LC can be controlled with
the timer control registers W1, W2 and W3.
Each function is described below.
Table 9 Function related timers
Circuit
Prescaler
Timer 1
Timer 2
Frequency divider
• Instruction clock (INSTCK)
8-bit programmable
• Prescaler output (ORCLK)
binary down counter
• Carrier generating circuit
output (CARRY, CARRY/2)
14-bit fixed dividing • Prescaler output (ORCLK)
frequency
Timer LC
Frequency
dividing ratio
4, 8
1 to 256
16384
• f(XCIN)
4-bit programmable • Bit 3 of timer 2
binary down counter
18
Count source
Structure
• System clock (STCK)
Use of output signal
Control
register
• Timer 1 and 2 count sources
W1
• Timer 1 interrupt
• Port CARR output control
W1
W2
• Timer 2 interrupt
W2
• Divider for LCD
• Watchdog timer
1 to 16
• Divider for LCD
• Carrier output
W3
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INSTCK
Frequency
dividing circuit
(divided by 4)
MR0
XIN
XCIN
MR3
0
0
W12
0
1/4
0
1
1/8
1
ORCLK
Frequency
dividing circuit
(divided by 3)
1
Prescaler
W13
1
STCK
W11,W10
W20 (Note 1)
00,01
ORCLK
0
10
CARRY
1
Timer 1
interrupt
T1F
Timer 1 (8)
1
11
2
Reload register R1 (8)
(T1AB) (Note 2)
(TAB1)
W31
STCK
1
Carrier wave
output control
Register B Register A
W30 (Note 1)
Count
0
source
1
To port CARR
Timer LC (4)
Reload register LC (4)
1
2
LCD clock
0
WRST instruction
S
WEF
W23 (Note 3)
Reset signal
Q
R
0
ORCLK
1
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Count
source
Timer 2
WDF
D
T
System
reset
Q
W22, W21
00
01
T2F
Timer 2
interrupt
Not available
10,11
Notes 1: Count source is stopped by setting to “0.”
2: When the T1AB instruction is executed after
setting W20 to “1,” data is written only to
reload register R1.
3: When the contents of W23 changes from “0”
to “1,” the count value of timer 2 is initialized.
Fig. 19 Timers structure
19
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Table 10 Timer control registers
at reset : 00002
Timer control register W1
W13
Prescaler control bit
W12
Prescaler dividing ratio selection bit
0
1
Stop (prescaler state initialized)
Operating
0
Instruction clock (INSTCK) divided by 4
1
Instruction clock (INSTCK) divided by 8
Count source
W11 W10
W11
Timer 1 count source selection bits
W10
0
0
0
1
1
Carrier output (CARRY)
Carrier output divided by 2 (CARRY/2)
at reset : 10002
Timer control register W2
0
1
Timer 2 count source selection bit
at power down : – – – 02
Timer 2 count value selection bits
W21
W20
Timer 1 control bit
0
0
Count source
W31
Timer LC count source selection bit
W30
Timer LC control bit
14
0
Underflow occur every 2 count
1
1
0
Underflow occur every 213 count
Not available
1
1
Not available
Stop (timer 1 state retained)
Operating
0
1
at reset : 002
Timer control register W3
at power down : state retained
R/W
0
Bit 3 of timer 2 is output (timer 2 count source divided by 16)
1
0
State clock (STCK)
Stop (timer LC state retained)
1
Operating
Note: “R” represents read enabled, and “W” represents write enabled.
“–” represents state retained.
(1) Timer control registers
● Timer control register W1
Register W1 controls the count source of timer 1, the
frequency dividing ratio and count operation of prescaler.
Set the contents of this register through register A with
the TW1A instruction. The TAW1 instruction can be used
to transfer the contents of register W1 to register A.
● Timer control register W2
Register W2 controls the count operation of timer 1 and
count operation and count source of timer 2. Set the
contents of this register through register A with the TW2A
instruction. The TAW2 instruction can be used to transfer
the contents of register W2 to register A.
● Timer control register W3
Register W3 controls the count operation and count source
of timer LC. Set the contents of this register through
register A with the TW3A instruction. The TAW3 instruction
can be used to transfer the contents of register W3 to
register A.
20
R/W
f(XCIN)
Prescaler output (ORCLK)
W22 W21
W22
R/W
Prescaler output (ORCLK)
0
1
1
W23
at power down : 00002
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(2) Precautions
Note the following for the use of timers.
● Prescaler
Stop the prescaler operation to change its frequency
dividing ratio.
● Count source
Stop timer 1 or timer LC counting to change its count
source. When timer 2 count source changes from f(XCIN)
to ORCLK (W23 = “0” → W23 = “1”), the count value of
timer 2 is initialized. However, when timer 2 count source
changes from ORCLK to f(XCIN) (W23 = “1” → W23 = “0”)
or the same count source is set again (W23 = “0” → W23
= “0” or W23 = “1” → W23 = “1”), the count value of timer
2 is not initialized.
● Timer 2
Timer 2 has the watchdog timer function (WDT). When
timer 2 is used as the WDT, note that the processing to
initialize the count value and the execution of the WRST
instruction.
● Reading the count value
Stop the prescaler and then execute the TAB1 instruction
to read timer 1 data.
● Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
(3) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio
can be selected. The count source of prescaler is the
instruction clock (INSTCK).
Use the bit 2 of register W1 to select the prescaler dividing
ratio and the bit 3 to start and stop its operation. When the bit
3 of register W1 is cleared to “0,” prescaler is initialized, and
the output signal (ORCLK) stops.
(4) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload
register (R1). When timer 1 stops, data can be set
simultaneously in timer 1 and the reload register (R1) with
the T1AB instruction. When timer 1 is operating, data can be
set only in the reload register (R1) with the T1AB instruction.
When setting the next count data to reload register R1 while
timer 1 is operating, be sure to set data before timer 1
underflows.
Timer 1 starts counting after the following process;
➀ set data in timer 1,
➁ select the count source with bits 0 and 1 of register W1,
➂ set the bit 0 of register W2 to “1.”
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 interrupt request flag (T1F) is set to “1,” new data is
loaded from reload register R1, and count continues (autoreload function).
When a value set in reload register R1 is n, timer 1 divides
the count source signal by n + 1 (n = 0 to 255).
Data can be read from timer 1 to registers A and B. Stop
counting and then execute the TAB1 instruction to read its
data.
(5) Timer 2 (interrupt function)
Timer 2 is a 14-bit binary down counter.
Timer 2 starts counting after the following process;
➀ select the count source with the bit 3 of register W2, and
➁ the clock as a count source is supplied.
Timer 2 stops counting and its count value is retained when
supply of a clock as a count source stops. Timer 2 is initialized
at reset and when the count source changes from f(XCIN)
(W23=“0”) to ORCLK (W23=“1”).
The count value to set the timer 2 interrupt request flag (T2F)
to “1” can be selected from every 8192 count or every 16384
count with bits 1 and 2 of register W2. The count source signal
divided by 16 is output from timer 2.
Timer 2 can be used as a counter for clock in the clock
operating mode (POF instruction executed).
(6) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC
reload register (RLC). Data can be set simultaneously in timer
LC and the reload register (RLC) with the TLCA instruction.
Timer LC starts counting after the following process;
➀ set data in timer LC,
➁ select the count source with the bit 1 of register W3,
➂ set the bit 0 of register W3 to “1.”
Timer LC is the timer for LCD clock generating. Also, it can
be used as the multi-carrier generator by setting the bit 1 of
register W3 to “1” and selecting the system clock (STCK) as
a count source. When the multi-carrier generator is selected,
the waveform which is the timer LC underflow signal divided
by 2 can be output as a carrier wave from port CARR. At this
time, stop the carrier generating circuit and LCD control circuit.
When the multi-carrier generator (duty ratio: 1/2 fixed) is used,
the enable/stop of the carrier wave output from port CARR
can be set by the stop of timer LC or the carrier wave output
auto-control function by timer 1.
(7) Timer interrupt request flags (T1F and T2F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with
the skip instructions (SNZT1 and SNZT2).
Use the interrupt control register V1 to select an interrupt or
a skip instruction.
An interrupt request flag is cleared to “0” when an interrupt
occurs or when the next instruction is skipped with a skip
instruction.
21
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WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a
program runs wild. Watchdog timer consists of timer 2, watchdog
timer enable flag (WEF), and watchdog timer flag (WDF).
When the WRST instruction is executed after system is released
from reset, the WEF flag is set to “1.” At this time, the watchdog
timer starts operating. When the WEF flag is set to “1,” it cannot
be cleared to “0” until system reset is performed. Also, when the
WRST instruction is not executed once, watchdog timer does
not operate because the WEF flag retains “0.”
When the watchdog timer is operating, the WDF flag is set to “1”
every time the bit 12 of timer 2 is cleared from “1” to “0.” This
means that count is performed 8192 times. When the bit 12 of
timer 2 is cleared from “1” to “0” while the WDF flag is set to “1,”
the internal reset signal is generated and system reset is
performed.
The WDF flag can be cleared to “0” with the WRST instruction.
In the RAM back-up mode, through timer 2 count operation stops,
its count value is retained and the WDF flag is initialized.
In the clock operating mode, timer 2 count operation is continued
and the WDF flag is initialized.
When using the watchdog timer, execute the WRST instruction
at a certain cycle which consists of timer 2’s 8191 counts or less
to keep the microcomputer operation normal.
3FFF16
Value of timer 2 1FFF16
0000 16
WEF flag
“1”
“0”
WDF flag
“1”
“0”
Internal reset
signal
“H”
“L”
System reset
WRST instruction WRST instruction
execution
execution
Fig. 20 Watchdog timer function
The contents of the WDF flag are initialized in the RAM back-up
mode.
If the WDF flag is set to “1” at the same time that the
microcomputer enters the RAM back-up mode, system reset may
be performed.
When using the watchdog timer and the RAM back-up mode,
initialize the WDF flag with the WRST instruction just before the
microcomputer enters the RAM back-up mode (refer to Figure
21).
•
••
•
•
•
WRST
; Clear WDF flag
EPOF
; POF instruction execution enabled
POF2
Oscillation stop (RAM back-up mode)
Fig. 21 Program example to enter the RAM back-up mode
when using the watchdog timer
22
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CARRIER GENERATING CIRCUIT
The 4551 Group has a carrier generating circuit that generates
the transfer waveform by dividing the system clock (STCK) for
each remote control carrier wave. Each carrier waveform can be
output by setting the carrier wave selection register (C1).
Also, timer 1 can auto-control the carrier wave output from port
CARR by setting the carrier wave output control register (C2).
Carrier wave selection register C1
Register C1
Setting value
STCR instruction
0
0
0
Output waveform
SPCR instruction
Carrier wave
Frequency
C13 C12 C11 C10
0
(at reset: 0 1 1 1 2, at power down: 0 1 1 1 2, W)
Duty
“H”
“L”
1/3
STCK/24
0
0
0
1
“H”
“L”
0
0
1
0
“H”
“L”
1/2
1/4
STCK/16
0
0
1
1
“H”
“L”
0
1
0
0
“H”
“L”
0
1
0
1
1
1
0
1
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
“H”
“L”
1/2
STCK/2
1/2
No carrier wave
No available
“H”
“L”
“L” fixed
“H”
“L”
1/3
STCK/12
1
0
0
1
“H”
“L”
1/2
1
0
1
0
“H”
“L”
1/4
STCK/8
1
0
1
1
“H”
“L”
1
1
0
0
“H”
“L”
1/2
STCK
1/2
Note:“W” represents write enabled.
Fig. 22 Carrier wave selection register
23
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Table 11 Carrier generating circuit control register and control flag
Carrier wave output control register C2
C20
Carrier wave output auto-control bit
at reset : 02
CR
Carrier wave generating control
W
Auto-control output by timer 1 is invalid
Auto-control output by timer 1 is valid
0
1
Carrier wave generating control flag CR
at power down : 02
at reset : 02
0
1
at power down : 02
W
Carrier wave generating stop (SPCR instruction)
Carrier wave generating start (STCR instruction)
Note: “W” represents write enabled.
(1) Carrier generating circuit related registers
● Carrier wave selection register C1
Each carrier waveform can be selected by setting the register
C1. Set the contents of this register through register A with
the TC1A instruction.
● Carrier wave output control register C2
Timer 1 can auto-control the output enable interval and the
output disable interval of the carrier wave output from port
CARR by setting the register C2. Set the contents of this
register through register A with the TC2A instruction.
The setting of the output enable/disable interval is described
below.
➀ Validate the carrier wave output auto-control function
(C20=“1”).
➁ Select the carrier wave or the carrier wave divided by 2
as the timer 1 count source.
➂ Set the count value (the output enable interval of carrier
wave from port CARR) to timer 1.
➃ Operate timer 1 (W20=“1”).
➄ Operate the carrier generating circuit (STCR instruction
executed).
➅ Set the next count value (the output disable interval of
carrier wave from port CARR) to reload register R1 before
timer 1 underflow occurs.
The carrier wave is output from port CARR until the first timer
1 underflow occurs. The output of the carrier wave from port
CARR is disabled and the next count value is loaded from
reload register R1 to timer 1 by the first timer 1 underflow.
Then, the output of carrier wave is disabled until the second
timer 1 underflow. Also, the next enable interval of the carrier
wave output can be set by setting the third count value to
timer 1 reload register before the second timer 1 underflow
occurs. If the carrier wave output auto-control function is
invalidated (C20=“0”) while the carrier wave output is autocontrolled, the output of port CARR retains the state when
the auto-control is invalidated regardless of timer 1 underflow.
This state can be terminated by timer 1 stop (W20=“0”). When
the carrier wave output auto-control function is validated
(C20=“1”) again after it is invalidated (C20=“0”), the autocontrol of carrier wave output is started again when the next
timer 1 underflow occurs.
24
(2) Carrier wave generating control flag (CR)
The CR flag is used to control the carrier wave generating
operation of the carrier generating circuit. The CR flag is “1”
and the carrier wave generating is started by executing the
STCR instruction. The CR flag is “0” and the carrier wave
generating is stopped by executing the SPCR instruction. The
CR flag is “0” at system reset.
(3) Note on the carrier generating circuit stop
In order to stop the carrier wave which has the cycle longer
than that of the instruction clock with the SPCR instruction,
stop it at the point when the carrier wave outputs “L” level in
the SPCR instruction execution cycle.
If this condition is not satisfied, the last “H” output interval of
carrier wave is shortened.
(4) Notes when using the carrier wave output auto-control function
● Execute the STCR instruction after setting the timer 1 and
register C2 in order to start the carrier generating circuit
operation.
● Stop the timer 1 (W2 0 =“0”) after stopping the carrier
generating circuit (SPCR instruction executed) while the
carrier wave output is disabled in order to stop the carrier
wave output auto-control operation.
● If the carrier wave output auto-control function is invalidated
(C20=“0”) while the carrier wave output is auto-controlled,
the output of port CARR retains the state when the autocontrol is invalidated regardless of timer 1 underflow. This
state can be terminated by timer 1 stop (W20=“0”).
When the carrier wave output auto-control function is
validated (C20=“1”) again after it is invalidated (C2 0=“0”),
the auto-control of carrier wave output is started again when
the next timer 1 underflow occurs. However, when the carrier
wave output auto-control bit is changed during timer 1
underflow, the error-operation may occur.
● Use the carrier wave or the carrier wave divided by 2 as the
timer 1 count source when the carrier wave output autocontrol function is selected.
If the ORCLK is used as the count source, a hazard may
occur in port CARR output because ORCLK is not
synchronized with the carrier wave.
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Timer 1 start
▲
Timer 1
underflow
“1”
“0”
Port CARR
output
“H”
“L”
a
b
c
d
(C20)←1
▲
▲
Set the interval Set the interval “b” to
“a” to timer 1. reload register R1.
▲
Set the interval “d” to
reload register R1.
▲
Set the interval “c” to
reload register R1.
Carrier wave output start
Timer 1 underflow
“1”
“0”
Port CARR output
“H”
“L”
Register C20
“1”
“0”
▲
Carrier wave output start
(C20)←0
▲
▲
(C20)←1 (C20)←0
▲
(C20)←1
Fig. 23 Carrier wave output auto-control by timer 1
25
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LCD FUNCTION
The 4551 Group has an LCD (Liquid Crystal Display) controller/
driver. When proper voltage is applied to the LCD power supply
input pins and data are set in timer control registers (W2, W3),
timer LC, LCD control registers (L1, L2), and LCD RAM, the LCD
controller/driver automatically reads the display data and controls
the LCD display by setting duty and bias.
4 common signal output pins and 20 segment signal output pins
can be used to drive the LCD. By using these pins, up to 80
segments (when 1/4 duty and 1/3 bias are selected) can be
controlled to display. When the required number of segment pins
is 19 or less, pins SEG16–SEG19 (4) can be used as input ports
P20–P23.
(1) Duty and bias
There are 3 combinations of duty and bias for displaying data
on the LCD. Use bits 0 and 1 of LCD control register (L1) to
select the proper display method for the LCD panel being
used.
(2) LCD clock control
The LCD clock is determined by the timer 2 count source
selection bit (W23), timer LC control bit (W30), and timer LC.
Accordingly, the frequency (F) of the LCD clock is obtained
by the following formula. Numbers (➀ to ➄) shown below the
formula correspond to numbers in Figure 24, respectively.
● When using the prescaler output (ORCLK) as timer 2 count
source (W23=“1”)
1
16
F = ORCLK ✕
➀
✕
➁➂
1
✕
LC + 1
➃
1
2
➄
● When using the f(XCIN) as timer 2 count source (W23=“0”)
1
F = f(XCIN) ✕
✕
16
➀
➁➂
1
LC + 1
➃
1
✕
2
➄
[LC: 0 to 15]
● 1/2 duty, 1/2 bias
● 1/3 duty, 1/3 bias
● 1/4 duty, 1/3 bias
The frame frequency and frame period for each display
method can be obtained by the following formula:
Table 12 Duty and maximum number of displayed pixels
Duty
Maximum number of displayed pixels
1/2
1/3
40 segments
60 segments
➀
W23
XCIN
ORCLK
Used COM pins
COM0, COM1 (Note)
COM0–COM2 (Note)
80 segments
1/4
Note: Leave unused COM pins open.
0
Frame frequency =
Frame period =
n
➂
➁
STCK
1/16
W31
1
F: LCD clock frequency
1/n: Duty
(Note)
W30
0
1
0
1
Fig. 24 LCD clock control circuit structure
(Hz)
(s)
COM0–COM3
Note: Count source is stopped by clearing to “0.”
26
n
F
F
➃
Timer LC
➄
1/2
LCD clock
L13 L12 L11 L10
LCD on/off
control
1/2, 1/3, 1/4
Counter
Decoder
Common driver
COM0 COM2
COM1
COM3
LCD clock
(from timer block)
Bias control
Control
signal
Multiplexer
(Note)
VLC3
SEG15
Register A
RAM
...
RAM
Selector
...
Selector
Segment
driver
.................
–
Segment
...
driver
SEG0
– P23/SEG19
RAM
Selector
Segment
driver
Multiplexer
.................
P20/SEG16
Note: VLC3=VDD.
L23 L22 L21 L20
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Fig. 25 LCD controller/driver structure
27
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(4) LCD drive waveform
When “1” is written to a bit in the LCD RAM data, the voltage
difference between common pin and segment pin which
correspond to the bit automatically becomes lVLC3l and the
display pixel at the cross section turns on.
When returning from reset, and in the RAM back-up mode, a
display pixel turns off because every segment output pin and
common output pin becomes VLC3 level (=VDD).
(3) LCD RAM
RAM contains areas corresponding to the liquid crystal display.
When “1” is written to this LCD RAM, the display pixel
corresponding to the bit is automatically displayed.
Z
X
Bit
Y
1
1
0
8
9
10
11
12
13
14
15
COM
3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM3
2
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM2
Note: The area marked “
1
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM1
0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM0
3
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM3
2
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM2
1
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM1
0
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM0
3
SEG16
SEG17
SEG18
SEG19
2
2
1
SEG16 SEG16
SEG17 SEG17
SEG18 SEG18
SEG19 SEG19
0
SEG16
SEG17
SEG18
SEG19
COM3 COM2 COM1 COM0
” is not the LCD display RAM.
Fig. 26 LCD RAM map
Table 13 LCD control registers
at reset : 00002
LCD control register L1
L13
Not used
L12
LCD on/off bit
L11
LCD duty and bias selection bits
0
P23/SEG19 pin function switch bit
L22
P22/SEG18 pin function switch bit
L21
P21/SEG17 pin function switch bit
L20
P20/SEG16 pin function switch bit
Duty
L10
0
0
1
1/2
1/2
0
1/3
1/3
1
1/4
1/3
Not available
at reset : 11112
0
SEG19
1
P23
0
1
SEG18
P22
0
SEG17
1
0
P21
SEG16
1
P20
Note: “R” represents read enabled, and “W” represents write enabled.
28
Bias
L11
LCD control register L2
L23
Off
On
1
0
R/W
This bit has no function, but read/write is enabled
1
0
1
1
L10
at power down : state retained
at power down : state retained
W
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1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 2, 8) in RAM.
1 frame (2/F)
M (1, 2, 8)
COM0
0 (bit 0)
COM1
1
X
1/F
Voltage level
VLC3
VLC1=VLC2
COM1
VSS
COM0
X (bit 3)
VLC3
VLC1=VLC2
VSS
SEG16
SEG16
COM1
SEG16
COM0
SEG16
ON
OFF
1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 2, 8) in RAM.
1 frame (3/F)
M (1, 2, 8)
COM0
1/F
Voltage level
1 (bit 0)
COM1
0
COM2
1
X (bit 3)
VLC3
VLC2
VLC1
VSS
COM2
COM1
SEG16
COM0
SEG16
COM2
SEG16
COM1
SEG16
COM0
SEG16
ON
OFF
ON
VLC3
VLC2
VLC1
VSS
1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 2, 8) in RAM.
1 frame (4/F)
M (1, 2, 8)
COM0
COM1
COM2
COM3
1/F
Voltage level
0 (bit 0)
1
VLC3
VLC2
VLC1
VSS
COM3
0
1 (bit 3)
COM2
SEG16
COM1
COM0
F: LCD clock frequency
X: Set an arbitrary value.
(These bits are not
related to set the drive
waveform at each duty.)
SEG16
COM3
SEG16
COM2
SEG16
COM1
SEG16
COM0
SEG16
ON
OFF
ON
OFF
VLC3
VLC2
VLC1
VSS
Fig. 27 LCD controller/driver structure
29
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RESET FUNCTION
____________
System reset is performed by applying “L” level to RESET pin
for 1 machine cycle or more when the following condition is
satisfied;
• the value of supply voltage is the minimum value or more of
the recommended operating conditions.
____________
Then when “H” level is applied to RESET pin, software starts
from address 0 in page 0.
f(XIN)
RESET
“H”
“L”
(Note)
f(XIN) is counted
10757 to 10786 times
Software start
(Address 0 in page 0)
Note: The number of clock cycles depends on the internal state of
the microcomputer when reset is performed.
Fig. 28 Reset release timing
Reset input
=
1machine cycle or more
f(XIN) is counted
10757 to 10786 times
0.85VDD
Software start
(Address 0 in page 0)
RESET
0.3VDD
Note: Keep the value of supply voltage the minimum value or more
of the recommended operating conditions.
(Note)
Fig. 29 RESET pin input waveform and reset operation
(1) Power-on reset
Reset can be automatically performed at power on (poweron reset) by the built-in power-on reset circuit. When the builtin power-on reset circuit is used, the time for the supply voltage
to reach the minimum operating voltage must be set to 100
µ s or less. If the rising time exceeds 100 µs, connect a
capacitor between the RESET pin and VSS at the shortest
distance, and input “L” level to RESET pin until the value of
supply voltage reaches the minimum operating voltage.
VDD
Pull-up
transistor
RESET
pin
Internal reset
signal
Power-on
reset circuit
Voltage drop detection circuit
(Note)
This symbol represents a parasitic
diode.
Applied potential to RESET pin must
Power-on
be VDD or less.
Fig. 30 Power-on reset circuit example
30
Reset state
Watchdog timer
output
WEF
Note:
Power-on reset circuit
output voltage
Internal reset signal
Reset released
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(2) Internal state at reset
Table 14 shows port state at reset, and Figure 31 shows
internal state at reset (they are retained after system is
released from reset).
The contents of timers, registers, flags and RAM except those
shown in Figure 31 are undefined, so set the initial values to
them.
Table 14 Port state at reset
Name
D0–D4, D5/INT
D6/XCIN, D7/XCOUT
P00–P03
P10–P13
P20/SEG16–P23/SEG19
SEG0–SEG15
COM0–COM3
CARR
Function
State
D0–D4, D5
D6, D7
High impedance (Note 1)
P00–P03
“H” (VDD) level (Note 1)
P10–P13
P20–P23
(Notes 1, 2)
High impedance
SEG0–SEG15
COM0–COM3
CARR
VLC3 (VDD) level
“L” (VSS) level
Notes 1: Output latch is set to “1.”
2: The pull-up transistor is turned off.
• Program counter (PC) ............................................................................................
0 0 0 0 0 0
0
0
0
0
0
0
0
0
Address 0 in page 0 is set to program counter.
0
• Interrupt enable flag (INTE) ...................................................................................
• Power down flag (P) ..............................................................................................
0
• External 0 interrupt request flag (EXF0) ...............................................................
0
0 0 0 0
• Interrupt control register V1 ...................................................................................
• Interrupt control register I1 ....................................................................................
0 0 0 0
(Interrupt disabled)
(Interrupt disabled)
0
• Timer 1 interrupt request flag (T1F) ......................................................................
0
• Timer 2 interrupt request flag (T2F) ......................................................................
• Watchdog timer flag (WDF) ...................................................................................
0
0
• Watchdog timer enable flag (WEF) .......................................................................
0 0 0 0
• Timer control register W1 ......................................................................................
• Timer control register W2 ......................................................................................
0 0 0 0
0 0
• Timer control register W3 ......................................................................................
(Prescaler stopped)
(Timer 1 stopped)
(Timer LC stopped)
1 0 0 0
• Clock control register MR ......................................................................................
• Carrier wave selection register C1 ........................................................................
0 1 1 1
0
• Carrier wave output control register C2 ................................................................
0
• Carrier wave generating control flag CR ...............................................................
• LCD control register L1 ..........................................................................................
0 0 0 0
1 1 1 1
• LCD control register L2 ..........................................................................................
(Carrier wave output disabled)
(LCD off)
(Port P2 selected)
0 0 0 0
• Pull-up control register PU0 ..................................................................................
• General-purpose register V2 .................................................................................
0 0 0 0
0
• Carry flag (CY) .......................................................................................................
0 0 0 0
• Register A ..............................................................................................................
• Register B ..............................................................................................................
0 0 0 0
✕ ✕ ✕
• Register D ..............................................................................................................
• Register E ..............................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Data pointer X ........................................................................................................
0 0 0 0
0 0 0 0
• Data pointer Y ........................................................................................................
✕ ✕
• Data pointer Z ........................................................................................................
• Stack pointer (SP) ..................................................................................................
1 1 1
“✕” represents undefined.
Fig. 31 Internal state at reset
31
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VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply
voltage drops below a set value.
Pull-up transistor
Internal reset signal
RESET pin
Power-on
reset circuit
Voltage drop detection circuit
Watchdog timer output
WEF
Fig. 32 Voltage drop detection reset circuit
Voltage drop
detection circuit
Operating
Voltage drop
detection circuit
Stop
Voltage drop
Voltage drop
detection circuit detection circuit
Operating
Stop
VDD
Detection voltage
Internal reset
signal
“H”
“L”
The microcomputer starts operation after the
f(XIN) is counted 10757 to 10786 times.
Fig. 33 Voltage drop detection circuit operation waveform
32
Voltage drop detection
circuit
Operating
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POWER DOWN FUNCTION
Table 15 Functions and states retained at power down
The 4551 Group has 2-type power down functions.
Function
● Clock operating mode .................................. POF instruction
● RAM back-up mode .................................... POF2 instruction
Power down is performed by executing each instruction. Above
power down functions are different from reset in start conditions.
Table 15 shows the function and states retained at power down.
Figure 36 shows the state transition.
operating back-up
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port level
Clock control register MR
● Return from power down state ............. Warm start condition
● Return from reset state .......................... Cold start condition
Timer control register W1
(1) Clock operating mode
The following functions and states are retained.
● RAM
● Reset circuit
● XCIN–XCOUT oscillation
● LCD display
● Timer 2
Interrupt control register I1
Timer control registers W2, W3
Interrupt control register V1
Carrier wave control registers and flag (C1, C2, CR)
LCD display function
LCD control registers L1, L2
Timer LC
Timer 1 function
Timer 2 function
(2) RAM back-up mode
The following functions and states are retained.
● RAM
● Reset circuit
Unlike the clock operating mode, all oscillations stop in the
RAM back-up mode.
External 0 interrupt request flag (EXF0)
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Watchdog timer flag (WDF)
Watchdog timer enable flag (WEF)
Interrupt enable flag (INTE)
(3) Warm start condition
The system returns from the power down state when;
● the external wakeup signal is input or the timer 2 underflow
occurs
in the clock operating mode, or when;
● the external wakeup signal is input
in the RAM back-up mode.
In either case, the CPU starts executing the software from
address 0 in page 0. In this case, the P flag is “1.”
Power down
Clock
RAM
✕
✕
O
O
O
O
✕
O
✕
O
✕
O
O
O
✕
O
✕
✕
O
O
O
O
✕
O
✕
O
✕
(Note 3)
O
(Note 4)
✕
O
✕
✕
O
O
✕
O
✕
✕
✕
✕
General-purpose register V2
Notes 1: “O” represents that the function can be retained, and
“✕” represents that the function is initialized.
Registers and flags other than the above are undefined
at power down, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack
register and is initialized to “1112” at power down.
3: LCD is turned off.
4: The state of the timer is undefined.
(4) Cold start condition
The CPU starts executing the software from address 0 in
page 0 when;
● reset pulse is input to RESET pin, or
● reset by watchdog timer is performed.
In this case, the P flag is “0.”
33
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(5) Identification of the start condition
Warm start or cold start can be identified by examining the
state of the power down flag (P) with the SNZP instruction.
The warm start condition (timer 2 or external wakeup signal)
can be identified by examining the state of T2F flag.
POF instruction
or
POF2 instruction
Reset input
Software start
Powerdown flag P
S
Q
Yes
P = “1”
?
No
R
Yes
T2F = “1”
?
Cold start
● Set source
POF or POF2 instruction executed
● Clear source
Reset input
No
Return by timer 2
underflow
Return by external
wakeup signal
Fig. 34 Set source and clear source of the P flag
Fig. 35 Start condition identified example using the SNZP instruction
(6) Return signal
An external wakeup signal or timer 2 interrupt request flag is
used to return from the clock operating mode.
An external wakeup signal is used to return from the RAM
back-up mode because the oscillation is stopped. Table 16
shows the return condition for each return source.
(7) Port P1 control register
● Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P1 pull-up
transistor and the ON/OFF of the key-on wakeup function.
Set the contents of this register through register A with
the TPU0A instruction. In addition, the TAPU0 instruction
can be used to transfer the contents of register PU0 to
register A.
Table 16 Return source and return condition
External wakeup
signal
Return source
Return condition
Remarks
Ports P0, P1 Returns by an external falling Port P0 shares the falling edge detection circuit with port P1. The key-on
edge input (“H”→“L”).
wakeup function of port P0 is always valid. The only key-on wakeup
function of the port P1 bit of which the pull-up transistor is turned on is
valid. Set all the port using the key-on wakeup function to “H” level before
going into the power down state.
Timer 2 interrupt Returns by timer 2 underflow and The timer 2 interrupt request flag (T2F) can be used only when system
setting T2F to “1.”
returns from the clock operating mode (POF instruction execution).
request flag
However, if the POF and POF2 instructions are executed while the T2F =
“1”, its operation is recognized as the return condition and system returns
from the clock operating mode.
Note: P1 pin has the pull-up transistor which can be turned on/off by software.
Table 17 Pull-up control register
Pull-up control register PU0
PU03
PU02
PU01
Port P13 pull-up transistor
control bit
Port P12 pull-up transistor
control bit
Port P11 pull-up transistor
control bit
at reset : 00002
at power down : state retained
0
1
Pull-up transistor OFF, no key-on wakeup
0
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
1
0
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
0
PU00
Pull-up transistor ON, key-on wakeup
control bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
Port P10 pull-up transistor
34
1
R/W
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
(8) State transition
State transition is described using Figure 36.
Reset
(Stabilizing time a )
Clock
operating
mode
f(XIN):Stop
f(XCIN) :
Oscillation
System clock;
f(XIN)/4
MR=(11002)
POF execution
C ,G
Return input 1, 2
C ,G
Return input 1, 2
D ,H
(Stabilizing time c )
(Note 1)
me
d)
MR3 ← 0
(Note 2)
M
1
MRR0 ←
0← 0
R
←
3
M R0
← 0
M
1
1
MR
3← 0
MR 0 ←
R
←
M 3
(Note 2) 3 ← 1
MR
0
MR2 ← 0
(Stabilizing time d )
F
f(XIN):Oscillation
f(XCIN):Oscillation
System clock;
f(XIN)
MR=(01002)
System clock;
f(XCIN)/4
MR=(11012)
MR3 ← 0
M
MRR1 ←
(St
abi 3 ← 0
lizin
1
g
D
f(XIN):Stop
f(XCIN):Oscillation
System clock;
f(XCIN)/4
MR=(11112)
tim
e
c
1 )
←
1
1
MR 3 ←
MR
System clock;
f(XCIN)
MR=(01012)
0
1 ← 0 c)
R
←
M R3 time
M ilizing
ab
(St
M
MR R1 ←
3
← 1
0
MR3 ← 1
MR3 ← 0
Return input 1
A ,E
(Stabilizing time a )
RAM
back-up
mode
f(XIN):Stop
f(XCIN):Stop
POF2 execution
B ,F
Return input 1
B ,F
(Stabilizing time a )
POF2 execution
f(XIN):Oscillation
f(XCIN):Oscillation
MR3 ← 1
A ,E
(Note 2)
G
C
POF execution
D ,H
MR3 ← 1
f(XIN):Oscillation
f(XCIN):Oscillation
MR1 ← 1
(Stabilizing time c )
(Note 1)
g ti
(Stabilizing time c )
Return input 1, 2
B ,F
f(XIN):Oscillation
f(XCIN):Oscillation
ab
(St
MR1 ← 1
B ,F
izin
ing
iliz
B
MR0 ← 1
J
0
M
MRR2 ←
2← 0
R
←
2
← 0 MMR3
1
(Note 2)
M
1
MRR3 ←
3
2← 1
← 1
)(
MRR3 ←
0
e d Stab
il
tim
M
K
System clock;
f(XIN)
MR=(00002)
MR0 ← 1
POF execution
MR2 ← 0
MR2 ← 1
f(XCIN):Stop
MR3 ← 0
MR0 ← 0
(Note 2)
f(XIN):Oscillation
f(XCIN):Stop
MR2 ← 1
System clock;
f(XIN)/4
MR=(10002)
(Stabilizing time c )
(Stabilizing time a ) f(XIN):Stop
MR3 ← 1
MR0 ← 0
Clock
operating
mode
POF2 execution
E
A
f(XIN):Oscillation
f(XCIN):Stop
MR1 ← 0
Return input 1
A ,E
I
(Stabilizing time d )
A ,E
MR1 ← 0
POF execution
H
f(XIN):Stop
f(XCIN):Oscillation
System clock;
f(XCIN)
MR=(01112)
C ,G
Return input 1
C ,G
(Stabilizing time b )
POF2 execution
D ,H
Return input 1
D ,H
(Stabilizing time b )
Stabilizing time a : An interval required to stabilize the f(XIN) oscillation is automatically generated by hardware.
Stabilizing time b : An interval required to stabilize the f(XCIN) oscillation is automatically generated by hardware.
Stabilizing time c : Generate an interval required to stabilize the f(XIN) oscillation in state C or G by software at the
transition D→C, D→G, H→C, H→G, J→C, or J→G.
Stabilizing time d : Generate an interval required to stabilize the f(XCIN) oscillation in state B, F by software at the
transition A→B, E→F, A→F, or E→B.
Return input 1: External wakeup signal (P00–P03, P10–P13)
Return input 2: Timer 2 interrupt request flag
Notes 1. MR3=“1”→The microcomputer starts its operation after counting f(XCIN) clock signal 59 to 70 times.
MR3=“0”→The microcomputer starts its operation after counting f(XCIN) clock signal 32 to 43 times.
2. When the following 2 conditions are satisfied, the transition A→E, B→F, A→F, C→F, G→F represented
by “
” can be executed.
(1) VDD = 2.2 V to 5.5 V (One Time PROM version: VDD = 2.5 V to 5.5 V), f(XIN) ≤ 1.0 MHz
(2) VDD = 4.5 V to 5.5 V, f(XIN) ≤ 2.0 MHz
Fig. 36 State transition
35
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
CLOCK CONTROL
The clock control circuit consists of the following circuits.
● Clock generating circuit
● Control circuit to stop the clock oscillation
● System clock (STCK) selection circuit
● Instruction clock (INSTCK) generating circuit
● Control circuit to return from the power down state
MR0
XIN
XOUT
OSC
Multiplexer
Frequency
dividing circuit
(divided by 4)
MR3
Internal clock
1
0
generating circuit
INSTCK
(divided by 3)
STCK
MR1
XCIN
OSC
XCOUT
POF instruction
R
Q
S
POF2 instruction
R
S
RESET
Q
T2F flag
Falling detected
Ports P0, P1
Fig. 37 Clock control circuit structure
(1) Clock control register
● Clock control register MR
Register MR controls the system clock. Set the contents
of this register through register A with the TMRA
instruction. In addition, the TAMR instruction can be used
to transfer the contents of register MR to register A.
Table 18 Clock control register
Clock control register MR
at reset : 10002
0
MR3
System clock (STCK) selection bit
1
MR2
f(XCIN) oscillation circuit control bit
MR1
f(XIN) oscillation circuit control bit
0
1
0
1
MR0=0 f(XIN)
MR0=1 f(XCIN)
MR0=0 f(XIN)/4
MR0=1 f(XCIN)/4
f(XCIN) oscillation stop, ports D6 and D7 selected
f(XCIN) oscillation enabled, ports D6 and D7 not selected
Oscillation enabled
Oscillation stop
f(XIN)
0
f(XCIN)
1
Note: “R” represents read enabled, and “W” represents write enabled.
MR0
36
Clock selection bit
at power down : state retained
R/W
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
(2) f(XIN) clock generating circuit
Clock signal f(X IN) is obtained by externally connecting a
ceramic resonator. Connect this external circuit to pins XIN
and XOUT at the shortest distance. A feedback resistor is built
in between pins XIN and XOUT.
(3) f(XCIN) clock generating circuit
Clock signal f(XCIN) is obtained by externally connecting a
quartz-crystal oscillator. Connect this external circuit to pins
XCIN and XCOUT at the shortest distance. A feedback resistor
is built in between pins XCIN and XCOUT.
M34551
XIN
CIN
Note: Externally connect a
damping resistor Rd
depending on the
XOUT
oscillation frequency.
(A feedback resistor is
built-in.)
Rd
Use the resonator
manufacturer’s
recommended value
COUT
because constants such
as capacitance depend
on the resonator.
ROM ORDERING METHOD
Please submit the information described below when ordering
Mask ROM.
(1) M34551M4-XXXFP Mask ROM Order Confirmation Form
..............................................................................................1
(2) Data to be written into mask ROM ......................... EPROM
(three sets containing the identical data)
(3) Mark Specification Form ..................................................... 1
Fig. 38 Ceramic resonator external circuit
Note: Externally connect a
damping resistor Rd
depending on the
XCOUT
oscillation frequency.
(A feedback resistor is
built-in.)
Rd
Use the quartz-crystal
oscillator manufacturer’s
recommended value
COUT
because constants such
as capacitance depend
on the quartz-crystal
oscillator.
M34551
XCIN
CIN
Fig. 39 Quartz-crystal oscillator external circuit
37
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
LIST OF PRECAUTIONS
➀ Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins
VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire.
In the built-in PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to VSS
through a resistor about 5 kΩ (connect this resistor to CNVSS/
VPP pin as close as possible).
➁ Prescaler
Stop the prescaler operation to change its frequency dividing
ratio.
➂ Count source
Stop timer 1 or timer LC counting to change its count source.
When timer 2 count source changes from f(XCIN) to ORCLK
(W23 = “0” → W23 = “1”), the count value of timer 2 is initialized.
However, when timer 2 count source changes from ORCLK to
f(XCIN) (W23 = “1” → W23 = “0”) or the same count source is
set again (W23 = “0” → W23 = “0” or W23 = “1” → W23 = “1”),
the count value of timer 2 is not initialized.
• Use the carrier wave or the carrier wave divided by 2 as the
timer 1 count source when the carrier wave output autocontrol function is selected.
If the ORCLK is used as the count source, a hazard may
occur in port CARR output because ORCLK is not
synchronized with the carrier wave.
➇ D5/INT pin
When the interrupt valid waveform of D5/INT pin is changed
with the bit 2 of register I1 in software, be careful about the
following notes.
• Clear the bit 0 of register V1 to “0” and then change the
interrupt valid waveform of D5/INT pin with the bit 2 of register
I1 (refer to Figure 40➀).
• Clear the bit 2 of register I1 to “0” and execute the SNZ0
instruction to clear the EXF0 flag after executing at least
one instruction (refer to Figure 40➁). Depending on the input
state of the D5/INT pin, the external 0 interrupt request flag
(EXF0) may be set to “1” when the interrupt valid waveform
is changed.
...
LA
4
TV1A
➃ Timer 2
Timer 2 has the watchdog timer function (WDT). When timer 2
is used as the WDT, note that the processing to initialize the
count value and the execution of the WRST instruction.
➄ Reading the count value
Stop the prescaler and then execute the TAB1 instruction to
read timer 1 data.
➅ Writing to reload register R1
Write the data to reload register R1 while timer 1 is operating,
avoid a timing when timer 1 underflows.
➆ Notes when using the carrier wave output auto-control function
• Execute the STCR instruction after setting the timer 1 and
register C2 in order to start the carrier generating circuit
operation.
• Stop the timer 1 (W2 0 =“0”) after stopping the carrier
generating circuit (SPCR instruction executed) while the
carrier wave output is disabled in order to stop the carrier
wave output auto-control operation.
• If the carrier wave output auto-control function is invalidated
(C20=“0”) while the carrier wave output is auto-controlled,
the output of port CARR retains the state when the autocontrol is invalidated regardless of timer 1 underflow. This
state is released by timer 1 stop (W20=“0”).
When the carrier wave output auto-control function is
validated (C20=“1”) again after it is invalidated (C20=“0”),
the auto-control of carrier wave output is started again when
the next timer 1 underflow occurs. However, when the carrier
wave output auto-control bit is changed during timer 1
underflow, the error-operation may occur.
38
LA
TI1A
; (✕✕✕02)
; The SNZ0 instruction is valid
➀
4
; Change of the interrupt valid waveform
➁
NOP
SNZ0
NOP
...
;The SNZ0 instruction is executed
✕ : this bit is not related to the setting of INT.
Fig. 40 External 0 interrupt program example
➈ One Time PROM version
The operating power voltage of the One Time PROM version
is within the range of 2.5 V to 5.5 V.
➉ Multifunction
Note that the port D5 output function can be used even when
INT function is selected.
11 Power
down instruction (POF instruction, POF2 instruction)
Execute the POF or POF2 instruction immediately after
executing the EPOF instruction to enter the power down state.
Note that system cannot enter the power down state when
executing only the POF or POF2 instruction.
12 Program
counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
LIST OF INSTRUCTION FUNCTION
TBA
(B) ← (A)
TAY
(A) ← (Y)
TYA
(Y) ← (A)
TEAB
Function
Mnemonic
(A) ← → (M(DP))
XAMI j
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
Function
Mnemonic
SB j
(Mj(DP)) ← 1
j = 0 to 3
RB j
(Mj(DP)) ← 0
j = 0 to 3
SZB j
j = 0 to 15
(Mj(DP)) = 0 ?
j = 0 to 3
(E7–E4) ← (B)
(E3–E0) ← (A)
LA n
(A) ← n
n = 0 to 15
TABE
Grouping
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
(DR2–DR0) ← (A2–A0)
TAD
(A2–A0) ← (DR2–DR0)
(A3) ← 0
TAZ
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
(A) ← (X)
TASP
(A2–A0) ← (SP2–SP0)
(A3) ← 0
TABP p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
SEAM
(A) = (M(DP)) ?
SEA n
(A) = n ?
n = 0 to 15
Ba
(PCL) ← a6–a0
BL p, a
(PCH) ← p
(PCL) ← a6–a0
BLA p
(PCH) ← p
(PC L ) ← (DR 2 –DR 0 ,
(PC L ) ← (DR 2 –DR 0 ,
A3–A0)
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Branch operation
Register to register transfer
(A) ← (B)
Grouping
Bit operation
TAB
Function
Comparison
operation
Mnemonic
RAM to register transfer
Grouping
LZ z
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
(A) ← (A) + (M(DP))
AMC
(A) ← (A) + (M(DP))
+ (CY)
BM a
(A) ← (A) + n
n = 0 to 15
(Z) ← z, z = 0 to 3
INY
(Y) ← (Y) + 1
DEY
(Y) ← (Y) – 1
TAM j
(A) ← (M(DP))
(X) ← (X)EXOR(j)
(PCH) ← 2
(PCL) ← a6–a0
(CY) ← Carry
An
AND
(A) ← (A)AND(M(DP))
OR
(A) ← (A)OR(M(DP))
SC
(CY) ← 1
RC
(CY) ← 0
SZC
(CY) = 0 ?
CMA
(A) ← (A)
RAR
→ CY → A3A2A1A0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
Subroutine operation
RAM addresses
LXY x, y
Arithmetic operation
A3–A0)
AM
BML p, a (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
BMLA p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0,
A3–A0)
XAM j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(PC) ← (SK(SP))
(SP) ← (SP) – 1
j = 0 to 15
XAMD j
RTI
Return operation
RAM to register transfer
j = 0 to 15
RT
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(Y) ← (Y) – 1
39
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
LIST OF INSTRUCTION FUNCTION (CONTINUED)
DI
(INTE) ← 0
EI
(INTE) ← 1
SNZ0
(EXF0) = 1 ?
Interrupt operation
After skipping the next
instruction,
(EXF0) ← 0
SNZI0
I12 = 1 : (INT0) = “H” ?
I12 = 0 : (INT0) = “L” ?
TAV1
(A) ← (V1)
TV1A
(V1) ← (A)
TAI1
(A) ← (I1)
Grouping
Mnemonic
TLCA
(TLC) ← (A)
(RLC) ← (A)
SNZT1
(T1F) = 1 ?
After skipping the next
TW1A
SPCR
Carrier wave
generating stop
TC2A
(C20) ← (A0)
(T2F) ← 0
NOP
(PC) ← (PC) + 1
(A) ← (P0)
POF
Transition to clock
(T2F) = 1 ?
After skipping the next
instruction,
operating mode
OP0A
(P0) ← (A)
IAP1
(A) ← (P1)
OP1A
(P1) ← (A)
IAP2
(A) ← (P2)
CLD
(D) ← 1
POF2
Transition to RAM
back-up mode
(I1) ← (A)
(A) ← (W1)
(W1) ← (A)
TAW2
(A) ← (W2)
TW2A
(W2) ← (A)
TAW3
(A1, A0) ← (W31, W30)
Input/Output operation
TAW1
Mnemonic
Function
TC1A
(C1) ← (A)
Carrier wave
generating start
(T1F) ← 0
SNZT2
Grouping
STCR
instruction,
IAP0
TI1A
Function
Carrier wave generating operation
Function
RD
SD
EPOF
Other operation
Mnemonic
Timer operation
Grouping
Power down instruction
(POF, POF2) valid
SNZP
(P) = 1 ?
WRST
(WDF) ← 0, (WEF) ← 1
(Y) = 0 to 9
TAMR
(A) ← (MR)
(D(Y)) ← 1
TMRA
(MR) ← (A)
TAV2
(A) ← (V2)
TV2A
(V2) ← (A)
(D(Y)) ← 0
(Y) = 0 to 9
TAB1
T1AB
(W31, W30) ← (A1, A0)
TPU0A
(PU0) ← (A)
(A) ← (T13–T10)
TAPU0
(A) ← (PU0)
at timer 1 stop (W20=0)
TL1A
(L1) ← (A)
TAL1
(A) ← (L1)
TL2A
(L2) ← (A)
(B) ← (T17–T14)
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
At timer 1 operating
(W20=1),
(R17–R14) ← (B)
(R13–R10) ← (A)
40
LCD control operation
Timer operation
TW3A
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
INSTRUCTION CODE TABLE
D9–D4 000000 000001 000010 000011 000100000101000110 000111001000 001001001010001011 001100 001101001110 001111
Hex.
notation
00
01
0000
0
NOP
BLA
0001
1
–
0010
2
POF
0011
3
0100
4
DI
RD
0101
5
EI
SD SEAn
0110
6
RC
–
0111
7
SC
1000
8
1001
9
1010
A
1011
B
AMC
1100
C
1101
D
1110
1111
D3–
D0
010000011000
010111011111
0E
0F
TABP TABP TABP TABP
0
16
32* 48* BML BML
BL
BL
BM
B
LA
1
TABP TABP TABP TABP
BML BML
1
17
33* 49*
BL
BL
BM
B
A
2
LA
2
TABP TABP TABP TABP
BML BML
2
18
34* 50*
BL
BL
BM
B
TAZ
A
3
LA
3
TABP TABP TABP TABP
BML BML
3
19
35* 51*
BL
BL
BM
B
TAV1
A
4
LA
4
TABP TABP TABP TABP
BML BML
20
4
36* 52*
BL
BL
BM
B
–
RTS TAV2
A
5
LA
5
TABP TABP TABP TABP
BML BML
5
21
37* 53*
BL
BL
BM
B
SEAM
–
RTI
–
A
6
LA
6
TABP TABP TABP TABP
BML
38* 54* BML
6
22
BL
BL
BM
B
DEY
–
–
–
–
A
7
LA
7
TABP TABP TABP TABP
BML
39* 55* BML
7
23
BL
BL
BM
B
POF2 AND
–
SNZ0
LZ
0
–
A
8
LA
8
TABP TABP TABP TABP
BML BML
8
24
40* 56*
BL
BL
BM
B
TDA
–
LZ
1
–
A
9
LA
9
TABP TABP TABP TABP
41* 57* BML BML
9
25
BL
BL
BM
B
LZ
2
–
A
10
LA
10
TABP TABP TABP TABP
10
26
42* 58* BML BML
BL
BL
BM
B
A
EPOF 11
LA
11
TABP TABP TABP TABP
11
43* 59* BML BML
27
BL
BL
BM
B
04
05
06
07
SZB
BMLA
0
–
TASP
A
0
LA
0
CLD
SZB
1
–
–
TAD
A
1
–
SZB
2
–
–
TAX
SZB
3
–
–
–
–
RT
SNZP INY
OR
–
03
02
AM TEAB TABE SNZI0
08
09
0A
0B
0C
0D
10–17 18–1F
–
–
LZ
3
TYA CMA
–
–
RB
0
SB
0
A
12
LA
12
TABP TABP TABP TABP
12
28
44* 60* BML BML
BL
BL
BM
B
–
RAR
–
–
RB
1
SB
1
A
13
LA
13
TABP TABP TABP TABP
13
45* 61* BML BML
29
BL
BL
BM
B
E
TBA
TAB
–
TV2A
RB
2
SB
2
A
14
LA
14
TABP TABP TABP TABP
14
46* 62* BML BML
30
BL
BL
BM
B
F
–
TAY SZC TV1A
RB
3
SB
3
A
15
LA
15
TABP TABP TABP TABP
BML BML
15
31
47* 63*
BL
BL
BM
B
–
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show
the low-order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The
hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only
the first word of each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below. * cannot be used at M34551M4.
The second word
BL
10 paaa
aaaa
BML
10 paaa
aaaa
BLA
10 pp00
pppp
BMLA
10 pp00
pppp
SEA
00 0111
nnnn
SZD
00 0010
1011
41
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
INSTRUCTION CODE TABLE (CONTINUED)
110000
D9–D4 100000 100001100010 100011100100 100101100110 100111101000 101001101010 101011101100 101101101110 101111
111111
Hex.
notation
20
0000
0
–
0001
1
–
0010
2
0011
D3–
D0
24
25
TW3A OP0A T1AB
–
–
–
OP1A
–
–
–
–
–
–
–
–
3
–
–
–
–
–
TAI1
0100
4
–
–
–
–
–
0101
5
–
–
–
–
0110
6
–
TMRA
–
0111
7
–
TI1A
1000
8
–
1001
9
1010
28
2F
30–3F
IAP0 TAB1 SNZT1
–
WRST
TMA TAM XAM XAMI XAMD
LXY
0
0
0
0
0
IAP1
–
SNZT2
–
–
TMA TAM XAM XAMI XAMD
LXY
1
1
1
1
1
TAMR IAP2
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
2
2
2
2
2
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
3
3
3
3
3
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
4
4
4
4
4
–
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
5
5
5
5
5
–
–
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
6
6
6
6
6
–
–
–
TAPU0
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
7
7
7
7
7
–
–
–
–
–
–
–
–
STCR TC1A
TMA TAM XAM XAMI XAMD
LXY
8
8
8
8
8
–
–
–
–
–
–
–
–
–
SPCR TC2A
TMA TAM XAM XAMI XAMD
LXY
9
9
9
9
9
A
TL1A
–
–
–
TAL1
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
10
10
10
10
10
1011
B
TL2A
–
–
–
TAW1
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
11
11
11
11
11
1100
C
–
–
–
–
TAW2
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
12
12
12
12
12
1101
D
TLCA
–
TPU0A
–
TAW3
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
13
13
13
13
13
1110
E
TW1A
–
–
–
–
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
14
14
14
14
14
1111
F
TW2A
–
–
–
–
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
15
15
15
15
15
23
27
2E
2A
22
26
2D
29
21
2B
2C
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the
low-order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The
hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the
first word of each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
The second word
10
paaa
aaaa
BML
10
paaa
aaaa
BLA
10
pp00
pppp
BL
42
BMLA
10
pp00
pppp
SEA
00
0111
nnnn
SZD
00
0010
1011
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register to register transfer
instructions
Hexadecimal
notation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS
Function
TAB
0
0
0
0
0
1
1
1
1
0
0
1
E
1
1
(A) ← (B)
TBA
0
0
0
0
0
0
1
1
1
0
0
0
E
1
1
(B) ← (A)
TAY
0
0
0
0
0
1
1
1
1
1
0
1
F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
0
1
1
0
0
0
0
C
1
1
(Y) ← (A)
TEAB
0
0
0
0
0
1
1
0
1
0
0
1
A
1
1
(E7–E4) ← (B)
(E3–E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0
2
A
1
1
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
0
0
0
0
1
0
1
0
0
1
0
2
9
1
1
(DR2–DR0) ← (A2–A0)
TAD
0
0
0
1
0
1
0
0
0
1
0
5
1
1
1
(A2–A0) ← (DR2–DR0)
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0
5
3
1
1
(A1, A0) ← (Z1, Z0)
RAM addresses
(A3, A2) ← 0
TAX
0
0
0
1
0
1
0
0
1
0
0
5
2
1
1
(A) ← (X)
TASP
0
0
0
1
0
1
0
0
0
0
0
5
0
1
1
(A2–A0) ← (SP2–SP0)
(A3) ← 0
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3
x
y
1
1
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
LZ z
0
0
0
0
4
8
1
1
(Z) ← z, z = 0 to 3
1
0
0
1
0
z1 z0
+z
INY
0
0
0
0
0
1
0
0
1
1
0
1
3
1
1
(Y) ← (Y) + 1
DEY
0
0
0
0
0
1
0
1
1
1
0
1
7
1
1
(Y) ← (Y) – 1
43
MITSUBISHI MICROCOMPUTERS
4551 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
–
–
Transfers the contents of register B to register A.
–
–
Transfers the contents of register A to register B.
–
–
Transfers the contents of register Y to register A.
–
–
Transfers the contents of register A to register Y.
–
–
Transfers the contents of registers A and B to register E.
–
–
Transfers the contents of register E to registers A and B.
–
–
Transfers the contents of register A to register D.
–
–
Transfers the contents of register D to register A.
–
–
Transfers the contents of register Z to register A.
–
–
Transfers the contents of register X to register A.
–
–
Transfers the contents of stack pointer (SP) to register A.
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register
Y.
Detailed description
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
–
–
Loads the value z in the immediate field to register Z.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
44
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
TAM j
1
0
1
1
0
0
j
j
j
j
Hexadecimal
notation
2 C
j
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Function
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2 D
j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
RAM to register transfer
j = 0 to 15
XAMD j
1
0
1
1
1
1
j
j
j
j
2 F
j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j
1
0
1
1
1
0
j
j
j
j
2 E
j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
1
0
1
0
1
1
j
j
j
j
2 B
j
1
1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
LA n
0
0
0
1
1
1
n
n
n
n
0 7
n
1
1
(A) ← n
Arithmetic operation
n = 0 to 15
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
0 8
+p
p
1
3
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(Note)
Note: p is 0 to 31 for M34551M4 and p is 0 to 63 for M34551E8.
45
MITSUBISHI MICROCOMPUTERS
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Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
Detailed description
performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
–
–
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
Continuous
–
Loads the value n in the immediate field to register A.
description
When the LA instructions are continuously coded and executed, only the first LA instruction is executed
and other LA instructions coded continuously are skipped.
–
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in
address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.
When this instruction is executed, 1 stage of stack register is used.
46
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
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Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
Hexadecimal
notation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
Function
AM
0
0
0
0
0
0
1
0
1
0
0 0 A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
0
1
0
1
1
0 0 B
1
1
(A) ← (A) + (M(DP))+ (CY)
(CY) ← Carry
An
0
0
0
1
1
0
n
n
n
n
0 6 n
1
1
(A) ← (A) + n
operation
Comparison
Bit operation
Arithmetic operation
n = 0 to 15
AND
0
0
0
0
0
1
1
0
0
0
0 1 8
1
1
(A) ← (A)AND(M(DP))
OR
0
0
0
0
0
1
1
0
0
1
0 1 9
1
1
(A) ← (A)OR(M(DP))
SC
0
0
0
0
0
0
0
1
1
1
0 0 7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
0
1
1
0
0 0 6
1
1
(CY) ← 0
SZC
0
0
0
0
1
0
1
1
1
1
0 2 F
1
1
(CY) = 0 ?
CMA
0
0
0
0
0
1
1
1
0
0
0 1 C
1
1
(A) ← (A)
RAR
0
0
0
0
0
1
1
1
0
1
0 1 D
1
1
→ CY → A3A2A1A0
SB j
0
0
0
1
0
1
1
1
j
j
0 5
C
+j
1
1
(Mj(DP)) ← 1
j = 0 to 3
RB j
0
0
0
1
0
0
1
1
j
j
0 4
C
+j
1
1
(Mj(DP)) ← 0
j = 0 to 3
SZB j
0
0
0
0
1
0
0
0
j
j
0 2
j
1
1
(Mj(DP)) = 0 ?
j = 0 to 3
SEAM
0
0
0
0
1
0
0
1
1
0
0 2
6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
0
1
0
0
1
0
1
0 2
5
2
2
(A) = n ?
n = 0 to 15
0
0
0
1
1
1
n
n
n
n
0 7
n
47
MITSUBISHI MICROCOMPUTERS
4551 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
–
–
–
Overflow = 0
Detailed description
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY
remains unchanged.
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag
CY.
–
Adds the value n in the immediate field to register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
–
–
Performs the AND operation between the contents of register A and the contents of M(DP), and stores
the result in register A.
–
–
Performs the OR operation between the contents of register A and the contents of M(DP), and stores
the result in register A.
–
1
Sets carry flag CY to “1.”
–
0
Clears carry flag CY to “0.”
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
–
–
Stores the one’s complement for register A’s contents in register A.
–
48
0/1 Rotates the contents of register A including the contents of carry flag CY to the right by 1 bit.
–
–
Sets the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to “1.”
–
–
Clears the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to “0.”
(Mj(DP)) = 0
j = 0 to 3
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field)
of M(DP) is “0.”
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
(A) = n
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Branch operation
instructions
Hexadecimal
notation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
Function
Ba
0
1
1
a6 a5 a4 a3 a2 a1 a0
1 8 a
+a
1
1
(PCL) ← a6–a0
BL p, a
0
0
1
1
0 E p
+p
2
2
(PCH) ← p
(PCL) ← a6–a0
1
p4 p3 p2 p1 p0
(Note)
BLA p
BM a
1
0
p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+a
0
0
0
0
1
0
0 1
0
1
0
p5 p4 0
0
p3 p2 p1 p0
2 p
p
0
1
0
a6 a5 a4 a3 a2 a1 a0
1 a
a
0
0
0
0
2
2
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(Note)
1
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
Subroutine operation
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
0
0
1
1
0
p4 p3 p2 p1 p0
0 C p
+p
2
2
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
BMLA p
1
0
p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+a
0
0
0
1
1
0
0 3
0
1
0
p5 p4 0
0
p3 p2 p1 p0
2 p
p
0
0
0
0
(PCL) ← a6–a0
(Note)
2
2
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
Return operation
(PCL) ← (DR2–DR0, A3–A0)
(Note)
RTI
0
0
0
1
0
0
0
1
1
0
0 4
6
1
1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
0
0
0
1
0
0
0
1
0
0
0 4
4
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
0
0
0
1
0
0
0
1
0
1
0 4
5
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Note: p is 0 to 31 for M34551M4 and p is 0 to 63 for M34551E8.
49
MITSUBISHI MICROCOMPUTERS
4551 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
–
–
Branch within a page : Branches to address a in the identical page.
–
–
Branch out of a page : Branches to address a in page p.
–
–
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and
A in page p.
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers
D and A in page p.
–
–
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous
Detailed description
description of the LA/LXY instruction, register A and register B to the states just before interrupt.
–
–
Returns from subroutine to the routine called the subroutine.
Skip unconditionally
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction unconditionally.
50
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
Hexadecimal
notation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
Function
DI
0
0
0
0
0
0
0
1
0
0
0 0
4
1
1
(INTE) ← 0
EI
0
0
0
0
0
0
0
1
0
1
0 0
5
1
1
(INTE) ← 1
SNZ0
0
0
0
0
1
1
1
0
0
0
0 3
8
1
1
(EXF0) = 1 ?
After skipping the next instruction,
Interrupt operation
(EXF0) ← 0
SNZI0
0
0
0
0
1
1
1
0
1
0
0 3
A
1
1
I12 = 1 : (INT) = “H” ?
I12 = 0 : (INT) = “L” ?
TAV1
0
0
0
1
0
1
0
1
0
0
0 5 4
1
1
(A) ← (V1)
TV1A
0
0
0
0
1
1
1
1
1
1
0 3 F
1
1
(V1) ← (A)
TAI1
1
0
0
1
0
1
0
0
1
1
2 5 3
1
1
(A) ← (I1)
TI1A
1
0
0
0
0
1
0
1
1
1
2 1 7
1
1
(I1) ← (A)
SNZT1
1
0
1
0
0
0
0
0
0
0
2 8 0
1
1
(T1F) = 1 ?
After skipping the next instruction
(T1F) ← 0
SNZT2
1
0
1
0
0
0
0
0
0
1
2 8 1
1
1
(T2F) = 1 ?
After skipping the next instruction
Timer operation
(T2F) ← 0
TAW1
1
0
0
1
0
0
1
0
1
1
2 4 B
1
1
(A) ← (W1)
TW1A
1
0
0
0
0
0
1
1
1
0
2 0 E
1
1
(W1) ← (A)
TAW2
1
0
0
1
0
0
1
1
0
0
2 4 C
1
1
(A) ← (W2)
TW2A
1
0
0
0
0
0
1
1
1
1
2 0 F
1
1
(W2) ← (A)
TAW3
1
0
0
1
0
0
1
1
0
1
2 4 D
1
1
(A1, A0) ← (W31, W30)
TW3A
1
0
0
0
0
1
0
0
0
0
2 1 0
1
1
(W31, W30) ← (A1, A0)
51
MITSUBISHI MICROCOMPUTERS
4551 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
–
–
Clears the interrupt enable flag INTE to “0,” and disables the interrupt.
–
–
Sets the interrupt enable flag INTE to “1,” and enables the interrupt.
(EXF0) = 1
–
Skips the next instruction when the contents of EXF0 flag is “1.”
After skipping, clears the EXF0 flag to “0.”
(INT) = “H”
–
When bit 2 (I12) of register I1 is “1” : Skips the next instruction when the level of INT pin is “H.”
–
When bit 2 (I12) of register I1 is “0” : Skips the next instruction when the level of INT pin is “L.”
–
–
Transfers the contents of interrupt control register V1 to register A.
–
–
Transfers the contents of register A to interrupt control register V1.
–
–
Transfers the contents of interrupt control register I1 to register A.
–
–
Transfers the contents of register A to interrupt control register I1.
(T1F) = 1
–
Skips the next instruction when the contents of T1F flag is “1.”
After skipping, clears T1F flag.
(T2F) =1
–
Skips the next instruction when the contents of T2F flag is “1.”
Detailed description
However, I12 = 1
(INT) = “L”
However, I12 = 0
After skipping, clears T2F flag.
52
–
–
Transfers the contents of timer control register W1 to register A.
–
–
Transfers the contents of register A to timer control register W1.
–
–
Transfers the contents of timer control register W2 to register A.
–
–
Transfers the contents of register A to timer control register W2.
–
–
Transfers the contents of timer control register W3 to register A.
–
–
Transfers the contents of register A to timer control register W3.
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
TAB1
1
0
0
1
1
1
0
0
0
0
Hexadecimal
notation
2 7 0
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Function
(B) ← (T17–T14)
(A) ← (T13–T10)
T1AB
1
0
0
0
1
1
0
0
0
0
2 3 0
1
1
At timer 1 stop (W20=0),
Timer operation
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
At timer 1 operating (W20=1),
(R17–R14) ← (B)
(R13–R10) ← (A)
TLCA
1
0
0
0
0
0
1
1
0
1
2 0 D
1
1
(TLC) ← (A)
Input/Output operation
(RLC) ← (A)
IAP0
1
0
0
1
1
0
0
0
0
0
2 6 0
1
1
(A) ← (P0)
OP0A
1
0
0
0
1
0
0
0
0
0
2 2 0
1
1
(P0) ← (A)
IAP1
1
0
0
1
1
0
0
0
0
1
2 6 1
1
1
(A) ← (P1)
OP1A
1
0
0
0
1
0
0
0
0
1
2 2 1
1
1
(P1) ← (A)
IAP2
1
0
0
1
1
0
0
0
1
0
2 6 2
1
1
(A) ← (P2)
CLD
0
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 1
RD
0
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 9
SD
0
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 9
TPU0A
1
0
0
0
1
0
1
1
0
1
2 2 D
1
1
(PU0) ← (A)
TAPU0
1
0
0
1
0
1
0
1
1
1
2 5 7
1
1
(A) ← (PU0)
53
MITSUBISHI MICROCOMPUTERS
4551 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
–
–
–
–
Detailed description
Transfers the contents of timer 1 to registers A and B.
When stopping (W20=0), transfers the contents of registers A and B to timer 1 and timer 1 reload
register.
When operating (W20=1), transfers the contents of registers A and B only to timer 1 reload register.
54
–
–
Transfers the contents of register A to timer LC and timer LC reload register.
–
–
Transfers the input of port P0 to register A.
–
–
Outputs the contents of register A to port P0.
–
–
Transfers the input of port P1 to register A.
–
–
Outputs the contents of register A to port P1.
–
–
Transfers the input of port P2 to register A.
–
–
Sets port D to “1.”
–
–
Clears a bit of port D specified by register Y to “0.”
–
–
Sets a bit of port D specified by register Y to “1.”
–
–
Transfers the contents of register A to pull-up control register PU0.
–
–
Transfers the contents of pull-up control register PU0 to register A.
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Other operation
Carrier generating circuit
operation
LCD control
operation
instructions
Hexadecimal
notation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
Function
TL1A
1
0
0
0
0
0
1
0
1
0
2 0 A
1
1
(L1) ← (A)
TAL1
1
0
0
1
0
0
1
0
1
0
2 4 A
1
1
(A) ← (L1)
TL2A
1
0
0
0
0
0
1
0
1
1
2 0 B
1
1
(L2) ← (A)
TC1A
1
0
1
0
1
0
1
0
0
0
2 A 8
1
1
(C1) ← (A)
STCR
1
0
1
0
0
1
1
0
0
0
2 9 8
1
1
Carrier wave generating start
SPCR
1
0
1
0
0
1
1
0
0
1
2 9 9
1
1
Carrier wave generating stop
TC2A
1
0
1
0
1
0
1
0
0
1
2 A 9
1
1
(C20) ← (A0)
NOP
0
0
0
0
0
0
0
0
0
0
0 0 0
1
1
(PC) ← (PC) + 1
POF
0
0
0
0
0
0
0
0
1
0
0 0 2
1
1
Transition to clock operating mode
POF2
0
0
0
0
0
0
1
0
0
0
0 0 8
1
1
Transition to RAM back-up mode
EPOF
0
0
0
1
0
1
1
0
1
1
5 B
1
1
Power down instruction (POF, POF2) valid
SNZP
0
0
0
0
0
0
0
0
1
1
0 0 3
1
1
(P) = 1 ?
WRST
1
0
1
0
1
0
0
0
0
0
2 A 0
1
1
(WDF) ← 0, (WEF) ← 1
TAMR
1
0
0
1
0
1
0
0
1
0
2 5 2
1
1
(A) ← (MR)
TMRA
1
0
0
0
0
1
0
1
1
0
2 1 6
1
1
(MR) ← (A)
TAV2
0
0
0
1
0
1
0
1
0
1
0 5 5
1
1
(A) ← (V2)
TV2A
0
0
0
0
1
1
1
1
1
0
0 3 E
1
1
(V2) ← (A)
0
55
MITSUBISHI MICROCOMPUTERS
4551 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
–
–
Transfers the contents of register A to LCD control register L1.
–
–
Transfers the contents of register L1 to register A.
–
–
Transfers the contents of register A to LCD control register L2.
–
–
Transfers the contents of register A to carrier wave selection register C1.
–
–
Starts generating carrier wave.
–
–
Stops generating carrier wave.
–
–
Transfers the contents of register A to carrier wave output control register C2.
–
–
No operation
–
–
Puts the system in clock operating mode state by executing the POF instruction after executing the
EPOF instruction.
Detailed description
f(XCIN) oscillation, LCD, timer LC and timer 2 are operated.
–
–
Puts the system in RAM back-up mode state by executing the POF2 instruction after executing the
EPOF instruction.
Oscillation is stopped.
–
–
Validates the power down instruction (POF, POF2) which is executed after the EPOF instruction by
executing the EPOF instruction.
(P) = 1
–
Skips the next instruction when P flag is “1.”
After skipping, P flag remains unchanged.
56
–
–
Operates the watchdog timer and initializes the watchdog timer flag (WDF).
–
–
Transfers the contents of clock control register MR to register A.
–
–
Transfers the contents of register A to clock control register MR.
–
–
Transfers the contents of general-purpose register V2 to register A.
–
–
Transfers the contents of register A to general-purpose register V2.
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
SYMBOL
The symbols shown below are used in the following list of instruction function and machine instructions.
Contents
Symbol
A
B
Register A (4 bits)
DR
Register D (3 bits)
Register E (8 bits)
E
V1
V2
I1
W1
W2
W3
C1
C2
CR
L1
L2
PU0
MR
X
Y
Z
Register B (4 bits)
General-purpose register V2 (4 bits)
Interrupt control register I1 (4 bits)
Timer control register W1 (4 bits)
R2
RLC
STCK
INSTK
T1
T2
TLC
External 0 interrupt request flag
Power down flag
D
P0
P1
Port D (8 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (4 bits)
Carrier wave selection register C1 (4 bits)
x
Hexadecimal variable
Carrier wave output control register C2 (1 bit)
Carrier wave generating control flag
y
Hexadecimal variable
Hexadecimal variable
LCD control regiser L1
z
p
Hexadecimal variable
LCD control register L2
Pull-up control register PU0 (4 bits)
n
Hexadecimal constant which represents the
immediate value
Clock control register MR (4 bits)
i
Hexadecimal constant which represents the
Register X (4 bits)
Register Y (4 bits)
j
immediate value
Hexadecimal constant which represents the
Register Z (2 bits)
Program counter (14 bits)
High-order 7 bits of program counter
CY
R1
P
Interrupt enable flag
P2
PC
SP
EXF0
Timer control register W2 (4 bits)
Timer control register W3 (2 bits)
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
PCL
SK
WDF
INTE
Contents
Watchdog timer flag
Interrupt control register V1 (4 bits)
DP
PCH
Symbol
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
Stack pointer (3 bits)
immediate value
A 3A 2A 1A 0
Binary notation of hexadecimal variable A
(same for others)
←
Direction of data movement
↔
?
Data exchange between a register and memory
( )
Decision of state shown before “?”
Contents of registers and memories
Carry flag
—
Negate, Flag unchanged after executing
Timer 1 reload register
Timer 2 reload register
M(DP)
instruction
RAM address pointed by the data pointer
Timer LC reload register
System clock
Instruction clock
Timer 1
Timer 2
Timer LC
a
p, a
Label indicating address a6 a5 a4 a3 a2 a1 a0
C
+
Hex. C + Hex. number x (also same for others)
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p5 p4 p3 p2 p1 p0
x
Timer 1 interrupt request flag
T1F
Timer 2 interrupt request flag
T2F
Note : The 4551 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not
increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count
becomes “1” if the TABP p, RT, or RTS instruction is skipped.
57
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
0
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
0
1
This bit has no function, but read/write is enabled.
0
Prescaler control bit
W12
Prescaler dividing ratio selection bit
at reset : 00002
at power down : 00002
0
Stop (prescaler state initialized)
1
Operating
0
1
Instruction clock (INSTCK) divided by 4
Instruction clock (INSTCK) divided by 8
Timer 1 count source selection bits
W10
0
0
0
1
1
0
1
1
W23
Prescaler output (ORCLK)
Carrier output (CARRY)
Carrier output divided by 2 (CARRY/2)
at reset : 10002
Timer control register W2
Timer 2 count source selection bit
f(XCIN)
1
Prescaler output (ORCLK)
0
Timer 2 count value selection bits
W20
0
1
1
W21
Timer 1 control bit
0
1
Timer LC count source selection bit
Underflow occur every 214 count
Underflow occur every 213 count
0
Not available
1
Not available
Stop (timer 1 state retained)
Operating
at power down : state retained
R/W
0
Bit 3 of timer 2 is output (timer 2 count source divided by 16)
1
State clock (STCK)
0
Stop (timer LC state retained)
Timer LC control bit
W30
1
Operating
Note: “R” represents read enabled, and “W” represents write enabled.
“–” represents state retained.
58
R/W
Count source
0
1
at reset : 002
Timer control register W3
W31
at power down : – – – 02
0
W22 W21
W22
R/W
Count source
W11 W10
W11
R/W
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
1
Timer control register W1
W13
at power down : 00002
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
CONTROL REGISTERS (CONTINUED)
Interrupt control register I1
I13
I12
Not used
at reset : 00002
0
1
R/W
This bit has no function, but read/write is enabled.
0
Falling waveform (“L” level of INT pin is recognized with the SNZI0
1
instruction)
Rising waveform (“H” level of INT pin is recognized with the SNZI0
Interrupt valid waveform for INT pin
selection bit (Note 2)
at power down : state retained
instruction)
I11
Not used
I10
Not used
0
1
0
1
Pull-up control register PU0
PU03
PU02
PU01
PU00
Port P13 pull-up transistor
0
1
0
Port P11 pull-up transistor
control bit
Port P10 pull-up transistor
control bit
1
0
1
0
1
Clock control register MR
System clock (STCK) selection bit
1
MR2
f(XCIN) oscillation circuit control bit
MR1
f(XIN) oscillation circuit control bit
0
1
0
1
at power down : state retained
R/W
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
at reset : 10002
0
MR3
This bit has no function, but read/write is enabled.
at reset : 00002
control bit
Port P12 pull-up transistor
control bit
This bit has no function, but read/write is enabled.
at power down : state retained
R/W
MR0=0 f(XIN)
MR0=1 f(XCIN)
MR0=0 f(XIN)/4
MR0=1 f(XCIN)/4
f(XCIN) oscillation stop, ports D6 and D7 selected
f(XCIN) oscillation enabled, ports D6 and D7 not selected
Oscillation enabled
Oscillation stop
f(XIN)
0
f(XCIN)
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Depending on the input state of D5/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents of
I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after
executing at least one instruction.
MR0
Clock selection bit
59
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
CONTROL REGISTERS (CONTINUED)
Carrier wave selection register C1
at reset : 01112
C13 C12 C11 C10
Carrier wave selection bits
Carrier wave output auto-control bit
0
0
STCK/24
1/3
0
0
0
0
0
1
1
0
STCK/24
STCK/16
1/2
1/4
0
0
1
1
STCK/16
1/2
0
0
1
1
0
0
0
1
STCK/2
No carrier wave
1/2
0
1
1
0
Not available
0
1
1
0
1
0
1
0
“L” fixed
STCK/12
1/3
1
0
0
1
STCK/12
1/2
1
1
0
0
1
1
0
1
STCK/8
STCK/8
1/4
1/2
1
1
0
0
STCK
1/2
1
1
1
1
0
1
1
0
No carrier wave
Not available
1
1
1
1
“L” fixed
at reset : 02
Carrier wave generating control
Note: “W” represents write enabled.
60
at power down : 02
0
Auto-control output by timer 1 is invalid
1
Auto-control output by timer 1 is valid
at reset : 02
0
1
W
Duty
0
Carrier wave generating control flag CR
CR
Carrier wave frequency
0
Carrier wave output control register C2
C20
at power down : 01112
at power down : 02
Carrier wave generating stop (SPCR instruction)
Carrier wave generating start (STCR instruction)
W
W
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
CONTROL REGISTERS (CONTINUED)
at reset : 00002
LCD control register L1
L13
Not used
L12
LCD on/off bit
L11
LCD duty and bias selection bits
0
L23
P23/SEG19 pin function switch bit
L22
P22/SEG18 pin function switch bit
L21
P21/SEG17 pin function switch bit
L20
P20/SEG16 pin function switch bit
General-purpose register V2
Off
On
1
Duty
Bias
L11
L10
0
0
0
1
0
1/2
1/3
1/2
1/3
1
1/4
1/3
Not available
at reset : 11112
LCD control register L2
R/W
This bit has no function, but read/write is enabled
1
0
1
1
L10
at power down : state retained
0
1
SEG19
P23
0
SEG18
1
0
P22
SEG17
1
P21
0
1
SEG16
P20
at reset : 00002
at power down : state retained
W
at power down : 00002
R/W
4-bit general-purpose register.
The data transfer between register A and this register is performed with the TV2A and TAV2 instructions.
Note: “R” represents read enabled, and “W” represents write enabled.
61
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VI
VO
VO
VO
Pd
Topr
Tstg
Conditions
Parameter
Supply voltage
Input voltage P0, P1, P2, RESET, XIN, XCIN
Output voltage P0, P1, D
Output transistors in cut-off state
Output voltage CARR, XOUT, XCOUT
Output voltage SEG, COM
Power dissipation
Operating temperature range
Storage temperature range
Ratings
Unit
–0.3 to 7.0
–0.3 to VDD+0.3
V
V
–0.3 to VDD+0.3
V
–0.3 to VDD+0.3
–0.3 to VDD+0.3
V
V
300
mW
–20 to 70
–40 to 125
°C
°C
RECOMMENDED OPERATING CONDITIONS
(Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Symbol
Parameter
Mask ROM version
Conditions
f(XIN) ≤ 4.0 MHz, ceramic resonator,
STCK=f(XIN)/4
f(XIN) ≤ 1.0 MHz, ceramic resonator,
Limits
Min.
Typ.
Max.
Unit
2.2
5.5
2.5
5.5
4.5
5.5
2.0
5.5
V
STCK=f(XIN)
f(XIN) ≤ 4.0 MHz, ceramic resonator,
VDD
Supply voltage One Time PROM version
STCK=f(XIN)/4
f(XIN) ≤ 1.0 MHz, ceramic resonator,
STCK=f(XIN)
V
f(XIN) ≤ 8.0 MHz, ceramic resonator,
STCK=f(XIN)/4
f(XIN) ≤ 2.0 MHz, ceramic resonator,
STCK=f(XIN)
VRAM
VSS
RAM back-up voltage
VIH
“H” level input voltage P0, P1, P2
“H” level input voltage XIN
VIH
VIH
VIH
VIL
VIL
VIL
RAM back-up
Supply voltage
“H” level input voltage RESET
“H” level input voltage INT
“L” level input voltage P0, P1, P2
“L” level input voltage XIN
“L” level input voltage RESET
“L” level input voltage INT
VIL
IOL(peak) “L” level peak output current
P0, P1, D0–D7, CARR
IOL(avg) “L” level average output current
P0, P1, D0–D7, CARR (Note)
IOH(peak) “H” level peak output current
CARR
IOH(avg) “H” level average output current
CARR (Note)
f(XCIN) clock frequency
f(XCIN)
0.8VDD
VDD
V
V
0.7VDD
VDD
V
0.85VDD
0.8VDD
VDD
VDD
V
V
0
0.3VDD
V
0
0
0.3VDD
0.3VDD
V
V
0
0.2VDD
V
10
4
mA
0
VDD=5.0 V
VDD=3.0 V
VDD=5.0 V
VDD=3.0 V
5
VDD=5.0 V
–30
VDD=3.0 V
VDD=5.0 V
–15
VDD=3.0 V
mA
–15
–7
Quarts-crystal oscillator
32
VDD = 0 to 2.2 V
Valid power supply rising time for Mask ROM version
TPON
One Time PROM version VDD = 0 to 2.5 V
power-on reset circuit
Note: The average output current is the average current value at the 100 ms interval.
62
mA
2
mA
50
kHz
100
µs
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
ELECTRICAL CHARACTERISTICS
(Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Typ.
Max.
“L” level output voltage
IOL = 5 mA
VDD = 5.0 V
0.9
P0, P1, D0–D7, CARR, RESET
IOL = 2 mA
VDD = 3.0 V
0.9
VOH
“H” level output voltage CARR
IOH = –15 mA
IOH = –7 mA
VDD = 5.0 V
VDD = 3.0 V
IIH
IIL
“H” level input current P0, P1, P2, RESET
“L” level input current P1, P2
IOZ
Output current at off-state D0–D7
VOL
2.4
1.0
1
–1
1
VDD = 5.0 V, f(XCIN) = 32 kHz, f(XIN) = 8 MHz
2.5
5.0
2.3
4.6
f(XIN) = 1 MHz
STCK = f(XIN)
VDD = 3.0 V, f(XCIN) = 32 kHz, f(XIN) = 4 MHz
1.4
2.8
STCK = f(XIN)/4
0.7
1.4
STCK = f(XIN)/4
VDD = 5.0 V
f(XIN) = 2 MHz
V
V
VI = VDD (Note 1)
VI = 0 V (Note 1)
VO = VDD
Unit
µA
µA
µA
f(XCIN) = 32 kHz
at active high-speed mode
while LCD is operating
IDD
Supply current
(Note 2)
at active low-speed mode
while LCD is operating
at clock operating mode
while LCD is operating
at RAM back-up mode
P0, P1
RPH
Pull-up resistor
value
RESET
INT
VT+ – VT– Hysteresis
RESET
VDD = 3.0 V
f(XCIN) = 32 kHz
f(XIN) = 1 MHz
0.6
1.2
STCK = f(XIN)
f(XIN) = 500 kHz
0.4
0.8
VDD = 5.0 V
f(XIN) = stop
STCK = f(XCIN)/4
60
140
STCK = f(XCIN)
75
180
VDD = 3.0 V
f(XIN) = stop
STCK = f(XCIN)/4
25
60
f(XCIN) = 32 kHz
STCK = f(XCIN)
30
80
f(XIN) = stop
f(XCIN) = 32 kHz
VDD = 5.0 V
27.5
60
Ta=25 °C
VDD = 3.0 V
10
17.5
f(XIN) = stop
f(XCIN) = 32 kHz
VDD = 5.0 V
f(XCIN) = 32 kHz
µA
COM output impedance
RSEG
SEG output impedance
LCD power supply internal resistor value
0.1
f(XIN) = stop, f(XCIN) = stop
VDD = 5.0 V, VI = 0 V
20
VDD = 3.0 V, VI = 0 V
40
VDD = 5.0 V, VI = 0 V
VDD = 3.0 V, VI = 0 V
12
25
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
Impedance between VLC3 and VSS
µA
65
20
VDD = 3.0 V
f(XIN) = stop, f(XCIN) = stop, Ta = 25 °C
VDD = 3.0 V
RCOM
mA
50
100
30
60
0.5
1.0
10
125
250
70
130
1.5
0.6
1.6
1.8
2.2
kΩ
kΩ
V
0.4
1.3
µA
V
6.5
8
9
11
kΩ
kΩ
600 1200 kΩ
300
Ta=25 °C
(Note 3)
Notes 1: In this case, the pull-up transistor of port P1 is turned off and the port P2 function is selected by software.
2: The current value includes the current dissipation of the LCD power supply internal resistor (RVLC).
3: VLC3=VDD.
RVLC
63
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
BASIC TIMING DIAGRAM
Machine cycle
Mi
Parameter
Pin name
System clock
STCK
Port D output
D0–D7
Ports P0, P1 output
P00–P03
P10–P13
Ports P0, P1 and
P2 input
P00–P03
P10–P13
P20–P23
Interrupt input
INT
64
Mi+1
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
BUILT-IN PROM VERSION
Table 20 shows the product of built-in PROM version. Figure 41
shows the pin configurations of built-in PROM version. The One
Time PROM version has pin-compatibility with the mask ROM
version.
In addition to the mask ROM version, the 4551 Group has the
programmable ROM version software compatible with mask
ROM. The One Time PROM version has PROM which can only
be written to and not be erased.
The built-in PROM version has functions similar to those of the
mask ROM version, but it has a PROM mode that enables writing
to built-in PROM.
Table 20 Product of built-in PROM version
Product
PROM size
RAM size
(✕ 10 bits)
(✕ 4 bits)
ROM type
Package
M34551E8-XXXFP
8192 words
280 words
One Time PROM [shipped after writing]
(shipped after writing and test in factory)
48P6S-A
One Time PROM [shipped in blank]
M34551E8FP
RESET
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
PIN CONFIGURATION (TOP VIEW)
38 37 36 35 34 33 32 31 30 29 28 27 26 25
SEG9
39
24
D7/XCOUT
SEG10
40
23
D6/XCIN
SEG11
41
22
CNVSS
SEG12
42
21
XOUT
VSS
43
20
XIN
SEG13
44
19
VSS
SEG14
45
18
VDD
SEG15
46
17
CARR
P20 / SEG16
47
16
D5 / INT
P21 / SEG17
48
15
D4
10 11 12 13 14
D3
P02
9
D2
P01
8
D1
P00
7
D0
P23 / SEG19
6
P13
5
P12
4
P11
3
P10
2
P03
1
P22 / SEG18
M34551E8-XXXFP
Outline 48P6S-A
Fig. 41 Pin configuration of built-in PROM version
65
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
(1) PROM mode
The built-in PROM version has a PROM mode in addition to
a normal operation mode. The PROM mode is used to write
to and read from the built-in PROM.
In the PROM mode, the programming adapter can be used
with a general-purpose PROM programmer to write to or read
from the built-in PROM as if it were M5M27C256K.
Programming adapter is listed in Table 21. Contact addresses
at the end of this book for the appropriate PROM programmer.
• Writing and reading of built-in PROM
Programming voltage is 12.5 V. Write the program in the
PROM of the built-in PROM version as shown in Figure
42.
(2) Notes on handling
➀ A high-voltage is used for writing. Take care that
overvoltage is not applied. Take care especially at turning
on the power.
➁ For the One Time PROM version shipped in blank,
Mitsubishi Electric corp. does not perform PROM writing
test and screening in the assembly process and following
processes. In order to improve reliability after writing,
performing writing and test according to the flow shown in
Figure 43 before using is recommended.
Table 21 Programming adapter
Microcomputer
M34551E8-XXXFP, M34551E8FP
Address
000016
1
1
1
D4 D3
D2
D1
D0
Low-order 5 bits
1FFF16
400016
Programming adapter
PCA7414
1
1
1
D4 D3
D2
D1
D0
High-order 5 bits
5FFF16
7FFF16
Set “FF16” to the shaded area.
Fig. 42 PROM memory map
(Products shipped in blank: PROM contents is not written in
factory when shipped)
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device
Note: Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150°C exceeding 100
hours.
Fig. 43 Flow of writing and test of the product shipped in
blank
66
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Notes regarding these materials
•
•
•
•
•
•
© 1997 MITSUBISHI ELECTRIC CORP.
KI-9711 Printed in Japan (ROD) II
New publication, effective Nov. 1997.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
1.0
4551 GROUP DATA SHEET
Revision Description
First Edition
Rev.
date
971130
(1/1)
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