MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER DESCRIPTION/FEATURES • • • Serial I/O ..................................... 3 (CS controller, external clock) High-breakdown-voltage output port ......................................... 25 • Segment output ............................................ 8 to 20 • Digit output ................................................... 5 to 16 (Ports P0 to P2 are also used as normal output ports) • Output breakdown .................................. Vcc – 45 V • Output current ............... –18 mA (at DIG selecting), –7 mA (at SEG selecting) • Pull-down resistor .........................................built-in • Dimmer switch ............................................ 4 levels A-D converter ................................................... 8-bit ✕ 4 channels • Absolute accuracy ....................................... ±3 LSB • • • • Noise filter ..................................................... built-in (in serial input pin and clock pin, 2 MHz sampling) • FLD display data ............................................. input • A-D conversion data ..................................... output • Command ....................................................... input Package ......................................................................... 36P2R-G Oscillation circuit ........... CR oscillation cirucit (external capacitor) • Oscillation frequency..................................... 2 MHz Power source voltage .................................................. 4.0 to 5.5 V FLD0 FLD1 FLD2 FLD3 FLD4 FLD5 FLD6 FLD7 FLD8 FLD9 FLD10 FLD11 FLD12 FLD13 FLD14 FLD15 FLD16 VEE 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 PIN CONFIGURATION (TOP VIEW) 15 16 17 18 FLD19 FLD18 FLD17 13 FLD22/P2 14 12 FLD23/P1 FLD21 11 FLD20 10 VCC FLD24/P0 9 7 AN0 8 6 AN1 VSS 5 OSC 4 3 CS AN3 2 SCLK AN2 1 SDATA M35502AFP Package type: 36P2R-G Fig.1 Pin configuration of M35502AFP MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER FUNCTIONAL BLOCK FLD15–FLD8 FLD7–FLD0 21 22 23 24 25 26 27 28 VEE 29 30 31 32 33 34 35 36 19 FLD16 20 FLD17 18 FLD18 17 FLD19 16 FLD20 15 Mode register FLD21 14 Display control circuit FLD22/P2 13 Memory address FLD23/P1 12 FLD24/P0 11 Display RAM Transfer counter Command analytic circuit SDATA 1 Noise filter SCLK 2 Noise filter Byte end Serial I/O CS 3 Trigger VCC 10 VSS 8 Clock generating circuit 9 OSC Fig.2 Functional block diagram 2 Selector /A-D control circuit 4 5 6 AN3–AN0 7 A-D MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER PIN DESCRIPTION Table 1 Pin description Pin Name Input Output Function VCC, VSS Power source • Apply voltage of 5 V to V CC, and 0 V to VSS. VEE Pull-down power source • Applies voltage supplied to pull-down resistors. OSC Clock input Input • Connect an external capacitor to this pin. CS Chip select CMOS input • Serial transfer is possible by inputting “L” signal. • Pull-up resistor is built in. SCLK Serial clock CMOS input Noise filter • Clock for serial transfer is input. • Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not. SDATA Serial input/ output CMOS input N-channel Noise filter open-drain • Serial data is input/output. • In input mode, read a clock twice with 2 MHz sampling clock and judge if it is a noise or not. FLD24/P0 – FLD22/P2 Digit/Port P-channel open-drain • Pin for ordinary output or digit output. • At reset this por t is set to VEE level through a pull-down resistor. FLD21– FLD0 Segment/Digit P-channel open-drain • Pin for digit output or segment output. • At reset this por t is set to VEE level through a pull-down resistor. ____ PORT BLOCK (1) Digit/Port pin (3) SDATA pin Dimmer signal (Note) Data bus Digit data Serial output Latch ✽ VEE (2) Segmen/Digit pin Noise filter (4) CS pin CS input Dimmer signal (Note) Segment/Digit data Serial input (5) SCLK pin Latch ✽ Serial clock input Noise filter VEE (6) A-D input A-D conversion input ✽ High-breakdown-voltage P-channel transistor Not e : Dimmer signal is for setting the Toff time. Fig.3 Port block diagram 3 MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER COMMAND STYLE Display data setting (Command 0) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 a4 a3 a2 a1 a0 Digit start pin setting 0 0 0 0 : FLD18 0 0 0 1 : FLD17 0 0 1 0 : FLD16 0 0 1 1 : FLD15 0 1 0 0 : FLD14 0 1 0 1 : FLD13 0 1 1 0 : FLD12 0 1 1 1 : FLD11 1 0 0 0 : FLD10 1 0 0 1 : FLD9 1 0 1 0 : FLD8 Serial data transfer setting 1 : 3-byte transfer 0 : 4-byte transfer Display state setting (Command 1) 1 1 0 M4 M3 M2 M1 M0 Display ON or OFF setting 1 : ON 0 : OFF Display duty setting 1 1 : 15/16 1 0 : 6/16 0 1 : 4/16 0 0 : 3/16 DIG/PORT switch setting (Note ) 0 0 : P0 output of command 3 valid 0 1 : P0, P1 output of command 3 valid 1 0 : P0, P1, P2 output of command 3 valid 1 1 : All port is set as DIG. Number of timing selecting (Command 2) 1 0 1 – T3 T2 T1 T0 Number of timing setting 0 0 0 0 : T16 0 0 0 1 : T15 0 0 1 0 : T14 0 0 1 1 : T13 0 1 0 0 : T12 0 1 0 1 : T11 0 1 1 0 : T10 0 1 1 1 : T9 1 0 0 0 : T8 1 0 0 1 : T7 1 0 1 0 : T6 1 0 1 1 : T5 Port data setting (Command 3) 1 0 0 – – p2 p1 p0 P2–P0 output data N ote : DIG/PORT switch setting becomes valid when command 3 (port data setting) is accepted. When command 3 is not used, set “112” to these bits. Fig.4 Command style 4 MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER SERIAL I/O PROTOCOL Byte protocol CS CLK SDATA(input) b0 b1 b2 b3 b4 b5 b6 b7 SDATA(output) b0 b1 b2 b3 b4 b5 b6 b7 Note: SDATA is in high-impedance state during CS signal is “H”. Command protocol Display data setting (Command 0) CS CLK SDATA(input) Command 0 Data 1 Data 2 Data i Notes 1: The serial data which is transmitted after executing command 0 is recognized as a display data. 2: Set the CS signal to “H” level after transferring a display data. Other setting except display data setting (Command 1 to 3) CS CLK SDATA(input) Command Fig.5 Serial I/O protocol 5 MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER SERIAL COMMUNICATION FORMAT (DISPLAY DATA, A-D OUTPUT) When using 25 high-breakdown-voltage ports (segment + grid) (4-byte transfer) CS CLK SDATA X AD 0 AD 1 AD 2 AD 3 C om m and 0 FLD 0-7 FLD FLD 8-15 16-23 FLD FLD 24 16-23 Tn AD valid data FLD 24 FLD 0-7 FLD FLD 8-15 16-23 T2 Output mode FLD 24 T1 Input mode The SDATA pin becoms output mode from after the CS pin falling until the 5th byte of serial data. The SDATA becomes command input mode from the 6th byte of serial data. When using 24 high-breakdown-voltage ports (segment + grid) (3-byte transfer) CS CLK SDATA X AD 0 AD 1 AD 2 AD 3 C om m and 0 FLD 0-7 AD valid data FLD FLD 8-15 16-23 Tn FLD 0-7 FLD 0-7 Tn-1 FLD FLD 8-15 16-23 FLD 0-7 FLD FLD 8-15 16-23 T1 T2 Input mode Output mode The SDATA pin becoms output mode from after the CS pin falling until the 5th byte of serial data. The SDATA becomes command input mode from the 6th byte of serial data. When using 16 high-breakdown-voltage ports (segment + grid) or less (3-byte transfer) CS CLK SDATA X AD 0 AD 1 AD 2 AD valid data Output mode AD 3 C om m and 0 FLD 0-7 FLD 8-15 Tn Dummy data FLD 0-7 FLD 0-7 Tn-1 FLD 8-15 T2 Dummy data FLD 0-7 FLD 8-15 Dummy data T1 Input mode Transfer dummy data to the third byte of each timing. The SDATA pin becoms output mode from after the CS pin falling until the 5th byte of serial data. The SDATA becomes command input mode from the 6th byte of serial data. Fig.6 Serial communication format 6 MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER FLD DISPLAY TIMING Gn Tn Tn-1 T1 Tn Tn-1 Gn-1 G1 Segment output Tscan=0ns Tdisp Digit Tdisp = 384 µs (oscillation frequency f(OSC) = 2.0 MHz) Toff = 312 µs (3/16 ✕ Tdisp) 288 µs (4/16 ✕ Tdisp) 240 µs (6/16 ✕ Tdisp) 24 µs (15/16 ✕ Tdisp) Segment Toff Tdisp Fig.7 FLD display timing diagram SEGMENT/DIGIT SETTING EXAMPLE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PORT FLD P2 P1 P0 FLD0 FLD1 FLD2 FLD3 FLD4 FLD5 FLD6 FLD7 FLD8 FLD9 FLD10 FLD11 FLD12 FLD13 FLD14 FLD15 FLD16 FLD17 FLD18 FLD19 FLD20 FLD21 FLD22 FLD23 FLD24 Grid: 5 S egm ent: 8 Grid: 7 Grid: 10 S egm ent: 8 S egm ent: 8 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 GRID5 GRID4 GRID3 GRID2 GRID1 SEG1 SEG1 SEG2 SEG2 SEG3 SEG3 SEG4 SEG4 SEG5 SEG5 SEG6 SEG6 SEG7 SEG7 SEG8 SEG8 GRID7 GRID10 GRID6 GRID9 GRID5 GRID8 GRID4 GRID7 GRID3 GRID6 GRID2 GRID5 GRID1 GRID4 GRID3 GRID2 GRID1 Grid: 7 Segm ent:18 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 GRID7 GRID6 GRID5 GRID4 GRID3 GRID2 GRID1 Fig.8 Segment/Digit setting example 7 MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER BIT ALLOCATION FOR DISPLAY RAM ADDRESS b7 b0 0016 0116 0216 0316 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 18 FLD 10 FLD 2 FLD 17 FLD 9 FLD 1 0416 0516 0616 0716 FLD FLD FLD FLD FLD 23 22 21 20 19 FLD FLD FLD FLD FLD 15 14 13 12 11 FLD FLD FLD FLD FLD 7 6 5 4 3 0816 0916 0A16 0B16 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD FLD FLD FLD 23 22 21 20 FLD FLD FLD FLD 15 14 13 12 FLD FLD FLD FLD 4 7 6 5 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 FLD 11 FLD 3 1816 1916 1A16 1B16 FLD FLD FLD 23 22 21 FLD FLD FLD 15 14 13 FLD FLD FLD 7 6 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 1C16 1D16 1E16 1F16 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 Fig.9 Bit allocation for display RAM 8 FLD FLD 18 17 FLD 24 FLD 16 FLD 8 FLD 0 FLD 24 FLD 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 0 2 1 b0 b7 2016 2116 T1 2216 2316 FLD 17 FLD 9 FLD 1 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 18 FLD 10 FLD 2 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD FLD 18 17 FLD FLD 10 9 FLD FLD 2 1 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD FLD 18 17 FLD FLD 10 9 FLD FLD 2 1 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD FLD 18 17 FLD FLD 10 9 FLD FLD 2 1 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 2416 2516 T2 2616 2716 2816 2916 T3 2A16 2B16 2C16 2D16 T4 2E16 2F16 3016 3116 T5 3216 3316 3416 3516 T6 3616 3716 3816 3916 T7 3A16 3B16 3C16 3D16 T8 3E16 3F16 FLD 24 FLD 16 FLD 8 FLD 0 FLD 24 FLD 16 FLD 8 FLD 0 FLD 24 FLD 16 FLD 8 FLD 0 FLD 24 FLD 16 FLD 8 FLD 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 T9 T10 T11 T12 T13 T14 T15 T16 MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER CLOCK GENERATING CIRCUIT Oscillating circuit is built up by connecting a capacitor between pins OSC and VSS. When supplying a clock externally, input it to the OSC pin. OSC OSC External oscillation circuit COSC VCC VSS Fig.10 CR generating circuit Fig.11 External clock input circuit HANDLING OF UNUSED PINS Handle unused pins as the follow. Table 2 Handling of unused pins Pin Handling Segment Open Digit Open Analog input Connect to VCC or VSS through a resistor. POWER-ON RESET Reset can be performed automatically during power on (power-on reset) by the built-in power-on reset circuit. VDD Reset state Internal reset signal Poweron Reset released Fig.12 Power-on reset 9 MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER ABSOLUTE MAXIMUM RATINGS Symbol VCC VEE VI VI VO Parameter Power source voltage Pull-down power source voltage Input voltage AN0 – AN3 __ Input voltage CS, SDATA, SCLK Output voltage FLD0 – FLD24 VO Output voltage Pd Topr Tstg Power dissipation Operating temperature Storage temperature • All voltage are based on VSS. • Output transistors are cut off. • A waveform: 450 µs or more frequency and 30 µs or less pulse width. • Connect only capacitor load (CL = 200pF). • All voltage are based on VSS. • Output transistors are cut off. Ta = 25 °C SDATA RECOMMENDED OPERATING CONDITIONS Symbol VCC VSS VEE VIH VIL ΣIOH(peak) ΣIOH(avg) IOH(peak) IOH(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) f(OSC) f(SCLK) Unit –0.3 to 6.5 VCC–45 to VCC+0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 VCC–45 to VCC+0.3 VCC–50 to VCC+0.3 V V V V V –0.3 to VCC +0.3 V 600 –20 to 85 –40 to 125 mW °C °C (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Parameter Min. 4.0 Power source voltage Power source voltage Pull-down power source voltage __ “H” input voltage CS, SCLK, SDATA __ “L” input voltage CS, SCLK, SDATA RECOMMENDED OPERATING CONDITIONS Symbol Ratings Conditions Limits Typ. 5.0 0 VCC –38 0.75VCC 0 Max. 5.5 VCC VCC 0.25VCC Unit V V V V V (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Parameter “H” total peak output current FLD0 – FLD24 “H” total average output current FLD0 – FLD24 “H” peak output current FLD0 – FLD24 (at DIG selecting) “H” peak output current FLD0 – FLD24 (at SEG selecting) “L” peak output current SDATA “H” peak output current FLD0 – FLD24 (at DIG selecting) “H” average output current FLD0 – FLD24 (at SEG selecting) “L” average output current SDATA Clock input oscillation frequency Serial I/O external clock frequency Min. Limits Typ. (Note 1) (Note 2) (Note 2) (Note 3) (Note 3) (Note 4) 1.4 2.0 250 Max. –240 –120 –40 –20 10 –18 –7 5.0 2.6 Unit mA mA mA mA mA mA mA mA MHz kHz Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: When the oscillation frequency has a 50 % duty cycle. 10 MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER ELECTRICAL CHARACTERISTICS Symbol Parameter VOH “H” output voltage VOL VT+ — VT– IIH IIL “L” output voltage Hysteresis “H” input current “L” input current ILOAD Output load current ILEAK Output leakage current VRAM ICC Test conditions DIG output SEG output SDATA ____ SDATA, SCLK, CS ____ SDATA, SCLK, CS SDATA, SCLK ____ CS OSC FLD0 – FLD24 FLD0 – FLD24 ELECTRICAL CHARACTERISTICS Symbol (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) VEE = VCC–36 V VOL = VCC Output transistors “off” VEE = VCC–38 V VOL = VCC–38 V Output transistors “off” Limits Typ. Max. 750 V V V V µA µA µA µA µA –10 µA 2.0 0.5 5.0 –5.0 250 –500 –4.0 500 Unit (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Parameter Test conditions RAM hold voltage Power source current A-D CONVERTER CHARACTERISTICS When clock is stopped Min. 2.0 Limits Typ. 1.5 VCC = 5 V, f(XIN) = 2.0 MHz Output transistors “off” at A-D converter operating Max. 5.5 2.5 Unit V mA (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter — — Resolution Absolute accuracy (excluding quantization error) Conversion time Analog input voltage Analog port input current Ladder resistor Tconv VIA IIA RLADDER IOH = –18 mA IOH = –7 mA IOL = 5 mA VCC = 5.0 V VI = VCC VI = VSS Min. VCC–2.0 VCC–2.0 Test conditions Min. Limits Typ. VCC = 5.12 V 0 0.5 35 Max. 8 ±3 100 VCC 5.0 Unit Bits LSB tc(OSC) V µA kΩ 11 MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER TIMING REQUIREMENTS (V CC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tc (OSC) twH (OSC) twL (OSC) tc (SCLK) twH (SCLK) twL (SCLK) tsu(SDATA-SCLK) th(S__ CLK -SDATA) tsu __ (CS) th(CS) tre (SCLK) Parameter Min. 384 120 120 5 2 3 2 3 50 tc(OSC) 50 tc(OSC) 50 tc(OSC) Reset input “L” pulse width Clock input “H” pulse width Clock input “L” pulse width Serial clock input cycle time (Note) Serial clock input “H” pulse width (Note) Serial clock input “L” pulse width (Note) Serial input setup time (Note) Serial input hold time (Note) Serial input setup time Serial input hold time Serial clock interval time Limits Typ. Max. Unit ns ns ns CLKs CLKs CLKs CLKs CLKs ns ns ns Note: The unit means a number of noise filter sampling clock (tc(OSC)). SWITCHING CHARACTERISTICS Symbol (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Parameter Test conditions td(SCLK -SOUT ) tv(S CLK-S OUT) tr(Pch) Serial I/O output delay time (Note 1) Serial I/O output valid time COSC External capacitor size (Note 2) Min. CL = 100pF VEE = VCC –36 V 18 Measuring condition: Ta = 25°C, Vcc = 5.0 V) Frequency - External capacitor size Frequency f(OSC) [MHz] 3.0 2.5 2.0 1.5 1.0 0.5 0 20 30 40 50 60 70 External capacitor size COSC (pF) Fig. 13 Standard characteristic example of f(OSC)–COSC 12 80 Unit CLKs ns µs 1.8 Note 1: The unit means a number of noise filter sampling clock (tc(OSC)). 2: An external capacitor size varies with a mounted condition. 10 Max. 3 0 High-breakdown-voltage P-channel open-drain output rising time 0 Limits Typ. 80 pF MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER Serial I/O clock output port P-channel output port RL CL CL VEE Fig.14 Output switching characteristics measurement circuit diagram CS SCLK trec(SCLK) tsu(CS) th(CS) tC(SCLK) tWH(SCLK) tWL(SCLK) SCLK 0.8VCC 0.2VCC tsu(SDATA-SCLK) th(SCLK-SDATA) 0.8VCC 0.2VCC SDATA (input) td(SCLK-SDATA) tv(SCLK-SDATA) SDATA (output) Fig.15 Timing diagram 13 MITSUBISHI LINEAR IC’s M35502AFP FLD CONTROLLER PACKAGE OUTLINE 36P2R-G Plastic 36pin 450mil SSOP EIAJ Package Code SSOP36-P-450-0.80 JEDEC Code — Weight(g) 0.53 e b2 19 E HE e1 I2 36 Lead Material Alloy 42 Recommended Mount Pad F Symbol 1 18 A D G A2 e b L L1 y A1 c z Z1 14 Detail G Detail F A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2 Dimension in Millimeters Min Nom Max 2.3 — — 0.2 0.1 0 — 2.0 — 0.4 0.3 0.25 0.22 0.15 0.10 15.2 15.0 14.8 8.6 8.4 8.2 — 0.8 — 10.7 10.4 10.1 0.7 0.5 0.3 — 1.0 — — 0.7 — — — 0.85 0.15 — — 0¡ — 10¡ — 0.5 — — 11.43 — — — 1.27 HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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No. M35502AFP DATA SHEET Revision Description Rev. date 1.0 First Edition 990726 1.1 Font error is revised. 000414 (1/1)