Samsung M366S1724CT0-C1L Pc100 unbuffered dimm(168pin) spd specification(128mb c-die base) Datasheet

SERIAL PRESENCE DETECT
PC100 Unbuffered DIMM
PC100 Unbuffered DIMM(168pin)
SPD Specification(128Mb C-die base)
Rev. 0.1
Apr. 2000
Rev 0.1 Apr. 2000
SERIAL PRESENCE DETECT
PC100 Unbuffered DIMM
M366S1724CT0-C1H/C1L
• Organization : 16Mx64
• Composition : 8Mx16 *8
• Used component part # : K4S281632C-TC1H/C1L
• # of rows in module : 2 Rows
• # of banks in component : 4 banks
• Feature : 1,375mil height & double sided component
• Refresh : 4K/64ms
• Contents ;
Byte #
Function Described
Function Supported
-1H
0
# of bytes written into serial memory at module manufacturer
1
Total # of bytes of SPD memory device
2
Fundamental memory type
3
-1L
Hex value
-1H
Note
-1L
128bytes
80h
256bytes (2K-bit)
08h
SDRAM
04h
# of row address on this assembly
12
0Ch
1
4
# of column address on this assembly
9
09h
1
5
# of module Rows on this assembly
2 Rows
02h
6
Data width of this assembly
64 bits
40h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
9
SDRAM cycle time @CAS latency of 3
10ns
10ns
A0h
A0h
2
10
SDRAM access time from clock @CAS latency of 3
6ns
6ns
60h
60h
2
11
DIMM configuration type
12
Refresh rate & type
13
Primary SDRAM width
14
Error checking SDRAM width
15
Minimum clock delay for back-to-back random column address
16
SDRAM device attributes : Burst lengths supported
17
SDRAM device attributes : # of banks on SDRAM device
18
LVTTL
01h
Non parity
00h
15.625us, support self refresh
80h
x16
10h
None
00h
tCCD = 1CLK
01h
1, 2, 4, 8 & full page
8Fh
4 banks
04h
SDRAM device attributes : CAS latency
2&3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Non-buffered, non-registered
& redundant addressing
00h
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
0Eh
precharge all, auto precharge
23
SDRAM cycle time @CAS latency of 2
10ns
12ns
A0h
C0h
2
24
SDRAM access time from clock @CAS latency of 2
6ns
7ns
60h
70h
2
25
SDRAM cycle time @CAS latency of 1
-
-
00h
00h
26
SDRAM access time from clock @CAS latency of 1
-
-
00h
00h
27
Minimum row precharge time (=tRP)
20ns
20ns
14h
14h
28
Minimum row active to row active delay (tRRD)
20ns
20ns
14h
14h
29
Minimum RAS to CAS delay (=tRCD)
20ns
20ns
14h
14h
30
Minimum activate precharge time (=tRAS)
50ns
50ns
32h
31
Module Row density
32
Command and address signal input setup time
2ns
2ns
20h
20h
33
Command and address signal input hold time
1ns
1ns
10h
10h
34
Data signal input setup time
2ns
2ns
20h
20h
2 Rows of 64MB
32h
10h
Rev 0.1 Apr. 2000
SERIAL PRESENCE DETECT
Byte #
Function Described
PC100 Unbuffered DIMM
Function Supported
-1H
35
36~61
Data signal input hold time
62
SPD data revision code
63
Checksum for bytes 0 ~ 62
64
Manufacturer JEDEC ID code
65~71
1ns
Superset information (maybe used in future)
Manufacturing location
73
-1H
1ns
10h
10h
00h
PC100 SPD Spec. Ver. 1.2A
12h
-
Note
-1L
-
...... Manufacturer JEDEC ID code
72
Hex value
-1L
0Eh
3Eh
Samsung
CEh
Samsung
00h
Onyang Korea
01h
Manufacturer part # (Memory module)
M
4Dh
74
Manufacturer part # (DIMM configuration)
3
33h
75
Manufacturer part # (Data bits)
Blank
20h
76
...... Manufacturer part # (Data bits)
6
36h
77
...... Manufacturer part # (Data bits)
6
36h
78
Manufacturer part # (Mode & operating voltage)
S
53h
79
Manufacturer part # (Module depth)
1
31h
80
...... Manufacturer part # (Module depth)
7
37h
81
Manufacturer part # (Refresh, # of banks in Comp. & interface)
2
32h
82
Manufacturer part # (Composition component)
4
34h
83
Manufacturer part # (Component revision)
C
43h
84
Manufacturer part # (Package type)
T
54h
85
Manufacturer part # (PCB revision & type)
86
Manufacturer part # (Hyphen)
87
Manufacturer part # (Power)
88
Manufacturer part # (Minimum cycle time)
1
1
31h
31h
89
Manufacturer part # (Minimum cycle time)
H
L
48h
4Ch
90
Manufacturer part # (TBD)
91
Manufacturer revision code (For PCB)
92
...... Manufacturer revision code (For component)
93
Manufacturing date (Week)
-
-
3
94
Manufacturing date (Year)
-
-
3
95~98
Assembly serial #
-
-
4
99~125
Manufacturer specific data (may be used in future)
Undefined
-
5
100MHz
64h
126
System frequency for 100MHz
127
PC100 specification details
128+
Unused storage locations
0
30h
"-"
2Dh
C
43h
Blank
20h
0
30h
C-die (4th Gen.)
43h
Detailed 100MHz Information
Undefined
FFh
FDh
-
5
Note : 1. The bank select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #.
5. These bytes are Undefined and can be used for Samsung ′s own purpose.
Rev 0.1 Apr. 2000
SERIAL PRESENCE DETECT
PC100 Unbuffered DIMM
M366S3323CT0-C1H/C1L
• Organization : 32Mx64
• Composition : 16Mx8 *16
• Used component part # : K4S280832C-TC1H/C1L
• # of rows in module : 2 Rows
• # of banks in component : 4 banks
• Feature : 1,375mil height & double sided component
• Refresh : 4K/64ms
• Contents ;
Byte #
Function Described
Function Supported
-1H
0
# of bytes written into serial memory at module manufacturer
1
Total # of bytes of SPD memory device
2
Fundamental memory type
3
-1L
Hex value
-1H
Note
-1L
128bytes
80h
256bytes (2K-bit)
08h
SDRAM
04h
# of row address on this assembly
12
0Ch
1
4
# of column address on this assembly
10
0Ah
1
5
# of module Rows on this assembly
2 Rows
02h
6
Data width of this assembly
64 bits
40h
7
...... Data width of this assembly
8
Voltage interface standard of this assembly
9
-
00h
LVTTL
01h
SDRAM cycle time @CAS latency of 3
10ns
10ns
A0h
A0h
2
10
SDRAM access time from clock @CAS latency of 3
6ns
6ns
60h
60h
2
11
DIMM configuration type
12
Refresh rate & type
13
Primary SDRAM width
14
Error checking SDRAM width
15
Minimum clock delay for back-to-back random column address
Non parity
00h
15.625us, support self refresh
80h
x8
08h
None
00h
tCCD = 1CLK
01h
1, 2, 4, 8 & full page
8Fh
4 banks
04h
16
SDRAM device attributes : Burst lengths supported
17
SDRAM device attributes : # of banks on SDRAM device
18
SDRAM device attributes : CAS latency
2&3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Non-buffered, non-registered
& redundant addressing
00h
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
0Eh
precharge all, auto precharge
23
SDRAM cycle time @CAS latency of 2
10ns
12ns
A0h
C0h
2
24
SDRAM access time from clock@CAS latency of 2
6ns
7ns
60h
70h
2
25
SDRAM cycle time @CAS latency of 1
-
-
00h
00h
26
SDRAM access time from clock@CAS latency of 1
-
-
00h
00h
27
Minimum row precharge time (=tRP)
20ns
20ns
14h
14h
28
Minimum row active to row active delay (tRRD)
20ns
20ns
14h
14h
29
Minimum RAS to CAS delay (=tRCD)
20ns
20ns
14h
14h
30
Minimum activate precharge time (=tRAS)
50ns
50ns
32h
31
Module Row density
32
Command and address signal input setup time
2ns
2ns
20h
20h
33
Command and address signal input hold time
1ns
1ns
10h
10h
34
Data signal input setup time
2ns
2ns
20h
20h
32h
20h
2 Rows of 128MB
Rev 0.1 Apr. 2000
SERIAL PRESENCE DETECT
Byte #
Function Described
PC100 Unbuffered DIMM
Function Supported
-1H
35
36~61
Data signal input hold time
62
SPD data revision code
63
Checksum for bytes 0 ~ 62
64
Manufacturer JEDEC ID code
65~71
1ns
Superset information (maybe used in future)
Manufacturing location
73
-1H
1ns
10h
10h
00h
PC100 SPD Spec. Ver. 1.2A
12h
-
Note
-1L
-
...... Manufacturer JEDEC ID code
72
Hex value
-1L
17h
47h
Samsung
CEh
Samsung
00h
Onyang Korea
01h
Manufacturer part # (Memory module)
M
4Dh
74
Manufacturer part # (DIMM configuration)
3
33h
75
Manufacturer part # (Data bits)
Blank
20h
76
...... Manufacturer part # (Data bits)
6
36h
77
...... Manufacturer part # (Data bits)
6
36h
78
Manufacturer part # (Mode & operating voltage)
S
53h
79
Manufacturer part # (Module depth)
3
33h
80
...... Manufacturer part # (Module depth)
3
33h
81
Manufacturer part # (Refresh, # of banks in Comp. & interface)
2
32h
82
Manufacturer part # (Composition component)
3
33h
83
Manufacturer part # (Component revision)
C
43h
84
Manufacturer part # (Package type)
T
54h
85
Manufacturer part # (PCB revision & type)
86
Manufacturer part # (Hyphen)
87
Manufacturer part # (Power)
88
Manufacturer part # (Minimum cycle time)
1
1
31h
31h
89
Manufacturer part # (Minimum cycle time)
H
L
48h
4Ch
90
Manufacturer part # (TBD)
91
Manufacturer revision code (For PCB)
92
...... Manufacturer revision code (For component)
93
Manufacturing date (Week)
-
-
3
94
Manufacturing date (Year)
-
-
3
95~98
Assembly serial #
-
-
4
99~125
Manufacturer specific data (may be used in future)
Undefined
-
5
100MHz
64h
126
System frequency for 100MHz
127
PC100 specification details
128+
Unused storage locations
0
30h
"-"
2Dh
C
43h
Blank
20h
0
30h
C-die (4th Gen.)
43h
Detailed 100MHz Information
Undefined
FFh
FDh
-
5
Note : 1. The bank select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #.
5. These bytes are Undefined and can be used for Samsung ′s own purpose.
Rev 0.1 Apr. 2000
SERIAL PRESENCE DETECT
PC100 Unbuffered DIMM
M374S3323CT0-C1H/C1L
• Organization : 32Mx72
• Composition : 16Mx8 *18
• Used component part # : K4S280832C-TC1H/C1L
• # of rows in module : 2 Rows
• # of banks in component : 4 banks
• Feature : 1,375mil height & double sided component
• Refresh : 4K/64ms
• Contents ;
Byte #
Function Described
Function Supported
-1H
0
# of bytes written into serial memory at module manufacturer
1
Total # of bytes of SPD memory device
2
Fundamental memory type
3
-1L
Hex value
-1H
Note
-1L
128bytes
80h
256bytes (2K-bit)
08h
SDRAM
04h
# of row address on this assembly
12
0Ch
1
4
# of column address on this assembly
10
0Ah
1
5
# of module Rows on this assembly
2 Rows
02h
6
Data width of this assembly
72 bits
48h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
9
SDRAM cycle time @CAS latency of 3
10
SDRAM access time from clock @CAS latency of 3
11
DIMM configuration type
12
Refresh rate & type
13
14
15
Minimum clock delay for back-to-back random column address
16
SDRAM device attributes : Burst lengths supported
17
SDRAM device attributes : # of banks on SDRAM device
18
LVTTL
01h
10ns
10ns
A0h
A0h
2
6ns
6ns
60h
60h
2
ECC
02h
15.625us, support self refresh
80h
Primary SDRAM width
x8
08h
Error checking SDRAM width
x8
08h
tCCD = 1CLK
01h
1, 2, 4, 8 & full page
8Fh
4 banks
04h
SDRAM device attributes : CAS latency
2&3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Non-buffered, non-registered
& redundant addressing
00h
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
0Eh
precharge all, auto precharge
23
SDRAM cycle time @CAS latency of 2
10ns
12ns
A0h
C0h
2
24
SDRAM access time from clock @CAS latency of 2
6ns
7ns
60h
70h
2
25
SDRAM cycle time @CAS latency of 1
-
-
00h
00h
26
SDRAM access time from clock @CAS latency of 1
-
-
00h
00h
27
Minimum row precharge time (=tRP)
20ns
20ns
14h
14h
28
Minimum row active to row active delay (tRRD)
20ns
20ns
14h
14h
29
Minimum RAS to CAS delay (=tRCD)
20ns
20ns
14h
14h
30
Minimum activate precharge time (=tRAS)
50ns
50ns
32h
31
Module Row density
32
Command and address signal input setup time
2ns
2ns
20h
20h
33
Command and address signal input hold time
1ns
1ns
10h
10h
34
Data signal input setup time
2ns
2ns
20h
20h
32h
20h
2 Rows of 128MB
Rev 0.1 Apr. 2000
SERIAL PRESENCE DETECT
Byte #
Function Described
PC100 Unbuffered DIMM
Function Supported
-1H
35
36~61
Data signal input hold time
62
SPD data revision code
63
Checksum for bytes 0 ~ 62
64
Manufacturer JEDEC ID code
65~71
1ns
Superset information (maybe used in future)
Manufacturing location
73
-1H
1ns
10h
10h
00h
PC100 SPD Spec. Ver. 1.2A
12h
-
Note
-1L
-
...... Manufacturer JEDEC ID code
72
Hex value
-1L
29h
59h
Samsung
CEh
Samsung
00h
Onyang Korea
01h
Manufacturer part # (Memory module)
M
4Dh
74
Manufacturer part # (DIMM configuration)
3
33h
75
Manufacturer part # (Data bits)
Blank
20h
76
...... Manufacturer part # (Data bits)
7
37h
77
...... Manufacturer part # (Data bits)
4
34h
78
Manufacturer part # (Mode & operating voltage)
S
53h
79
Manufacturer part # (Module depth)
3
33h
80
...... Manufacturer part # (Module depth)
3
33h
81
Manufacturer part # (Refresh, # of banks in Comp. & interface)
2
32h
82
Manufacturer part # (Composition component)
3
33h
83
Manufacturer part # (Component revision)
C
43h
84
Manufacturer part # (Package type)
T
54h
85
Manufacturer part # (PCB revision & type)
86
Manufacturer part # (Hyphen)
87
Manufacturer part # (Power)
88
Manufacturer part # (Minimum cycle time)
1
1
31h
31h
89
Manufacturer part # (Minimum cycle time)
H
L
48h
4Ch
90
Manufacturer part # (TBD)
91
Manufacturer revision code (For PCB)
92
...... Manufacturer revision code (For component)
93
Manufacturing date (Week)
-
-
3
94
Manufacturing date (Year)
-
-
3
95~98
Assembly serial #
-
-
4
99~125
Manufacturer specific data (may be used in future)
Undefined
-
5
100MHz
64h
126
System frequency for 100MHz
127
PC100 specification details
128+
Unused storage locations
0
30h
"-"
2Dh
C
43h
Blank
20h
0
30h
C-die (4th Gen.)
43h
Detailed 100MHz Information
Undefined
FFh
FDh
-
5
Note : 1. The bank select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #.
5. These bytes are Undefined and can be used for Samsung ′s own purpose.
Rev 0.1 Apr. 2000
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