Renesas M38064E8DFS Single-chip 8-bit cmos microcomputer Datasheet

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3825 group is the 8-bit microcomputer based on the 740 family core technology.
The 3825 group has the LCD drive control circuit, an 8-channel AD converter, and a Serial I/O as additional functions.
The various microcomputers in the 3825 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 3825 Group,
refer the section on group expansion.
• Serial I/O ...................... 8-bit ✕ 1 (UART or Clock-synchronized)
• A-D converter .................................................. 8-bit ✕ 8 channels
• LCD drive control circuit
•
•
FEATURES
• Basic machine-language instructions ....................................... 71
• The minimum instruction execution time ............................ 0.5 µs
•
•
•
•
•
(at 8 MHz oscillation frequency)
Memory size
ROM .................................................................. 4 K to 60 K bytes
RAM ................................................................. 192 to 2048 bytes
Programmable input/output ports ............................................. 43
Software pull-up/pull-down resistors (Ports P0–P8)
Interrupts .................................................. 17 sources, 16 vectors
(includes key input interrupt)
Timers ........................................................... 8-bit ✕ 3, 16-bit ✕ 2
•
•
Bias ................................................................................... 1/2, 1/3
Duty ............................................................................ 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ......................................................................... 40
2 Clock generating circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage
In high-speed mode ................................................... 4.0 to 5.5 V
In middle-speed mode ............................................... 2.5 to 5.5 V
(M version: 2.2 to 5.5 V)
(Extended operating temperature version: 3.0 to 5.5 V)
In low-speed mode ..................................................... 2.5 to 5.5 V
(M version: 2.2 to 5.5 V)
(Extended operating temperature version: 3.0 to 5.5 V)
Power dissipation
In high-speed mode ........................................................... 32 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode .............................................................. 45 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
Operating temperature range ................................... – 20 to 85°C
(Extended operating temperature version: –40 to 85°C)
APPLICATIONS
Camera, household appliances, consumer electronics, etc.
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
P30/SEG18
P31/SEG19
P32/SEG20
P33/SEG21
P34/SEG22
P35/SEG23
P36/SEG24
P37/SEG25
P00/SEG26
P01/SEG27
P02/SEG28
P03/SEG29
P04/SEG30
P05/SEG31
P06/SEG32
P07/SEG33
P10/SEG34
P11/SEG35
P12/SEG36
P13/SEG37
P14/SEG38
P15/SEG39
PIN CONFIGURATION (TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VCC
VREF
AVSS
COM3
COM2
COM1
COM0
VL3
VL2
C2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
M38258MCMXXXFP
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
C1
VL1
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P57/ADT
P56/TOUT
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P51/INT3
P50/INT2
P47/SRDY
P46/SCLK
P45/TXD
P44/RXD
P43/INT1
P42/INT0
P41 / f(XIN)/5 / f(XIN)/10
P40 /f(XIN) / f(XIN)/2
P77
P76
P75
P74
1
Package type : 100P6S-A (100-pin plastic-molded QFP)
Fig. 1 Pin configuration of M38258MCMXXXFP
(The pin configuration of 100D0 is same as this.)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
P80/XCOUT
P81/XCIN
RESET
P70
P71
P72
P73
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SEG13
SEG14
SEG15
SEG16
SEG17
P30/SEG18
P31/SEG19
P32/SEG20
P33/SEG21
P34/SEG22
P35/SEG23
P36/SEG24
P37/SEG25
P00/SEG26
P01/SEG27
P02/SEG28
P03/SEG29
P04/SEG30
P05/SEG31
P06/SEG32
P07/SEG33
P10/SEG34
P11/SEG35
P12/SEG36
P13/SEG37
PIN CONFIGURATION (TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VCC
VREF
AVSS
COM3
COM2
COM1
COM0
VL3
VL2
C2
C1
VL1
76
50
77
49
78
48
79
80
47
46
45
44
43
42
41
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
M38258MCMXXXGP
M38258MCMXXXHP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P14/SEG38
P15/SEG39
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
P80/XCOUT
P81/XCIN
RESET
P70
P71
P72
P73
P74
P75
P76
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P57/ADT
P56/TOUT
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P51/INT3
P50/INT2
P47/SRDY
P46/SCLK
P45/TXD
P44/RXD
P43/INT1
P42/INT0
P41 / f(XIN)/5 / f(XIN)/10
P40 / f(XIN) / f(XIN)/2
P77
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Package type : GP ........................... 100P6Q-A (100-pin plastic-molded LQFP)
Package type : HP ........................... 100PFB-A (100-pin plastic-molded TQFP)
Fig. 2 Pin configuration of M38258MCMXXXGP, M38258MCMXXXHP
2
I/O port P7
I/O port P6
3 4 5 6 7 8 9 10
27 28 29 30 31 32 33 34
36 37
I/O port P8
P8 (2)
PCH
92 93
VREF
AVSS
(0 V)
TOUT
40
91
P5 (8)
I/O port P5
I/O port P4
P3 (8)
Output port P3
65 66 67 68 69 70 71 72
SI/O (8)
19 20 21 22 23 24 25 26
P4 (8)
ROM
Timer X (16)
Timer Y (16)
Timer 1 (8) Timer 2 (8)
Timer 3 (8)
Data bus
(0 V)
VSS
(5 V)
VCC
CNT R0, CNTR1
RTP0, RTP1
PS
P CL
S
Y
X
A
35
RESET
11 12 13 14 15 16 17 18
CPU
A-D converter (8)
P6 (8)
XCOUT φ
Subclock
output
P7 (8)
XCOUT
XCIN
XCIN
Subclock
input
Clock generating
circuit
39
38
ADT
Reset input
INT2, INT3
Clock
output
XOUT
INT0, INT1
Clock
input
XIN
Real time port function
FUNCTIONAL BLOCK DIAGRAM (Package : 100P6S-A)
I/O port P2
41 42 43 44 45 46 47 48
P2 (8)
LCD display
RAM
(20 bytes)
RAM
Output port P1
49 50 51 52 53 54 55 56
P1 (8)
Output port P0
57 58 59 60 61 62 63 64
P0 (8)
LCD
drive control
circuit
79
78
77
76
75
74
73
89
88
87
86
85
84
83
82
81
80
90
97
96
95
94
99
98
100
2
1
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
COM0
COM1
COM2
COM3
VL1
C1
C2
VL2
VL3
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 3 Functional block diagram
3
Key-on wake up
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1. Pin description (1)
Pin
Function
Name
Function except a port function
VCC, VSS
Power source
•Apply voltage of power source to V CC, and 0 V to VSS . (For the limits of VCC, refer to “Recommended operating conditions”.)
VREF
Analog reference
voltage
• Reference voltage input pin for A-D converter.
AVSS
Analog power
source
• GND input pin for A-D converter.
• Connect to VSS.
RESET
Reset input
• Reset input pin for active “L”
XIN
Clock input
XOUT
Clock output
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• This clock is used as the oscillating source of system clock.
VL1 – VL3
LCD power source
C 1 , C2
Charge-pump
capacitor pin
COM0 – COM3
Common output
SEG0 – SEG17
Segment output
P00/SEG26 –
P07/SEG33
Output port P0
P10/SEG34 –
P15/SEG39
Output port P1
P16, P17
I/O port P1
P20 – P27
I/O port P2
P30/SEG18 –
P37/SEG25
Output port P3
4
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage
• Input 0 – VL3 voltage to LCD
• External capacitor pins for a voltage multiplier (3 times) of LCD contorl.
• LCD common output pins
• COM2 and COM3 are not used at 1/2 duty ratio.
• COM3 is not used at 1/3 duty ratio.
• LCD segment output pins
•
•
•
•
8-bit output port
CMOS 3-state output structure
Pull-down control is enabled.
Port output control is enabled.
•
•
•
•
6-bit output port
CMOS 3-state output structure
Pull-down control is enabled.
Port output control is enabled.
•
•
•
•
•
2-bit I/O port
CMOS compatible input level
CMOS 3-state output structure
I/O direction register allows each pin to be individually programmed as either input or output.
Pull-up control is enabled.
•
•
•
•
8-bit Input port
CMOS compatible input level
CMOS 3-state output structure
I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
•
•
•
•
8-bit output port
CMOS 3-state output structure
Pull-down control is enabled.
Port output control is enabled.
• LCD segment pins
• Key input (key-on wake up) interrupt
input pins
• LCD segment pins
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2. Pin description (2)
Pin
Function
Name
Function except a port function
P40/f(XIN)/
f(XIN)/2,
P41/f(XIN)/5/
f(XIN)/10
I/O port P4
P42/INT0,
P43/INT1
•
•
•
•
8-bit I/O port
CMOS compatible input level
CMOS 3-state output structure
I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
• Interrupt input pins
• Serial I/O function pins
P44/RXD,
P45/TXD,
P46/SCLK,
P47/SRDY
P50/INT2,
P51/INT3
• Clock output pins
I/O port P5
P52/RTP0,
P53/RTP1
•
•
•
•
8-bit I/O port
CMOS compatible input level
CMOS 3-state output structure
I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
• Interrupt input pins
• Real time port function pins
P54/CNTR0,
P55/CNTR1
• Timers X, Y functions pins
P56/TOUT
• Timer 2 output pin
P57/ADT
• A-D trigger input pin
P60/AN0–
P67/AN7
I/O port P6
•
•
•
•
P70
Input port P7
• 1-bit input port
• CMOS compatible input level
P71–P77
I/O port P7
•
•
•
•
•
P80/XCOUT,
P81/XCIN
I/O port P8
•
•
•
•
8-bit I/O port
CMOS compatible input level
CMOS 3-state output structure
I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
• A-D conversion input pins
7-bit I/O port
CMOS compatible input level
CMOS 3-state output structure
I/O direction register allows each pin to be individually programmed as either input or output.
Pull-up control is enabled.
2-bit I/O port
CMOS compatible input level
CMOS 3-state output structure
I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
•Sub-clock generating circuit I/O pins
(Connect a resonator. External clock
cannot be used.)
5
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product M3825 8 M C M XXX HP
Package type
FP : 100P6S-A package
HP : 100PFB-A package
GP: 100P6Q-A package
FS : 100D0 package
ROM number
Omitted in One Time PROM version shipped in
blank and EPROM version.
Normally, using hyphen
When electrical characteristic, or division of quality
identification code using alphanumeric character
– : Standard
D : Extended operating temperature version
M : M version
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 4 Part numbering
6
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (STANDARD, ONE TIME
PROM VERSION, EPROM VERSION)
Packages
100PFB-A ................................ 0.4 mm-pitch plastic molded TQFP
100P6Q-A ................................ 0.5 mm-pitch plastic molded LQFP
100P6S-A ................................ 0.65 mm-pitch plastic molded QFP
100D0 ................... 0.65 mm-pitch ceramic LCC (EPROM version)
Mitsubishi plans to expand the 3825 group(Standard, One Time
PROM version, EPROM version) as follows.
Memory Type
Support for mask ROM, One Time PROM, and EPROM versions.
Memory Size
ROM size ............................................................ 16 K to 60 Kbytes
RAM size ............................................................ 640 to 2048 bytes
Memory Expansion Plan
ROM size (bytes)
Mass product
M38259EF
60K
56K
52K
48K
44K
40K
36K
Mass product
M38257M8/E8
32K
28K
Mass product
M38254M6
24K
20K
Mass product
M38254M4
16K
12K
8K
4K
256
512
640
768
1,024
1,536
2,048
RAM size (bytes)
Fig. 5 Memory expansion plan
7
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Currently products are listed below.
As of Dec. 2000
Table 3. List of products
Product
ROM size (bytes)
ROM size for User in ( )
RAM size (bytes)
M38254M4-XXXFP
M38254M4-XXXGP
M38254M6-XXXFP
M38254M6-XXXGP
M38257M8-XXXFP
M38257E8FP
M38257M8-XXXGP
M38257E8GP
M38257E8FS
M38259EFFP
M38259EFHP
M38259EFGP
M38259EFFS
16384
(16254)
640
24576
(24446)
640
32768
(32638)
1024
61440
(61310)
2048
8
Package
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6S-A
100P6Q-A
100P6Q-A
100D0
100P6S-A
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version (blank)
Mask ROM version
One Time PROM version (blank)
EPROM version
One Time PROM version (blank)
100PFB-A One Time PROM version (blank)
100P6Q-A One Time PROM version (blank)
100D0
EPROM version
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
(EXTENDED OPERATING TEMPERATURE VERSION)
Memory Size
ROM size ............................................................ 16 K to 60 Kbytes
RAM size ............................................................ 640 to 2048 bytes
Mitsubishi plans to expand the 3825 group (Extended operating
temperature version) as follows.
Packages
Memory Type
100P6S-A ................................ 0.65 mm-pitch plastic molded QFP
Support for mask ROM, one time PROM version.
Memory Expansion Plan
ROM size (bytes)
Mass product
M38259EFD
60K
56K
52K
Mass product
M38258MCD
48K
44K
40K
36K
Mass product
32K
28K
M38257M8D
Mass product
M38254M6D
24K
20K
Mass product
M38254M4D
16K
12K
8K
4K
256
512
640
768
1,024
1,536
2,048
RAM size (bytes)
Fig. 6 Memory expansion plan for extended operating temperature version
Currently products are listed below.
Table 4. List of products for extended operating temperature version
Product
M38254M4DXXXFP
M38254M6DXXXFP
M38257M8DXXXFP
M38258MCDXXXFP
M38259EFDFP
ROM size (bytes)
ROM size for User in ( )
16384
(16254)
24576
(24446)
32768
(32638)
49152
(49022)
61440
(61310)
As of Dec. 2000
RAM size (bytes)
Package
640
100P6S-A
Mask ROM version
640
100P6S-A
Mask ROM version
1024
100P6S-A
Mask ROM version
1536
100P6S-A
Mask ROM version
2048
100P6S-A
One Time PROM version (blank)
Remarks
9
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (M VERSION)
Packages
Mitsubishi plans to expand the 3825 group (M version) as follows.
100PFB-A ................................ 0.4 mm-pitch plastic molded TQFP
100P6Q-A ................................ 0.5 mm-pitch plastic molded LQFP
100P6S-A ................................ 0.65 mm-pitch plastic molded QFP
Memory Type
Support for mask ROM version.
Memory Size
ROM size ......................................................................... 48 Kbytes
RAM size ....................................................................... 1536 bytes
Memory Expansion Plan
ROM size (bytes)
60K
56K
52K
Mass product
M38258MCM
48K
44K
40K
36K
32K
28K
24K
20K
16K
12K
8K
4K
256
512
768
1,024
1,536
2,048
RAM size (bytes)
Fig. 7 Memory expansion plan for M version
Currently products are listed below.
As of Dec. 2000
Table 5. List of products for low power source version
Product
ROM size (bytes)
ROM size for User in ( )
RAM size (bytes)
M38258MCMXXXFP
M38258MCMXXXHP
M38258MCMXXXGP
10
49152
(49022)
1536
Package
Remarks
100P6S-A
Mask ROM version
100PFB-A
Mask ROM version
100P6Q-A
Mask ROM version
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 9.
Store registers other than those described in Figure 9 with program when the user needs them during interrupts or subroutine
calls.
The 3825 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
PCH
Stack pointer
b0
Program counter
PCL
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 8 740 Family CPU register structure
11
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
POP return
address from stack
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
(S)
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 9 Register push and pop at interrupt generation and subroutine call
Table 6 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
12
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 7 Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
N flag
Set instruction
SEC
–
SEI
SED
–
SET
–
–
Clear instruction
CLC
–
CLI
CLD
–
CLT
CLV
–
13
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN–XOUT selected (middle-/high-speed mode)
1 : XCIN–XCOUT selected (low-speed mode)
Fig. 10 Structure of CPU mode register
14
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Zero Page
The 256 bytes from addresses 000016 to 00FF 16 are called the
zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special Page
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page
addressing mode.
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(bytes)
000016
Address
XXXX16
192
00FF16
256
013F16
384
01BF16
512
023F16
640
02BF16
768
033F16
896
03BF16
1024
043F16
1536
063F16
2048
083F16
SFR area
004016
005416
LCD display RAM area
Zero page
010016
RAM
XXXX16
Reserved area
084016
Not used
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
4096
F00016
F08016
YYYY16
Reserved ROM area
(128 bytes)
8192
E00016
E08016
12288
D00016
D08016
16384
C00016
C08016
20480
B00016
B08016
24576
A00016
A08016
28672
900016
908016
32768
800016
808016
36864
700016
708016
40960
600016
608016
45056
500016
508016
49152
400016
408016
53248
300016
308016
FFFE16
57344
200016
208016
FFFF16
61440
100016
108016
ZZZZ16
ROM
FF0016
FFDC16
Interrupt vector area
Special page
Reserved ROM area
Fig. 11 Memory map diagram
15
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 Port P0 (P0)
000116
000216 Port P1 (P1)
000316 Port P1 output control register (P1C)
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
000616 Port P3 (P3)
000716
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
000A16 Port P5 (P5)
000B16 Port P5 direction register (P5D)
000C16 Port P6 (P6)
002516 Timer 2 (T2)
002616 Timer 3 (T3)
002716 Timer X mode register (TXM)
002816 Timer Y mode register (TYM)
002916 Timer 123 mode register (T123M)
002A16 Clock output control register (TCON)
002B16
002C16
000D16 Port P6 direction register (P6D)
000E16 Port P7 (P7)
000F16 Port P7 direction register (P7D)
001016 Port P8 (P8)
002D16
002E16
001116 Port P8 direction register (P8D)
001216
003116
003216
001316
003316
001416
001516
003416 A-D control register (ADCON)
003516 A-D conversion register (AD)
003616
003716
001616 PULL register A (PULLA)
001716 PULL register B (PULLB)
001816 Transmit/Receive buffer register(TB/RB)
001916 Serial I/O status register (SIOSTS)
001A16 Serial I/O control register (SIO1CON)
001B16 UART control register (UART CON)
001C16 Baud rate generator (BRG)
002F16
003016
003816 Segment output enable register (SEG)
003916 LCD mode register (LM)
003A16 Interrupt edge selection register (INTEDGE)
001D16
001E16
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1(IREQ1)
003D16 Interrupt request register 2(IREQ2)
003E16 Interrupt control register 1(ICON1)
001F16
003F16 Interrupt control register 2(ICON2)
Fig. 12 Memory map of special function register (SFR)
16
002016 Timer X (low) (TXL)
002116 Timer X (high) (T XH)
002216 Timer Y (low) (TYL)
002316 Timer Y (high) (T YH)
002416 Timer 1 (T1)
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
Direction Registers
The 3825 group has 43 programmable I/O pins arranged in seven
I/O ports (ports P16, P17, P2, P4–P6, P71–P77, P80 and P81). The
I/O ports have direction registers which determine the input/output
direction of each individual pin. (Ports P1 6 and P1 7 are shared
with bits 6 and 7 of the port P1 output control register). Each bit in
a direction register corresponds to one pin, and each pin can be
set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Port P1 Output Control Register
Bit 0 of the port P1 output control register (address 0003 16) enables control of the output of ports P10 to P15.
When the bit is set to “1”, the port output function is valid.
In this case, setting of the PULL register A to ports P10 to P15 is
invalid.
When resetting, bit 0 of the port P1 output control register is set to
“0” (the port output function is invalid.)
b7
b0
PULL register A
(PULLA : address 001616)
P0, P10–P15, P3 pull-down
(shared with P0 and P3 output
control : refer to the text)
P16–P17 pull-up
P20–P27 pull-up
P80, P81 pull-up
P40–P43 pull-up
P44–P47 pull-up
Not used (return “0” when read)
b7
b0
PULL register B
(PULLB : address 001716)
P50–P53 pull-up
P54–P57 pull-up
P60–P63 pull-up
P64–P67 pull-up
P71–P73 pull-up
P74–P77 pull-up
Not used (return “0” when read)
0 : Disable
1 : Enable
Note: The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
Fig. 13 Structure of PULL register A and PULL register B
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL register B (address 001716), ports P0 to P8 except P70 can control either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports. (except for ports
P0 and P3).
Ports P0 and P3 share the port output control function with bit 0 of
the PULL register A. When set to “1”, the port output function is invalid (Pull-down is valid).
When set to “0”, the port output function is valid (Pull-down is invalid).
The PULL register A setting is invalid for pins set to segment output with the segment output enable register.
17
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8. I/O ports functions
Pin
P00/SEG26–
P07/SEG33
Name
Port P0
P10/SEG34–
P15/SEG39
Input/Output
I/O Format
Non-Port Function
Output
CMOS 3-state output
LCD segment output
Output
CMOS 3-state output
LCD segment output
Port P1
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
Related SFRs
PULL register A
Segment output enable
register
PULL register A
Segment output enable
register
Port P1 output
control register
Diagram No.
(1)
(1)
PULL register A
(2)
Key-on wake up
interrupt input
PULL register A
Interrupt control register 2
(2)
LCD segment output
PULL register A
Segment output enable
register
(1)
Clock output
Clock output control
register
PULL register A
External interrupt input
PULL register A
Interrupt edge selection
register
P44/RXD
P54/TXD
P46/SCLK
P47/SRDY
Serial I/O function I/O
PULL register A
Serial I/O control register
Serial I/O status register
UART control register
(3)
(4)
(5)
(6)
P50/INT2,
P51/INT3
External interrupt input
PULL register B
Interrupt edge selection
register
(2)
P52/RTP0,
P53/RTP1
Real time port
function output
PULL register B
Timer X mode register
(7)
Timer X function I/O
PULL register B
Timer X mode register
(8)
P55/CNTR1
Timer Y function input
PULL register B
Timer Y mode register
(9)
P56/TOUT
Timer 2 output
PULL register B
Timer 123 mode register
(8)
P57/ADT
A-D trigger input
PULL register B
A-D control register
(9)
A-D conversion input
PULL register B
A-D control register
(10)
P16 , P17
P20–P27
Port P2
Input/output,
individual bits
P30/SEG18–
P37/SEG25
Port P3
Output
CMOS 3-state output
P40/f(XIN)/
f(XIN)/2,
P41/f(XIN)/5/
f(XIN)/10
P42/INT0,
P43/INT1
P54/CNTR0
P60/AN0–
P67/AN7
Port P4
Port P5
Port P6
P70
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
Input
Port P7
P71–P77
P80/XCOUT
Port P8
P81/XCIN
Input/output,
individual bits
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
COM0–COM3
Common
Output
LCD common output
SEG0–SEG17
Segment
Output
LCD segment output
(11)
Sub-clock
generating circuit
PULL register B
(12)
PULL register A
CPU mode register
(13)
LCD mode register
(15)
Note 1: When using double-function ports as functional I/O pins, refer the method to the relevant sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
18
(2)
(14)
(16)
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0, P10–P15, P3
LCD drive timing
Data bus
Segment data
Port latch
VL2/VL3/VCC
Segment/Port
Interface logic
level shift circuit
Port/Segment
Port ON/OFF
Segment
VL1/VSS
Port
Pull-down
(2) Ports P16, P17, P2, P40–P43, P50, P51
(3) Port P44
Pull-up control
Pull-up control
Serial I/O enable bit
Reception enable bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
Key-on wake up interrupt input
INT0–INT3 interrupt input
Serial I/O input
Except P16, P17, P40, P41
(4) Port P45
(5) Port P46
Pull-up control
P45/TXD P-channel output disable bit
Serial I/O enable bit
Transmission enable bit
Direction
register
Data bus
Serial I/O synchronization clock
selection bit
Serial I/O enable bit
Pull-up control
Serial I/O mode selection bit
Serial I/O enable bit
Direction
register
Data bus
Port latch
Serial I/O output
Port latch
Serial I/O clock output
Serial I/O clock input
(6) Port P47
(7) Ports P52, P53
Serial I/O mode selection bit
Serial I/O enable bit
SRDY output enable bit
Direction
register
Data bus
Port latch
Serial I/O ready output
Pull-up control
Pull-up control
Direction
register
Data bus
Port latch
Real time control bit
Real time port data
Fig. 14 Port block diagram (1)
19
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Ports P55, P57
(8) Ports P54, P56
Pull-up control
Pull-up control
Direction
register
Data bus
Direction
register
Port latch
Port latch
Data bus
Pulse output mode
Timer output
CNTR1 interrupt input
A-D trigger interrupt input
CNTR0 interrupt input
P54 only
(10) Port P6
Pull-up control
(11) Port P70
Direction
register
Data bus
Port latch
Data bus
A-D conversion input
Analog input pin selection bit
(12) Ports P71–P77
(13) Port P80
Port Xc switch bit + Pull-up control
Pull-up control
Port XC switch bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Oscillation circuit
Port P81
(14) Port P81
Port XC switch bit
Port Xc switch bit + Pull-up control
Port XC switch bit
Direction
register
(15) COM0–COM3
VL3
Port latch
Data bus
VL2
VL1
The gate input signal of each
transistor is controlled by the
LCD duty ratio and the bias
value.
Sub-clock generating circuit input
(16) SEG0–SEG17
VL2/VL3
VL1/VSS
Fig. 15 Port block diagram (2)
20
VSS
The voltage applied to the sources of
P-channel and N-channel transistors
is the controlled voltage by the bias
value.
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupt Operation
Interrupts occur by seventeen sources: eight external, eight internal, and one software.
By acceptance of an interrupt, the following operations are automatically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Table 9. Interrupt vector addresses and priority
Interrupt Source
Priority
Vector Addresses (Note 1)
Low
High
FFFC16
FFFD16
Reset (Note 2)
1
INT0
2
FFFB16
FFFA16
INT1
3
FFF916
FFF816
Serial I/O
reception
4
FFF716
FFF616
Serial I/O
transmission
5
FFF516
FFF416
Timer X
Timer Y
Timer 2
Timer 3
6
7
8
9
FFF316
FFF116
FFEF16
FFED16
FFF216
FFF016
FFEE16
FFEC16
CNTR0
10
FFEB16
FFEA16
CNTR1
11
FFE916
FFE816
Timer 1
12
FFE716
FFE616
INT2
13
FFE516
FFE416
INT3
14
FFE316
FFE216
Key input
(Key-on wake up)
15
FFE116
FFE016
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O data
reception
At completion of serial I/O transmit
shift or when transmission buffer is
empty
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 1 underflow
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At falling of conjunction of input
level for port P2 (at input mode)
At falling of ADT input
ADT
16
FFDF16
FFDE16
A-D conversion
BRK instruction
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At completion of A-D conversion
17
FFDD16
FFDC16
At BRK instruction execution
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
Valid when serial I/O is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(valid when an “L” level is applied)
Valid when ADT interrupt is selected
External interrupt
(Valid at falling)
Valid when A-D interrupt is
selected
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
21
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit or the interrupt source select bit
to “1”.
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding interrupt enable bit to “1” (enabled).
■Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
Timer Y mode register (address 2816)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: A-D control regsiter (address 3416)
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 16 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT3 interrupt edge selection bit
Not used (return “0” when read)
b7
b0
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
(IREQ1 : address 003C16)
b7
b0
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt request register 2
(IREQ2 : address 003D16)
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Timer 1 interrupt request bit
INT2 interrupt request bit
INT3 interrupt request bit
Key input interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
Interrupt control register 1
(ICON1 : address 003E16)
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
b7
b0
Interrupt control register 2
(ICON2 : address 003F16)
CNT R0 interrupt enable bit
CNT R1 interrupt enable bit
Timer 1 interrupt enable bit
INT2 interrupt enable bit
INT3 interrupt enable bit
Key input interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 17 Structure of interrupt-related registers
22
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt (Key-on Wake Up)
A Key-on wake up interrupt request is generated by applying a
falling edge to any pin of port P2 that have been set to input mode.
In other words, it is generated when AND of input level goes from
“1” to “0”. An example of using a key input interrupt is shown in
Figure 18, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P20–P23.
Port PXx
“L” level output
PULL register A
Bit 2 = “1”
Port P27
direction register = “1”
✽
✽✽
✽
✽✽
✽
✽✽
Key input interrupt request
Port P27
latch
P27 output
Port P26
direction register = “1”
Port P26
latch
P26 output
Port P25
direction register = “1”
Port P25
latch
P25 output
Port P24
direction register = “1”
✽
✽✽
✽
✽✽
✽
✽✽
✽
✽✽
Port P24
latch
P24 output
Port P23
direction register = “0”
P23 input
Port P2
Input reading circuit
Port P23
latch
Port P22
direction register = “0”
P22 input
Port P22
latch
Port P21
direction register = “0”
P21 input
✽
P20 input
Port P21
latch
Port P20
direction register = “0”
✽✽
Port P20
latch
✽ P-channel transistor for pull-up
✽ ✽ CMOS output buffer
Fig. 18 Connection example when using key input interrupt and port P2 block diagram
23
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
Read and write operation on 16-bit timer must be performed for
both high- and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing
during the read operation.
The 3825 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “00 16”,
an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
Real time port
control bit “1”
Data bus
P52 data for real time port
Q D
P52
Latch
P52 direction register “0”
P52 latch
Real time port
control bit “1”
Q D
P53
Latch
P53 direction register “0”
P53 latch
P53 data for real time port
Real time port
control bit “0”
P54/CNTR0
Timer X mode register
write signal
“1”
f(XIN)/16
(f(XCIN)/16 in low-speed mode✽)
Timer X stop
control bit
Timer X operatCNT R0 active
edge switch bit ing mode bits
“00”,“01”,“11”
“0”
Timer X write
control bit
Timer X (low) latch (8)
Timer X (high) latch (8)
Timer X (low) (8)
Timer X (high) (8)
Timer X
interrupt
request
“10”
“1”
Pulse width
measurement
mode
CNTR0 active
edge switch bit “0”
QS
Timer Y operating mode bits
“00”,“01”,“10”
T
“1”
P54 direction register
CNTR0
interrupt
request
Pulse output mode
Q
Pulse width HL continuously measurement mode
P54 latch
“11”
Rising edge detection
Pulse output mode
Period
measurement mode
Falling edge detection
CNT R1 active
edge switch bit
“0”
P55/CNTR1
f(XIN)/16
(f(XCIN)/16 in low-speed mode])
Timer Y stop
control bit
Timer Y (low) latch (8)
“00”,“01”,“11”
Timer Y (high) latch (8)
Timer Y (low) (8)
Timer Y (high) (8)
“10” Timer Y operating
mode bits
“1”
f(XIN)/16
(f(XCIN)/16 in low-speed mode])
Timer 1 count source
selection bit
“0”
Timer 1 latch (8)
XCIN
CNT R1
interrupt
request
Timer 2 count source
selection bit
Timer 2 latch (8)
“0”
Timer 1 (8)
Timer 2 (8)
“1”
“1”
Timer 2 write
control bit
Timer Y
interrupt
request
Timer 1
interrupt
request
Timer 2
interrupt
request
f(XIN)/16
(f(XCIN)/16 in low-speed mode])
TOUT output
active edge
switch bit “0”
P56/TOUT
TOUT output
control bit
QS
T
“1”
P56 latch
Q
P56 direction register
TOUT output control bit
f(XIN)/16(f(XCIN)/16 in low-speed mode])
✽Internal
clock φ = XCIN/2.
Fig. 19 Timer block diagram
24
“0”
Timer 3 latch (8)
Timer 3 (8)
“1”
Timer 3 count
source selection bit
Timer 3
interrupt
request
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR 0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the corresponding port P54 direction register to output mode.
(3) Event counter mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to input mode.
(4) Pulse width measurement mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the corresponding port P5 4 direction register to input
mode.
b7
b0
Timer X mode register
(TXM : address 002716)
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
P52 data for real time port
P53 data for real time port
Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNT R0 active edge switch bit
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width measurement
mode
Falling edge active for CNTR0 interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width measurement
mode
Rising edge active for CNT R0 interrupt
Timer X stop control bit
0 : Count start
1 : Count stop
Fig. 20 Structure of timer X mode register
●Timer X Write Control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, unexpected value may be set in
the high-order counter when the writing in high-order latch and the
underflow of timer X are performed at the same timing.
●Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P5 2 and P5 3 each time the timer X
underflows. (However, if the real time port control bit is changed
from “0” to “1” after set of the real time port data, data are output
independent of the timer X operation.) If the data for the real time
port is changed while the real time port function is valid, the
changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
■Note on CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
25
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Period measurement mode
CNTR 1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR 1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corresponding port P55 direction register to input mode.
(3) Event counter mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode.
(4) Pulse width HL continuously measurement mode
CNTR 1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P55 direction register to input mode.
■Note on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR 1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
26
b7
b0
Timer Y mode register
(TYM : address 002816)
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR1 interrupt
Timer Y stop control bit
0 : Count start
1 : Count stop
Fig. 21 Structure of timer Y mode register
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer
whenever the count source is changed.
●Timer 2 Write Control
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
●Timer 2 Output Control
When the timer 2 (T OUT) is output enabled, an inversion signal
from pin TOUT is output each time timer 2 underflows.
In this case, set the port P56 shared with the port TOUT to the output mode.
b7
b0
Timer 123 mode register
(T123M :address 002916)
TOUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
TOUT output control bit
0 : TOUT output disabled
1 : TOUT output enabled
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
1 : f(XCIN)
Not used (return “0” when read)
Note: Internal clock φ is f(XCIN)/2 in the low-speed mode.
■Note on Timer 1 to Timer 3
When the count source of timers 1 to 3 is changed, the timer
counting value may be changed large because a thin pulse is generated in count input of timer. If timer 1 output is selected as the
count source of timer 2 or timer 3, when timer 1 is written, the
counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Fig. 22 Structure of timer 123 mode register
27
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
(1) Clock Synchronous Serial I/O Mode
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O control register to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB (address 001816).
Data bus
Serial I/O control register
Address 001816
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
P44/RXD
Address 001A16
Shift clock
Clock control circuit
P46/SCLK
Serial I/O synchronization
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN)
(f(XCIN) in low-speed mode)
1/4
P47/SRDY
F/F
Baud rate generator
1/4
Address 001C16
Clock control circuit
Falling-edge detector
Shift clock
P45/TXD
Transmit shift register
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address 001916
T ran smit buffer register (T B)
Address 001816
Data bus
Serial I/O status register
Fig. 23 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RXD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY
Write signal to receive/transmit
buffer register (address 001816)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1 : T he transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE = 1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
3 : T he receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 24 Operation of clock synchronous serial I/O function
28
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
P44/RXD
Serial I/O control register Address 001A16
OE
Receive buffer register
Character length selection bit
STdetector
7 bits
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/16
8 bits
UART control register
Address 001B16
SP detector
PE FE
Clock control circuit
Serial I/O synchronization clock selection bit
P46/SCLK
BRG count source selection bit
f(XIN)
( f(XCIN) in low-speed
mode)
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
1/4
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
1/16
P45/TXD
Transmit shift register
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Serial I/O status register Address 001916
Transmit buffer register
Address 001816
Data bus
Fig. 25 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE=0
TBE=0
TSC=0
TBE=1
Serial output TXD
TSC=1✽
TBE=1
ST
D0
D1
SP
ST
D0
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
✽ Generated
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
D1
SP
ST
D0
D1
SP
at 2nd bit in 2-stop-bit mode
RBF=1
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : T he transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O control register.
3 : T he receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 26 Operation of UART serial I/O function
29
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Buffer/Receive Buffer Register (TB/
RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is writeonly and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer register is “0”.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE
(bit 7 of the Serial I/O Control Register) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register contains eight control bits for the serial I/O function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
■Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
➀Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃Set the serial I/O transmit interrupt enable bit to “1” (enabled).
30
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O status register
(SIOSTS : address 001916)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
b0
Serial I/O control register
(SIOCON : address 001A16)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Serial I/O synchronization clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronized serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronized serial I/O is
selected.
External clock input divided by 16 when UART is selected.
Overrun error flag (OE)
0: No error
1: Overrun error
SRDY output enable bit (SRDY)
0: P47 pin operates as ordinary I/O pin
1: P47 pin operates as SRDY output pin
Parity error flag (PE)
0: No error
1: Parity error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Framing error flag (FE)
0: No error
1: Framing error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Not used (returns “1” when read)
Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
b7
b7
b0 UART control regi ster
(UART CON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P44–P47 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P44–P47 operate as serial I/O pins)
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
Fig. 27 Structure of serial I/O control registers
31
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
Comparator and Control Circuit
The functional blocks of the A-D converter are described below.
The comparator and control circuit compare an analog input voltage with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500kHz during A-D conversion.
Use the clock divided from the main clock XIN as the internal clock
φ.
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the AD conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 controls the transistor which breaks the through
current of the resistor ladder. When bit 5, which is the AD external
trigger valid bit, is set to “1”, this bit enables A-D conversion even
by a falling edge of an ADT input. Set ports which share with ADT
pins to input when using an A-D external trigger.
b7
b0
A-D control register
(ADCON : address 003416)
Analog input pin selection bits
0 0 0 : P60/AN0
0 0 1 : P61/AN1
0 1 0 : P62/AN2
0 1 1 : P63/AN3
1 0 0 : P64/AN4
1 0 1 : P65/AN5
1 1 0 : P66/AN6
1 1 1 : P67/AN7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
VREF input switch bit
0 : OFF
1 : ON
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
1 : Interrupt request at ADT
input falling
Not used (returns “0” when read)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P67/AN7–P60/
AN0.
Fig. 28 Structure of A-D control register
Data bus
b7
b0
A-D control register
P57/ADT
3
ADT/A-D interrupt request
A-D control circuit
P60/AN0
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
Channel selector
P61/AN1
Comparator
A-D conversion
register
8
Resistor ladder
P67/AN7
AVSS
Fig. 29 A-D converter block diagram
32
VREF
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD DRIVE CONTROL CIRCUIT
The 3825 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display RAM
Segment output enable register
LCD mode register
Voltage multiplier
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 40 segment output pins and 4 common output pins
can be used.
Up to 160 pixels can be controlled for LCD display. When the LCD
•
•
•
•
•
•
•
•
•
b7
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel.
Table 10. Maximum number of display pixels at each duty ratio
Duty ratio
2
3
4
Maximum number of display pixel
80 dots
or 8 segment LCD 10 digits
120 dots
or 8 segment LCD 15 digits
160 dots
or 8 segment LCD 20 digits
b0
Segment output enable register
(SEG : address 003816)
Segment output enable bit 0
0 : Output ports P30–P35
1 : Segment output SEG18–SEG23
Segment output enable bit 1
0 : Output ports P36, P37
1 : Segment output SEG24,SEG25
Segment output enable bit 2
0 : Output ports P00–P05
1 : Segment output SEG26–SEG31
Segment output enable bit 3
0 : Output ports P06,P07
1 : Segment output SEG32,SEG33
Segment output enable bit 4
0 : Output port P10
1 : Segment output SEG34
Segment output enable bit 5
0 : Output ports P11–P15
1 : Segment output SEG35–SEG39
Not used (return “0” when read)
(Do not write “1” to this bit)
b7
b0
LCD mode register
(LM : address 003916)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 duty (use COM0, COM1)
1 0 : 3 duty (use COM0–COM2)
1 1 : 4 duty (use COM0–COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multiplier control bit
0 : Voltage multiplier disable
1 : Voltage multiplier enable
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of Clock input
1 0 : 4 division of Clock input
1 1 : 8 division of Clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
Fig. 30 Structure of segment output enable register and LCD mode register
33
Fig. 31 Block diagram of LCD controller/driver
34
Address 004116
Level
shift
Level
shift
Level
shift
SEG0
SEG1
SEG2
SEG3
Segment Segment Segment Segment
driver
driver
driver
driver
Level
shift
Selector Selector Selector Selector
Address 004016
Data bus
P30/SEG18
Level
shift
Bias control bit
VSS VL1 VL2 VL3 C1 C2
Bias control
Voltage multiplier
control bit
LCD display RAM
P14/SEG38 P15/SEG39
Segment Segment
driver
driver
Level
shift
Selector Selector
Address 005316
Level
Shift
Level
Shift
Level
Shift
COM0 COM1 COM2 COM3
Common Common Common Common
driver
driver
driver
driver
Level
Shift
2
Timing controller
2
LCD circuit
divider division
ratio selection bits
Duty ratio selection bits
LCD enable bit
LCDCK
LCD
divider
“1”
f(XIN)/8192
(f(XCIN)/8192 in lowspeed mode)
LCDCK count source
selection bit
“0”
f(XCIN)/ 32
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Voltage Multiplier (3 Times)
Table 11. Bias control and applied voltage to VL1–VL3
The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin
V L1. (However, when using a 1/2 bias, connect V L1 and VL2 and
apply voltage by external resistor division.)
The voltage multiplier control bit (bit 4 of the LCD mode register)
controls the voltage multiplier.
When voltage is input to the VL1 pin during operating the voltage
multiplier, voltage that is twice as large as VL1 occurs at the VL2
pin, and voltage that is three times as large as V L1 occurs at the
VL3 pin.
When using the voltage multiplier; after applying 1.3 V ≤ Voltage ≤ 2.3 V
to the V L1 pin, set the voltage multiplier control bit to “1” to select the
voltage multiplier enable.
When not using the voltage multiplier, apply proper voltage to the
LCD power input pins (VL1–VL3).
Bias Control and Applied Voltage to LCD
Power Input Pins
To the LCD power input pins (VL1–VL3), apply the voltage shown
in Table 11 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Bias value
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
VL2=VL1=1/2 VLCD
1/3 bias
1/2 bias
Note : V LCD is the maximum value of supplied voltage for the
LCD panel.
Table 12. Duty ratio control and common pins used
Duty
ratio
Duty ratio selection bits
2
Bit 1
0
Bit 0
1
3
4
1
1
0
1
Common pins used
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
Notes 1: COM2 and COM3 are open.
2: COM3 is open.
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
Contrast control
VL3
VL3
Contrast control
VL3
R1
VL2
VL2
C2
C2
R4
VL2
Open
C2
Open
C1
Open
R2
C1
C1
VL1
VL1
Open
VL1
R3
1/3 bias
when using the voltage multiplier
R1=R2=R3
1/3 bias
when not using the voltage multiplier
R5
R4=R5
1/2 bias
Fig. 32 Example of circuit at each bias
35
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD Display RAM
LCD Drive Timing
Address 004016 to 005316 is the designated RAM for the LCD display. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation;
f(LCDCK)=
(frequency of count source for LCDCK)
(divider division ratio for LCD)
Frame frequency=
f(LCDCK)
duty ratio
Bit
7
6
5
4
3
2
1
0
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
Fig. 33 LCD display RAM map
36
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
SEG1
SEG0
SEG3
SEG2
SEG5
SEG4
SEG7
SEG6
SEG9
SEG8
SEG11
SEG10
SEG13
SEG12
SEG15
SEG14
SEG17
SEG16
SEG19
SEG18
SEG21
SEG20
SEG23
SEG22
SEG25
SEG24
SEG27
SEG26
SEG29
SEG28
SEG31
SEG30
SEG33
SEG32
SEG35
SEG34
SEG37
SEG36
SEG39
SEG38
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
VL2=VL1
VSS
COM0
COM1
COM2
COM3
VL3
VSS
SEG0
OFF
COM3
ON
COM2
COM1
OFF
COM0
COM3
ON
COM2
COM1
COM0
1/3 duty
VL3
VL2=VL1
VSS
COM0
COM1
COM2
VL3
VSS
SEG0
ON
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
1/2 duty
VL3
VL2=VL1
VSS
COM0
COM1
VL3
VSS
SEG0
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1
COM0
COM1
COM0
COM1
COM0
COM1
COM0
Fig. 34 LCD drive waveform (1/2 bias)
37
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
VL2
VL1
VSS
COM0
COM1
COM2
COM3
VL3
SEG0
VSS
OFF
COM3
ON
COM2
COM1
OFF
COM0
COM3
ON
COM2
COM1
COM0
1/3 duty
VL3
VL2
VL1
VSS
COM0
COM1
COM2
VL3
SEG0
VSS
ON
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
1/2 duty
VL3
VL2
VL1
VSS
COM0
COM1
VL3
SEG0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1
COM0
COM1
COM0
COM1
COM0
COM1
COM0
Fig. 35 LCD drive waveform (1/3 bias)
38
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK OUTPUT FUNCTION
Selection of Output Clock Frequency
Input/output ports P40 and P41 can output clock. The input/output
ports and clock output function are put under double function controlled by the clock output control register (address 002A16).
Bit 2 (output clock frequency selection bit) of the clock output control register selects an output clock frequency.
When setting the output clock frequency selection bit to “0”, port
P40 becomes the frequency of f(XIN ) and port P41 becomes the
frequency of f(XIN)/5.
At this time, the output pulse of port P40 depends on the XIN input
pulse, while the output pulse of port P41 has duty ratio of about
40%.
When setting the output clock frequency selection bit to “1”, port
P40 becomes the frequency of f(XIN)/2 and port P41 becomes the
frequency of f(XIN)/10. At this time, the output pulses of both ports
P40 and P41 have duty ratio of 50%.
Selection of Input/Output Ports and Clock
Output Function
Bits 0 and 1 of the clock output control register can select between
the input/output ports and the clock output function.
When selecting the clock output function, clocks are output while
the direction register of ports P40 and P41 are set to output.
At the next cycle of rewriting the clock output control bit, P4 0 is
switched between the port output and the clock output.
In synchronization with the fall of the clock (resulting from dividing
XIN by 5) on rewriting the clock output control bit, P41 is switched
between the port output and the clock output.
b7
b0
Clock output control register
(TCON : address 002A16)
P40 clock output control bit
0 : I/O port
1 : Clock output
P41 clock output control bit
0 : I/O port
1 : Clock output
Output clock frequency selection bit
0 : P40←f(XIN), P41←f(XIN)/5
1 : P40←f(XIN)/2, P41←f(XIN)/10
Not used (return “0” when read)
Fig. 36 Structure of clock output control register
P40 port latch
“0”
“0”
XIN
P40 clock output
control bit
P40
1/2
“1” Output clock
frequency
selection bit
“1”
P40 direction register
P41 port latch
“0”
“0”
P41 clock output
control bit
1/5
P41
1/2
“1” Output clock
frequency
selection bit
“1”
P41 direction register
Fig. 37 Clock output function block diagram
39
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the quartz-crystal oscillator should be stable), reset is
released. After the reset is completed, the program starts from the
address contained in address FFFD16 (high-order byte) and address FFFC 16 (low-order byte). Make sure that the reset input
voltage meets V IL spec. when a power source voltage passes
VCC(min.).
Power on
RESET
VCC
Power
source
voltage
0V
Reset input
voltage
VIL spec.
0V
RESET
VCC
Power source voltage
detection circuit
Fig. 38 Example of reset circuit
Address
Register contents
(1) Port P0
000016
0016
(2) Port P1
000216
0016
(3) Port P1 output control register
000316
0016
(4) Port P2
000416
0016
(5) Port P2 direction register
000516
0016
(6) Port P3
000616
0016
(7) Port P4
000816
0016
(8) Port P4 direction register
000916
0016
(9) Port P5
000A16
0016
(10) Port P5 direction register
000B16
0016
(11) Port P6
000C16
0016
(12) Port P6 direction register
000D16
0016
(13) Port P7
000E16
0016
(14) Port P7 direction register
000F16
0016
(15) Port P8
001016
0016
(16) Port P8 direction register
001116
0016
(17) PULL register A
001616
0116
(18) PULL register B
001716
0016
(19) Serial I/O status register
001916 1 0 0 0 0 0 0 0
(20) Serial I/O control register
001A16
(21) UART control register
001B16 1 1 1 0 0 0 0 0
(22) Timer X (low)
002016
FF16
(23) Timer X (high)
002116
FF16
(24) Timer Y (low)
002216
FF16
(25) Timer Y (high)
002316
FF16
(26) Timer 1
002416
FF16
(27) Timer 2
002516
0116
(28) Timer 3
002616
FF16
(29) Timer X mode register
002716
00001166
(30) Timer Y mode register
002816
0016
(31) Timer 123 mode register
002916
0016
(32) Clock output control register
002A16
0016
(33) A-D control register
003416 0 0 0 0 1 0 0 0
(34)
003816
0016
(35) LCD mode register
003916
0016
(36)
003A16
0016
Segment output enable register
Interrupt edge selection register
0016
(37) CPU mode register
003B16 0 1 0 0 1 0 0 0
(38) Interrupt request register 1
003C16
0016
(39) Interrupt request register 2
003D16
0016
(40) Interrupt control register 1
003E16
0016
(41) Interrupt control register 2
003F16
0016
(42) Processor status register
(43) Program counter
(PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
(PCH)
Contents of address FFFD16
(PCL)
Contents of address FFFC16
Note: The contents of all other registers and RAM are undefined after
reset, so they must be initialized by software.
✕ : Undefined
Fig. 39 Internal state of microcomputer immediately after reset
40
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XIN
φ
RESET
Internal reset
Reset address from
vector table
Address
?
?
?
?
FFFC
FFFD
ADL
Data
ADH, ADL
A DH
SYNC
XIN : about 8000
clock cycles
Notes 1 : XIN and φ are in the relationship : f(XIN) = 8•f(φ)
2 : A question mark (?) indicates an undefined status that depends on the previous status.
Fig. 40 Reset sequence
41
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 3825 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No external resistor is needed between X IN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
To supply a clock signal externally, input it to the XIN pin and make
the X OUT pin open. The sub-clock X CIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the X IN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2)High-speed mode
The internal clock φ is half the frequency of XIN.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116”.
Either X IN or X CIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2.
The bits of the timer 123 mode register except bit 4 are cleared to
“0”. Set the timer 1 and timer 2 interrupt enable bits to disabled
(“0”) before executing the STP instruction.
Oscillator restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until
timer 2 underflows. This allows time for the clock circuit oscillation
to stabilize.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. The states of XIN and XCIN are the same as the state before the executing the WIT instruction. The internal clock restarts
at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
(3) Low-speed mode
• The internal clock φ is half the frequency of XCIN.
• A low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bit 5
of the CPU mode register to “1”.
When the main clock XIN is restarted, set enough time for oscillation to stabilize by programming.
Note: If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN and X CIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power-on and at returning from stop
mode. When switching the mode between middle/highspeed and low-speed, set the frequency in the condition
that f(XIN) > 3•f(XCIN).
XCIN XCOUT
Rf
XIN
Rd
CCOUT
CCIN
XOUT
CI N
COUT
Fig. 41 Ceramic resonator circuit
XCIN
Rf
XCOUT
XI N
XOUT
Open
Rd
External oscillation circuit
CCIN
CCOUT
VCC
VSS
Fig. 42 External clock input circuit
42
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCOUT
XCIN
“1”
“0”
Port XC switch bit
XIN
XOUT
Timer 1 count
source selection
bit
Internal system clock selection bit
(Note)
Low-speed mode
“1”
1/2
“0”
Middle-/High-speed mode
Timer 2 count
source selection
bit
“1”
1/4
1/2
Timer 1
“0”
“0”
Timer 2
“1”
Main clock division ratio selection bit
Middle-speed mode
“1”
Timing φ
(Internal clock)
“0”
High-speed mode
or Low-speed mode
Main clock stop bit
Q
S
S
R
STP instruction
WIT
instruction
R
Q
Q
S
R
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Note: When using the low-speed mode, set the port XC switch bit to “1”.
Fig. 43 Clock generating circuit block diagram
43
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
CM6
“0”
”
“0
CM
” 6
“1 M
C
”
“1
”
“0
“0 CM
” 4
C
“1 M
” 6
“1
”
“0
”
CM6
Middle-speed mode (f(φ) = 1 MHz)
“1”
High-speed mode (f(φ) = 4 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
CM7
“1”
CM6
“1”
“0”
CM7 = 1 (32 kHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
”
“0
CM5
“1”
5
Low-spe ed mode (f(φ) = 16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 1 (Middle-speed)
CM5 = 1 (8 MHz stopped)
CM4 = 1 (32 kHz oscillating)
CM”
“1
6
”
“0
CM
”
“1
CM6
“1”
Low-speed mode (f(φ) =16 kHz)
“0”
C
“0 M5
CM”
“1
6
”
“1
”
“0
”
CM7 = 1 (32 kHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
“0”
Low-speed mode (f(φ) =16 kHz)
CM5
“1”
CM7
“0”
“0”
“0”
CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillatin g)
CM7 = 0 (8 MHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz stopped)
“1”
CM4
“1”
4
High-speed mode (f(φ) = 4 MHz)
“0”
“0”
“1”
CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz sto pped)
CM4
“1”
Middle-speed mod e (f(φ) = 1 MHz)
Low-speed mode (f(φ) =16 kHz)
“0”
CM7 = 1 (32 kHz selected)
CM6 = 0 (High-speed)
CM5 = 1 (8 MHz stopped)
CM4 = 1 (32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port Xc switch bit
0: I/O port
1: XCIN, XCOUT
CM5 : Main clock (XIN–XOUT) stop bit
0: Oscillating
1: Stopped
CM6 : Main clock division ratio selection bit
0: f(XIN)/2 (high-speed mode)
1: f(XIN)/8 (middle-speed mode)
CM7 : Internal system clock selection bit
0: XIN–XOUT selected
(middle-/high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait
mode is ended.
3: Timer and LCD operate in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.
6: Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/highspeed mode.
7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. f indicates the internal clock.
Fig. 44 State transitions of internal clock φ
44
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Processor Status Register
Serial I/O
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to
“1”.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
Interrupt
A-D Converter
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a
BBC or BBS instruction.
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is at least 500kHz during an A-D conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direction registers.
45
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM production:
1.Mask ROM Order Confirmation Form✽
2.Mark Specification Form✽
3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
Table 13. Programming adapter
✽For the mask ROM confirmation and the mark specifications, refer to the “Mitsubishi MCU Technical Information” Homepage
(http://www.infomicom.mesc.co.jp/indexe.htm).
Package
Name of Programming Adapter
100PFB-A
PCA4738H-100A
100P6Q-A
PCA4738G-100A
100P6S-A
PCA4738F-100A
100D0
PCA4738L-100A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 45 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 45 Programming and testing of One Time PROM version
46
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Standard, One Time PROM Version)
Table 14. Absolute maximum ratings (Standard, One time PROM version)
Symbol
Parameter
Conditions
Power source voltage
VCC
Input voltage P16, P17, P20–P27, P40–P47,
VI
P50–P57, P60–P67, P80, P81
Input voltage P70–P77
VI
Input voltage VL1
VI
All voltages are based on VSS.
Output transistors are cut off.
Input voltage VL2
VI
VI
VI
VI
VO
Input voltage VL3
Input voltage C1, C2
Input voltage RESET, XIN
VO
Output voltage P00–P07, P10–P15, P30–P37
VO
VO
VO
VO
Pd
Topr
Tstg
Output voltage C1, C2
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81
Output voltage VL3
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
Operating temperature
Ratings
Unit
–0.3 to 7.0
V
–0.3 to VCC +0.3
V
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 7.0
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VCC
V
V
V
V
V
V
V
V
–0.3 to VL3
V
–0.3 to VCC +0.3
V
–0.3 to 7.0
–0.3 to VL3
V
V
V
mW
°C
°C
At output port
At segment output
–0.3 to VCC +0.3
300
Ta = 25°C
–20 to 85
Storage temperature
–40 to 125
Table 15. Recommended operating conditions (Standard, One time PROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
Parameter
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
VCC
Power source voltage
VSS
VREF
AVSS
Power source voltage
A-D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
“H” input voltage
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
“H” input voltage
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
“H” input voltage
RESET
“H” input voltage
XIN
“L” input voltage
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
“L” input voltage
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
“L” input voltage
RESET
“L” input voltage
XIN
VIA
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
Min.
4.0
2.5
2.5
Limits
Typ.
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
Unit
V
AVSS
VCC
V
V
V
V
0.7VCC
VCC
V
0.8VCC
0.8VCC
0.8VCC
VCC
VCC
VCC
V
V
V
0
0.3VCC
V
0
0
0
0.2VCC
0.2VCC
0.2VCC
V
V
V
2.0
VCC
0
47
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 16. Recommended operating conditions (Standard, One time PROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
ΣIOH(peak)
ΣIOH(peak)
“H” total peak output current
ΣIOL(peak)
“L” total peak output current
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
ΣIOH(avg)
Limits
Parameter
“H” total peak output current
Min.
Typ.
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P40–P47,P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P40–P47,P50–P57, P60–P67, P80, P81 (Note 1)
P71–P77 (Note 1)
P00–P07,P10–P17, P20–P27, P30–P37 (Note 1)
P40–P47, P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
Max.
–20
Unit
mA
–20
mA
20
20
40
mA
mA
–10
mA
mA
–10
mA
ΣIOL(avg)
“L” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
10
ΣIOL(avg)
“L” total average output current P40–P47, P50–P57, P60–P67, P80, P81 (Note 1)
ΣIOL(avg)
IOH(peak)
IOH(peak)
“L” total average output current P71–P77 (Note 1)
10
20
mA
mA
mA
–0.5
mA
–5.0
mA
IOL(peak)
IOL(peak)
“L” peak output current
P00–P07, P10–P15, P30–P37 (Note 2)
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 2)
P00–P07, P10–P15, P30–P37 (Note 2)
5.0
mA
10
mA
IOH(avg)
“H” average output current
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P70–P77, P80, P81 (Note 2)
P00–P07, P10–P15, P30–P37 (Note 3)
–0.1
mA
IOH(avg)
“H” average output current
–2.5
mA
IOL(avg)
2.5
mA
IOL(avg)
“L” average output current
“L” average output current
5.0
mA
f(CNTR0)
f(CNTR1)
Input frequency for timers X and Y
(duty cycle 50%)
4.0
MHz
(VCC ≤ 4.0 V)
f(XIN)
Main clock input oscillation frequency
(Note 4)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
“H” peak output current
“H” peak output current
“L” peak output current
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
P00–P07, P10–P15, P30–P37 (Note 3)
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
(4.0 V ≤ VCC ≤ 5.5 V)
(2✕VCC) MHz
–4
High-speed mode
(VCC ≤ 4.0 V)
Middle-speed mode
f(XCIN)
Sub-clock input oscillation frequency (Note 4, 5)
32.768
8.0
MHz
(4✕VCC)
–8
MHz
8.0
MHz
50
kHz
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
48
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 17. Electrical characteristics (Standard, One time PROM version)
(VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
VOH
“H” output voltage P00–P07, P10–P15, P30–P37
VOH
“H” output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81 (Note)
VOL
VOL
“L” output voltage P00–P07, P10–P15, P30–P37
“L” output voltage P16, P17, P20–P27,P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81 (Note)
VT+ – VT–
Hysteresis
VT+ – VT–
VT+ – VT–
Hysteresis
Hysteresis
“H” input current
IIH
INT0–INT3, ADT, CNTR0,
CNTR1, P20–P27
SCLK, RXD
RESET
P16, P17, P20–P27,P40–P47,
P50–P57, P60–P67, P70–P77,
P80, P81
IIH
“H” input current
RESET
IIH
“H” input current
XIN
“L” input current
P16, P17, P20–P27,P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81
IIL
IIL
IIL
IIL
“L” input current
P70
“L” input current
“L” input current
RESET
XIN
ILOAD
Output load current P00–P07, P10–P15, P30–P37
ILEAK
Output leak current P00–P07, P10–P15, P30–P37
Test conditions
IOH = –0.1 mA
IOH = –25 µA
VCC = 2.5 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 2.5 V
IOL = 5 mA
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
IOL = 10 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 2.5 V
Min.
VCC–2.0
Limits
Typ.
V
V
VCC–2.0
VCC–0.5
V
VCC–1.0
V
V
2.0
0.5
V
1.0
V
2.0
0.5
V
1.0
V
V
V
0.5
V
0.5
0.5
V
V
VI = VCC
VI = VSS
VI = VSS
VCC = 5.0 V, VO = VCC, Pull-downs “on”
Output transistors “off”
VCC = 3.0 V, VO = VCC, Pull-downs “on”
Output transistors “off”
VO = VCC, Pull-downs “off”
Output transistors “off”
VO = VSS, Pull-downs “off”
Output transistors “off”
Unit
VCC–1.0
RESET: VCC=2.5 V to 5.5 V
VI = VCC
VI = VCC
VI = VSS
Pull-ups “off”
VCC = 5 V, VI = VSS
Pull-ups “on”
VCC = 3 V, VI = VSS
Pull-ups “on”
Max.
5.0
µA
5.0
µA
µA
4.0
–5.0
µA
–30
–70
–140
µA
–6.0
–25
–45
µA
–5.0
µA
–5.0
µA
µA
–4.0
30
70
140
µA
6.0
25
45
µA
5.0
µA
–5.0
µA
Note: When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P80 is different from the
value above mentioned.
49
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 18. Electrical characteristics (Standard, One time PROM version)
(VCC =2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VRAM
ICC
Parameter
RAM retention voltage
Power source current
Test conditions
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
VL1
Power source voltage
IL1
Power source current (VL1)
(Note)
Ta = 25 °C
Limits
Typ.
When using voltage multiplier
VL1 = 1.8 V
VL1 < 1.3 V
Max.
5.5
V
13
mA
1.6
3.2
mA
25
36
µA
7.0
14
µA
15
22
µA
4.5
9.0
µA
0.1
1.0
10
1.3
Unit
6.4
Ta = 85 °C
Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
50
Min.
2.0
1.8
3.0
10
2.3
6.0
50
µA
V
µA
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 19. A-D converter characteristics (Standard, One time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-/high-speed mode, unless otherwise noted.)
Symbol
Parameter
Test conditions
–
–
Resolution
Absolute accuracy (excluding quantization error)
VCC = VREF = 5 V
tCONV
Conversion time
f(XIN) = 8 MHz
RLADDER
IVREF
IIA
Ladder resistor
Reference input current
Analog port input current
VREF = 5 V
Min.
Limits
Typ.
Max.
8
±2
12.5
(Note)
Unit
Bits
LSB
µs
12
35
100
kΩ
50
150
200
µA
5.0
µA
Note : When an internal trigger is used in middle-speed mode, it is 14 µs.
51
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 20. Timing requirements 1 (Standard, One time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RXD–SCLK)
th(SCLK–RXD)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
Min.
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 21. Timing requirements 2 (Standard, One time PROM version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
Parameter
Min.
2
125
45
40
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
tc(CNTR)
CNTR0, CNTR1 input cycle time
500/
(VCC–2)
ns
twH(CNTR)
CNTR0, CNTR1 input “H” pulse width
250/
(VCC–2)–20
ns
twL(CNTR)
CNTR0, CNTR1 input “L” pulse width
250/
(VCC–2)–20
ns
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
INT0 to INT3 input “H” pulse width
230
230
2000
950
950
400
200
ns
ns
ns
ns
ns
ns
ns
twL(SCLK)
tsu(RXD–SCLK)
th(SCLK–RXD)
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
52
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 22. Switching characteristics 1 (Standard, One time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Limits
Min.
Typ.
Max.
tc(SCLK)/2–30
tc(SCLK)/2–30
140
–30
10
10
30
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Table 23. Switching characteristics 2 (Standard, One time PROM version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Min.
tc(SCLK)/2–50
tc(SCLK)/2–50
Limits
Typ.
Max.
350
–30
20
20
50
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
53
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Extended Operating Temperature Version)
Table 24. Absolute maximum ratings (Extended operating temperature version)
Symbol
VCC
VI
VI
VI
VI
VI
VI
VI
VO
VO
VO
VO
VO
VO
Pd
Topr
Tstg
Parameter
Ratings
Unit
–0.3 to 7.0
V
–0.3 to VCC +0.3
V
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 7.0
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VCC
–0.3 to VL3
V
V
V
V
V
V
V
V
V
–0.3 to VCC +0.3
V
–0.3 to 7.0
–0.3 to VL3
V
V
V
mW
°C
°C
Conditions
Power source voltage
Input voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P80, P81
Input voltage P70–P77
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
All voltages are based on VSS.
Output transistors are cut off.
Input voltage RESET, XIN
Output voltage C1, C2
Output voltage P00–P07, P10–P15, P30–P37
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81
Output voltage VL3
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
At output port
At segment output
–0.3 to VCC +0.3
300
–40 to 85
–65 to 150
Ta = 25°C
Table 25. Recommended operating conditions (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted.)
Symbol
VCC
Parameter
Power source voltage
High-speed mode f(XIN)=8 MHz
Middle-speed mode
Ta = –20 to 85°C
f(XIN) = 8 MHz
Ta = –40 to –20°C
Low-speed mode
VSS
VREF
AVSS
VIA
Ta = –20 to 85°C
Ta = –40 to –20°C
Power source voltage
A-D conversion reference voltage
Analog power source voltage
Analog input voltage
AN0–AN7
VIL
“L” input voltage
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
RESET
XIN
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
VIL
VIL
“L” input voltage
RESET
“L” input voltage
XIN
VIH
VIH
VIH
VIH
VIL
54
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
Min.
4.0
2.5
3.0
2.5
3.0
Limits
Typ.
5.0
5.0
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
5.5
5.5
Unit
V
AVSS
VCC
V
V
V
V
0.7VCC
VCC
V
0.8VCC
0.8VCC
0.8VCC
VCC
VCC
VCC
V
V
V
0
0.3VCC
V
0
0
0
0.2VCC
V
0.2VCC
0.2VCC
V
2.0
VCC
0
V
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 26. Recommended operating conditions (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted.)
Symbol
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
Limits
Parameter
“H” total peak output current
“H” total peak output current
“L” total peak output current
Min.
Typ.
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P40–P47,P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
Unit
–20
mA
–20
mA
20
20
40
–10
mA
mA
mA
mA
–10
mA
10
10
20
–0.5
mA
mA
mA
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
P40–P47,P50–P57, P60–P67, P80, P81 (Note 1)
P71–P77 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P40–P47, P50–P57, P60–P67, P70–P71, P80, P81
(Note 1)
“L” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
“L” total average output current P40–P47, P50–P57, P60–P67, P80, P81 (Note 1)
“L” total average output current P71–P77 (Note 1)
“H” peak output current
P00–P07, P10–P15, P30–P37 (Note 2)
IOH(peak)
“H” peak output current
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 2)
–5.0
mA
IOL(peak)
mA
10
mA
IOH(avg)
“H” average output current
P00–P07, P10–P15, P30–P37 (Note 2)
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 2)
P00–P07, P10–P15, P30–P37 (Note 3)
5.0
IOL(peak)
“L” peak output current
“L” peak output current
–0.1
mA
IOH(avg)
“H” average output current
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
–2.5
mA
IOL(avg)
“H” average output current
P00–P07, P10–P15, P30–P37 (Note 3)
2.5
mA
IOL(avg)
“H” average output current
5.0
mA
4.0
MHz
ΣIOH(avg)
ΣIOH(avg)
f(CNTR0)
f(CNTR1)
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
Max.
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
(4.0 V ≤ VCC ≤ 5.5 V)
Input frequency for timers X and Y
(duty cycle 50%)
(VCC ≤ 4.0 V)
f(XIN)
Main clock input oscillation frequency
(Note 4)
f(XCIN)
Sub-clock input oscillation frequency (Note 4, 5)
mA
(2✕VCC)–4 MHz
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
8.0
High-speed mode
(VCC ≤ 4.0 V)
MHz
(4✕VCC)–8 MHz
Middle-speed mode
32.768
8.0
50
MHz
kHz
Notes 1 : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
2 : The peak output current is the peak current flowing in each port.
3 : The average output current is an average value measured over 100 ms.
4 : When the oscillation frequency has a duty cycle of 50%.
5 : When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
55
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 27. Electrical characteristics (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5V, Ta = –40 to –20°C, unless otherwise noted)
Symbol
Parameter
VOH
“H” output voltage P00–P07, P10–P15, P30–P37
VOH
“H” output voltage P16, P17, P20–P27,P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81 (Note)
VOL
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
“L” output voltage P00–P07, P10–P15, P30–P37
“L” output voltage P16, P17, P20–P27,P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81 (Note)
Hysteresis
INT0–INT3, ADT, CNTR0,
CNTR1, P20–P27
SCLK, RXD
Hysteresis
RESET
“H” input current
P16, P17, P20–P27,P40–P47,
P50–P57, P60–P67, P70–P77,
P80, P81
RESET
XIN
Hysteresis
IIH
IIH
IIH
“H” input current
“H” input current
“L” input current
IIL
P16, P17, P20–P27,P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81
IIL
IIL
IIL
“L” input current
P70
“L” input current
RESET
“L” input current
XIN
ILOAD
Output load current P00–P07, P10–P15, P30–P37
ILEAK
Output leak current P00–P07, P10–P15, P30–P37
Test conditions
IOH = –2.5 mA
IOH = –0.6 mA
VCC = 3.0 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 3.0 V
IOL = 5 mA
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 3.0 V
IOL = 10 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 3.0 V
Min.
VCC–2.0
Limits
Typ.
V
V
VCC–2.0
VCC–0.5
V
VCC–0.9
V
V
VO = VSS, Pull-downs “off”
Output transistors “off”
2.0
0.5
V
1.1
V
2.0
0.5
V
1.1
V
V
V
0.5
V
0.5
0.5
V
V
VI = VCC
VI = VSS
VI = VSS
VCC = 5.0 V, VO = VCC, Pull-downs “on”
Output transistors “off”
VCC = 3.0 V, VO = VCC, Pull-downs “on”
Output transistors “off”
VO = VCC, Pull-downs “off”
Output transistors “off”
Unit
VCC–0.9
RESET: VCC=2.5 V to 5.5 V
VI = VCC
VI = VCC
VI = VSS
Pull-ups “off”
VCC = 5 V, VI = VSS
Pull-ups “on”
VCC = 3 V, VI = VSS
Pull-ups “on”
Max.
5.0
µA
5.0
µA
µA
–5.0
µA
4.0
–30
–70
–140
µA
–6.0
–25
–45
µA
–5.0
µA
–5.0
µA
µA
–4.0
30
70
170
µA
6.0
25
55
µA
5.0
µA
–5.0
µA
Note : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P80 is different from the
value above mentioned.
56
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 28. Electrical characteristics (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted.)
Symbol
VRAM
Parameter
RAM retention voltage
Power source current
ICC
Test conditions
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
VL1
Power source voltage
IL1
Power source current (VL1)
(Note)
Min.
2.0
Ta = 25°C
Limits
Typ.
Unit
V
6.4
13
mA
1.6
3.2
mA
25
36
µA
7.0
14
µA
15
22
µA
4.5
9.0
µA
0.1
1.0
Ta = 85°C
When using voltage multiplier
VL1 = 1.8 V
VL1 < 1.3 V
Max.
5.5
µA
10
1.3
1.8
3.0
10
2.3
6.0
50
V
µA
Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
Table 29. A-D converter characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-/high-speed mode, unless otherwise noted.)
Symbol
Parameter
Test conditions
–
–
Resolution
Absolute accuracy (excluding quantization error)
VCC = VREF = 5 V
tCONV
Conversion time
f(XIN) = 8 MHz
RLADDER
IVREF
IIA
Ladder resistor
Reference input current
Analog iinput current
VREF = 5 V
Min.
Limits
Typ.
Max.
8
±2
12.5
(Note)
Unit
Bits
LSB
µs
12
35
100
kΩ
50
150
200
µA
5.0
µA
Note : When an internal trigger is used in middle-speed mode, it is 14 µs.
57
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 30. Timing reguirements 1 (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted.)
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RXD–SCLK)
th(SCLK–RXD)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
Min.
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 31. Timing reguirements 2 (Extended operating temperature version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, and VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –20°C, unless otherwise noted.)
Symbol
Parameter
Min.
2
125
45
40
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
tc(CNTR)
CNTR0, CNTR1 input cycle time
500/
(VCC–2)
ns
twH(CNTR)
CNTR0, CNTR1 input “H” pulse width
250/
(VCC–2)–20
ns
twL(CNTR)
CNTR0, CNTR1 input “L” pulse width
250/
(VCC–2)–20
ns
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RXD–SCLK)
th(SCLK–RXD)
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
230
230
2000
950
950
400
200
ns
ns
ns
ns
ns
ns
ns
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
58
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 32. Switching characteristics 1 (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted.)
Symbol
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Limits
Min.
Typ.
Max.
tc(SCLK)/2–30
tc(SCLK)/2–30
140
–30
10
10
30
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Table 33. Switching characteristics 2 (Extended operating temperature version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, and VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –20°C, unless otherwise noted.)
Limits
Symbol
Parameter
Typ.
Max.
Min.
twH(SCLK)
tc(SCLK)/2–50
Serial I/O clock output “H” pulse width
twL(SCLK)
tc(SCLK)/2–50
Serial I/O clock output “L” pulse width
td(SCLK–TXD)
Serial I/O output delay time (Note 1)
350
tv(SCLK–TXD)
–30
Serial I/O output valid time (Note 1)
tr(SCLK)
Serial I/O clock output rising time
50
tf(SCLK)
Serial I/O clock output falling time
50
tr(CMOS)
20
CMOS output rising time (Note 2)
50
tf(CMOS)
20
CMOS output falling time (Note 2)
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
59
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (M Version)
Table 34. Absolute maximum ratings (M version)
Symbol
VCC
VI
Parameter
Power source voltage
Input voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P80, P81
Input voltage P70–P77
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
VI
VI
VI
VI
VI
VI
VO
Input voltage RESET, XIN
Output voltage C1, C2
VO
Output voltage P00–P07, P10–P15, P30–P37
VO
VO
VO
VO
Pd
Topr
Tstg
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77
P80, P81
Output voltage VL3
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
Conditions
All voltages are based on VSS.
Output transistors are cut off.
At output port
At segment output
Ta = 25°C
Ratings
Unit
–0.3 to 7.0
V
–0.3 to VCC +0.3
V
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 7.0
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VCC
–0.3 to VL3
V
V
V
V
V
V
V
V
V
–0.3 to VCC +0.3
V
–0.3 to 7.0
–0.3 to VL3
–0.3 to VCC +0.3
300
–20 to 85
–40 to 125
V
V
V
mW
°C
°C
Table 35. Recommended operating conditions (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
Parameter
High-speed mode, f(XIN)=8 MHz
Middle-speed mode, f(XIN) = 8 MHz
Low-speed mode
VCC
Power source voltage
VSS
VREF
AVSS
VIA
Power source voltage
A-D conversion reference voltage
Analog power source voltage
Analog input voltage
AN0–AN7
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
60
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
“L” input voltage
RESET
XIN
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
“L” input voltage
RESET
“L” input voltage
XIN
Limits
Min.
4.0
2.2
2.2
Typ.
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
Unit
V
AVSS
VCC
V
V
V
V
0.7VCC
VCC
V
0.8VCC
0.8VCC
0.8VCC
VCC
VCC
VCC
V
V
V
0
0.3VCC
V
0
0
0
0.2VCC
V
V
V
VCC
2.0
0
0.2VCC
0.2VCC
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 36. Recommended operating conditions (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
Limits
Parameter
“H” total peak output current
“H” total peak output current
“L” total peak output current
Min.
Typ.
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P40–P47,P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
Unit
–20
mA
–20
mA
20
20
40
–10
mA
mA
mA
mA
–10
mA
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
P40–P47,P50–P57, P60–P67, P80, P81 (Note 1)
P71–P77 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P40–P47, P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
“L” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
“L” total average output current P40–P47, P50–P57, P60–P67, P80, P81 (Note 1)
“L” total average output current P71–P77 (Note 1)
“H” peak output current
P00–P07, P10–P15, P30–P37 (Note 2)
10
10
20
–0.5
mA
mA
mA
IOH(peak)
“H” peak output current
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 2)
–5.0
mA
IOL(peak)
mA
10
mA
IOH(avg)
“H” average output current
P00–P07, P10–P15, P30–P37 (Note 2)
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 2)
P00–P07, P10–P15, P30–P37 (Note 3)
5.0
IOL(peak)
“L” peak output current
“L” peak output current
–0.1
mA
IOH(avg)
“H” average output current
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
–2.5
mA
IOL(avg)
“H” average output current
P00–P07, P10–P15, P30–P37 (Note 3)
2.5
mA
IOL(avg)
“H” average output current
5.0
mA
ΣIOH(avg)
ΣIOH(avg)
f(CNTR0)
f(CNTR1)
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
Max.
P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
(4.0 V ≤ VCC ≤ 5.5 V)
Input frequency for timers X and Y
(duty cycle 50%)
(2.2 V ≤ VCC ≤ 4.0 V)
4.0
(10 ✕ VCC –
4) / 9
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
f(XIN)
Main clock input oscillation frequency
(Note 4)
f(XCIN)
Sub-clock input oscillation frequency (Note 4, 5)
8.0
High-speed mode
(2.2 V ≤ VCC ≤ 4.0 V)
(20 ✕ VCC –
8) / 9
Middle-speed mode
32.768
mA
MHz
MHz
MHz
MHz
8.0
MHz
50
kHz
Notes 1 : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
2 : The peak output current is the peak current flowing in each port.
3 : The average output current is an average value measured over 100 ms.
4 : When the oscillation frequency has a duty cycle of 50%.
5 : When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
61
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 37. Electrical characteristics (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
VOH
“H” output voltage P00–P07, P10–P15, P30–P37
VOH
“H” output voltage P16, P17, P20–P27,P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81 (Note)
VOL
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
“L” output voltage P00–P07, P10–P15, P30–P37
“L” output voltage P16, P17, P20–P27,P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81 (Note)
Hysteresis
Hysteresis
INT0–INT3, ADT, CNTR0,
CNTR1, P20–P27
SCLK, RXD
Hysteresis
RESET
“H” input current
P16, P17, P20–P27,P40–P47,
P50–P57, P60–P67, P70–P77,
P80, P81
RESET
XIN
IIH
IIH
IIH
“H” input current
“H” input current
“L” input current
IIL
P16, P17, P20–P27,P40–P47,
P50–P57, P60–P67, P70–P77,
P80, P81
IIL
IIL
IIL
“L” input current
P70
“L” input current
RESET
“L” input current
XIN
ILOAD
Output load current P00–P07, P10–P15, P30–P37
ILEAK
Output leak current P00–P07, P10–P15, P30–P37
Test conditions
IOH = –2.5 mA
IOH = –0.25 mA
VCC = 2.2 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 2.2 V
IOL = 5 mA
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.2 V
IOL = 10 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 2.2 V
Min.
VCC–2.0
Limits
Typ.
V
V
VCC–2.0
VCC–0.5
V
VCC–0.8
V
V
VO = VSS, Pull-downs “off”
Output transistors “off”
V
2.0
0.5
V
0.8
V
2.0
0.5
V
0.8
V
V
0.5
V
0.5
0.5
V
V
VI = VCC
VI = VSS
VI = VSS
VCC = 5.0 V, VO = VCC, Pull-downs “on”
Output transistors “off”
VCC = 2.2 V, VO = VCC, Pull-downs “on”
Output transistors “off”
VO = VCC, Pull-downs “off”
Output transistors “off”
Unit
VCC–0.8
RESET: VCC=2.2 V to 5.5 V
VI = VCC
VI = VCC
VI = VSS
Pull-ups “off”
VCC = 5 V, VI = VSS
Pull-ups “on”
VCC = 2.2 V, VI = VSS
Pull-ups “on”
Max.
5.0
µA
5.0
µA
µA
–5.0
µA
4.0
–30
–70
–140
µA
–6.0
–25
–45
µA
–5.0
µA
–5.0
µA
µA
–4.0
30
70
140
µA
6.0
25
45
µA
5.0
µA
–5.0
µA
Note : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P80 is different from the
value above mentioned.
62
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 38. Electrical characteristics (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
VRAM
Parameter
RAM retention voltage
Power source current
ICC
Test conditions
At clock stop mode
• High-speed mode, VCC = 5 V
Min.
2.0
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
VL1
Power source voltage
IL1
Power source current (VL1)
(Note)
Ta = 25°C
Limits
Typ.
Unit
V
6.4
13
mA
1.6
3.2
mA
25
36
µA
7.0
14
µA
15
22
µA
4.5
9.0
µA
0.1
1.0
µA
10
Ta = 85°C
When using voltage multiplier
VL1 = 1.8 V
VL1 < 1.3 V
Max.
5.5
1.3
1.8
3.0
10
2.3
6.0
50
V
µA
Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
Table 39. A-D converter characteristics (M version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-/high-speed mode, unless otherwise noted.)
Symbol
Parameter
Test conditions
–
–
Resolution
Absolute accuracy (excluding quantization error)
VCC = VREF = 5 V
tCONV
Conversion time
f(XIN) = 8 MHz
RLADDER
IVREF
IIA
Ladder resistor
Reference input current
Analog iinput current
VREF = 5 V
Min.
Limits
Typ.
Max.
Unit
8
Bits
±2
LSB
12.5
(Note)
µs
12
35
100
kΩ
50
150
200
µA
5.0
µA
Note : When an internal trigger is used in middle-speed mode, it is 14 µs.
63
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 40. Timing reguirements 1 (M Version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RXD–SCLK)
th(SCLK–RXD)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
Limits
Typ.
Min.
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 41. Timing reguirements 2 (M Version)
(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
µs
ns
ns
ns
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
tc(CNTR)
CNTR0, CNTR1 input cycle time
900 /
(VCC – 0.4)
ns
twH(CNTR)
CNTR0, CNTR1 input “H” pulse width
450 /
(VCC – 0.4) – 20
ns
twL(CNTR)
CNTR0, CNTR1 input “L” pulse width
450 /
(VCC – 0.4) – 20
ns
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RXD–SCLK)
th(SCLK–RXD)
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
64
2
125
45
40
230
230
2000
950
950
400
200
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 42. Switching characteristics 1 (M version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Limits
Parameter
Min.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Typ.
Max.
tc(SCLK)/2–30
tc(SCLK)/2–30
140
–30
10
10
30
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Table 43. Switching characteristics 2 (M version)
(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Parameter
Min.
tc(SCLK)/2–50
tc(SCLK)/2–50
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Limits
Typ.
Max.
350
–30
20
20
50
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
1 kΩ
Measurement output pin
Measurement output pin
100 pF
CMOS output
100 pF
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register (address
001B16) is “1” (N-channel open-drain output mode).
Fig. 46 Circuit for measuring output switching characteristics
65
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
0.8VCC
CNTR0, CNTR1
0.2VCC
tWH(INT)
INT0–INT3
tWL(INT)
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
XIN
0.8VCC
0.2VCC
tC(SCLK)
tf
SCLK
tr
tWL(SCLK)
0.8VCC
0.2VCC
tsu(RXD-SCLK)
td(SCLK-TXD)
Fig. 47 Timing diagram
66
th(SCLK-RXD)
0.8VCC
0.2VCC
RXD
TXD
tWH(SCLK)
tv(SCLK-TXD)
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINES
MMP
100P6S-A
EIAJ Package Code
QFP100-P-1420-0.65
Plastic 100pin 14✕20mm body QFP
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
81
1
b2
100
ME
HD
D
80
I2
Recommended Mount Pad
E
30
HE
Symbol
51
50
A
L1
c
A2
b
x
A1
F
e
M
L
Detail F
y
MMP
EIAJ Package Code
LQFP100-P-1414-0.50
Plastic 100pin 14✕14mm body LQFP
Weight(g)
0.63
JEDEC Code
–
Lead Material
Cu Alloy
MD
e
100P6Q-A
b2
I2
MD
ME
b2
HD
ME
31
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
Dimension in Millimeters
Min
Nom
Max
–
–
3.05
0.1
0.2
0
–
–
2.8
0.25
0.3
0.4
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
0.65
–
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
–
–
0.13
–
–
0.1
–
0°
10°
–
–
0.35
1.3
–
–
14.6
–
–
–
–
20.6
D
76
100
l2
Recommended Mount Pad
75
1
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
HE
E
Symbol
51
25
26
50
A
L1
F
A3
M
y
L
Detail F
Lp
c
x
A1
b
A3
A2
e
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
1.7
0.1
0.2
0
–
–
1.4
0.13
0.18
0.28
0.105
0.125
0.175
13.9
14.0
14.1
13.9
14.0
14.1
0.5
–
–
15.8
16.0
16.2
15.8
16.0
16.2
0.3
0.5
0.7
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.08
–
–
0.1
–
0°
10°
–
–
0.225
0.9
–
–
14.4
–
–
14.4
–
–
67
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MMP
100PFB-A
EIAJ Package Code
TQFP100-P-1212-0.40
Plastic 100pin 12✕12mm body TQFP
Weight(g)
0.37
Lead Material
Cu Alloy
MD
e
JEDEC Code
–
ME
HD
b2
D
100
76
1
I2
Recommended Mount Pad
75
25
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
HE
E
Symbol
51
26
50
A
L1
e
F
y
b
x
M
L
Detail F
x
y
b2
I2
MD
ME
c
A1
A3
A2
A3
Lp
100D0
Dimension in Millimeters
Min
Nom
Max
1.2
–
–
0.05
0.1
0.15
1.0
–
–
0.13
0.18
0.23
0.105
0.125
0.175
11.9
12.0
12.1
11.9
12.0
12.1
0.4
–
–
13.8
14.0
14.2
13.8
14.0
14.2
0.4
0.5
0.6
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.07
–
–
0.08
–
0°
10°
–
–
0.225
1.0
–
–
12.4
–
–
–
–
12.4
Glass seal 100pin QFN
EIAJ Package Code
–
JEDEC Code
–
Weight(g)
18.85±0.15
5.0MAX
21.0±0.13
3.5TYP
0.65TYP
0.45TYP
51
80
81
INDEX
68
0.35TYP
0.65TYP
12.35±0.15
1.075TYP
15.6±0.13
0.65TYP
50
31
100
30
1.075TYP
1
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•
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personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
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rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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Notes regarding these materials
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© 2001 MITSUBISHI ELECTRIC CORP.
Specifications subject to change without notice.
REVISION HISTORY
Rev.
3825 GROUP DATA SHEET
Date
Description
Summary
Page
1.0
01/23/98
First Edition
2.0
05/15/98
Low power source version is added.
2.1
07/13/99
7 to 10
17
43
53
The followings are mainly revised:
Group expnasion
(11) Port P70 of port bock diagram
Name in Table 11
The “L” input current parameter of IIL in Tables 25 and 35 is not P70–P77 but P71–
P77.
“•2 Clock generating circuits” of “FEATURES” is partly eliminated.
“•Power source voltage” of “FEATURES” is partly revised.
“Function” of “Vcc, Vss” into Table 1 is partly revised.
Figure 4 is partly revised.
Clause name and explanations of “GROUP EXPANSION (STANDARD, ONE TIME
PROM VERSION, EPROM VERSION)” are partly revised.
Table 3 is partly eliminated.
8
Table 4 is partly eliminated.
9
Clause name and explanations of “GROUP EXPANSION (M VERSION)” are partly
10
revised.
Figure name of Figure 7 is partly revised.
10
11 to 13 Explanations of “CENTRAL PROCESSING UNIT (CPU)” are added.
(12), (13), (14) into Figure 15 is partly revised.
20
Figure 19 is partly revised.
24
Figure 31 is partly revised.
34
Explanations of “RESET CIRCUIT” are partly revised.
40
Figure 38 is partly revised.
40
Explanations of “CLOCK GENERATING CIRCUIT” are partly eliminated.
42
Figure 43 is partly revised.
43
Explanations of “Decimal Calculations” of “NOTES ON PROGRAMMING” are partly
45
eliminated.
Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly added.
46
Explanations of “DATA REQUIRED FOR WRITING ORDERS” in Rev.2.1 are elimi46
nated.
Note number of “IOH(avg) P00–P07, P10–P15, P30–P37” into Table 16 is revised.
48
Test conditions of Icc into Table 18 are partly revised.
50
Test conditions of Icc into Table 28 are partly revised.
57
60 to 65 Table names of Tables 34 to 43 are partly revised.
Limits of AVss into Table 35 is partly revised.
60
Parameter of ΣIOH(avg) into Table 36 is partly revised.
61
Test conditions of Icc into Table 38 is partly revised.
63
3.0
12/11/00
1
1
4
6
7
3.1
02/06/01
22
24
30
46
Explanations of “■Notes on interrupts” are partly revised.
Figure 19 is partly revised.
“■Notes on serial I/O” is added.
Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly revised.
(1/1)
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