SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 D Package Options Include Plastic Small-Outline (D, NS, PS), Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs SN5400 . . . J PACKAGE SN54LS00, SN54S00 . . . J OR W PACKAGE SN7400, SN74S00 . . . D, N, OR NS PACKAGE SN74LS00 . . . D, DB, N, OR NS PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 2 13 3 12 VCC 2Y 2A 2B 4 11 5 10 6 9 7 8 1 8 2 7 3 6 4 5 VCC 2B 2A 2Y SN54LS00, SN54S00 . . . FK PACKAGE (TOP VIEW) 1B 1A NC VCC 4B 14 SN74LS00, SN74S00 . . . PS PACKAGE (TOP VIEW) 4Y 4B 4A GND 3B 3A 3Y 1Y NC 2A NC 2B 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1 Positive-NAND Gate in Small-Outline (PS) Package 1A 1B 1Y GND SN5400 . . . W PACKAGE (TOP VIEW) 1A 1B 1Y D Also Available as Dual 2-Input NC − No internal connection description/ordering information These devices contain four independent 2-input NAND gates. The devices perform the Boolean function Y = A • B or Y = A + B in positive logic. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) %(#"! "%' / 0121 '' %$$! $ $!$( #'$!! *$,!$ $() '' *$ %(#"! %(#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 description/ordering information (continued) ORDERING INFORMATION PDIP − N Tube SOIC − D 0°C 0 C to 70 70°C C SOP − NS −55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA SN74LS00N SN74LS00N SN74S00N SN74S00N Tape and reel SN7400DR Tube SN74LS00D Tape and reel SN74LS00DR Tube SN74S00D Tape and reel SN74S00DR Tape and reel SSOP − DB Tape and reel CDIP − J Tube Tube LCCC − FK SN7400N SN7400D SOP − PS CFP − W SN7400N Tube Tape and reel Tube TOP-SIDE MARKING 7400 LS00 S00 SN7400NSR SN7400 SN74LS00NSR 74LS00 SN74S00NSR 74S00 SN74LS00PSR LS00 SN74S00PSR S00 SN74LS00DBR LS00 SNJ5400J SNJ5400J SNJ54LS00J SNJ54LS00J SNJ54S00J SNJ54S00J SNJ5400W SNJ5400W SNJ54LS00W SNJ54LS00W SNJ54S00W SNJ54S00W SNJ54LS00FK SNJ54LS00FK SNJ54S00FK SNJ54S00FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H L L X H X L H logic diagram, each gate (positive logic) A Y B 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 schematic ’00 VCC 4 kΩ 130 Ω 1.6 kΩ A B Y 1 kΩ GND ’LS00 ’S00 VCC 20 kΩ VCC 120 Ω 8 kΩ 900 Ω 2.8 kΩ 50 Ω A 3.5 kΩ A B 12 kΩ 4 kΩ Y B Y 500 Ω 1.5 kΩ 250 Ω 3 kΩ GND GND Resistor values shown are nominal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage: ’00, ’S00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V ’LS00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package termal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN5400 VCC VIH Supply voltage VIL IOH Low-level input voltage IOL TA Low-level output current High-level input voltage SN7400 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 2 2 High-level output current −55 V V 0.8 0.8 V −0.4 −0.4 mA 16 mA 70 °C 16 Operating free-air temperature UNIT 125 0 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN5400 TEST CONDITIONS‡ PARAMETER VIK VOH VCC = MIN, VCC = MIN, II = −12 mA VIL = 0.8 V, VOL II VCC = MIN, VCC = MAX, VIH = 2 V, VI = 5.5 V IIH IIL VCC = MAX, VCC = MAX, VI = 2.4 V VI = 0.4 V IOS¶ VCC = MAX ICCH ICCL VCC = MAX, VCC = MAX, MIN TYP§ 2.4 3.4 SN7400 MAX MIN TYP§ 2.4 3.4 −1.5 IOH = −0.4 mA IOL = 16 mA 0.2 −1.5 0.4 0.2 1 UNIT V V 0.4 1 V mA 40 40 µA −1.6 −1.6 mA −55 mA 4 8 mA 12 22 12 ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § All typical values are at VCC = 5 V, TA = 25°C. ¶ Not more than one output should be shorted at a time. 22 mA 4 −20 MAX VI = 0 V VI = 4.5 V POST OFFICE BOX 655303 −55 4 • DALLAS, TEXAS 75265 8 −18 SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER tPLH FROM (INPUT) TO (OUTPUT) A or B Y SN5400 SN7400 TEST CONDITIONS MIN RL = 400 Ω, tPHL UNIT TYP MAX 11 22 7 15 CL = 15 pF ns recommended operating conditions (see Note 4) SN54LS00 VCC VIH Supply voltage VIL IOH Low-level input voltage IOL TA Low-level output current SN74LS00 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 High-level input voltage 2 2 High-level output current −55 V V 0.7 0.8 V −0.4 −0.4 mA 8 mA 70 °C 4 Operating free-air temperature UNIT 125 0 NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIK VOH SN54LS00 TEST CONDITIONS† PARAMETER VCC = MIN, VCC = MIN, II = −18 mA VIL = MAX, MIN TYP‡ SN74LS00 MAX MIN TYP‡ −1.5 IOH = −0.4 mA IOL = 4 mA 2.5 3.4 −1.5 2.7 0.25 MAX 0.4 3.4 UNIT V V 0.25 0.4 0.35 0.5 VOL VCC = MIN, VIH = 2 V II IIH VCC = MAX, VCC = MAX, VI = 7 V VI = 2.7V 0.1 0.1 20 20 µA IIL VCC = MAX, VI = 0.4 V −0.4 −0.4 mA IOS§ VCC = MAX −100 mA ICCH ICCL VCC = MAX, VCC = MAX, IOL = 8mA −20 −100 VI = 0 V VI = 4.5 V −20 V mA 0.8 1.6 0.8 1.6 mA 2.4 4.4 2.4 4.4 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER tPLH FROM (INPUT) TO (OUTPUT) A or B Y tPHL POST OFFICE BOX 655303 TEST CONDITIONS SN54LS00 SN74LS00 MIN RL = 2 kΩ, CL = 15 pF • DALLAS, TEXAS 75265 UNIT TYP MAX 9 15 10 15 ns 5 SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 recommended operating conditions (see Note 5) SN54S00 SN74S00 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current −1 −1 mA IOL TA Low-level output current 20 20 mA 70 °C High-level input voltage 2 Operating free-air temperature 2 −55 125 V V 0 NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54S00 TEST CONDITIONS† PARAMETER VIK VOH VCC = MIN, VCC = MIN, II = −18 mA VIL = 0.8 V, VOL II VCC = MIN, VCC = MAX, VIH = 2 V, VI = 5.5 V IIH IIL VCC = MAX, VCC = MAX, VI = 2.7 V VI = 0.5V IOS§ VCC = MAX ICCH ICCL VCC = MAX, VCC = MAX, MIN TYP‡ 2.5 3.4 SN74S00 MAX MIN TYP‡ 2.7 3.4 −1.2 IOH = −1 mA IOL = 20 mA −40 MAX −1.2 UNIT V V 0.5 0.5 1 1 50 50 µA −2 −2 mA −100 mA 10 16 mA 20 36 20 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. 36 mA VI = 0 V VI = 4.5 V −100 10 −40 V mA 16 switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER tPLH FROM (INPUT) TO (OUTPUT) A or B Y tPHL tPLH A or B Y tPHL 6 POST OFFICE BOX 655303 SN54S00 SN74S00 TEST CONDITIONS MIN RL = 280 Ω, CL = 15 pF RL = 280 Ω, CL = 50 pF • DALLAS, TEXAS 75265 UNIT TYP MAX 3 4.5 3 5 4.5 5 ns ns SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION SERIES 54/74 DEVICES VCC Test Point VCC RL From Output Under Test CL (see Note A) CL (see Note A) High-Level Pulse 1.5 V S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V 1 kΩ Test Point LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS S1 (see Note B) CL (see Note A) RL (see Note B) RL From Output Under Test VCC From Output Under Test Test Point 1.5 V 0V tw Low-Level Pulse 1.5 V tsu 0V In-Phase Output (see Note D) tPHL VOH 1.5 V Out-of-Phase Output (see Note D) 1.5 V 3V 1.5 V Waveform 1 (see Notes C and D) tPLZ VOH 1.5 V 1.5 V VOL VOL Waveform 2 (see Notes C and D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈1.5 V 1.5 V tPZH tPLH 1.5 V 0V tPZL VOL tPHL 1.5 V 0V Output Control (low-level enabling) 1.5 V tPLH 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 3V Data Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS Input th VOL + 0.5 V tPHZ VOH 1.5 V VOH − 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) JM38510/00104BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00104BCA JM38510/00104BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00104BDA JM38510/07001BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07001BCA JM38510/07001BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07001BDA JM38510/30001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 30001B2A JM38510/30001BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30001BCA JM38510/30001BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30001BDA JM38510/30001SCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/30001S CA JM38510/30001SDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/30001S DA M38510/00104BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00104BCA M38510/00104BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00104BDA M38510/07001BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07001BCA M38510/07001BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07001BDA M38510/30001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 30001B2A M38510/30001BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30001BCA M38510/30001BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30001BDA M38510/30001SCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/30001S CA Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) M38510/30001SDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/30001S DA SN5400J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN5400J SN54LS00J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS00J SN54S00J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54S00J SN7400D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7400 SN7400DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7400 SN7400DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7400 SN7400N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN7400N SN7400N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70 SN7400NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN7400N SN74LS00D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00 SN74LS00DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI 0 to 70 SN74LS00DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00 SN74LS00DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00 SN74LS00DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00 SN74LS00DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00 SN74LS00DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00 SN74LS00DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00 SN74LS00DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00 Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Orderable Device Status (1) Package Type Package Pins Package Qty Drawing SN74LS00DRG4 ACTIVE SOIC D 14 Eco Plan Lead/Ball Finish (2) 2500 Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU (4) Level-1-260C-UNLIM 0 to 70 LS00 SN74LS00J OBSOLETE CDIP J 14 TBD Call TI Call TI 0 to 70 SN74LS00N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS00N SN74LS00NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS00N SN74LS00NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS00 SN74LS00NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS00 SN74LS00PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00 SN74LS00PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00 SN74LS00PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00 SN74S00D NRND SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S00 SN74S00DE4 NRND SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S00 SN74S00DG4 NRND SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S00 SN74S00N NRND PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74S00N SN74S00N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70 SN74S00NE4 NRND PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74S00N SNJ5400J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5400J SNJ5400W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5400W SNJ5400WA OBSOLETE CFP WA 14 TBD A42 N / A for Pkg Type -55 to 125 SNJ5400WA SNJ54LS00FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54LS00FK SNJ54LS00J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS00J Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) SNJ54LS00W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS00W SNJ54S00FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54S 00FK SNJ54S00J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S00J SNJ54S00W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S00W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. 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OTHER QUALIFIED VERSIONS OF SN5400, SN54LS00, SN54LS00-SP, SN54S00, SN7400, SN74LS00, SN74S00 : Addendum-Page 4 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 • Catalog: SN7400, SN74LS00, SN54LS00, SN74S00 • Military: SN5400, SN54LS00, SN54S00 • Space: SN54LS00-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 5 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LS00DBR SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DB 14 2000 330.0 16.4 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74LS00DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LS00NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LS00PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LS00DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LS00DR SOIC D 14 2500 367.0 367.0 38.0 SN74LS00NSR SO NS 14 2000 367.0 367.0 38.0 SN74LS00PSR SO PS 8 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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