Samsung M470L6423EN0-CLB3 512mb unbuffered sodimm(based on stsop) Datasheet

512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
DDR SDRAM Unbuffered SODIMM
200pin Unbuffered SODIMM based on 256Mb E-die (x8)
with 64-bit Non ECC
Revision 1.3
March. 2004
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
Revision History
Revision 1.0 (May, 2003)
- First release
Revision 1.1 (August, 2003)
- Corrected typo.
Revision 1.2 (December, 2003)
- Corrected typo.
Revision 1.3 (March, 2004)
- Corrected package dimension.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
200Pin Unbuffered SODIMM based on 256Mb E-die (x8)
Ordering Information
Part Number
Density
Organization
Component Composition
Height
M470L6423EN0-C(L)B3/A2/B0
512MB
64M x 64
32Mx8 (K4H560838E) * 16EA
1,250mil
Operating Frequencies
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
Speed @CL2
133MHz
133MHz
B0(DDR266@CL=2.5)
100MHz
Speed @CL2.5
166MHz
133MHz
133MHz
CL-tRCD-tRP
2.5-3-3
2-3-3
2.5-3-3
Feature
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil), double (512MB) sided
• SSTL_2 Interface
• 54pin sTSOP(II)-300 package
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
Pin Configurations (Front side/back side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Front
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
/CK0
VSS
KEY
41
43
45
47
49
51
53
55
57
59
61
63
65
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
Pin
67
69
*71
*73
75
*77
*79
81
*83
85
87
*89
*91
93
*95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
/CK2
VDD
CKE1
DU
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
/WE
/CS0
*DU(A13)
VSS
DQ32
DQ33
VDD
DQS4
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
VDDID
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
68
70
*72
*74
76
*78
*80
82
*84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
*122
124
126
128
130
132
134
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
*DU/(RESET)
VSS
VSS
VDD
VDD
CKE0
DU(BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
/RAS
/CAS
/CS1
DU
VSS
DQ36
DQ37
VDD
DM4
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
/CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
KEY
42
44
46
48
50
52
54
56
58
60
62
64
66
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
Note 1. * : These pins are not used in this module.
2. Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84 are reserved for x72 module, and are not used on x64 module.
Pin 95,122 are NC for 8Mx16 based module & used for 16Mx8 based module.
3. Pins 89, 91 are reserved for x72 modules.
Pin Description
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0,CK0 ~ CK1, CK1
CKE0 ~ CKE1
CS0 ~ CS1
RAS
CAS
WE
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Pin Name
DM0 ~ 7
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
NC
Function
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Serial data I/O
Serial clock
Address in EEPROM
No connection
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
CS1
CS0
DQS4
DM4
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D0
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D8
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
CS
D4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D12
DQS5
DM5
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D1
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D9
DQS
CS
D5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D13
DQS6
DM6
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
DQS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D2
CS
DQS
D10
CS
DQS
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D14
DQS7
DM7
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D3
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D11
BA0 - BA1
BA0-BA1: DDR SDRAMs D0 - D15
A0 - A12
A0-A12 : DDR SDRAMs D0 - D15
RAS
RAS
: DDR SDRAMs D0 - D15
CAS
CAS
: DDR SDRAMs D0 - D15
CKE1
CKE
: DDR SDRAMs D8 - D15
CKE0
CKE
: DDR SDRAMs D0 - D7
WE
WE
: DDR SDRAMs D0 - D15
CS DQS
D7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D15
D0,D8 / D4,D12
R=120Ω
± 5%
CK0 / 1
CK0 / 1 Card
Edge
D1,D9 / D5,D13
CK2
10pF
D2,D10/ D6,D14
CK2
D3,D11/ D7,D15
*Clock Net Wiring
VDDSPD
VDD/VDDQ
SPD
D0 - D15
D0 - D15
VREF
D0 - D15
VSS
D0 - D15
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown
3. DQ, DQS, DM/DQS resistors: 22 Ohm.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
VDD, VDDQ
-1.0 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.5 * # of component
W
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Symbol
Min
Max
Supply voltage(for device with a nominal VDD of 2.5V)
Parameter
VDD
2.3
2.7
Unit
Note
I/O Supply voltage
VDDQ
2.3
2.7
V
I/O Reference voltage
VREF
0.49*VDDQ
0.51*VDDQ
V
1
I/O Termination voltage(system)
VTT
VREF-0.04
VREF+0.04
V
2
V
Input logic high voltage
VIH(DC)
VREF+0.15
VDDQ+0.3
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.36
VDDQ+0.6
V
3
V-I Matching: Pullup to Pulldown Current Ratio
VI(Ratio)
0.71
1.4
-
4
II
-2
2
uA
5
Input leakage current
Output leakage current
IOZ
-5
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
IOH
-16.8
mA
uA
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
IOL
16.8
mA
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
IOH
-9
mA
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOL
9
mA
Note : 1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same.
Peak-to peak noise on VREF may not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the
maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the
maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
DDR SDRAM IDD spec table
M470L6423EN0 [ (32M x 8) * 8, 512MB Non ECC Module ]
IDD6
(VDD=2.7V, T = 10°C)
Symbol
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Unit
IDD0
1,160
1,000
1,000
mA
IDD1
1,360
1,200
1,200
mA
IDD2P
48
48
48
mA
mA
IDD2F
400
320
320
IDD2Q
320
290
290
mA
IDD3P
560
480
480
mA
IDD3N
880
720
720
mA
IDD4R
1,720
1,480
1,480
mA
IDD4W
1,720
1,440
1,440
mA
IDD5
1,800
1,640
1,640
mA
Normal
48
48
48
mA
Low power
24
24
24
mA
2,680
2,360
2,360
mA
IDD7A
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
AC Operating Conditions
Parameter/Condition
Max
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
Input Differential Voltage, CK and CK inputs
VID(AC)
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
Unit
Note
V
3
VREF - 0.31
V
3
0.7
VDDQ+0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
CLOAD=30pF
VREF
=0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
Parameter
(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
Symbol
M470L6423EN0
Unit
Min
Max
CIN1
38
47
pF
Input capacitance(CKE0, CKE1)
CIN2
38
47
pF
Input capacitance(CS0, CS1)
CIN3
36
44
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
36
40
pF
Input capacitance(DM0~DM7)
CIN5
12
14
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
12
14
pF
Data input/output capacitance (CB0~CB7)
Cout2
12
14
pF
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS,WE )
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
AC Timming Parameters & Specifications
Parameter
Symbol
B3
(DDR333@CL=2.5))
Min
Max
A2
(DDR266@CL=2.0)
Min
Max
B0
(DDR266@CL=2.5))
Min
Unit
Row cycle time
tRC
60
65
65
ns
Refresh row cycle time
tRFC
72
75
75
ns
Row active time
tRAS
42
RAS to CAS delay
tRCD
18
20
20
ns
tRP
18
20
20
ns
Row active to Row active delay
tRRD
12
15
15
ns
Write recovery time
tWR
15
15
15
ns
Last data in to Read command
tWTR
1
1
1
tCK
Row precharge time
Col. address to Col. address delay
Clock cycle time
tCCD
CL=2.0
CL=2.5
Clock high level width
Clock low level width
70K
1
45
120K
1
45
120K
1
ns
tCK
7.5
12
7.5
12
10
12
ns
6
12
7.5
12
7.5
12
ns
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCK
tCK
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
tDQSQ
-
0.45
-
0.5
-
0.5
ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
ns
DQS-in hold time
tWPRE
0.25
0.25
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
0.2
0.2
tCK
DQS-out access time from CK/CK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
1.1
0.9
1.1
3
tDSC
0.9
tIS
0.75
0.9
0.9
ns
i,5.7~9
Address and Control Input hold time(fast)
tIH
0.75
0.9
0.9
ns
i,5.7~9
Address and Control Input setup time(slow)
tIS
0.8
1.0
1.0
ns
i, 6~9
Address and Control Input hold time(slow)
tIH
0.8
1.0
1.0
ns
i, 6~9
Data-out high impedence time from CK/CK
tHZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
1
Data-out low impedence time from CK/CK
tLZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
1
Input Slew Rate(for I/O pins)
0.9
12
Address and Control Input setup time(fast)
Input Slew Rate(for input only pins)
1.1
Note
Max
tCK
tSL(I)
0.5
0.5
0.5
V/ns
tSL(IO)
0.5
0.5
0.5
V/ns
Output Slew Rate(x4,x8)
tSL(O)
1.0
4.5
1.0
4.5
1.0
4.5
Output Slew Rate Matching Ratio(rise to fall)
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
V/ns
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
Parameter
Symbol
B3
Min
DDR SDRAM
A2
Max
Min
B0
Max
Min
Max
Unit
Note
Mode register set cycle time
tMRD
12
15
15
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
0.5
ns
7,8,9
DQ & DM hold time to DQS
tDH
0.45
0.5
0.5
ns
7,8,9
Control & Address input pulse width
tIPW
2.2
2.2
2.2
ns
DQ & DM input pulse width
tDIPW
1.75
1.75
1.75
ns
Power down exit time
tPDEX
6
7.5
7.5
ns
Exit self refresh to non-Read command
tXSNR
75
75
75
ns
Exit self refresh to read command
tXSRD
200
200
200
tCK
Refresh interval time
tREFI
7.8
Output DQS valid window
tQH
tHP
-tQHS
Clock half period
tHP
tCLmin
or tCHmin
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
tQHS
7.8
-
tHP
-tQHS
-
tCLmin
or tCHmin
0.55
0.6
7.8
us
1
-
tHP
-tQHS
-
ns
5
-
tCLmin
or tCHmin
-
ns
0.75
0.4
4
tWPST
0.4
0.6
0.4
tRAP
18
20
20
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
0.75
ns
0.6
tCK
3
tCK
11
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period
jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
∆tIS
∆tIH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+50
+50
0.3
+100
+100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
∆tDS
∆tDH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+75
+75
0.3
+150
+150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
8. I/O Setup/Hold Plateau Derating
I/O Input Level
∆tDS
∆tDH
(mV)
(ps)
(ps)
± 280
+50
+50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
∆tDS
∆tDH
(ns/V)
(ps)
(ps)
0
0
0
±0.25
+50
+50
±0.5
+100
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
<Reference>
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.
CK slew rate
(Single ended)
∆tIH/tIS
(ps)
∆tDSS/tDSH
(ps)
∆tAC/tDQSCK
(ps)
∆tLZ(min)
(ps)
∆tHZ(max)
(ps)
1.0V/ns
0
0
0
0
0
0.75V/ns
+50
+50
+50
-50
+50
0.5V/ns
+100
+100
+100
-100
+100
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
COMMAND
Register
Register
CKEn
CS
RAS
CAS
WE
Extended MRS
H
X
L
L
L
L
OP CODE
1, 2
Mode Register Set
H
X
L
L
L
L
OP CODE
1, 2
L
L
L
H
X
L
H
H
H
H
X
X
X
Entry
Self
Refresh
L
L
H
Bank Active & Row Addr.
H
X
L
L
H
H
V
Read &
Column Address
H
X
L
H
L
H
V
Write &
Column Address
Exit
H
H
BA0,1
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
X
L
H
L
L
H
X
L
H
H
L
H
All Banks
Active Power Down
H
X
Entry
H
L
Exit
L
H
Entry
H
L
Precharge Power Down Mode
Exit
DM
No operation (NOP) : Not defined
L
H
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
H
X
X
A10/AP
A12, A11
A9 ~ A0
CKEn-1
Auto Refresh
Refresh
DDR SDRAM
X
X
X
L
H
H
H
3
3
3
Row Address
L
Column
Address
H
Column
Address
H
L
X
H
4
4, 6
X
V
4
4
L
7
X
5
X
X
X
H
3
X
V
Note
X
8
9
9
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
2.70
(67.60)
2.50
(63.60)
0.07
(1.8)
Y
200
4042
0.157 Min
(4.00 Min)
0.157 Min
0.150 Max
(3.80 Max)
(4.00 Min)
0.79
(20.00)
2-φ 0.07
(1.80)
Z
0.098
2.45
2
1.896
(47.40)
0.17
(4.20)
0.096
(2.40)
0.16 ± 0.0039
(4.00 ± 0.10)
0.04 ± 0.0039
(1.00 ± 0.1)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
(2.55 Min)
0.456
11.40
0.086
2.15
199
3941
0.102 Min
0.24
(6.0)
1
1.25
(31.75)
Full R 2x
0.16 ± 0.039
(4.00 ± 0.10)
0.018 ± 0.001
(0.45 ± 0.03)
0.008 ± 0.006
(0.20 ± 0.15)
0.024 TYP
(0.60 TYP)
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 32Mx8 DDR SDRAM, sTSOP-300mil
SDRAM Part No. : K4H560838E-N***
Rev. 1.3 March. 2004
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