STMICROELECTRONICS M48Z512BV

M48Z512BV
3.3 V, 4 Mbit (512 K x 8 bit) ZEROPOWER® SRAM
Features
■
Integrated, ultra-low power SRAM, power-fail
control circuit, and battery
■
Conventional SRAM operation; unlimited
WRITE cycles
■
10 years of data retention in the absence of
power
■
Automatic power-fail chip deselect and WRITE
protection
■
3.0 to 3.6 V operation
– 2.9 V power-fail deselect
Description
■
Pin and function compatible with JEDEC
standard 512 K x 8 SRAMs
■
PMDIP32 is an ECOPACK® package
■
For 5 V applications, refer to the M48Z512A
The M48Z512BV ZEROPOWER® RAM is a nonvolatile, 4,194,304-bit static RAM organized as
524,288 words by 8 bits. The devices combine an
internal lithium battery, a CMOS SRAM and a
control circuit in a plastic, 32-pin DIP module.
32
August 2008
1
PMDIP32 (PM) module
Rev 1
1/20
www.st.com
1
Contents
M48Z512BV
Contents
1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
M48Z512BV
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PMDIP32 – 32-pin plastic DIP module, package mechanical data. . . . . . . . . . . . . . . . . . . 17
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20
List of figures
M48Z512BV
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
4/20
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PMDIP32 – 32-pin plastic DIP module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 17
M48Z512BV
1
Device overview
Device overview
Figure 1.
Logic diagram
VCC
19
8
A0-A18
W
DQ0-DQ7
M48Z512BV
E
G
VSS
AI02043
Table 1.
Signal names
A0-A18
DQ0-DQ7
Address inputs
Data inputs/outputs
E
Chip enable input
G
Output enable input
W
WRITE enable input
VCC
Supply voltage
VSS
Ground
5/20
Device overview
Figure 2.
M48Z512BV
DIP connections
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
M48Z512BV
9
10
11
12
13
14
15
16
VCC
A15
A17
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AI02044
Figure 3.
Block diagram
VCC
A0-A18
POWER
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
512K x 8
SRAM ARRAY
DQ0-DQ7
E
W
G
INTERNAL
BATTERY
VSS
6/20
AI02045
M48Z512BV
2
Operating modes
Operating modes
The M48Z512BV also has its own power-fail detect circuit. The control circuitry constantly
monitors the single VCC supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit WRITE protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low VCC. As VCC falls below the
switchover voltage (VSO), the control circuitry connects the battery which maintains data
until valid power returns.
The ZEROPOWER® RAM replaces industry standard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special WRITE timing or limitations on the number of
WRITEs that can be performed.
Table 2.
Operating modes(1)
Mode
VCC
Deselect
WRITE
3.0 to 3.6 V
READ
READ
Deselect
VSO to VPFD
Deselect
≤
(min)(2)
VSO(2)
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
X
X
X
High Z
CMOS standby
X
X
X
High Z
Battery backup mode
1. See Table 10 on page 16 for details.
2. X = VIH or VIL; VSO = battery backup switchover voltage.
2.1
READ mode
The M48Z512BV is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
4,194,304 locations in the static storage array. Thus, the unique address specified by the 19
address inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (tAVQV) after the last
address input signal is stable, providing that the E (chip enable) and G (output enable)
access times are also satisfied. If the E and G access times are not met, valid data will be
available after the later of chip enable access time (tELQV) or output enable access time
(tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the
outputs are activated before tAVQV, the data lines will be driven to an indeterminate state
until tAVQV. If the address inputs are changed while E and G remain low, output data will
remain valid for output data hold time (tAXQX) but will go indeterminate until the next address
access.
7/20
Operating modes
Figure 4.
M48Z512BV
Chip enable or output enable controlled, READ mode AC waveforms
tAVAV
A0-A18
VALID
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01221
1. WRITE enable (W) = high.
Figure 5.
Address controlled, READ mode AC waveforms
A0-A18
tAVAV
tAVQV
DQ0-DQ7
tAXQX
DATA VALID
AI01220
1. Chip enable (E) and output enable (G) = low, WRITE enable (W) = high.
8/20
M48Z512BV
Operating modes
Table 3.
READ mode AC characteristics
Parameter(1)
Symbol
Min
Max
Unit
tAVAV
READ cycle time
tAVQV
Address valid to output valid
85
ns
tELQV
Chip enable low to output valid
85
ns
tGLQV
Output enable low to output valid
45
ns
(2)
85
ns
Chip enable low to output transition
5
ns
tGLQX(2)
Output enable low to output transition
5
ns
tEHQZ(2)
Chip enable high to output Hi-Z
35
ns
tGHQZ(2)
Output enable high to output Hi-Z
25
ns
tELQX
tAXQX
Address transition to output transition
5
ns
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6 V (except where noted).
2. CL = 5 pF.
2.2
WRITE mode
The M48Z512BV is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E.
The addresses must be held valid throughout the cycle. E or W must return high for a
minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE
cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for
tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus
contention; although, if the output bus has been activated by a low on E and G, a low on W
will disable the outputs tWLQZ after W falls.
9/20
Operating modes
Figure 6.
M48Z512BV
WRITE enable controlled, WRITE AC waveforms
tAVAV
A0-A18
VALID
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DATA INPUT
DQ0-DQ7
tDVWH
AI01222
1. Output enable (G) = high.
Figure 7.
Chip enable controlled, WRITE AC waveforms
tAVAV
VALID
A0-A18
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01223
1. Output enable (G) = high.
10/20
M48Z512BV
Operating modes
Table 4.
WRITE mode AC characteristics
Parameter(1)
Symbol
Min
Max
Unit
tAVAV
WRITE cycle time
85
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable low
0
ns
tWLWH
WRITE enable pulse width
65
ns
tELEH
Chip enable low to chip enable high
75
ns
tWHAX
WRITE enable high to address transition
5
ns
tEHAX
Chip enable high to address transition
15
ns
tDVWH
Input valid to WRITE enable high
35
ns
tDVEH
Input valid to chip enable high
35
ns
tWHDX
WRITE enable high to input transition
0
ns
tEHDX
Chip enable high to input transition
10
ns
tWLQZ(2)(3)
WRITE enable low to output Hi-Z
30
ns
tAVWH
Address valid to WRITE enable high
75
ns
tAVEH
Address valid to chip enable high
75
ns
WRITE enable high to output transition
5
ns
tWHQX(2)(3)
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6 V (except where noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z512BV operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect,
WRITE protecting itself tWP after VCC falls below VPFD. All outputs become high impedance,
and all inputs are treated as “don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time tWP, WRITE protection
takes place. When VCC drops below VSO, the control circuit switches power to the internal
energy source which preserves data.
The internal coin cell will maintain data in the M48Z512BV after the initial application of VCC
for an accumulated period of at least 10 years when VCC is less than VSO. As system power
returns and VCC rises above VSO, the battery is disconnected, and the power supply is
switched to external VCC. WRITE protection continues for tER after VCC reaches VPFD to
allow for processor stabilization. After tER, normal RAM operation can resume.
For more information on battery storage life refer to the application note AN1012.
11/20
Operating modes
2.4
M48Z512BV
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (see Figure 8)
is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, ST recommends connecting a schottky
diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817
is recommended for through hole and MBRS120T3 is recommended for surface-mount).
Figure 8.
Supply voltage protection
VCC
VCC
0.1μF
DEVICE
VSS
AI02169
12/20
M48Z512BV
3
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 5.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
TA
Ambient operating temperature
0 to 70
°C
TSTG
Storage temperature (VCC off)
–40 to 85
°C
TBIAS
Temperature under bias
0 to 70
°C
260
°C
TSLD
(1)
Lead solder temperature for 10 seconds
VIO
Input or output voltages
–0.3 to 4.6
V
VCC
Supply voltage
–0.3 to 4.6
V
IO
Output current
20
mA
PD
Power dissipation
1
W
1. For DIP package: soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to
exceed 150°C for longer than 30 seconds). No preheating above 150°C, or direct exposure to IR reflow (or
IR preheat) allowed, to avoid damaging the Lithium battery.
Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
13/20
DC and AC parameters
4
M48Z512BV
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the dc and
ac characteristics of the device. The parameters in the following dc and ac characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 6.
Operating and AC measurement conditions(1)
Parameter
Value
Unit
3.0 to 3.6
V
0 to 70
°C
Load capacitance (CL)
50
pF
Input rise and fall times
≤5
ns
0 to 3
V
1.5
V
Supply voltage (VCC)
Ambient operating temperature (TA)
Input pulse voltages
Input and output timing ref. voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
Figure 9.
AC measurement load circuit
DEVICE
UNDER
TEST
CL = 50 pF
CL includes JIG capacitance
Table 7.
CIO(3)
AI03903
Capacitance
Parameter(1)(2)
Symbol
CIN
1.75 V
Min
Max
Unit
Input capacitance
10
pF
Input/output capacitance
10
pF
1. Effective capacitance measured with power supply at 3.3 V; sampled only, not 100% tested.
2. Outputs deselected.
3. At 25°C.
14/20
M48Z512BV
DC and AC parameters
Table 8.
Sym
ILI(2)
ILO
(2)
DC characteristics
Parameter
Input leakage current
Output leakage current
Test condition(1)
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
E = VIL
outputs open
50
mA
E = VIH
4
mA
E ≥ VCC – 0.2V
3
mA
ICC
Supply current
ICC1
Supply current (standby) TTL
ICC2
Supply current (standby) CMOS
VIL
Input low voltage
–0.3
0.6
V
VIH
Input high voltage
2.2
VCC + 0.3
V
VOL
Output low voltage
IOL = 2.1mA
0.4
V
VOH
Output high voltage
IOH = –1mA
2.2
V
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6 V (except where noted).
2. Outputs deselected.
15/20
DC and AC parameters
Table 9.
M48Z512BV
Power down/up AC characteristics
Parameter(1)
Symbol
Min
Typ
Max
Unit
tF
VCC fall time, VPFD to VSS
150
µs
tR
VCC rise time, VSS to VPFD
150
µs
tWP
WRITE protect time
tER
E recovery time
25
µs
70
140
ms
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6 V (except where noted).
Table 10.
Power down/up trip points DC characteristics
Parameter(1)(2)
Symbol
VPFD
Power-fail deselect voltage
VSO
Battery backup switchover voltage
tDR
(3)
Min
Typ
Max
Unit
2.8
2.9
3.0
V
2.4
Expected data retention time
V
10
Years
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6 V (except where noted).
3. At 25°C, VCC = 0 V.
Figure 10. Power down/up mode AC waveforms
tR
tF
VCC
VPFD
VSO
VSS
tDR
tWP
INPUTS
RECOGNIZED
(Including E)
OUTPUTS
VALID
tER
DON’T CARE
HIGH-Z
RECOGNIZED
VALID
AI02385
16/20
M48Z512BV
5
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 11. PMDIP32 – 32-pin plastic DIP module, package outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
PMDIP
1. Drawing is not to scale.
Table 11.
PMDIP32 – 32-pin plastic DIP module, package mechanical data
mm
inches
Symb
Typ
Min
Max
A
9.27
9.52
A1
0.38
B
0.43
0.59
0.017
0.023
C
0.20
0.33
0.008
0.013
D
42.42
43.18
1.670
1.700
E
18.03
18.80
0.710
0.740
e1
2.29
2.79
0.090
0.110
e3
Typ
Min
Max
0.365
0.375
0.015
38.10
1.50
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
1.91
2.79
0.075
0.110
N
32
32
17/20
Part numbering
6
M48Z512BV
Part numbering
Table 12.
Ordering information scheme
Example:
M48Z
512BV
–85
PM
1
Device type
M48Z
Supply voltage and WRITE protect voltage
512BV: VCC = 3.0 to 3.6 V; VPFD = 2.8 to 3.0 V
Speed
–85 = 85 ns
Package
PM = PMDIP32
Temperature range
1 = 0 to 70°C
Shipping method
blank = ECOPACK® package, tubes
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
18/20
M48Z512BV
7
Revision history
Revision history
Table 13.
Document revision history
Date
Revision
15-Aug-2008
1
Changes
Initial release
19/20
M48Z512BV
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