STMicroelectronics M54HC373B1R Octal d-type latch with 3 state output hc373 non inverting - hc533 inverting Datasheet

M54/74HC373
M54/74HC533
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT
HC373 NON INVERTING - HC533 INVERTING
.
.
.
.
.
.
.
.
HIGH SPEED
tPD = 11 ns (TYP.) AT VCC = 5 V
LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH= 6 mA (MIN.)
BALANCED PROPAGATION DELAYS
tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS373/533
DESCRIPTION
The M54/74HC373/533 are high speed CMOS
OCTAL LATCH WITH 3-STATE OUTPUTS
2
fabricated with in silicon gate C MOS technology.
These ICs achive the high speed operation similar
to equivalent LSTTL while maintaning the CMOS
low power dissipation.
These 8 bit D-Type latches are controlled by a latch
enable input (LE) and a output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic level
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R
M74HCXXXM1R
M74HCXXXB1R
M74HCXXXC1R
of D input data. While the OE input is at low level,
the eight outputs will be in a normal logic state (high
or low logic level) and while high level the outpts will
be in a high impedance state.
The application designer has a choise of
combination of inverting and non inverting outputs.
The three state output configuration and the wide
choise of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against discharge and transient excess voltage.
PIN CONNECTION (top view)
HC373
October 1993
HC533
HC373
HC533
1/13
M54/M74HC373/533
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION (HC373)
PIN No
SYMBOL
1
OE
2, 5, 6, 9,
12, 15, 16,
19
Q0 to Q7
3, 4, 7, 8,
13, 14, 17,
18
D0 to D7
11
LE
10
20
GND
V CC
NAME AND FUNCTION
PIN DESCRIPTION (HC533)
PIN No
SYMBOL
1
OE
3 State outputs
2, 5, 6, 9,
12, 15, 16,
19
Q0 to Q7
3 State outputs
Data Inputs
3, 4, 7, 8,
13, 14, 17,
18
D0 to D7
Data Inputs
3 State output Enable
Input (Active LOW)
Latch Enable Input
11
LE
Ground (0V)
Positive Supply Voltage
10
20
GND
VCC
NAME AND FUNCTION
3 State output Enable
Input (Active LOW)
Latch Enable Input
Ground (0V)
Positive Supply Voltage
IEC LOGIC SYMBOLS
HC373
2/13
HC533
M54/M74HC373/533
TRUTH TABLE
INPUTS
OUTPUTS
OE
H
LE
X
D
X
Q (HC373)
Z
Q (HC533)
Z
L
L
L
L
H
H
X
L
H
NO CHANGE *
L
H
NO CHANGE *
H
L
X: DON’T CARE
Z: HIGH IMPEDANCE
*: Q/Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE LE INPUT IS TAKEN LOW LOGIC LEVEL.
LOGIC DIAGRAMS
HC373
HC533
3/13
M54/M74HC373/533
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VCC
VI
Supply Voltage
DC Input Voltage
-0.5 to +7
-0.5 to VCC + 0.5
V
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
IOK
DC Input Diode Current
DC Output Diode Current
± 20
± 20
mA
mA
IO
DC Output Source Sink Current Per Output Pin
± 35
mA
DC VCC or Ground Current
± 70
mA
500 (*)
mW
ICC or IGND
Parameter
PD
Power Dissipation
Tstg
TL
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
300
o
o
C
C
Absolute Maximum Ratings are those values beyond which damage tothe device may occur. Functional operation under these conditions is not implied.
(*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
VI
Input Voltage
VO
Top
Output Voltage
Operating Temperature:
tr, tf
Input Rise and Fall Time
4/13
M54HC Series
M74HC Series
VCC = 2 V
Value
2 to 6
Unit
V
0 to VCC
V
0 to VCC
-55 to +125
-40 to +85
0 to 1000
V
C
o
C
ns
VCC = 4.5 V
0 to 500
VCC = 6 V
0 to 400
o
M54/M74HC373/533
DC SPECIFICATIONS
Test Conditions
Symbol
VIH
V IL
Parameter
High Level Input
Voltage
Low Level Input
Voltage
Value
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
2.0
1.5
1.5
1.5
4.5
6.0
3.15
4.2
3.15
4.2
3.15
4.2
High Level
Output Voltage
0.5
0.5
0.5
4.5
1.35
1.35
1.35
2.0
4.5
6.0
4.5
VOL
Low Level Output
Voltage
6.0
2.0
4.5
6.0
4.5
6.0
II
IOZ
ICC
Input Leakage
Current
3 State Output
Off State Current
Quiescent Supply
Current
1.8
1.8
Unit
V
2.0
6.0
V OH
-40 to 85 oC -55 to 125 oC
74HC
54HC
Min. Max. Min. Max.
V
1.8
1.9
2.0
1.9
1.9
VI =
IO=-20 µA
VIH
or
V IL IO=-6.0 mA
4.4
5.9
4.5
6.0
4.4
5.9
4.4
5.9
4.18
4.31
4.13
4.10
IO=-7.8 mA
5.68
5.8
0.0
5.63
5.60
V
VI =
IO= 20 µA
VIH
or
V IL IO= 6.0 mA
0.1
0.1
0.1
0.0
0.1
0.1
0.1
0.0
0.17
0.1
0.26
0.1
0.33
0.1
0.40
IO= 7.8 mA
0.18
V
0.26
0.33
0.40
VI = VCC or GND
±0.1
±1
±1
µA
VI = VIH or VIL
VO = VCC or GND
6.0 VI = VCC or GND
±0.5
±5.0
±10
µA
4
40
80
µA
6.0
6.0
5/13
M54/M74HC373/533
AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6 ns)
Test Conditions
o
Symbol
Parameter
VCC
(V)
tTLH
tTHL
Output Transition
Time
2.0
tPLH
tPHL
Propagation
Delay Time
(LE, D - Q, Q)
tPZL
tPZH
3 State Output
Enable Time
tPLZ
tPHZ
3 State Output
Disable Time
tW(H)
Minimum Pulse
Width (LE)
ts
th
Minimum Set-up
Time
Minimum Hold
Time
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
TA = 25 C
54HC and 74HC
Min. Typ. Max.
25
60
CL
(pF)
50
50
150
50
RL = 1 KΩ
150
RL = 1 KΩ
50
RL = 1 KΩ
6.0
2.0
7
6
42
14
12
12
10
125
25
21
15
13
155
31
26
18
15
190
38
32
57
19
16
39
175
35
30
125
220
44
37
155
265
53
45
190
13
11
54
18
15
25
21
175
35
30
31
26
220
44
37
38
32
265
53
45
30
14
125
25
155
31
190
38
13
15
21
75
26
95
32
110
CPD (*)
Input Capacitance
Out put
Capacitance
Power Dissipation
Capacitance
Unit
ns
ns
ns
ns
ns
ns
4.5
6.0
2.0
50
6
6
16
15
13
50
19
16
65
22
19
75
ns
4.5
6.0
2.0
4.5
50
4
3
10
9
5
5
13
11
5
5
15
13
5
5
ns
5
10
5
10
5
10
50
6.0
CIN
COUT
Value
-40 to 85 oC -55 to 125 oC
74HC
54HC
Min. Max. Min. Max.
75
90
5
10
38
ns
pF
pF
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC •fIN + ICC/8 (per Flip Flop) and the
CPD when n pcs of Flip Flop operate, can be gained by following equation: CPD (TOTAL) = 22 + 16 x n [pF]
6/13
M54/M74HC373/533
SWITCHING CHARACTERISTICS TEST WAVEFORM
tPLH, tPHL, (D - Q, Q)
tPLH, tPHL (LE - Q, Q), ts, th, tW
tPLZ, tPZL
The 1KΩ load resistors should be connected between
outputs and VCC line and the 50pF load capacitors
should be connected between outputsand GND line.
All inputs except OE input should be connected to VCC
line or GND line such that outputs will be in low logic
level while OE input is held low.
tPHZ, tPZH
The 1KΩ load resistors and the 50pF load capacitors
should be connected between each output and GND
line.
All inputs except OE input should be connected to VCC
or GND line such that output will be in high logic level
while OE input is held low.
7/13
M54/M74HC373/533
TEST CIRCUIT ICC (Opr.)
INPUT WAVEFORM IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICS TEST.
8/13
M54/M74HC373/533
Plastic DIP20 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
a1
0.254
B
1.39
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.010
1.65
0.055
0.065
b
0.45
0.018
b1
0.25
0.010
D
25.4
1.000
E
8.5
0.335
e
2.54
0.100
e3
22.86
0.900
F
7.1
0.280
I
3.93
0.155
L
Z
3.3
0.130
1.34
0.053
P001J
9/13
M54/M74HC373/533
Ceramic DIP20 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
25
0.984
B
7.8
0.307
D
E
3.3
0.5
e3
0.130
1.78
0.020
22.86
0.070
0.900
F
2.29
2.79
0.090
0.110
G
0.4
0.55
0.016
0.022
I
1.27
1.52
0.050
0.060
L
0.22
0.31
0.009
0.012
M
0.51
1.27
0.020
0.050
N1
P
Q
4° (min.), 15° (max.)
7.9
8.13
5.71
0.311
0.320
0.225
P057H
10/13
M54/M74HC373/533
SO20 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
2.65
0.10
0.104
0.20
a2
MAX.
0.004
0.007
2.45
0.096
b
0.35
0.49
0.013
0.019
b1
0.23
0.32
0.009
0.012
C
0.50
0.020
c1
45° (typ.)
D
12.60
13.00
0.496
0.512
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.40
7.60
0.291
0.299
L
0.50
1.27
0.19
0.050
M
S
0.75
0.029
8° (max.)
P013L
11/13
M54/M74HC373/533
PLCC20 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
9.78
10.03
0.385
0.395
B
8.89
9.04
0.350
0.356
D
4.2
4.57
0.165
0.180
d1
2.54
0.100
d2
0.56
0.022
E
7.37
8.38
0.290
0.330
e
1.27
0.050
e3
5.08
0.200
F
0.38
0.015
G
0.101
0.004
M
1.27
0.050
M1
1.14
0.045
P027A
12/13
M54/M74HC373/533
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
13/13
Similar pages