Numonyx M58WR016QB70ZB6 16 mbit and 32 mbit (x16, multiple bank, burst) 1.8v supply flash memory Datasheet

M58WR016QT M58WR016QB
M58WR032QT M58WR032QB
16 Mbit and 32 Mbit (x16, Multiple Bank, Burst)
1.8V supply Flash memories
Feature summary
■
■
Supply voltage
– VDD = 1.7V to 2V for Program, Erase and
Read
– VDDQ = 1.7V to 2.24V for I/O Buffers
– VPP = 12V for fast Program (optional)
FBGA
Synchronous / Asynchronous Read
– Synchronous Burst Read mode: 66MHz
– Asynchronous/ Synchronous Page Read
mode
– Random access: 60ns, 70ns, 80ns
■
Synchronous Burst Read Suspend
■
Programming time
– 8µs by Word typical for Fast Factory
Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
■
Memory blocks
– Multiple Bank memory array: 4 Mbit Banks
– Parameter blocks (top or bottom location)
■
Dual operations
– Program Erase in one bank while Read in
others
– No delay between Read and Write
operations
■
Block locking
– All blocks locked at Power up
– Any combination of blocks can be locked
– WP for Block Lock-Down
■
Security
– 128 bit user programmable OTP cells
– 64 bit unique device number
■
Common Flash Interface (CFI)
■
100,000 program/erase cycles per block
November 2007
VFBGA56 (ZB)
7.7 x 9 mm
■
Electronic signature
– Manufacturer Code: 20h
– Device Codes:
M58WR016QT (Top): 8812h.
M58WR016QB (Bottom): 8813h
M58WR032QT (Top): 8814h
M58WR032QB (Bottom): 8815h
■
ECOPACK® package available
Rev 2
1/110
www.numonyx.com
1
Contents
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
2.1
Address Inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2
Data Input/Output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7
Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.11
VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.12
VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.13
VPP Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.14
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.15
VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3
Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Command interface - standard commands . . . . . . . . . . . . . . . . . . . . . 20
2/110
5.1
Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
6
5.3
Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5
Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.7
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.8
Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.9
Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.10
Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.11
Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.12
Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.13
Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.14
Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Command interface - factory program commands . . . . . . . . . . . . . . . 28
6.1
Bank Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2
Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3
Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4
Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5
7
Contents
6.4.1
Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.2
Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.3
Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.4
Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Quadruple Enhanced Factory Program command . . . . . . . . . . . . . . . . . . 32
6.5.1
Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.2
Load Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.3
Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.4
Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.0.1
Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . 35
7.0.2
Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.0.3
Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.0.4
Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.0.5
VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.0.6
Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Contents
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9
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
7.0.7
Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.0.8
Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . 37
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1
Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2
X-Latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3
Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.4
Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.5
Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.6
Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.7
Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.8
Wrap Burst Bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.9
Burst length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1
Asynchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2
Synchronous Burst Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2.1
9.3
Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10
Dual operations and Multiple Bank architecture . . . . . . . . . . . . . . . . . 49
11
Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.1
Reading a Block’s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2
Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.3
Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.4
Lock-Down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.5
Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 52
12
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 54
13
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
15
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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16
Contents
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Appendix B Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
C.1
Enhanced Factory Program pseudo code. . . . . . . . . . . . . . . . . . . . . . . . 102
C.2
Quadruple Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . 104
Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 105
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5/110
List of tables
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
6/110
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
M58WR016QT/B Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
M58WR032QT/B Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Factory Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Configuration Register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Program/Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Asynchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Synchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Reset and Power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, package mechanical
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Daisy chain ordering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Top boot block addresses, M58WR016QT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Bottom boot block addresses, M58WR016QB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Top boot block addresses, M58WR032QT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Bottom boot block addresses, M58WR032QB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CFI Query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Burst Read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Command interface states - modify table, next output state. . . . . . . . . . . . . . . . . . . . . . . 106
Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . . 108
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
M58WR016QT/B memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
M58WR032QT/B memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
X-Latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Asynchronous Random Access Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Asynchronous Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Synchronous Burst Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Single Synchronous Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Synchronous Burst Read Suspend AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Reset and Power-up AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline . . . . . 73
Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Double Word Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Quadruple Word Program flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Program Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 96
Block Erase flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Erase Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Protection Register Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 100
Enhanced Factory Program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Quadruple Enhanced Factory Program flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7/110
Summary description
1
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Summary description
The M58WR016QT/B and M58WR032QT/B are 16 Mbit (1 Mbit x16) and 32 Mbit (2 Mbit
x16) non-volatile Flash memories, respectively. They will be referred to as M58WRxxxQT/B
throughout the document unless otherwise specified.
The M58WRxxxQT/B may be erased electrically at block level and programmed in-system
on a Word-by-Word basis using a 1.7V to 2V VDD supply for the circuitry and a 1.7V to
2.24V VDDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided
to speed up customer programming.
The VPP pin can also be used as a control pin to provide absolute protection against
program or erase.
The device features an asymmetrical block architecture.
●
M58WR016QT/B has an array of 39 blocks, and is divided into 4 Mbit banks. There are
3 banks each containing 8 main blocks of 32 KWords, and one parameter bank
containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords.
●
M58WR032QT/B has an array of 71 blocks, and is divided into 4 Mbit banks. There are
7 banks each containing 8 main blocks of 32 KWords, and one parameter bank
containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords.
The Multiple Bank Architecture allows Dual Operations, while programming or erasing in
one bank, Read operations are possible in other banks. Only one bank at a time is allowed
to be in Program or Erase mode. It is possible to perform burst reads that cross bank
boundaries. The bank architectures are summarized in Table 2 and Table 3, and the
memory maps are shown in Figure 3 and Figure 4. The Parameter Blocks are located at the
top of the memory address space for the M58WR016QT and M58WR032QT, and at the
bottom for the M58WR016QB and M58WR032QB.
Each block can be erased separately. Erase can be suspended, in order to perform program
in any other block, and then resumed. Program can be suspended to read data in any other
block and then resumed. Each block can be programmed and erased over 100,000 cycles
using the supply voltage VDD. There are two Enhanced Factory programming commands
available to speed up programming.
Program and Erase commands are written to the Command Interface of the memory. An
internal Program/Erase Controller takes care of the timings necessary for program and
erase operations. The end of a program or erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The device supports synchronous burst read and asynchronous read from all blocks of the
memory array; at power-up the device is configured for asynchronous read. In synchronous
burst mode, data is output on each clock cycle at frequencies of up to 66MHz. The
synchronous burst read operation can be suspended and resumed.
The device features an Automatic Standby mode. When the bus is inactive during
Asynchronous Read operations, the device automatically switches to the Automatic Standby
mode. In this condition the power consumption is reduced to the standby value IDD4 and the
outputs are still driven.
The M58WRxxxQT/B features an instant, individual block locking scheme that allows any
block to be locked or unlocked with no latency, enabling instant code and data protection. All
blocks have three levels of protection. They can be locked and locked-down individually
8/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Summary description
preventing any accidental programming or erasure. There is an additional hardware
protection against program and erase. When VPP ≤VPPLK all blocks are protected against
program or erase. All blocks are locked at Power- Up.
The device includes a Protection Register to increase the protection of a system’s design.
The Protection Register is divided into two segments: a 64 bit segment containing a unique
device number written by Numonyx, and a 128 bit segment One-Time-Programmable (OTP)
by the user. The user programmable segment can be permanently protected. Figure 5
shows the Protection Register Memory Map.
The memory is offered in a VFBGA56, 7.7 x 9mm, 8x7 active ball array, 0.75 mm pitch
package and is supplied with all the bits erased (set to ’1’).
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
9/110
Summary description
Figure 1.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Logic Diagram
VDD VDDQ VPP
16
A0-Amax(1)
DQ0-DQ15
W
E
G
RP
M58WR016QT
M58WR016QB
M58WR032QT
M58WR032QB
WAIT
WP
L
K
VSS
VSSQ
AI10170
1. Amax is equal to A19 for the M58WR016QT/B and to A20 for the M58WR032QT/B.
Table 1.
Signal names
A0-Amax(1)
Address Inputs
DQ0-DQ15
Data Input/Outputs, Command Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset
WP
Write Protect
K
Clock
L
Latch Enable
WAIT
Wait
VDD
Supply Voltage
VDDQ
Supply Voltage for Input/Output Buffers
VPP
Optional Supply Voltage for Fast Program & Erase
VSS
Ground
VSSQ
Ground Input/Output Supply
NC
Not Connected Internally
1. Amax is equal to A19 for the M58WR016QT/B and to A20 for the M58WR032QT/B.
10/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 2.
Summary description
VFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A11
A8
VSS
VDD
VPP
A18
A6
A4
B
A12
A9
A20
K
RP
A17
A5
A3
C
A13
A10
NC
L
W
A19
A7
A2
D
A15
A14
WAIT
A16
DQ12
WP
NC
A1
E
VDDQ
DQ15
DQ6
DQ4
DQ2
DQ1
E
A0
F
VSS
DQ14
DQ13
DQ11
DQ10
DQ9
DQ0
G
G
DQ7
VSSQ
DQ5
VDD
DQ3
VDDQ
DQ8
VSSQ
AI09301
1. Ball B3 is A20 in the M58WR032QT/B and it is Not Connected internally (NC) in the M58WR016QT/B.
Table 2.
M58WR016QT/B Bank architecture
Number
Bank Size
Parameter Blocks
Main Blocks
Parameter Bank
4 Mbits
8 blocks of 4 KWords
7 blocks of 32 KWords
Bank 1
4 Mbits
-
8 blocks of 32 KWords
Bank 2
4 Mbits
-
8 blocks of 32 KWords
Bank 3
4 Mbits
-
8 blocks of 32 KWords
11/110
Summary description
Table 3.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
M58WR032QT/B Bank architecture
Parameter Bank
4 Mbits
8 blocks of 4 KWords
7 blocks of 32 KWords
Bank 1
4 Mbits
-
8 blocks of 32 KWords
Bank 2
4 Mbits
-
8 blocks of 32 KWords
Bank 3
4 Mbits
-
8 blocks of 32 KWords
----
Main Blocks
----
Parameter Blocks
----
Bank Size
----
Number
Bank 6
4 Mbits
-
8 blocks of 32 KWords
Bank 7
4 Mbits
-
8 blocks of 32 KWords
Figure 3.
M58WR016QT/B memory map
M58WR016QB - Bottom Boot Block
Address lines A0-A19
M58WR016QT - Top Boot Block
Address lines A0-A19
00000h
07FFFh
8 Main
Blocks
Bank 3
38000h
3FFFFh
40000h
47FFFh
32 KWord
8 Main
Blocks
32 KWord
8 Main
Blocks
Parameter
Bank
F0000h
F7FFFh
F8000h
F8FFFh
FF000h
FFFFFh
78000h
7FFFFh
80000h
87FFFh
32 KWord
8 Parameter
Blocks
4KWord
32 KWord
7 Main
Blocks
32 KWord
32 KWord
8 Main
Blocks
32 KWord
32 KWord
8 Main
Blocks
Bank 2
32 KWord
4 KWord
8 Parameter
Blocks
Bank 3
4 KWord
4 KWord
Bank 1
32 KWord
7 Main
Blocks
07000h
07FFFh
08000h
0FFFFh
38000h
3FFFFh
40000h
47FFFh
32 KWord
Bank 1
B8000h
BFFFFh
C0000h
C7FFFh
Parameter
Bank
32 KWord
Bank 2
78000h
7FFFFh
80000h
87FFFh
00000h
00FFFh
32 KWord
B8000h
BFFFFh
C0000h
C7FFFh
F8000h
FFFFFh
32 KWord
32 KWord
8 Main
Blocks
32 KWord
AI10171
12/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 4.
M58WR032QT/B memory map
M58WR032QB - Bottom Boot Block
Address lines A0-A20
M58WR032QT - Top Boot Block
Address lines A0-A20
000000h
007FFFh
32 KWord
038000h
03FFFFh
32 KWord
100000h
107FFFh
8 Main
Blocks
1B8000h
1BFFFFh
1C0000h
1C7FFFh
1F0000h
1F7FFFh
1F8000h
1F8FFFh
1FF000h
1FFFFFh
078000h
07FFFFh
080000h
087FFFh
0B8000h
0BFFFFh
0C0000h
0C7FFFh
32 KWord
8 Main
Blocks
8 Parameter
Blocks
4KWord
32 KWord
7 Main
Blocks
32 KWord
32 KWord
8 Main
Blocks
32 KWord
32 KWord
8 Main
Blocks
Bank 2
32 KWord
Bank 1
4 KWord
Bank 1
32 KWord
8 Main
Blocks
007000h
007FFFh
008000h
00FFFFh
038000h
03FFFFh
040000h
047FFFh
32 KWord
Bank 2
178000h
17FFFFh
180000h
187FFFh
Parameter
Bank
32 KWord
Bank 3
138000h
13FFFFh
140000h
147FFFh
000000h
000FFFh
8 Main
Blocks
Bank 7
Parameter
Bank
Summary description
32 KWord
32 KWord
8 Main
Blocks
Bank 3
32 KWord
0F8000h
0FFFFFh
32 KWord
1C0000h
1C7FFFh
32 KWord
1F8000h
1FFFFFh
32 KWord
32 KWord
7 Main
Blocks
32 KWord
4 KWord
8 Parameter
Blocks
Bank 7
4 KWord
8 Main
Blocks
AI10172
13/110
Signal descriptions
2
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Signal descriptions
See Figure 1: Logic Diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-Amax)
Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.
2.2
Data Input/Output (DQ0-DQ15)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
or inputs a command or the data to be programmed during a Bus Write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is deselected, the outputs are high
impedance and the power consumption is reduced to the stand-by level.
2.4
Output Enable (G)
The Output Enable controls data outputs during the Bus Read operation of the memory.
2.5
Write Enable (W)
The Write Enable controls the Bus Write operation of the memory’s Command Interface.
The data and address inputs are latched on the rising edge of Chip Enable or Write Enable
whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at VIL, the Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (refer to Table 14: Lock status).
14/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
2.7
Signal descriptions
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to Table 19: DC characteristics - currents
for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration
Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset
mode the device enters asynchronous read mode, but a negative transition of Chip Enable
or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to VRPH (refer to Table 20: DC characteristics - voltages).
2.8
Latch Enable (L)
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can
be kept Low (also at board level) when the Latch Enable function is not required or
supported.
2.9
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at VIL. Clock is don't care during asynchronous
read and in write operations.
2.10
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is
at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance.
The WAIT signal is not gated by Output Enable.
2.11
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (Read, Program and Erase).
2.12
VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered
independently from VDD. VDDQ can be tied to VDD or can use a separate supply.
15/110
Signal descriptions
2.13
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
VPP Program supply voltage
VPP is a power supply pin. The Supply Voltage VDD and the Program Supply Voltage VPP
can be applied in any order. The pin can also be used as a control input.
The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low
voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than
VPPLK gives an absolute protection against program or erase, while VPP in the VPP1 range
enables these functions (see Tables 19 and 20, DC Characteristics for the relevant values).
VPP is only sampled at the beginning of a program or erase; a change in its value after the
operation has started does not have any effect and program or erase operations continue.
If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be
stable until the Program/Erase algorithm is completed.
2.14
VSS Ground
VSS ground is the reference for the core supply. It must be connected to the system ground.
2.15
VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be
connected to VSS.
Note:
16/110
Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1µF ceramic
capacitor close to the pin (high frequency, inherently low inductance capacitors should be as
close as possible to the package). See Figure 9: AC measurement load circuit. The PCB
track widths should be sufficient to carry the required VPP program and erase currents.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
3
Bus operations
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus
Write, Address Latch, Output Disable, Standby and Reset. See Table 4: Bus operations, for
a summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the
memory and do not affect Bus Write operations.
3.1
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a read operation. The Chip Enable input
should be used to enable the device. Output Enable should be used to gate data onto the
output. The data read depends on the previous command written to the memory (see
Command Interface section). See Figures 10, 11, 12 and 13 Read AC Waveforms, and
Tables 21 and 22 Read AC Characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write Commands to the memory or latch Input Data to be
programmed. A bus write operation is initiated when Chip Enable and Write Enable are at
VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the
rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also
be latched prior to the write operation by toggling Latch Enable. In this case the Latch
Enable should be tied to VIH during the bus write operation.
See Figures 16 and 17, Write AC Waveforms, and Tables 23 and 24, Write AC
Characteristics, for details of the timing requirements.
3.3
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be
at VIL during address latch operations. The addresses are latched on the rising edge of
Latch Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at VIH.
17/110
Bus operations
3.5
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in stand-by when Chip Enable and Reset are at VIH. The
power consumption is reduced to the stand-by level and the outputs are set to high
impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable
switches to VIH during a program or erase operation, the device enters Standby mode when
finished.
3.6
Reset
During Reset mode the memory is deselected and the outputs are high impedance. The
memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the
Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If
Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory
content is no longer valid.
Table 4.
Bus operations(1)
Operation
Bus Read
WAIT(2)
E
G
W
L
RP
VIL
VIL
VIH
VIL(3)
VIH
Data Output
VIH
Data Input
Bus Write
VIL
VIH
VIL
VIL(3)
Address Latch
VIL
X
VIH
VIL
VIH
Data Output or Hi-Z(4)
Output Disable
VIL
VIH
VIH
X
VIH
Hi-Z
Standby
VIH
X
X
X
VIH
Hi-Z
Hi-Z
X
X
X
X
VIL
Hi-Z
Hi-Z
Reset
1. X = Don't care.
2. WAIT signal polarity is configured using the Set Configuration Register command.
3. L can be tied to VIH if the valid address has been previously latched.
4. Depends on G.
18/110
DQ15-DQ0
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
4
Command interface
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. An internal
Program/Erase Controller handles all timings and verifies the correct execution of the
Program and Erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time to monitor the progress or the result of the operation.
The Command Interface is reset to read mode when power is first applied, when exiting from
Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly.
Any invalid combination of commands will be ignored.
Refer to Table 5: Command codes and Appendix D, Tables 43, 44, 45 and 46, Command
Interface States - Modify and Lock Tables, for a summary of the Command Interface.
The Command Interface is split into two types of commands: Standard commands and
Factory Program commands. The following sections explain in detail how to perform each
command.
Table 5.
Command codes
Hex Code
Command
01h
Block Lock Confirm
03h
Set Configuration Register Confirm
10h
Alternative Program Setup
20h
Block Erase Setup
2Fh
Block Lock-Down Confirm
30h
Enhanced Factory Program Setup
35h
Double Word Program Setup
40h
Program Setup
50h
Clear Status Register
56h
Quadruple Word Program Setup
60h
Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set
Configuration Register Setup
70h
Read Status Register
75h
Quadruple Enhanced Factory Program Setup
80h
Bank Erase Setup
90h
Read Electronic Signature
98h
Read CFI Query
B0h
Program/Erase Suspend
C0h
Protection Register Program
D0h
Program/Erase Resume, Block Erase Confirm, Bank Erase Confirm, Block
Unlock Confirm or Enhanced Factory Program Confirm
FFh
Read Array
19/110
Command interface - standard commands
5
M58WR016QT, M58WR016QB, M58WR032QT,
Command interface - standard commands
The following commands are the basic commands used to read, write to and configure the
device. Refer to Table 6: Standard commands, in conjunction with the following text
descriptions.
5.1
Read Array command
The Read Array command returns the addressed bank to Read Array mode. One Bus Write
cycle is required to issue the Read Array command and return the addressed bank to Read
Array mode. Subsequent read operations will read the addressed location and output the
data. A Read Array command can be issued in one bank while programming or erasing in
another bank. However if a Read Array command is issued to a bank currently executing a
Program or Erase operation the command will be executed but the output data is not
guaranteed.
5.2
Read Status Register command
The Status Register indicates when a Program or Erase operation is complete and the
success or failure of operation itself. Issue a Read Status Register command to read the
Status Register content. The Read Status Register command can be issued at any time,
even during Program or Erase operations.
The following read operations output the content of the Status Register of the addressed
bank. The Status Register is latched on the falling edge of E or G signals, and can be read
until E or G returns to VIH. Either E or G must be toggled to update the latched data. See
Table 9 for the description of the Status Register Bits. This mode supports asynchronous or
single synchronous reads only.
5.3
Read Electronic Signature command
The Read Electronic Signature command reads the Manufacturer and Device Codes, the
Block Locking Status, the Protection Register, and the Configuration Register.
The Read Electronic Signature command consists of one write cycle to an address within
one of the banks. A subsequent Read operation in the same bank will output the
Manufacturer Code, the Device Code, the protection Status of the blocks in the targeted
bank, the Protection Register, or the Configuration Register (see Table 7).
If a Read Electronic Signature command is issued in a bank that is executing a Program or
Erase operation the bank will go into Read Electronic Signature mode, subsequent Bus
Read cycles will output the Electronic Signature data and the Program/Erase controller will
continue to program or erase in the background. This mode supports asynchronous or
single synchronous reads only, it does not support page mode or synchronous burst reads.
20/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - standard com-
5.4
Read CFI Query command
The Read CFI Query command is used to read data from the Common Flash Interface
(CFI). The Read CFI Query Command consists of one Bus Write cycle, to an address within
one of the banks. Once the command is issued subsequent Bus Read operations in the
same bank read from the Common Flash Interface.
If a Read CFI Query command is issued in a bank that is executing a Program or Erase
operation the bank will go into Read CFI Query mode, subsequent Bus Read cycles will
output the CFI data and the Program/Erase controller will continue to Program or Erase in
the background. This mode supports asynchronous or single synchronous reads only, it
does not support page mode or synchronous burst reads.
The status of the other banks is not affected by the command (see Table 12). After issuing a
Read CFI Query command, a Read Array command should be issued to the addressed
bank to return the bank to Read Array mode.
See Appendix B, Tables 33, 34, 35, 36, 37, 38, 39, 40, 41 and 42 for details on the
information contained in the Common Flash Interface memory area.
5.5
Clear Status Register command
The Clear Status Register command can be used to reset (set to ‘0’) error bits SR1, SR3,
SR4 and SR5 in the Status Register. One bus write cycle is required to issue the Clear
Status Register command. The Clear Status Register command does not change the Read
mode of the bank.
The error bits in the Status Register do not automatically return to ‘0’ when a new command
is issued. The error bits in the Status Register should be cleared before attempting a new
Program or Erase command.
21/110
Command interface - standard commands
5.6
M58WR016QT, M58WR016QB, M58WR032QT,
Block Erase command
The Block Erase command can be used to erase a block. It sets all the bits within the
selected block to ’1’. All previous data in the block is lost. If the block is protected then the
Erase operation will abort, the data in the block will not be changed and the Status Register
will output the error. The Block Erase command can be issued at any moment, regardless of
whether the block has been programmed or not.
Two Bus Write cycles are required to issue the command.
●
The first bus cycle sets up the Erase command.
●
The second latches the block address in the internal state machine and starts the
Program/Erase Controller.
If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5
are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot
be guaranteed when the Erase operation is aborted, the block must be erased again.
Once the command is issued the device outputs the Status Register data when any address
within the bank is read. At the end of the operation the bank will remain in Read Status
Register mode until a Read Array, Read CFI Query or Read Electronic Signature command
is issued.
During Erase operations the bank containing the block being erased will only accept the
Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend command, all other commands will be ignored. Refer to Dual
Operations section for detailed information about simultaneous operations allowed in banks
not being erased. Typical Erase times are given in Table 15: Program/Erase times and
endurance cycles.
See Appendix C, Figure 24: Block Erase flowchart and pseudo code, for a suggested
flowchart for using the Block Erase command.
5.7
Program command
The memory array can be programmed Word-by-Word. Only one Word in one bank can be
programmed at any one time. If the block is protected, the program operation will abort, the
data in the block will not be changed and the Status Register will output the error.
Two bus write cycles are required to issue the Program Command.
●
The first bus cycle sets up the Program command.
●
The second latches the Address and the Data to be written and starts the
Program/Erase Controller.
After programming has started, read operations in the bank being programmed output the
Status Register content.
During Program operations the bank being programmed will only accept the Read Array,
Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase
Suspend command. Refer to Dual Operations section for detailed information about
simultaneous operations allowed in banks not being programmed. Typical Program times
are given in Table 15: Program/Erase times and endurance cycles.
Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the
program operation is aborted, the memory location must be reprogrammed.
See Appendix C, Figure 20: Program flowchart and pseudo code, for the flowchart for using
the Program command.
22/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - standard com-
5.8
Program/Erase Suspend command
The Program/Erase Suspend command is used to pause a Program or Block Erase
operation. A Bank Erase operation cannot be suspended.
One bus write cycle is required to issue the Program/Erase command. Once the
Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will
be set to ‘1’. The command can be addressed to any bank.
During Program/Erase Suspend the Command Interface will accept the Program/Erase
Resume, Read Array (cannot read the erase-suspended block or the program-suspended
Word), Read Status Register, Read Electronic Signature and Read CFI Query commands.
Additionally, if the suspend operation was Erase then the Clear status Register, Program,
Block Lock, Block Lock-Down or Block Unlock commands will also be accepted. The block
being erased may be protected by issuing the Block Lock, Block Lock-Down or Protection
Register Program commands. Only the blocks not being erased may be read or
programmed correctly. When the Program/Erase Resume command is issued the operation
will complete. Refer to the Dual Operations section for detailed information about
simultaneous operations allowed during Program/Erase Suspend.
During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip
Enable to VIH. Program/Erase is aborted if Reset turns to VIL.
See Appendix C, Figure 23: Program Suspend & Resume flowchart and pseudo code, and
Figure 25: Erase Suspend & Resume flowchart and pseudo code for flowcharts for using the
Program/Erase Suspend command.
5.9
Program/Erase Resume command
The Program/Erase Resume command can be used to restart the Program/Erase Controller
after a Program/Erase Suspend command has paused it. One Bus Write cycle is required to
issue the command. The command can be written to any address.
The Program/Erase Resume command does not change the read mode of the banks. If the
suspended bank was in Read Status Register, Read Electronic signature or Read CFI
Query mode the bank remains in that mode and outputs the corresponding data. If the bank
was in Read Array mode subsequent read operations will output invalid data.
If a Program command is issued during a Block Erase Suspend, then the erase cannot be
resumed until the programming operation has completed. It is possible to accumulate
suspend operations. For example: suspend an erase operation, start a programming
operation, suspend the programming operation then read the array. See Appendix C,
Figure 23: Program Suspend & Resume flowchart and pseudo code, and Figure 25: Erase
Suspend & Resume flowchart and pseudo code, for flowcharts for using the Program/Erase
Resume command.
23/110
Command interface - standard commands
5.10
M58WR016QT, M58WR016QB, M58WR032QT,
Protection Register Program command
The Protection Register Program command is used to Program the 128 bit user One-TimeProgrammable (OTP) segment of the Protection Register and the Protection Register Lock.
The segment is programmed 16 bits at a time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.
Two write cycles are required to issue the Protection Register Program command.
●
The first bus cycle sets up the Protection Register Program command.
●
The second latches the Address and the Data to be written to the Protection Register
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The segment can be protected by programming bit 1 of the Protection Lock Register (see
Figure 5: Protection Register Memory Map). Attempting to program a previously protected
Protection Register will result in a Status Register error. The protection of the Protection
Register is not reversible.
The Protection Register Program cannot be suspended. See Appendix C, Figure 27:
Protection Register Program flowchart and pseudo code, for a flowchart for using the
Protection Register Program command.
5.11
Set Configuration Register command
The Set Configuration Register command is used to write a new value to the Configuration
Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read
mode and the valid Clock edge configuration.
Two Bus Write cycles are required to issue the Set Configuration Register command.
●
The first cycle writes the setup command and the address corresponding to the
Configuration Register content.
●
The second cycle writes the Configuration Register data and the confirm command.
Read operations output the memory array content after the Set Configuration Register
command is issued.
The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1
on A1, etc.; the other address bits are ignored.
24/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - standard com-
5.12
Block Lock command
The Block Lock command is used to lock a block and prevent Program or Erase operations
from changing the data in it. All blocks are locked at power-up or reset.
Two Bus Write cycles are required to issue the Block Lock command.
●
The first bus cycle sets up the Block Lock command.
●
The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 14 shows the Lock Status after issuing a Block Lock command.
The Block Lock bits are volatile, once set they remain set until a hardware reset or powerdown/power-up. They are cleared by a Block Unlock command. Refer to the section, Block
Locking, for a detailed explanation. See Appendix C, Figure 26: Locking operations
flowchart and pseudo code, for a flowchart for using the Lock command.
5.13
Block Unlock command
The Block Unlock command is used to unlock a block, allowing the block to be programmed
or erased. Two Bus Write cycles are required to issue the Block Unlock command.
●
The first bus cycle sets up the Block Unlock command.
●
The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 14 shows the protection status after issuing a Block Unlock command.
Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 26:
Locking operations flowchart and pseudo code, for a flowchart for using the Unlock
command.
5.14
Block Lock-Down command
A locked or unlocked block can be locked-down by issuing the Block Lock-Down command.
A locked-down block cannot be programmed or erased, or have its protection status
changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled
and the locked blocks can be individually unlocked by the Block Unlock command.
Two Bus Write cycles are required to issue the Block Lock-Down command.
●
The first bus cycle sets up the Block Lock command.
●
The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Locked-Down blocks revert to the locked (and not locked-down) state when the
device is reset on power-down. Table 14 shows the Lock Status after issuing a Block LockDown command. Refer to the section, Block Locking, for a detailed explanation and
Appendix C, Figure 26: Locking operations flowchart and pseudo code, for a flowchart for
using the Lock-Down command.
25/110
Command interface - standard commands
Table 6.
M58WR016QT, M58WR016QB, M58WR032QT,
Standard commands(1)
Commands
Cycles
Bus Operations
1st Cycle
2nd Cycle
Op.
Add
Data
Op.
Add
Data
Read Array
1+
Write
BKA
FFh
Read
WA
RD
Read Status Register
1+
Write
BKA
70h
Read
BKA(2)
SRD
Read Electronic
Signature
1+
Write
BKA
90h
Read
BKA(2)
ESD
Read CFI Query
1+
Write
BKA
98h
Read
BKA(2)
QD
Clear Status Register
1
Write
X
50h
Block Erase
2
Write
BKA or
BA(3)
20h
Write
BA
D0h
Program
2
Write
BKA or
WA(3)
40h or
10h
Write
WA
PD
Program/Erase Suspend
1
Write
X
B0h
Program/Erase Resume
1
Write
X
D0h
Protection Register
Program
2
Write
PRA
C0h
Write
PRA
PRD
Set Configuration
Register
2
Write
CRD
60h
Write
CRD
03h
Block Lock
2
Write
BKA or
BA(3)
60h
Write
BA
01h
Block Unlock
2
Write
BKA or
BA(3)
60h
Write
BA
D0h
Block Lock-Down
2
Write
BKA or
BA(3)
60h
Write
BA
2Fh
1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data,
ESD=Electronic Signature Data, QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program
Data, PRA=Protection Register Address, PRD=Protection Register Data, CRD=Configuration Register
Data.
2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7.
3. Any address within the bank can be used.
26/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - standard comTable 7.
Electronic signature codes
Code
Address (h)
Manufacturer Code
Bank Address + 00
Data (h)
0020
Top
Bank Address + 01
8812h (M58WR016QT)
8814h (M58WR032QT)
Bottom
Bank Address + 01
8813h (M58WR016QB)
8815h (M58WR032QB)
Device Code
Locked
0001
Unlocked
0000
Locked and LockedDown
Block Protection
Block Address + 02
Unlocked and LockedDown
0003
0002
Reserved
Bank Address + 03
Reserved
Configuration Register
Bank Address + 05
CR(1)
Numonyx Factory Default
Protection Register
Lock
OTP Area Permanently
Locked
0002
Bank Address + 80
0000
Bank Address + 81
Bank Address + 84
Unique Device Number
Bank Address + 85
Bank Address + 8C
OTP Area
Protection Register
1. CR = Configuration Register.
Figure 5.
Protection Register Memory Map
PROTECTION REGISTER
8Ch
User Programmable OTP
85h
84h
Unique device number
81h
80h
Protection Register Lock
1
0
AI08149
27/110
Command interface - factory program commands
6
M58WR016QT, M58WR016QB, M58WR032QT,
Command interface - factory program commands
The Factory Program commands are used to speed up programming. They require VPP to
be at VPPH except for the Bank Erase command which also operates at VPP = VDD. Refer to
Table 8: Factory Program commands, in conjunction with the following text descriptions.
The use of Factory Program commands requires certain operating conditions.
6.1
●
VPP must be set to VPPH (except for Bank Erase comand),
●
VDD must be within operating range,
●
Ambient temperature, TA must be 25°C ± 5°C,
●
The targeted block must be unlocked.
Bank Erase command
The Bank Erase command can be used to erase a bank. It sets all the bits within the
selected bank to ’1’. All previous data in the bank is lost. The Bank Erase command will
ignore any protected blocks within the bank. If all blocks in the bank are protected then the
Bank Erase operation will abort and the data in the bank will not be changed. The Status
Register will not output any error.
Bank Erase operations can be performed at both VPP = VPPH and VPP = VDD.
Two Bus Write cycles are required to issue the command.
●
The first bus cycle sets up the Bank Erase command.
●
The second latches the bank address in the internal state machine and starts the
Program/Erase Controller.
If the second bus cycle is not Write Bank Erase Confirm (D0h), Status Register bits SR4 and
SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity
cannot be guaranteed when the Erase operation is aborted, the bank must be erased again.
Once the command is issued the device outputs the Status Register data when any address
within the bank is read. At the end of the operation the bank will remain in Read Status
Register mode until a Read Array, Read CFI Query or Read Electronic Signature command
is issued.
During Bank Erase operations the bank being erased will only accept the Read Array, Read
Status Register, Read Electronic Signature and Read CFI Query command, all other
commands will be ignored.
For optimum performance, Bank Erase commands should be limited to a maximum of 100
Program/Erase cycles per Block. After 100 Program/Erase cycles the internal algorithm will
still operate properly but some degradation in performance may occur.
Dual Operations are not supported during Bank Erase operations and the command cannot
be suspended.
Typical Erase times are given in Table 15: Program/Erase times and endurance cycles.
28/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
6.2
Command interface - factory pro-
Double Word Program command
The Double Word Program command improves the programming throughput by writing a
page of two adjacent words in parallel. The two words must differ only for the address A0. If
the block is protected, the Double Word Program operation will abort, the data in the block
will not be changed and the Status Register will output the error.
Three bus write cycles are necessary to issue the Double Word Program command.
●
The first bus cycle sets up the Double Word Program Command.
●
The second bus cycle latches the Address and the Data of the first word to be written.
●
The third bus cycle latches the Address and the Data of the second word to be written
and starts the Program/Erase Controller.
Read operations in the bank being programmed output the Status Register content after the
programming has started.
During Double Word Program operations the bank being programmed will only accept the
Read Array, Read Status Register, Read Electronic Signature and Read CFI Query
command, all other commands will be ignored. Dual operations are not supported during
Double Word Program operations and the command cannot be suspended. Typical Program
times are given in Table 15: Program/Erase times and endurance cycles.
Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the
program operation is aborted, the memory locations must be reprogrammed.
See Appendix C, Figure 21: Double Word Program flowchart and pseudo code, for the
flowchart for using the Double Word Program command.
29/110
Command interface - factory program commands
6.3
M58WR016QT, M58WR016QB, M58WR032QT,
Quadruple Word Program command
The Quadruple Word Program command improves the programming throughput by writing a
page of four adjacent words in parallel. The four words must differ only for the addresses A0
and A1. If the block is protected, the Quadruple Word Program operation will abort, the data
in the block will not be changed and the Status Register will output the error.
Five bus write cycles are necessary to issue the Quadruple Word Program command.
●
The first bus cycle sets up the Double Word Program Command.
●
The second bus cycle latches the Address and the Data of the first word to be written.
●
The third bus cycle latches the Address and the Data of the second word to be written.
●
The fourth bus cycle latches the Address and the Data of the third word to be written.
●
The fifth bus cycle latches the Address and the Data of the fourth word to be written
and starts the Program/Erase Controller.
Read operations to the bank being programmed output the Status Register content after the
programming has started.
Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the
program operation is aborted, the memory locations must be reprogrammed.
During Quadruple Word Program operations the bank being programmed will only accept
the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query
command, all other commands will be ignored.
Dual operations are not supported during Quadruple Word Program operations and the
command cannot be suspended. Typical Program times are given in Table 15:
Program/Erase times and endurance cycles.
See Appendix C, Figure 22: Quadruple Word Program flowchart and pseudo code, for the
flowchart for using the Quadruple Word Program command.
6.4
Enhanced Factory Program command
The Enhanced Factory Program command can be used to program large streams of data
within any one block. It greatly reduces the total programming time when a large number of
Words are written to a block at any one time.
Dual operations are not supported during the Enhanced Factory Program operation and the
command cannot be suspended.
For optimum performance the Enhanced Factory Program commands should be limited to a
maximum of 10 program/erase cycles per block. If this limit is exceeded the internal
algorithm will continue to work properly but some degradation in performance is possible.
Typical Program times are given in Table 15. If the block is protected, the Enhanced Factory
Program operation will abort, the data in the block will not be changed and the Status
Register will output the error.
The Enhanced Factory Program command has four phases: the Setup Phase, the Program
Phase to program the data to the memory, the Verify Phase to check that the data has been
correctly programmed and reprogram if necessary and the Exit Phase. Refer to Table 8:
Factory Program commands, and Figure 28: Enhanced Factory Program flowchart.
30/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
6.4.1
Command interface - factory pro-
Setup Phase
The Enhanced Factory Program command requires two Bus Write operations to initiate the
command.
●
The first bus cycle sets up the Enhanced Factory Program command.
●
The second bus cycle confirms the command.
The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready. After
the confirm command is issued, read operations output the Status Register data. The read
Status Register command must not be issued as it will be interpreted as data to program.
6.4.2
Program Phase
The Program Phase requires n+1 cycles, where n is the number of Words (refer to Table 8:
Factory Program commands, and Figure 28: Enhanced Factory Program flowchart).
Three successive steps are required to issue and execute the Program Phase of the
command.
1.
Use one Bus Write operation to latch the Start Address and the first Word to be
programmed. The Status Register Bank Write Status bit SR0 should be read to check
that the P/E.C. is ready for the next Word.
2.
Each subsequent Word to be programmed is latched with a new Bus Write operation.
The address can either remain the Start Address, in which case the P/E.C. increments
the address location or the address can be incremented in which case the P/E.C.
jumps to the new address. If any address that is not in the same block as the Start
Address is given with data FFFFh, the Program Phase terminates and the Verify Phase
begins. The Status Register bit SR0 should be read between each Bus Write cycle to
check that the P/E.C. is ready for the next Word.
3.
Finally, after all Words have been programmed, write one Bus Write operation with data
FFFFh to any address outside the block containing the Start Address, to terminate the
programming phase. If the data is not FFFFh, the command is ignored.
The memory is now set to enter the Verify Phase.
31/110
Command interface - factory program commands
6.4.3
M58WR016QT, M58WR016QB, M58WR032QT,
Verify Phase
The Verify Phase is similar to the Program Phase in that all Words must be resent to the
memory for them to be checked against the programmed data. The Program/Erase
Controller checks the stream of data with the data that was programmed in the Program
Phase and reprograms the memory location if necessary.
Three successive steps are required to execute the Verify Phase of the command.
1.
Use one Bus Write operation to latch the Start Address and the first Word, to be
verified. The Status Register bit SR0 should be read to check that the Program/Erase
Controller is ready for the next Word.
2.
Each subsequent Word to be verified is latched with a new Bus Write operation. The
Words must be written in the same order as in the Program Phase. The address can
remain the Start Address or be incremented. If any address that is not in the same
block as the Start Address is given with data FFFFh, the Verify Phase terminates.
Status Register bit SR0 should be read to check that the P/E.C. is ready for the next
Word.
3.
Finally, after all Words have been verified, write one Bus Write operation with data
FFFFh to any address outside the block containing the Start Address, to terminate the
Verify Phase.
If the Verify Phase is successfully completed the memory remains in Read Status Register
mode. If the Program/Erase Controller fails to reprogram a given location, the error will be
signaled in the Status Register.
6.4.4
Exit Phase
Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has returned to Read
mode. A full Status Register check should be done to ensure that the block has been
successfully programmed. See the section on the Status Register for more details.
6.5
Quadruple Enhanced Factory Program command
The Quadruple Enhanced Factory Program command can be used to program one or more
pages of four adjacent words in parallel. The four words must differ only for the addresses
A0 and A1.
Dual operations are not supported during Quadruple Enhanced Factory Program operations
and the command cannot be suspended. If the block is protected, the Quadruple Enhanced
Factory Program operation will abort, the data in the block will not be changed and the
Status Register will output the error.
The Quadruple Enhanced Factory Program command has four phases: the Setup Phase,
the Load Phase where the data is loaded into the buffer, the combined Program and Verify
Phase where the loaded data is programmed to the memory and then automatically
checked and reprogrammed if necessary and the Exit Phase. Unlike the Enhanced Factory
Program it is not necessary to resubmit the data for the Verify Phase. The Load Phase and
the Program and Verify Phase can be repeated to program any number of pages within the
block.
32/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
6.5.1
Command interface - factory pro-
Setup Phase
The Quadruple Enhanced Factory Program command requires one Bus Write operation to
initiate the load phase. After the setup command is issued, read operations output the
Status Register data. The Read Status Register command must not be issued as it will be
interpreted as data to program.
6.5.2
Load Phase
The Load Phase requires 4 cycles to load the data (refer to Table 8: Factory Program
commands, and Figure 29: Quadruple Enhanced Factory Program flowchart). Once the first
Word of each Page is written it is impossible to exit the Load phase until all four Words have
been written.
Two successive steps are required to issue and execute the Load Phase of the Quadruple
Enhanced Factory Program command.
1.
Use one Bus Write operation to latch the Start Address and the first Word of the first
Page to be programmed. For subsequent Pages the first Word address can remain the
Start Address (in which case the next Page is programmed) or can be any address in
the same block. If any address with data FFFFh is given that is not in the same block as
the Start Address, the device enters the Exit Phase. For the first Load Phase Status
Register bit SR7 should be read after the first Word has been issued to check that the
command has been accepted (bit SR7 set to ‘0’). This check is not required for
subsequent Load Phases.
2.
Each subsequent Word to be programmed is latched with a new Bus Write operation.
The address is only checked for the first Word of each Page as the order of the Words
to be programmed is fixed.
The memory is now set to enter the Program and Verify Phase.
6.5.3
Program and Verify Phase
In the Program and Verify Phase the four Words that were loaded in the Load Phase are
programmed in the memory array and then verified by the Program/Erase Controller. If any
errors are found the Program/Erase Controller reprograms the location. During this phase
the Status Register shows that the Program/Erase Controller is busy, Status Register bit
SR7 set to ‘0’, and that the device is not waiting for new data, Status Register bit SR0 set to
‘1’. When Status Register bit SR0 is set to ‘0’ the Program and Verify phase has terminated.
Once the Verify Phase has successfully completed subsequent pages in the same block can
be loaded and programmed. The device returns to the beginning of the Load Phase by
issuing one Bus Write operation to latch the Address and the first of the four new Words to
be programmed.
6.5.4
Exit Phase
Finally, after all the pages have been programmed, write one Bus Write operation with data
FFFFh to any address outside the block containing the Start Address, to terminate the Load
and Program and Verify Phases.
Status Register bit SR7 set to ‘1’ and bit SR0 set to ‘0’ indicate that the Quadruple
Enhanced Factory Program command has terminated. A full Status Register check should
be done to ensure that the block has been successfully programmed. See the section on the
Status Register for more details.
33/110
Command interface - factory program commands
M58WR016QT, M58WR016QB, M58WR032QT,
If the Program and Verify Phase has successfully completed the memory returns to Read
mode. If the P/E.C. fails to program and reprogram a given location, the error will be
signaled in the Status Register.
Table 8.
Factory Program commands(1)
Command
Phase
Cycles
Bus Write Operations
1st
2nd
3rd
Add
Data
Add
Data
Final -1
Add
Data
Final
Add
Data
Add
Data
WA3
PD3
WA4
PD4
Bank Erase
2
BKA
80h
BKA
D0h
Double Word Program(2)
3
BKA or
WA1(3)
35h
WA1
PD1
WA2
PD2
Quadruple Word
Program(4)
5
BKA or
WA1(3)
56h
WA1
PD1
WA2
PD2
2+
n+1
BKA or
WA1(3)
30h
BA or
WA1(6)
D0h WA1(7) PD1
WAn(8) PAn
NOT
FFFFh
WA1(7)
n+1
WA1(7)
PD1
WA2(8)
PD2 WA3(8) PD3
WAn(8) PAn
NOT
FFFFh
WA1(7)
5
BKA or
WA1(3)
75h
WA1(7)
PD1 WA2(9) PD2
WA3(9) PD3 WA4(9)
Setup,
Enhanced Program
Factory
Program(5) Verify, Exit
Setup,
first Load
First
Program &
Verify
Quadruple
Enhanced Subsequent
Factory Loads
Program(4)(5)
Subsequent
Program &
Verify
Exit
PD4
Automatic
4
WA1i(7)
PD1i WA2i(9) PD2i WA3i(9) PD3i
WA4i(9) PD4i
Automatic
1
NOT
FFFFh
WA1(7)
1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address.
2. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0.
3. Any address within the bank can be used.
4. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
5. A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register
and check that the memory is ready to accept the next data. n = number of Words, i = number of Pages to be programmed.
6. Any address within the block can be used.
7. WA1 is the Start Address. NOT WA1 is any address that is not in the same block as WA1.
8. Address can remain Starting Address WA1 or be incremented.
9. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so
subsequent Words in each Page can be written to any address.
34/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
7
Status Register
Status Register
The Status Register provides information on the current or previous Program or Erase
operations. Issue a Read Status Register command to read the contents of the Status
Register, refer to Read Status Register Command section for more details. To output the
contents, the Status Register is latched and updated on the falling edge of the Chip Enable
or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH.
The Status Register can only be read using single asynchronous or single synchronous
reads. Bus Read operations from any address within the bank, always read the Status
Register during Program and Erase operations.
The various bits convey information about the status and any errors of the operation. Bits
SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset
by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the
device but must be reset by issuing a Clear Status Register command or a hardware reset.
If an error bit is set to ‘1’ the Status Register should be reset before issuing another
command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the
addressed bank.
The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to
Table 9 in conjunction with the following text descriptions.
7.0.1
Program/Erase Controller Status Bit (SR7)
The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is
active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to
‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the
Program/Erase Controller is inactive, and the device is ready to process a new command.
The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend
command is issued until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses the bit is High.
During Program, Erase, operations the Program/Erase Controller Status bit can be polled to
find the end of the operation. Other bits in the Status Register should not be tested until the
Program/Erase Controller completes the operation and the bit is High.
After the Program/Erase Controller completes its operation the Erase Status, Program
Status, VPP Status and Block Lock Status bits should be tested for errors.
7.0.2
Erase Suspend Status Bit (SR6)
The Erase Suspend Status bit indicates that an Erase operation has been suspended or is
going to be suspended in the addressed block. When the Erase Suspend Status bit is High
(set to ‘1’), a Program/Erase Suspend command has been issued and the memory is
waiting for a Program/Erase Resume command.
The Erase Suspend Status should only be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive). SR7 is set within the Erase
Suspend Latency time of the Program/Erase Suspend command being issued therefore the
memory may still complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns
Low.
35/110
Status Register
7.0.3
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Erase Status Bit (SR5)
The Erase Status bit can be used to identify if the memory has failed to verify that the block
or bank has erased correctly. When the Erase Status bit is High (set to ‘1’), the
Program/Erase Controller has applied the maximum number of pulses to the block or bank
and still failed to verify that it has erased correctly. The Erase Status bit should be read once
the Program/Erase Controller Status bit is High (Program/Erase Controller inactive).
Once set High, the Erase Status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new Program or Erase
command is issued, otherwise the new command will appear to fail.
7.0.4
Program Status Bit (SR4)
The Program Status bit is used to identify a Program failure or an attempt to program a ‘1’ to
an already programmed bit when VPP = VPPH.
When the Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied
the maximum number of pulses to the byte and still failed to verify that it has programmed
correctly.
After an attempt to program a '1' to an already programmed bit, the Program Status bit SR4
only goes High (set to '1') if VPP = VPPH (if VPP is different from VPPH, SR4 remains Low (set
to '0') and the attempt is not shown).
The Program Status bit should be read once the Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).
Once set High, the Program Status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new command is
issued, otherwise the new command will appear to fail.
7.0.5
VPP Status Bit (SR3)
The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program
and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase
operation. Indeterminate results can occur if VPP becomes invalid during an operation.
When the VPP Status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid
voltage; when the VPP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below
the VPP Lockout Voltage, VPPLK, the memory is protected and Program and Erase
operations cannot be performed.
Once set High, the VPP Status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new Program or Erase
command is issued, otherwise the new command will appear to fail.
36/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
7.0.6
Status Register
Program Suspend Status Bit (SR2)
The Program Suspend Status bit indicates that a Program operation has been suspended in
the addressed block. When the Program Suspend Status bit is High (set to ‘1’), a
Program/Erase Suspend command has been issued and the memory is waiting for a
Program/Erase Resume command. The Program Suspend Status should only be
considered valid when the Program/Erase Controller Status bit is High (Program/Erase
Controller inactive). SR2 is set within the Program Suspend Latency time of the
Program/Erase Suspend command being issued therefore the memory may still complete
the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Program Suspend Status bit
returns Low.
7.0.7
Block Protection Status Bit (SR1)
The Block Protection Status bit can be used to identify if a Program or Block Erase operation
has tried to modify the contents of a locked block.
When the Block Protection Status bit is High (set to ‘1’), a Program or Erase operation has
been attempted on a locked block.
Once set High, the Block Protection Status bit can only be reset Low by a Clear Status
Register command or a hardware reset. If set High it should be reset before a new
command is issued, otherwise the new command will appear to fail.
7.0.8
Bank Write/Multiple Word Program Status Bit (SR0)
The Bank Write Status bit indicates whether the addressed bank is programming or erasing.
In Enhanced Factory Program mode the Multiple Word Program bit shows if a Word has
finished programming or verifying depending on the phase. The Bank Write Status bit
should only be considered valid when the Program/Erase Controller Status SR7 is Low (set
to ‘0’).
When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low
(set to ‘0’), the addressed bank is executing a Program or Erase operation. When the
Program/Erase Controller Status bit is Low (set to ‘0’) and the Bank Write Status bit is High
(set to ‘1’), a Program or Erase operation is being executed in a bank other than the one
being addressed.
In Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to ‘0’),
the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to
‘1’) the device is not ready for the next Word.
Note:
Refer to Appendix C: Flowcharts and pseudo codes, for using the Status Register.
37/110
Status Register
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Table 9.
Bit
SR7
SR6
SR5
SR4
SR3
SR2
SR1
Status Register bits
Name
Type
P/E.C. Status
Status
Erase Suspend
Status
Status
Erase Status
Error
Program Status
Logic
Level(1)
Definition
'1'
Ready
'0'
Busy
'1'
Erase Suspended
'0'
Erase In progress or Completed
'1'
Erase Error
'0'
Erase Success
'1'
Program Error
'0'
Program Success
'1'
VPP Invalid, Abort
'0'
VPP OK
'1'
Program Suspended
'0'
Program In Progress or Completed
'1'
Program/Erase on protected Block, Abort
'0'
No operation to protected blocks
Error
VPP Status
Error
Program Suspend
Status
Status
Block Protection
Status
Error
SR7 = ‘1’ Not Allowed
'1'
Bank Write Status
SR7 = ‘0’
Program or erase operation in a bank
other than the addressed bank
SR7 = ‘1’
No Program or erase operation in the
device
SR7 = ‘0’
Program or erase operation in
addressed bank
Status
'0'
SR0
SR7 = ‘1’ Not Allowed
Multiple Word
Program Status
Status
(Enhanced Factory
Program mode)
'1'
SR7 = ‘0’
SR7 = ‘1’ the device is exiting from EFP
'0'
SR7 = ‘0’
1. Logic level '1' is High, '0' is Low.
38/110
the device is NOT ready for the next
word
the device is ready for the next Word
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
8
Configuration Register
Configuration Register
The Configuration Register is used to configure the type of bus access that the memory will
perform. Refer to Read Modes section for details on read operations.
The Configuration Register is set through the Command Interface. After a Reset or PowerUp the device is configured for asynchronous page read (CR15 = 1). The Configuration
Register bits are described in Table 10. They specify the selection of the burst length, burst
type, burst X latency and the Read operation. Refer to Figures 6 and 7 for examples of
synchronous burst configurations.
8.1
Read Select Bit (CR15)
The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus
Read operations. When the Read Select bit is set to ’1’, read operations are asynchronous;
when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst
Read is supported in both parameter and main blocks and can be performed across banks.
On reset or power-up the Read Select bit is set to’1’ for asynchronous access.
8.2
X-Latency Bits (CR13-CR11)
The X-Latency bits are used during Synchronous Read operations to set the number of
clock cycles between the address being latched and the first data becoming available. For
correct operation the X-Latency bits can only assume the values in Table 10: Configuration
Register bits.
The correspondence between X-Latency settings and the maximum sustainable frequency
must be calculated taking into account some system parameters. Two conditions must be
satisfied:
1.
Depending on whether tAVK_CPU or tDELAY is supplied either one of the following two
equations must be satisfied:
(n + 1) tK ≥ tACC - tAVK_CPU + tQVK_CPU
(n + 2) tK ≥ tACC + tDELAY + tQVK_CPU
2.
and also
tK > tKQV + tQVK_CPU
where:
●
n is the chosen X-Latency configuration code
●
tK is the clock period
●
tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last
●
tDELAY is address valid, L Low, or E Low to clock, whichever occurs last
●
tQVK_CPU is the data setup time required by the system CPU,
●
tKQV is the clock to data valid time
●
tACC is the random access time of the device.
Refer to Figure 6: X-Latency and data output configuration example.
39/110
Configuration Register
8.3
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Wait Polarity Bit (CR10)
In synchronous burst mode the Wait signal indicates whether the output data are valid or a
WAIT state must be inserted. The Wait Polarity bit is used to set the polarity of the Wait
signal. When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait
Polarity bit is set to ‘1’ the Wait signal is active High (default).
8.4
Data Output Configuration Bit (CR9)
The Data Output Configuration bit determines whether the output remains valid for one or
two clock cycles. When the Data Output Configuration Bit is ’0’ the output data is valid for
one clock cycle, when the Data Output Configuration Bit is ’1’ the output data is valid for two
clock cycles.
The Data Output Configuration depends on the condition:
●
tK > tKQV + tQVK_CPU
where tK is the clock period, tQVK_CPU is the data setup time required by the system CPU
and tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output
Configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 6: X-Latency and
data output configuration example.
8.5
Wait Configuration Bit (CR8)
In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When WAIT is
asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid. When the Wait bit
is ’0’ the Wait output pin is asserted during the wait state. When the Wait bit is ’1’ (default)
the Wait output pin is asserted one clock cycle before the wait state.
8.6
Burst Type Bit (CR7)
The Burst Type bit is used to configure the sequence of addresses read as sequential or
interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses;
when the Burst Type bit is ’1’ (default) the memory outputs from sequential addresses. See
Table 11: Burst type definition, for the sequence of addresses output from a given starting
address in each mode.
8.7
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during
Synchronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of
the Clock is the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock
is active.
8.8
Wrap Burst Bit (CR3)
The burst reads can be confined inside the 4 or 8 Word boundary (wrap) or overcome the
boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When
40/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Configuration Register
the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does
not wrap.
8.9
Burst length Bits (CR2-CR0)
The Burst Length bits set the number of Words to be output during a Synchronous Burst
Read operation as result of a single address latch cycle. They can be set for 4 Words, 8
Words, 16 Words or continuous burst, where all the words are read sequentially.
In continuous burst mode the burst sequence can cross bank boundaries.
In continuous burst mode or in 4, 8, 16 Words no-wrap, depending on the starting address,
the device asserts the WAIT output to indicate that a delay is necessary before the data is
output.
If the starting address is aligned to a 4 Word boundary no wait states are needed and the
WAIT output is not asserted.
If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will
be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 16 Word
boundary, to indicate that the device needs an internal delay to read the successive words in
the array. WAIT will be asserted only once during a continuous burst access. See also
Table 11: Burst type definition.
CR14, CR5 and CR4 are reserved for future use.
41/110
Configuration Register
Table 10.
Bit
CR15
CR14
CR13-CR11
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Configuration Register bits
Description
Value
Description
0
Synchronous Read
1
Asynchronous Read (Default at power-on)
010
2 clock latency
011
3 clock latency
100
4 clock latency
101
5 clock latency
111
Reserved (default)
Read Select
Reserved
X-Latency
Other configurations reserved
CR10
CR9
CR8
CR7
CR6
CR5-CR4
CR3
CR2-CR0
42/110
0
WAIT is active Low
1
WAIT is active high (default)
0
Data held for one clock cycle
1
Data held for two clock cycles (default)
0
WAIT is active during wait state
1
WAIT is active one data cycle before wait state (default)
0
Interleaved
1
Sequential (default)
0
Falling Clock edge
1
Rising Clock edge (default)
0
Wrap
1
No Wrap (default)
001
4 Words
010
8 Words
011
16 Words
111
Continuous (CR7 must be set to ‘1’) (default)
Wait Polarity
Data Output
Configuration
Wait Configuration
Burst Type
Valid Clock Edge
Reserved
Wrap Burst
Burst Length
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Mode
Table 11.
Start
Add
Configuration Register
Burst type definition
4 Words
8 Words
Sequential Interleaved Sequential Interleaved
16 Words
Sequential
Interleaved
Continuous
Burst
0
0-1-2-3
0-1-2-3
0-1-2-3-4-5-60-1-2-3-4-5- 0-1-2-3-4-5- 0-1-2-3-4-5-6-7-8-97-8-9-10-11- 0-1-2-3-4-5-6...
6-7
6-7
10-11-12-13-14-15
12-13-14-15
1
1-2-3-0
1-0-3-2
1-2-3-4-5-6-7-8-9- 1-0-3-2-5-4-7- 1-2-3-4-5-6-71-2-3-4-5-6- 1-0-3-2-5-410-11-12-13-14-15- 6-9-8-11-10- ...15-WAIT-167-0
7-6
0
13-12-15-14
17-18...
2
2-3-0-1
2-3-0-1
2-3-0-1-6-7-4- 2-3-4-5-6-7...152-3-4-5-6-7- 2-3-0-1-6-7- 2-3-4-5-6-7-8-9-105-10-11-8-9- WAIT-WAIT-160-1
4-5
11-12-13-14-15-0-1
14-15-12-13
17-18...
3
3-0-1-2
3-2-1-0
3-4-5-6-7-8-9-10- 3-2-1-0-7-6-5- 3-4-5-6-7...153-4-5-6-7-0- 3-2-1-0-7-611-12-13-14-15-0- 4-11-10-9-8WAIT-WAIT1-2
5-4
1-2
15-14-13-12 WAIT-16-17-18...
7-6-5-4
7-8-9-10-11-127-6-5-4-3-2-17-0-1-2-3-4- 7-6-5-4-3-2- 7-8-9-10-11-12-1313-14-15-WAIT0-15-14-135-6
1-0
14-15-0-1-2-3-4-5-6
WAIT-WAIT-1612-11-10-9-8
17...
Wrap
...
7
7-4-5-6
...
12
12-13-14-15-1617-18...
13
13-14-15-WAIT16-17-18...
14
14-15-WAITWAIT-16-1718....
15
15-WAIT-WAITWAIT-16-17-18...
43/110
Configuration Register
Mode
Table 11.
Start
Add
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Burst type definition (continued)
4 Words
8 Words
Sequential Interleaved Sequential Interleaved
16 Words
Sequential
Interleaved
0
0-1-2-3
0-1-2-3-4-56-7
0-1-2-3-4-5-6-7-8-910-11-12-13-14-15
1
1-2-3-4
1-2-3-4-5-67-8
1-2-3-4-5-6-7-8-910-11-12-13-14-15WAIT-16
2
2-3-4-5
2-3-4-5-6-78-9...
2-3-4-5-6-7-8-9-1011-12-13-14-15WAIT-WAIT-16-17
3-4-5-6
3-4-5-6-7-89-10
3-4-5-6-7-8-9-1011-12-13-14-15WAIT-WAIT-WAIT16-17-18
7-8-9-10
7-8-9-10-1112-13-14
7-8-9-10-11-12-1314-15-WAIT-WAITWAIT-16-17-18-1920-21-22
12
12-13-1415
12-13-1415-16-1718-19
12-13-14-15-16-1718-19-20-21-22-2324-25-26-27
13
13-14-15WAIT-16
13-14-15WAIT-16-1718-19-20
13-14-15-WAIT-1617-18-19-20-21-2223-24-25-26-27-28
14
14-15WAITWAIT-1617
14-15-WAITWAIT-16-1718-19-20-21
14-15-WAIT-WAIT16-17-18-19-20-2122-23-24-25-26-2728-29
15
15-WAITWAITWAIT-1617-18
15-WAITWAIT-WAIT16-17-1819-20-21-22
15-WAIT-WAITWAIT-16-17-18-1920-21-22-23-24-2526-27-28-29-30
3
Continuous
Burst
No-wrap
...
7
Same as for
Wrap (Wrap /No
Wrap has no
effect on
Continuous
Burst)
...
Figure 6.
X-Latency and data output configuration example
X-latency
1st cycle
2nd cycle
3rd cycle
4th cycle
K
E
L
Amax-A0
VALID ADDRESS
44/110
tDELAY
tAVK_CPU
tQVK_CPU
tACC
tK
tKQV
tQVK_CPU
DQ15-DQ0
VALID DATA VALID DATA
Notes: 1. Settings shown: X-latency = 4, Data Output held for one clock cycle.
2. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
AI10174
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 7.
Configuration Register
Wait configuration example
E
K
L
Amax-A0(1)
DQ15-DQ0
VALID ADDRESS
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT
CR8 = '0'
CR10 = '0'
WAIT
CR8 = '1'
CR10 = '0'
WAIT
CR8 = '0'
CR10 = '1'
WAIT
CR8 = '1'
CR10 = '1'
Note: Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
AI10175
45/110
Read modes
9
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Read modes
Read operations can be performed in two different ways depending on the settings in the
Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read
operation is Asynchronous; if the data output is synchronized with clock, the read operation
is Synchronous.
The Read mode and data output format are determined by the Configuration Register. (See
Configuration Register section for details). All banks supports both asynchronous and
synchronous read operations. The Multiple Bank architecture allows read operations in one
bank, while write operations are being executed in another (see Tables 12 and 13).
9.1
Asynchronous Read mode
In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the
data corresponding to the address latched, that is the memory array, Status Register,
Common Flash Interface or Electronic Signature depending on the command issued. CR15
in the Configuration Register must be set to ‘1’ for Asynchronous operations.
In Asynchronous Read mode a Page of data is internally read and stored in a Page Buffer.
The Page has a size of 4 Words and is addressed by A0 and A1 address inputs. The
address inputs A0 and A1 are not gated by Latch Enable in Asynchronous Read mode.
The first read operation within the Page has a longer access time (Tacc, Random access
time), subsequent reads within the same Page have much shorter access times. If the Page
changes then the normal, longer timings apply again.
Asynchronous Read operations can be performed in two different ways, Asynchronous
Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read
takes full advantage of the internal page storage so different timings are applied.
During Asynchronous Read operations, after a bus inactivity of 150ns, the device
automatically switches to the Automatic Standby mode. In this condition the power
consumption is reduced to the standby value and the outputs are still driven.
In Asynchronous Read mode, the WAIT signal is always asserted.
See Table 21: Asynchronous Read AC characteristics, Figure 10: Asynchronous Random
Access Read AC waveforms, and Figure 11: Asynchronous Page Read AC waveforms for
details.
46/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
9.2
Read modes
Synchronous Burst Read mode
In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It
is possible to perform burst reads across bank boundaries.
Synchronous Burst Read mode can only be used to read the memory array. For other read
operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single
Synchronous Read or Asynchronous Random Access Read must be used.
In Synchronous Burst Read mode the flow of the data output depends on parameters that
are configured in the Configuration Register.
A burst sequence is started at the first clock edge (rising or falling depending on Valid Clock
Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip
Enable, whichever occurs last. Addresses are internally incremented and after a delay of 2
to 5 clock cycles (X latency bits CR13-CR11) the corresponding data are output on each
clock cycle.
The number of Words to be output during a Synchronous Burst Read operation can be
configured as 4, 8, 16 Words, or Continuous (Burst Length bits CR2-CR0). The data can be
configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9).
The order of the data output can be modified through the Burst Type and the Wrap Burst bits
in the Configuration Register. The burst sequence may be configured to be sequential or
interleaved (CR7). The burst reads can be confined inside the 4, 8 or 16 Word boundary
(Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to the Burst
Length (4, 8 or 16 Words) the wrapped configuration has no impact on the output sequence.
Interleaved mode is not allowed in Continuous Burst Read mode or with No Wrap
sequences.
A WAIT signal may be asserted to indicate to the system that an output delay will occur. This
delay will depend on the starting address of the burst sequence; the worst case delay will
occur when the sequence is crossing a 16 Word boundary and the starting address was at
the end of a four word boundary.
WAIT is asserted during X latency, the Wait state and at the end of 4-, 8- or 16-Word burst.
It is only deasserted when output data are valid. In Continuous Burst Read mode a Wait
state will occur when crossing the first 16 Word boundary. If the burst starting address is
aligned to a 4 Word Page, the Wait state will not occur.
The WAIT signal can be configured to be active Low or active High (default) by setting CR10
in the Configuration Register. The WAIT signal is meaningful only in Synchronous Burst
Read mode, in other modes, WAIT is always asserted (except for Read Array mode).
See Table 22: Synchronous Read AC characteristics, and Figure 12: Synchronous Burst
Read AC waveforms, for details.
47/110
Read modes
9.2.1
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Synchronous Burst Read Suspend
A Synchronous Burst Read operation can be suspended, freeing the data bus for other
higher priority devices. It can be suspended during the initial access latency time (before
data is output) in which case the initial latency time can be reduced to zero, or after the
device has output data. When the Synchronous Burst Read operation is suspended, internal
array sensing continues and any previously latched internal data is retained. A burst
sequence can be suspended and resumed as often as required as long as the operating
conditions of the device are met.
A Synchronous Burst Read operation is suspended when E is low and the current address
has been latched (on a Latch Enable rising edge or on a valid clock edge). The clock signal
is then halted at VIH or at VIL, and G goes high.
When G becomes low again and the clock signal restarts, the Synchronous Burst Read
operation is resumed exactly where it stopped.
WAIT being gated by E remains active and will not revert to high-impedance when G goes
high. So if two or more devices are connected to the system’s READY signal, to prevent bus
contention the WAIT signal of the Flash memory should not be directly connected to the
system’s READY signal.
See Table 22: Synchronous Read AC characteristics and Figure 14: Synchronous Burst
Read Suspend AC waveforms, for details.
9.3
Single Synchronous Read mode
Single Synchronous Read operations are similar to Synchronous Burst Read operations
except that only the first data output after the X latency is valid. Synchronous Single Reads
are used to read the Electronic Signature, Status Register, CFI, Block Protection Status,
Configuration Register Status or Protection Register. When the addressed bank is in Read
CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is always
asserted.
See Table 22: Synchronous Read AC characteristics and Figure 13: Single Synchronous
Read AC waveforms, for details.
48/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
10
Dual operations and Multiple Bank
Dual operations and Multiple Bank architecture
The Multiple Bank Architecture of the M58WRxxxQT/B provides flexibility for software
developers by allowing code and data to be split with 4Mbit granularity. The Dual Operations
feature simplifies the software management of the device and allows code to be executed
from one bank while another bank is being programmed or erased.
The Dual operations feature means that while programming or erasing in one bank, Read
operations are possible in another bank with zero latency (only one bank at a time is allowed
to be in Program or Erase mode). If a Read operation is required in a bank which is
programming or erasing, the Program or Erase operation can be suspended. Also if the
suspended operation was Erase then a Program command can be issued to another block,
so the device can have one block in Erase Suspend mode, one programming and other
banks in Read mode. Bus Read operations are allowed in another bank between setup and
confirm cycles of program or erase operations. The combination of these features means
that read operations are possible at any moment.
Tables 12 and 13 show the dual operations possible in other banks and in the same bank.
For a complete list of possible commands refer to Appendix D: Command interface state
tables.
Table 12.
Dual operations allowed in other banks
Commands allowed in another bank
Status of
bank
Read
Array
Read
Read
Status
CFI
Register Query
Read
Electronic Program
Signature
Block
Erase
Program/ Program/
Erase
Erase
Suspend Resume
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programming
Yes
Yes
Yes
Yes
–
–
Yes
–
Erasing
Yes
Yes
Yes
Yes
–
–
Yes
–
Program
Suspended
Yes
Yes
Yes
Yes
–
–
–
Yes
Erase
Suspended
Yes
Yes
Yes
Yes
Yes
–
–
Yes
49/110
Dual operations and Multiple Bank architecture
Table 13.
M58WR016QT, M58WR016QB, M58WR032QT,
Dual operations allowed in same bank
Commands allowed in same bank
Status of
bank
Idle
Programming
Erasing
Read
Array
Read
Read
Read
Block
Status
CFI
Electronic Program
Erase
Register Query Signature
Program/ Program/
Erase
Erase
Suspend Resume
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(1)
Yes
Yes
Yes
–
–
Yes
–
(1)
Yes
Yes
Yes
–
–
Yes
–
–
–
Program
Suspended
Yes(2)
Yes
Yes
Yes
–
–
–
Yes
Erase
Suspended
Yes(2)
Yes
Yes
Yes
Yes(2)
–
–
Yes
1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase
has completed.
2. Not allowed in the Block or Word that is being erased or programmed.
50/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
11
Block locking
Block locking
The M58WRxxxQT/B features an instant, individual block locking scheme that allows any
block to be locked or unlocked with no latency. This locking scheme has three levels of
protection.
●
Lock/Unlock - this first level allows software-only control of block locking.
●
Lock-Down - this second level requires hardware interaction before locking can be
changed.
●
VPP ≤VPPLK - the third level offers a complete hardware protection against program and
erase on all blocks.
The protection status of each block can be set to Locked, Unlocked, and Lock-Down.
Table 14, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C,
Figure 26, shows a flowchart for the locking operations.
11.1
Reading a Block’s lock status
The lock status of every block can be read in the Read Electronic Signature mode of the
device. To enter this mode write 90h to the device. Subsequent reads at the address
specified in Table 7, will output the protection status of that block. The lock status is
represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the
Lock command and cleared by the Unlock command. It is also automatically set when
entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down
command. It cannot be cleared by software, only by a hardware reset or power-down.
The following sections explain the operation of the locking system.
11.2
Locked state
The default status of all blocks on power-up or after a hardware reset is Locked (states
(0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any
program or erase operations attempted on a locked block will return an error in the Status
Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the
appropriate software commands. An Unlocked block can be Locked by issuing the Lock
command.
11.3
Unlocked state
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware reset or when the device is powereddown. The status of an unlocked block can be changed to Locked or Locked-Down using the
appropriate software commands. A locked block can be unlocked by issuing the Unlock
command.
51/110
Block locking
11.4
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Lock-Down state
Blocks that are Locked-Down (state (0,1,x))are protected from program and erase
operations (as for Locked blocks) but their protection status cannot be changed using
software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the
Lock-Down command. Locked-Down blocks revert to the Locked state when the device is
reset or powered-down.
The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in
the Lock-Down state (0,1,x) are protected from program, erase and protection status
changes. When WP=1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down
blocks can be individually unlocked to the (1,1,0) state by issuing the software command,
where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and
unlocked (1,1,0) as desired while WP remains high. When WP is Low, blocks that were
previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes
made while WP was high. Device reset or power-down resets all blocks, including those in
Lock-Down, to the Locked state.
11.5
Locking operations during Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the
standard locking command sequences to unlock, lock or lock-down a block. This is useful in
the case when another block needs to be updated while an erase operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command,
then check the status register until it indicates that the erase operation has been
suspended. Next write the desired Lock command sequence to a block and the lock status
will be changed. After completing any desired lock, read, or program operations, resume the
erase operation with the Erase Resume command.
If a block is locked or locked-down during an erase suspend of the same block, the locking
status bits will be changed immediately, but when the erase is resumed, the erase operation
will complete. Locking operations cannot be performed during a program suspend. Refer to
Appendix Appendix D: Command interface state tables, for detailed information on which
commands are valid during erase suspend.
52/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Table 14.
Block locking
Lock status
Current Protection Status(1)
(WP, DQ1, DQ0)
Next Protection Status(1) (WP, DQ1, DQ0)
Current
State
Program/Erase
Allowed
After Block
Lock
Command
After Block
Unlock
Command
After Block
Lock-Down
Command
After WP
transition
1,0,0
yes
1,0,1
1,0,0
1,1,1
0,0,0
1,0,1(2)
no
1,0,1
1,0,0
1,1,1
0,0,1
1,1,0
yes
1,1,1
1,1,0
1,1,1
0,1,1
1,1,1
no
1,1,1
1,1,0
1,1,1
0,1,1
0,0,0
yes
0,0,1
0,0,0
0,1,1
1,0,0
0,0,1(2)
no
0,0,1
0,0,0
0,1,1
1,0,1
0,1,1
no
0,1,1
0,1,1
0,1,1
1,1,1 or 1,1,0(3)
1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for
a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL.
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
53/110
Program and erase times and endurance cycles
12
M58WR016QT, M58WR016QB, M58WR032QT,
Program and erase times and endurance cycles
The Program and Erase times and the number of Program/ Erase cycles per block are
shown in Table 15. Exact erase times may change depending on the memory array
condition. The best case is when all the bits in the block or bank are at ‘0’ (preprogrammed).
The worst case is when all the bits in the block or bank are at ‘1’ (not preprogrammed).
Usually, the system overhead is negligible with respect to the erase time.
In the M58WRxxxQT/B the maximum number of Program/ Erase cycles depends on the VPP
voltage supply used.
Table 15.
Program/Erase times and endurance cycles(1)
Parameter
Condition
Min
Parameter Block (4 KWord)(2)
Erase
Main Block
(32 KWord)
Typical
after 100k
Typ
Max
W/E
Cycles
Unit
0.3
1
2.5
s
Preprogrammed
0.8
3
4
s
Not Preprogrammed
1.1
4
s
Preprogrammed
3
s
4.5
s
Bank (4Mbit)
VPP = VDD
Not Preprogrammed
Program(3)
Suspend
Latency
Word
10
Parameter Block (4 KWord)
32
ms
Main Block (32 KWord)
256
ms
100
µs
Program
5
10
µs
Erase
5
20
µs
Program/Erase Main Blocks
Cycles (per
Parameter Blocks
Block)
54/110
10
100,000
cycles
100,000
cycles
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Program and erase times and endurProgram/Erase times and endurance cycles(1) (continued)
Table 15.
Parameter
Erase
Min
Unit
Parameter Block (4 KWord)
0.25
2.5
s
Main Block (32 KWord)
0.8
4
s
Bank (4Mbit)
3.5
s
Word/ Double Word/ Quadruple
Word(4)
8
Quad-Enhanced
Factory
10
ms
Enhanced Factory
25
ms
Quadruple Word(4)
8
ms
Word
32
ms
Quad-Enhanced
Factory
80
ms
Enhanced Factory
200
ms
Word(4)
64
ms
256
ms
520
s
510
ms
Parameter
Block (4
KWord)
VPP = VPPH
Condition
Typical
after 100k
Typ
Max
W/E
Cycles
(3)
Program
Main Block
(32 KWord)
Quadruple
Word
Quad-Enhanced
(4)
Bank (4Mbit) Factory
Quadruple Word(4)
Program/Erase Main Blocks
Cycles (per
Parameter Blocks
Block)
100
µs
1000 cycles
2500 cycles
1. TA = –40 to 85°C; VDD = 1.7V to 2.2V; VDDQ = 2.2V to 3.3V.
2. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms).
3. Values are liable to change with the external system-level overhead (command sequence and Status
Register polling execution).
4. Measurements performed at 25°C. TA = 25°C ±5°C for Quadruple Word, Double Word and Quadruple
Enhanced Factory Program.
55/110
Maximum rating
13
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 16.
Absolute maximum ratings
Value
Symbol
Unit
Min
Max
Ambient Operating Temperature
–40
85
°C
TBIAS
Temperature Under Bias
–40
125
°C
TSTG
Storage Temperature
–65
155
°C
VIO
Input or Output Voltage
–0.5
VDDQ+0.6
V
VDD
Supply Voltage
–0.2
2.45
V
Input/Output Supply Voltage
–0.2
2.45
V
Program Voltage
–0.2
14
V
Output Short Circuit Current
100
mA
Time for VPP at VPPH
100
hours
TA
VDDQ
VPP
IO
tVPPH
56/110
Parameter
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
14
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 17: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 17.
Operating and AC measurement conditions
M58WRxxxQT/B
Parameter
60
70
80
Unit
Min
Max
Min
Max
Min
Max
VDD Supply Voltage
1.7
2
1.7
2
1.7
2
V
VDDQ Supply Voltage
1.7
2.24
1.7
2.24
1.7
2.24
V
VPP Supply Voltage (Factory
environment)
11.4
12.6
11.4
12.6
11.4
12.6
V
VPP Supply Voltage (Application
environment)
–0.4
VDDQ+0.4
–0.4
VDDQ+0.4
–0.4
VDDQ+0.4
V
Ambient Operating Temperature
–40
85
–40
85
–40
85
°C
Load Capacitance (CL)
30
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref.
Voltages
Figure 8.
30
30
pF
5
5
5
ns
0 to VDDQ
0 to VDDQ
0 to VDDQ
V
VDDQ/2
VDDQ/2
VDDQ/2
V
AC measurement I/O waveform
VDDQ
VDDQ/2
0V
AI06161
57/110
DC and AC parameters
Figure 9.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
AC measurement load circuit
VDDQ
VDDQ
VDD
16.7kΩ
DEVICE
UNDER
TEST
CL
0.1µF
16.7kΩ
0.1µF
CL includes JIG capacitance
Table 18.
Symbol
CIN
COUT
Capacitance(1)
Parameter
Input Capacitance
Output Capacitance
1. Sampled only, not 100% tested.
58/110
AI06162
Test Condition
Min
Max
Unit
VIN = 0V
6
8
pF
VOUT = 0V
8
12
pF
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Table 19.
Symbol
DC and AC parameters
DC characteristics - currents
Parameter
Test Condition
Min
Typ
Max
Unit
0V ≤VIN ≤VDDQ
±1
µA
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤VOUT ≤VDDQ
Supply Current
Asynchronous Read (f=6MHz)
E = VIL, G = VIH
3
6
mA
4 Word
7
16
mA
8 Word
10
18
mA
16 Word
12
22
mA
Continuous
13
25
mA
4 Word
8
17
mA
8 Word
11
20
mA
16 Word
14
25
mA
Continuous
16
30
mA
Supply Current
Synchronous Read (f=54MHz)
IDD1
Supply Current
Synchronous Read (f=66MHz)
IDD2
Supply Current (Reset)
RP = VSS ± 0.2V
10
50
µA
IDD3
Supply Current (Standby)
E = VDDQ ± 0.2V
K = VSS
10
50
µA
IDD4
Supply Current (Automatic
Standby)
E = VIL, G = VIH
10
50
µA
VPP = VPPH
8
15
mA
VPP = VDD
10
20
mA
VPP = VPPH
8
15
mA
VPP = VDD
10
20
mA
Program/Erase in one
Bank, Asynchronous
Read in another Bank
13
26
mA
Program/Erase in one
Bank, Synchronous
Read in another Bank
23
45
mA
E = VDDQ ± 0.2V
K = VSS
10
50
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP Supply Current (Read)
VPP ≤VDD
0.2
5
µA
VPP Supply Current (Standby)
VPP ≤VDD
0.2
5
µA
Supply Current (Program)
IDD5(1)
Supply Current (Erase)
IDD6(1)(2)
IDD7(1)
Supply Current (Dual
Operations)
Supply Current Program/
Erase Suspended (Standby)
VPP Supply Current (Program)
IPP1(1)
VPP Supply Current (Erase)
IPP2
IPP3
(1)
1. Sampled only, not 100% tested.
2. VDD Dual Operation current is the sum of read and program or erase currents.
59/110
DC and AC parameters
Table 20.
Symbol
60/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
DC characteristics - voltages
Parameter
Test Condition
Min
Typ
Max
Unit
VIL
Input Low Voltage
–0.5
0.4
V
VIH
Input High Voltage
VDDQ –0.4
VDDQ + 0.4
V
VOL
Output Low Voltage
IOL = 100µA
0.1
V
VOH
Output High Voltage
IOH = –100µA
VDDQ –0.1
VPP1
VPP Program VoltageLogic
Program, Erase
1.3
1.8
3.3
V
VPPH
VPP Program Voltage
Factory
Program, Erase
11.4
12
12.6
V
VPPLK
Program or Erase
Lockout
0.4
V
VLKO
VDD Lock Voltage
1
V
VRPH
RP pin Extended High
Voltage
3.3
V
V
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
DC and AC parameters
Figure 10. Asynchronous Random Access Read AC waveforms
A0-Amax(2)
VALID
VALID
tAVAV
tAVLH
tAXQX
tLHAX
L
tLLLH
tLLQV
tLHGL
tELLH
tELQV
E
tEHQZ
tELQX
tEHQX
G
tGHQX
tGLQV
tGHQZ
tGLQX
Hi-Z
tEHTZ
tELTV
WAIT
tAVQV
DQ0-DQ15
Hi-Z
VALID
Valid Address Latch
Outputs Enabled
Data Valid
Notes: 1. Write Enable, W, is High, WAIT is active Low.
2. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
Standby
AI10178
61/110
62/110
(1)
DQ0-DQ15
WAIT
G
E
L
A0-A1
Hi-Z
tELTV
tELQX
tGLQV
tGLQX
tELQV
Valid Address Latch
tELLH
tLLQV
tLLLH
tAVLH
VALID ADDRESS
tAVAV
Enabled
Outputs
tLHGL
tLHAX
VALID DATA
Valid Data
VALID DATA
VALID ADDRESS
VALID DATA
tAVQV1
VALID ADDRESS
VALID ADDRESS
Note 1. WAIT is active Low.
2. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
A2-Amax(2)
VALID DATA
VALID ADDRESS
AI10179
Standby
DC and AC parameters
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 11. Asynchronous Page Read AC waveforms
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Table 21.
DC and AC parameters
Asynchronous Read AC characteristics
M58WRxxxQT/B
Symbol
Alt
Read Timings
Unit
60
70
80
tAVAV
tRC
Address Valid to Next Address Valid
Min
60
70
80
ns
tAVQV
tACC
Address Valid to Output Valid
(Random)
Max
60
70
80
ns
tAVQV1
tPAGE
Address Valid to Output Valid (Page)
Max
20
20
25
ns
tAXQX(1)
tOH
Address Transition to Output Transition
Min
0
0
0
ns
Chip Enable Low to Wait Valid
Max
11
14
14
ns
tELTV
Latch Timings
Parameter
tELQV
(2)
tCE
Chip Enable Low to Output Valid
Max
60
70
80
ns
tELQX
(1)
tLZ
Chip Enable Low to Output Transition
Min
0
0
0
ns
Chip Enable High to Wait Hi-Z
Max
14
17
17
ns
tEHTZ
(1)
tOH
Chip Enable High to Output Transition
Min
0
0
0
ns
tEHQZ(1)
tHZ
Chip Enable High to Output Hi-Z
Max
14
17
17
ns
tGLQV(2)
tOE
Output Enable Low to Output Valid
Max
20
20
25
ns
tGLQX(1)
tOLZ
Output Enable Low to Output Transition
Min
0
0
0
ns
tGHQX(1)
tOH
Output Enable High to Output
Transition
Min
0
0
0
ns
tGHQZ(1)
tDF
Output Enable High to Output Hi-Z
Max
14
14
14
ns
tAVLH
tAVADVH
Address Valid to Latch Enable High
Min
7
9
9
ns
tELLH
tELADVH
Chip Enable Low to Latch Enable High
Min
10
10
10
ns
tLHAX
tADVHAX
Latch Enable High to Address
Transition
Min
7
9
9
ns
Min
7
9
9
ns
tEHQX
tLLLH
tADVLADVH Latch Enable Pulse Width
tLLQV
tADVLQV
Latch Enable Low to Output Valid
(Random)
Max
60
70
80
ns
tLHGL
tADVHGL
Latch Enable High to Output Enable
Low
Min
0
0
0
ns
1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
63/110
64/110
Hi-Z
tELKH
Hi-Z
tLLLH
Address
Latch
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
X Latency
tGLQX
Note 2
tKHTV
Note 1
VALID
Valid Data Flow
tKHQV
VALID
Note 2
tKHTX
tKHQX
VALID
Boundary
Crossing
Note 2
NOT VALID
Data
Valid
tGHQZ
Standby
AI10180
tEHTZ
tEHQZ
tEHQX
tEHEL
VALID
tGHQX
Notes 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.
2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
3. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, K, can be configured as the active edge.
Here the active edge of K is the rising one.
4. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
WAIT
G
E
K(3)
L
A0-Amax(3)
DQ0-DQ15
DC and AC parameters
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 12. Synchronous Burst Read AC waveforms
Hi-Z
tELKH
Hi-Z
tLLLH
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
tGLQV
tGLQX
Note 1
Note 3
tKHTV
tKHQV
VALID
NOT VALID
NOT VALID
NOT VALID
tGHQZ
tGHQX
tEHEL
tEHQZ
AI10181
tEHTZ
NOT VALID
tEHQX
NOT VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.
2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
3. WAIT is always asserted when addressed bank is in Read CFI, Read SR or Read electronic signature mode.
WAIT signals valid data if the addressed bank is in Read Array mode.
4. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, K, can be configured as the active edge.
Here the active edge of K is the rising one.
5. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
WAIT(2)
G
E
K(4)
L
A0-Amax(5)
DQ0-DQ15
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
DC and AC parameters
Figure 13. Single Synchronous Read AC waveforms
65/110
66/110
tELKH
tLLLH
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
tGLQV
tGLQX
Note 1
tKHQV
VALID
VALID
tGHQZ
Note 3
tGHQX
tEHEL
tEHQZ
AI10182
tEHTZ
NOT VALID
tEHQX
NOT VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
3. The CLOCK signal can be held high or low
4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge.
Here, the active edge is the rising one.
5. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
WAIT(2)
G
E
K(4)
L
Hi-Z
Hi-Z
A0-Amax(5)
DQ0-DQ15
DC and AC parameters
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 14. Synchronous Burst Read Suspend AC waveforms
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
DC and AC parameters
Figure 15. Clock input AC waveform
tKHKL
tKHKH
tr
tf
tKLKH
AI06981
Table 22.
Synchronous Read AC characteristics(1) (2)
M58WRxxxQT/B
Synchronous Read Timings
Symbol
Parameter
Unit
60
70
80
tAVKH
tAVCLKH
Address Valid to Clock High
Min
7
9
9
ns
tELKH
tELCLKH
Chip Enable Low to Clock High
Min
7
9
9
ns
tELTV
Chip Enable Low to Wait Valid
Max
11
14
14
ns
tEHEL
Chip Enable Pulse Width
(subsequent synchronous reads)
Min
14
14
14
ns
tEHTZ
Chip Enable High to Wait Hi-Z
Max
11
14
14
ns
tKHAX
tCLKHAX
Clock High to Address Transition
Min
7
9
9
ns
tKHQV
tKHTV
tCLKHQV
Clock High to Output Valid
Clock High to WAIT Valid
Max
11
14
14
ns
tKHQX
tKHTX
tCLKHQX
Clock High to Output Transition
Clock High to WAIT Transition
Min
3
4
4
ns
Min
7
9
9
ns
18.5
18.5
ns
tLLKH
Clock Specifications
Alt
tADVLCLKH Latch Enable Low to Clock High
Clock Period (f=54MHz)
Min
Clock Period (f=66MHz)
Min
15
tKHKL
tKLKH
Clock High to Clock Low
Clock Low to Clock High
Min
3.5
4.5
4.5
ns
tf
tr
Clock Fall or Rise Time
Max
3
3
3
ns
tKHKH
tCLK
ns
1. Sampled only, not 100% tested.
2. For other timings please refer to Table 21: Asynchronous Read AC characteristics.
67/110
68/110
tWHDX
CONFIRM COMMAND
OR DATA INPUT
tVPHWH
tWHVPL
tWHWPL
tQVVPL
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
PROGRAM OR ERASE
tELKV
tWHEL
tWHGL
tWHAV
tWHAX
CMD or DATA
VALID ADDRESS
tAVWH
tWPHWH
tWHWL
tWHEH
tWHLL
tWLWH
tLHAX
COMMAND
tLLLH
SET-UP COMMAND
tDVWH
tGHWL
tELWL
tELLH
tAVLH
BANK ADDRESS
Note: Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
K
VPP
WP
DQ0-DQ15
W
G
E
L
A0-Amax
tAVAV
AI10183b
DC and AC parameters
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 16. Write AC waveforms, Write Enable controlled
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
DC and AC parameters
Write AC characteristics, Write Enable controlled(1)
Table 23.
M58WRxxxQT/B
Symbol
Alt
tAVAV
80
60
70
80
ns
tAVLH
Address Valid to Latch Enable High
Min
7
9
9
ns
tAVWH(2)
Address Valid to Write Enable High
Min
40
45
50
ns
Data Valid to Write Enable High
Min
40
45
50
ns
Chip Enable Low to Latch Enable High
Min
10
10
10
ns
Chip Enable Low to Write Enable Low
Min
0
0
0
ns
tELQV
Chip Enable Low to Output Valid
Min
60
70
80
ns
tELKV
Chip Enable Low to Clock Valid
Min
7
9
9
ns
tGHWL
Output Enable High to Write Enable
Low
Min
14
17
17
ns
tLHAX
Latch Enable High to Address
Transition
Min
7
9
9
ns
tLLLH
Latch Enable Pulse Width
Min
7
9
9
ns
Write Enable High to Address Valid
Min
0
0
0
ns
tAH
Write Enable High to Address Transition
Min
0
0
0
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
0
ns
Write Enable High to Chip Enable Low
Min
20
25
25
ns
tWHGL
Write Enable High to Output Enable
Low
Min
0
0
0
ns
tWHLL
Write Enable High to Latch Enable Low
Min
0
0
0
ns
tWHWL
tWPH Write Enable High to Write Enable Low
Min
20
25
25
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
40
45
50
ns
tQVVPL
Output (Status Register) Valid to VPP
Low
Min
0
0
0
ns
tQVWPL
Output (Status Register) Valid to Write
Protect Low
Min
0
0
0
ns
tELWL
Write Enable Controlled Timings
70
Min
tDS
tELLH
tCS
tWHAV(2)
tWHAX
(2)
tWHEL(3)
Protection Timings
Unit
60
Address Valid to Next Address Valid
tDVWH
tWC
Parameter
tVPHWH
tVPS VPP High to Write Enable High
Min
200
200
200
ns
tWHVPL
Write Enable High to VPP Low
Min
200
200
200
ns
tWHWPL
Write Enable High to Write Protect Low
Min
200
200
200
ns
tWPHWH
Write Protect High to Write Enable High
Min
200
200
200
ns
1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept low.
3. tWHEL has this value when reading from the targeted bank or when reading from any address after a Set
Configuration Register command has been issued. System designers should take this into account and
may insert a software No-Op instruction to delay the first read in the same bank after issuing any
command, or to delay the first read to any address after issuing a Set Configuration Register command. If
the first read after the command is a Read Array operation in a different bank and no changes to the
Configuration Register have been issued, tWHEL is 0ns.
69/110
70/110
tELEH
tLHAX
COMMAND
SET-UP COMMAND
tDVEH
tLLLH
tELLH
tGHEL
tWLEL
tAVLH
BANK ADDRESS
tEHDX
tEHEL
tEHWH
CMD or DATA
tEHAX
CONFIRM COMMAND
OR DATA INPUT
tVPHEH
tWPHEH
tAVEH
VALID ADDRESS
Note: Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
K
VPP
WP
DQ0-DQ15
E
G
W
L
A0-Amax
tAVAV
tEHVPL
tEHWPL
tELKV
tWHEL
tEHGL
tQVVPL
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
PROGRAM OR ERASE
AI10184b
DC and AC parameters
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 17. Write AC waveforms, Chip Enable controlled
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Table 24.
DC and AC parameters
Write AC characteristics, Chip Enable controlled(1)
M58WRxxxQT/B
Symbol
Chip Enable Controlled Timings
tAVAV
Alt
tWC
Unit
60
70
80
Address Valid to Next Address Valid
Min
60
70
80
ns
tAVEH
Address Valid to Chip Enable High
Min
40
45
50
ns
tAVLH
Address Valid to Latch Enable High
Min
7
9
9
ns
tDVEH
tDS
Data Valid to Chip Enable High
Min
40
45
50
ns
tEHAX
tAH
Chip Enable High to Address Transition
Min
0
0
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
0
ns
tEHEL
tCPH Chip Enable High to Chip Enable Low
Min
20
25
25
ns
Chip Enable High to Output Enable Low
Min
0
0
0
ns
Chip Enable High to Write Enable High
Min
0
0
0
ns
Chip Enable Low to Clock Valid
Min
7
9
9
ns
Chip Enable Low to Chip Enable High
Min
40
45
50
ns
tELLH
Chip Enable Low to Latch Enable High
Min
10
10
10
ns
tELQV
Chip Enable Low to Output Valid
Min
60
70
80
ns
tGHEL
Output Enable High to Chip Enable Low
Min
14
17
17
ns
tLHAX
Latch Enable High to Address Transition
Min
7
9
9
ns
tLLLH
Latch Enable Pulse Width
Min
7
9
9
ns
Write Enable High to Chip Enable Low
Min
20
25
25
ns
Write Enable Low to Chip Enable Low
Min
0
0
0
ns
tEHVPL
Chip Enable High to VPP Low
Min
200
200
200
ns
tEHWPL
Chip Enable High to Write Protect Low
Min
200
200
200
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
0
0
ns
tQVWPL
Output (Status Register) Valid to Write
Protect Low
Min
0
0
0
ns
Min
200
200
200
ns
Min
200
200
200
ns
tEHGL
tEHWH
tCH
tELKV
tELEH
tCP
tWHEL(2)
tWLEL
Protection Timings
Parameter
tVPHEH
tWPHEH
tCS
tVPS VPP High to Chip Enable High
Write Protect High to Chip Enable High
1. Sampled only, not 100% tested.
2. tWHEL has this value when reading from the targeted bank or when reading from any address after a Set
Configuration Register command has been issued. System designers should take this into account and
may insert a software No-Op instruction to delay the first read in the same bank after issuing any
command, or to delay the first read to any address after issuing a Set Configuration Register command. If
the first read after the command is a Read Array operation in a different bank and no changes to the
Configuration Register have been issued, tWHEL is 0ns.
71/110
DC and AC parameters
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 18. Reset and Power-up AC waveforms
tPHWL
tPHEL
tPHGL
tPHLL
W, E, G, L
tPLWL
tPLEL
tPLGL
tPLLL
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI06976
Table 25.
Symbol
Reset and Power-up AC characteristics
Parameter
tPLWL
tPLEL
tPLGL
tPLLL
Reset Low to
Write Enable Low,
Chip Enable Low,
Output Enable Low,
Latch Enable Low
tPHWL
tPHEL
tPHGL
tPHLL
tPLPH(1),(2)
tVDHPH(3)
Test Condition
60
70
80
Unit
During Program
Min
10
10
10
µs
During Erase
Min
20
20
20
µs
Other Conditions
Min
80
80
80
ns
Reset High to
Write Enable Low
Chip Enable Low
Output Enable Low
Latch Enable Low
Min
30
30
30
ns
RP Pulse Width
Min
50
50
50
ns
Supply Voltages High to Reset
High
Min
50
50
50
µs
1. The device Reset is possible but not guaranteed if tPLPH < 50ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.
72/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
15
Package mechanical
Package mechanical
Figure 19. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package
Outline
D
D1
FD
FE
E
SD
E1
ddd
BALL "A1"
e
e
b
A
A2
A1
BGA-Z38
1. Drawing is not to scale.
Table 26.
VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, package mechanical
data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.000
A1
Max
0.0394
0.200
0.0079
A2
0.660
0.0260
b
0.350
0.300
0.400
0.0138
0.0118
0.0157
D
7.700
7.600
7.800
0.3031
0.2992
0.3071
D1
5.250
–
–
0.2067
–
–
ddd
0.080
0.0031
e
0.750
–
–
0.0295
–
–
E
9.000
8.900
9.100
0.3543
0.3504
0.3583
E1
4.500
–
–
0.1772
–
–
FD
1.225
–
–
0.0482
–
–
FE
2.250
–
–
0.0886
–
–
SD
0.375
–
–
0.0148
–
–
73/110
Part numbering
16
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Part numbering
Table 27.
Ordering information scheme
Example:
Device Type
M58
Architecture
W = Multiple Bank, Burst Mode
Operating Voltage
R = VDD = 1.7V to 2V, VDDQ = 1.7V to 2.24V
Density
016 = 16 Mbit (x16)
032 = 32 Mbit (x16)
Technology
Q = 0.11µm technology
Parameter Location
T = Top Boot
B = Bottom Boot
Speed
60 = 60ns
70 = 70ns
80 = 80ns
Package
ZB = VFBGA56, 7.7x9mm, 0.75mm pitch
Temperature Range
6 = –40 to 85°C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = ECOPACK® Package, Standard Packing
F = ECOPACK® Package, Tape & Reel Packing
74/110
M58WR016QT
70 ZB 6 T
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Table 28.
Part numbering
Daisy chain ordering scheme
Example:
M58WR016QT
ZB T
Device Type
M58WR016Q
Daisy Chain
ZB = VFBGA56, 7.7x9mm, 0.75mm pitch
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = ECOPACK® Package, Standard Packing
F = ECOPACK®, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of
available options (Speed, Package, etc.) or for further information on any aspect of this
device, please contact the Numonyx Sales Office nearest to you.
75/110
Block address tables
Appendix A
Block address tables
Table 29.
(1)
Bank 2
Bank 1
Parameter Bank
Bank
76/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Top boot block addresses, M58WR016QT
#
Size (KWord)
Address Range
0
4
FF000-FFFFF
1
4
FE000-FEFFF
2
4
FD000-FDFFF
3
4
FC000-FCFFF
4
4
FB000-FBFFF
5
4
FA000-FAFFF
6
4
F9000-F9FFF
7
4
F8000-F8FFF
8
32
F0000-F7FFF
9
32
E8000-EFFFF
10
32
E0000-E7FFF
11
32
D8000-DFFFF
12
32
D0000-D7FFF
13
32
C8000-CFFFF
14
32
C0000-C7FFF
15
32
B8000-BFFFF
16
32
B0000-B7FFF
17
32
A8000-AFFFF
18
32
A0000-A7FFF
19
32
98000-9FFFF
20
32
90000-97FFF
21
32
88000-8FFFF
22
32
80000-87FFF
23
32
78000-7FFFF
24
32
70000-77FFF
25
32
68000-6FFFF
26
32
60000-67FFF
27
32
58000-5FFFF
28
32
50000-57FFF
29
32
48000-4FFFF
30
32
40000-47FFF
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Bank 3
Table 29.
Block address tables
Top boot block addresses, M58WR016QT (continued)
31
32
38000-3FFFF
32
32
30000-37FFF
33
32
28000-2FFFF
34
32
20000-27FFF
35
32
18000-1FFFF
36
32
10000-17FFF
37
32
08000-0FFFF
38
32
00000-07FFF
1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;
Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
Table 30.
Bank 1
Bank 2
Bank 3
Bank(1)
Bottom boot block addresses, M58WR016QB
#
Size (KWord)
Address Range
38
32
F8000-FFFFF
37
32
F0000-F7FFF
36
32
E8000-EFFFF
35
32
E0000-E7FFF
34
32
D8000-DFFFF
33
32
D0000-D7FFF
32
32
C8000-CFFFF
31
32
C0000-C7FFF
30
32
B8000-BFFFF
29
32
B0000-B7FFF
28
32
A8000-AFFFF
27
32
A0000-A7FFF
26
32
98000-9FFFF
25
32
90000-97FFF
24
32
88000-8FFFF
23
32
80000-87FFF
22
32
78000-7FFFF
21
32
70000-77FFF
20
32
68000-6FFFF
19
32
60000-67FFF
18
32
58000-5FFFF
17
32
50000-57FFF
16
32
48000-4FFFF
15
32
40000-47FFF
77/110
Block address tables
Parameter Bank
Table 30.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Bottom boot block addresses, M58WR016QB (continued)
14
32
38000-3FFFF
13
32
30000-37FFF
12
32
28000-2FFFF
11
32
20000-27FFF
10
32
18000-1FFFF
9
32
10000-17FFF
8
32
08000-0FFFF
7
4
07000-07FFF
6
4
06000-06FFF
5
4
05000-05FFF
4
4
04000-04FFF
3
4
03000-03FFF
2
4
02000-02FFF
1
4
01000-01FFF
0
4
00000-00FFF
1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only;
Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
Table 31.
Parameter Bank
Bank(1)
78/110
Top boot block addresses, M58WR032QT
#
Size (KWord)
Address Range
0
4
1FF000-1FFFFF
1
4
1FE000-1FEFFF
2
4
1FD000-1FDFFF
3
4
1FC000-1FCFFF
4
4
1FB000-1FBFFF
5
4
1FA000-1FAFFF
6
4
1F9000-1F9FFF
7
4
1F8000-1F8FFF
8
32
1F0000-1F7FFF
9
32
1E8000-1EFFFF
10
32
1E0000-1E7FFF
11
32
1D8000-1DFFFF
12
32
1D0000-1D7FFF
13
32
1C8000-1CFFFF
14
32
1C0000-1C7FFF
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Bank 4
Bank 3
Bank 2
Bank 1
Table 31.
Block address tables
Top boot block addresses, M58WR032QT (continued)
15
32
1B8000-1BFFFF
16
32
1B0000-1B7FFF
17
32
1A8000-1AFFFF
18
32
1A0000-1A7FFF
19
32
198000-19FFFF
20
32
190000-197FFF
21
32
188000-18FFFF
22
32
180000-187FFF
23
32
178000-17FFFF
24
32
170000-177FFF
25
32
168000-16FFFF
26
32
160000-167FFF
27
32
158000-15FFFF
28
32
150000-157FFF
29
32
148000-14FFFF
30
32
140000-147FFF
31
32
138000-13FFFF
32
32
130000-137FFF
33
32
128000-12FFFF
34
32
120000-127FFF
35
32
118000-11FFFF
36
32
110000-117FFF
37
32
108000-10FFFF
38
32
100000-107FFF
39
32
0F8000-0FFFFF
40
32
0F0000-0F7FFF
41
32
0E8000-0EFFFF
42
32
0E0000-0E7FFF
43
32
0D8000-0DFFFF
44
32
0D0000-0D7FFF
45
32
0C8000-0CFFFF
46
32
0C0000-0C7FFF
79/110
Block address tables
Bank 7
Bank 6
Bank 5
Table 31.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Top boot block addresses, M58WR032QT (continued)
47
32
0B8000-0BFFFF
48
32
0B0000-0B7FFF
49
32
0A8000-0AFFFF
50
32
0A0000-0A7FFF
51
32
098000-09FFFF
52
32
090000-097FFF
53
32
088000-08FFFF
54
32
080000-087FFF
55
32
078000-07FFFF
56
32
070000-077FFF
57
32
068000-06FFFF
58
32
060000-067FFF
59
32
058000-05FFFF
60
32
050000-057FFF
61
32
048000-04FFFF
62
32
040000-047FFF
63
32
038000-03FFFF
64
32
030000-037FFF
65
32
028000-02FFFF
66
32
020000-027FFF
67
32
018000-01FFFF
68
32
010000-017FFF
69
32
008000-00FFFF
70
32
000000-007FFF
1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;
Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
Table 32.
Bank 7
Bank(1)
80/110
Bottom boot block addresses, M58WR032QB
#
Size (KWord)
Address Range
70
32
1F8000-1FFFFF
69
32
1F0000-1F7FFF
68
32
1E8000-1EFFFF
67
32
1E0000-1E7FFF
66
32
1D8000-1DFFFF
65
32
1D0000-1D7FFF
64
32
1C8000-1CFFFF
63
32
1C0000-1C7FFF
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Bank 3
Bank 4
Bank 5
Bank 6
Table 32.
Block address tables
Bottom boot block addresses, M58WR032QB (continued)
62
32
1B8000-1BFFFF
61
32
1B0000-1B7FFF
60
32
1A8000-1AFFFF
59
32
1A0000-1A7FFF
58
32
198000-19FFFF
57
32
190000-197FFF
56
32
188000-18FFFF
55
32
180000-187FFF
54
32
178000-17FFFF
53
32
170000-177FFF
52
32
168000-16FFFF
51
32
160000-167FFF
50
32
158000-15FFFF
49
32
150000-157FFF
48
32
148000-14FFFF
47
32
140000-147FFF
46
32
138000-13FFFF
45
32
130000-137FFF
44
32
128000-12FFFF
43
32
120000-127FFF
42
32
118000-11FFFF
41
32
110000-117FFF
40
32
108000-10FFFF
39
32
100000-107FFF
38
32
0F8000-0FFFFF
37
32
0F0000-0F7FFF
36
32
0E8000-0EFFFF
35
32
0E0000-0E7FFF
34
32
0D8000-0DFFFF
33
32
0D0000-0D7FFF
32
32
0C8000-0CFFFF
31
32
0C0000-0C7FFF
81/110
Block address tables
Parameter Bank
Bank 1
Bank 2
Table 32.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Bottom boot block addresses, M58WR032QB (continued)
30
32
0B8000-0BFFFF
29
32
0B0000-0B7FFF
28
32
0A8000-0AFFFF
27
32
0A0000-0A7FFF
26
32
098000-09FFFF
25
32
090000-097FFF
24
32
088000-08FFFF
23
32
080000-087FFF
22
32
078000-07FFFF
21
32
070000-077FFF
20
32
068000-06FFFF
19
32
060000-067FFF
18
32
058000-05FFFF
17
32
050000-057FFF
16
32
048000-04FFFF
15
32
040000-047FFF
14
32
038000-03FFFF
13
32
030000-037FFF
12
32
028000-02FFFF
11
32
020000-027FFF
10
32
018000-01FFFF
9
32
010000-017FFF
8
32
008000-00FFFF
7
4
007000-007FFF
6
4
006000-006FFF
5
4
005000-005FFF
4
4
004000-004FFF
3
4
003000-003FFF
2
4
002000-002FFF
1
4
001000-001FFF
0
4
000000-000FFF
1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only;
Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
82/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Appendix B
Common Flash Interface
Common Flash Interface
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the Read CFI Query Command is issued the device enters CFI Query mode and the
data structure is read from the memory. Tables 33, 34, 35, 36, 37, 38, 39, 40, 41 and 42
show the addresses used to retrieve the data. The Query data is always presented on the
lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0.
The CFI data structure also contains a security area where a 64 bit unique security number
is written (see Figure 5: Protection Register Memory Map). This area can be accessed only
in Read mode by the final user. It is impossible to change the security number after it has
been written by Numonyx. Issue a Read Array command to return to Read mode.
Table 33.
Query structure overview(1)
Offset
Sub-section Name
Description
00h
Reserved
Reserved for algorithm-specific information
10h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
System Interface Information
Device timing & voltage information
27h
Device Geometry Definition
Flash device layout
P
Primary Algorithm-specific Extended Query
table
Additional information specific to the Primary
Algorithm (optional)
A
Alternate Algorithm-specific Extended Query Additional information specific to the
table
Alternate Algorithm (optional)
80h
Security Code Area
Lock Protection Register
Unique device Number and
User Programmable OTP
1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are
listed the main sub-sections detailed in Tables 34, 35, 36 and 37. Query data is always presented on the
lowest order data outputs.
83/110
Common Flash Interface
Table 34.
CFI Query identification string
Offset
Sub-section
Name
00h
0020h
01h
8812h
8813h
8814h
8815h
02h
reserved
03h
reserved
04h-0Fh
reserved
10h
0051h
11h
0052h
12h
0059h
13h
0003h
14h
0000h
15h
16h
0000h
18h
0000h
1Ah
Description
Manufacturer Code
Value
Numonyx
Top (M58WR016QT)
Bottom (M58WR016QB)
Top (M58WR032QT)
Bottom (M58WR032QB)
Device Code
Reserved
reserved
Reserved
"Q"
Query Unique ASCII String "QRY"
"R"
"Y"
Primary Algorithm Command Set and
Control Interface ID code 16 bit ID code
defining a specific algorithm
offset = P = 0039h Address for Primary Algorithm extended
Query table (see Table 36)
0000h
17h
19h
84/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
p = 39h
Alternate Vendor Command Set and
Control Interface ID Code second vendor specified algorithm supported
NA
value = A = 0000h Address for Alternate Algorithm extended
Query table
0000h
NA
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Table 35.
Common Flash Interface
CFI query system interface information
Offset
Data
Description
Value
1Bh
0017h
VDD Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 millivolts
1.7V
1Ch
0020h
VDD Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 millivolts
2V
1Dh
00B4h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 millivolts
11.4V
1Eh
00C6h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 millivolts
12.6V
1Fh
0004h
Typical time-out per single byte/word program = 2n µs
16µs
n
0000h
Typical time-out for multi-Byte program = 2 µs
21h
000Ah
Typical time-out per individual block erase =
2n
22h
0000h
Typical time-out for full chip erase = 2n ms
20h
23h
24h
0003h
0000h
NA
ms
NA
n
Maximum time-out for word program = 2 times typical
Maximum time-out for multi-Byte program =
1s
2n
times typical
n
128µs
NA
25h
0002h
Maximum time-out per individual block erase = 2 times typical
4s
26h
0000h
Maximum time-out for chip erase = 2n times typical
NA
85/110
Common Flash Interface
Table 36.
Offset
Word Mode
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Device geometry definition
Data
0015h(1)
27h
(2)
Description
Device Size = 2n in number of bytes
28h
29h
0001h
0000h
Flash Device Interface Code description
2Ah
2Bh
0000h
0000h
Maximum number of bytes in multi-byte program or page = 2n
2Ch
0002h
Number of identical sized erase block regions within the
device
bit 7 to 0 = x = number of Erase Block Regions
2
001Eh
0000h
M58WR016QT/B Erase Block Region 1 Information
Number of identical-size erase blocks = 001Eh+1
31
003Eh
0000h
M58WR032QT/B Erase Block Region 1 Information
Number of identical-size erase blocks = 003Eh+1
63
2Fh
30h
0000h
0001h
Erase Block Region 1 Information
Block size in Region 1 = 0100h * 256 byte
31h
32h
0007h
0000h
Erase Block Region 2 Information
Number of identical-size erase blocks = 0007h+1
33h
34h
0020h
0000h
Erase Block Region 2 Information
Block size in Region 2 = 0020h * 256 byte
TOP DEVICES
2Dh
2Eh
35h
38h
BOTTOM DEVICES
2 MBytes
4 MBytes
0016h
Reserved for future erase block region information
x16
Async.
NA
64 KByte
8
8 KByte
NA
2Dh
2Eh
0007h
0000h
Erase Block Region 1 Information
Number of identical-size erase block = 0007h+1
2Fh
30h
0020h
0000h
Erase Block Region 1 Information
Block size in Region 1 = 0020h * 256 byte
001Eh
0000h
M58WR016QT/B Erase Block Region 2 Information
Number of identical-size erase block = 001Eh+1
31
003Eh
0000h
M58WR032QT/B Erase Block Region 2 Information
Number of identical-size erase block = 003Eh+1
63
0000h
0001h
Erase Block Region 2 Information
Block size in Region 2 = 0100h * 256 byte
31h
32h
33h
34h
35h
38h
Reserved for future erase block region information
1. Applies to M58WR016QT/B only.
2. Applies to M58WR032QT/B only.
86/110
Value
8
8 KByte
64 KByte
NA
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Table 37.
Common Flash Interface
Primary algorithm-specific extended query table
Offset
Data
(P)h = 39h
0050h
0052h
Description
Value
"P"
Primary Algorithm extended Query table unique ASCII string
“PRI”
0049h
"R"
"I"
(P+3)h = 3Ch
0031h
Major version number, ASCII
"1"
(P+4)h = 3Dh
0033h
Minor version number, ASCII
"3"
(P+5)h = 3Eh
00E6h
Extended Query table contents for Primary Algorithm. Address
(P+5)h contains less significant byte.
0003h
(P+7)h = 40h
0000h
(P+8)h = 41h
0000h
bit 0Chip Erase supported (1 = Yes, 0 = No)
bit 1Erase Suspend supported (1 = Yes, 0 = No)
bit 2Program Suspend supported (1 = Yes, 0 = No)
bit 3Legacy Lock/Unlock supported (1 = Yes, 0 = No)
bit 4Queued Erase supported (1 = Yes, 0 = No)
bit 5Instant individual block locking supported (1 = Yes, 0 = No)
bit 6Protection bits supported (1 = Yes, 0 = No)
bit 7Page mode read supported (1 = Yes, 0 = No)
bit 8Synchronous read supported (1 = Yes, 0 = No)
bit 9Simultaneous operation supported (1 = Yes, 0 = No)
bit 10 to 31Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then
another 31 bit field of optional features follows at the end of the
bit-30 field.
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query
(P+9)h = 42h
0001h
Yes
bit 0Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1Reserved; undefined bits are ‘0’
(P+A)h = 43h
0003h
(P+B)h = 44h
0000h
Block Protect Status
Defines which bits in the Block Status Register section of the
Query are implemented.
bit 0Block protect Status Register Lock/Unlock
bit active(1 = Yes, 0 = No)
bit 1Block Lock Status Register Lock-Down bit active (1 = Yes,
0 = No)
bit 15 to 2Reserved for future use; undefined bits are ‘0’
Yes
Yes
VDD Logic Supply Optimum Program/Erase voltage (highest
performance)
(P+C)h = 45h
0018h
1.8V
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
VPP Supply Optimum Program/Erase voltage
(P+D)h = 46h
00C0h
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
12V
87/110
Common Flash Interface
Table 38.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Protection Register Information
Offset
Data
(P+E)h = 47h
0001h
(P+F)h = 48h
0080h
(P+10)h = 49h
0000h
(P+11)h = 4Ah
0003h
(P+12)h = 4Bh
0004h
Table 39.
Description
Value
Number of protection register fields in JEDEC ID space.
0000h indicates that 256 fields are available.
Protection Field 1: Protection Description
Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
Bits 16-23 2n bytes in factory pre-programmed region
Bits 24-31 2n bytes in user programmable region
1
0080h
8 Bytes
16 Bytes
Burst Read information
Offset
Data
Description
Value
(P+13)h = 4Ch
Page-mode read capability
bits 0-7’n’ such that 2n HEX value represents the number of
0003h
read-page bytes. See offset 28h for device word width to
determine page-mode data output width.
(P+14)h = 4Dh
0004h
(P+15)h = 4Eh
Synchronous mode read capability configuration 1
bit 3-7Reserved
bit 0-2’n’ such that 2n+1 HEX value represents the maximum
number of continuous synchronous reads when the device is
configured for its maximum word width. A value of 07h
indicates that the device is capable of continuous linear bursts
0001h
that will output data until the internal burst counter reaches the
end of the device’s burstable address space. This field’s 3-bit
value can be written directly to the read configuration register
bit 0-2 if the device is configured for its maximum word width.
See offset 28h for word width to determine the burst data
output width.
4
(P+16)h = 4Fh
0002h Synchronous mode read capability configuration 2
8
(P+17)h = 50h
0003h Synchronous mode read capability configuration 3
16
(P+18)h = 51h
0007h Synchronous mode read capability configuration 4
Cont.
Table 40.
8
Bytes
Number of synchronous mode read configuration fields that
follow.
4
Bank and erase block region information(1) (2)
TOP DEVICES
BOTTOM DEVICES
Description
Offset
Data
Offset
Data
(P+19)h = 52h
02h
(P+19)h = 52h
02h
Number of Bank Regions within the device
1. The variable P is a pointer which is defined at CFI offset 15h.
2. Bank Regions. There are two Bank Regions, see Table 29 and Table 30 for the M58WR016QT/B and see
Table 31 and Table 32 for the M58WR032QT/B.
88/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Table 41.
Common Flash Interface
Bank and erase block region 1 information(1)
TOP DEVICES
BOTTOM DEVICES
Description
Offset
Data
Offset
Data
(P+1A)h = 53h
01h
03h(2)
(P+1A)h = 53h
(P+1B)h = 54h
(P+1C)h = 55h
(P+1D)h = 56h
(P+1E)h = 57h
07h(3)
00h
11h
00h
00h
Number of identical banks within Bank Region 1
(P+1B)h = 54h
(P+1C)h = 55h
(P+1D)h = 56h
(P+1E)h = 57h
00h
11h
Number of program or erase operations allowed in
Bank region 1:
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase operations
00h
Number of program or erase operations allowed in
other banks while a bank in same region is
programming
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase operations
00h
Number of program or erase operations allowed in
other banks while a bank in this region is erasing
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase operations
Types of erase block regions in Bank region 1
n = number of erase block regions with contiguous
same-size erase blocks.
Symmetrically blocked banks have one blocking
region.(4)
(P+1F)h = 58h
01h
(P+1F)h = 58h
02h
(P+20)h = 59h
07h
(P+20)h = 59h
07h
(P+21)h = 5Ah
00h
(P+21)h = 5Ah
00h
(P+22)h = 5Bh
00h
(P+22)h = 5Bh
20h
(P+23)h = 5Ch
01h
(P+23)h = 5Ch
00h
(P+24)h = 5Dh
64h
(P+24)h = 5Dh
64h
(P+25)h = 5Eh
00h
(P+25)h = 5Eh
00h
(P+26)h = 5Fh
(P+27)h = 60h
01h
03h
(P+26)h = 5Fh
(P+27)h = 60h
Bank Region 1 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase
blocks in each bank
Bits 16-31: n×256 = number of bytes in erase block
region
Bank Region 1 (Erase Block Type 1)
Minimum block erase cycles × 1000
01h
Bank Region 1 (Erase Block Type 1): BIts per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved 5Eh 01 5Eh 01
03h
Bank Region 1 (Erase Block Type 1): Page mode
and synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
89/110
Common Flash Interface
Table 41.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Bank and erase block region 1 information(1) (continued)
TOP DEVICES
BOTTOM DEVICES
Description
Offset
Data
Offset
Data
(P+28)h = 61h
06h
Bank Region 1 Erase Block Type 2 Information
(P+29)h = 62h
00h
(P+2A)h = 63h
00h
Bits 0-15: n+1 = number of identical-sized
erase blocks
(P+2B)h = 64h
01h
Bits 16-31: n×256 = number of bytes in erase block
region
(P+2C)h = 65h
64h
(P+2D)h = 66h
00h
(P+2E)h = 67h
(P+2F)h = 68h
Bank Region 1 (Erase Block Type 2)
Minimum block erase cycles × 1000
01h
Bank Region 1 (Erase Block Type 2): BIts per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank Region 1 (Erase Block Type 2): Page mode
and synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
1. The variable P is a pointer which is defined at CFI offset 15h.
2. Applies to the M58WR016QT/B only.
3. Applies to the M58WR032QT/B only.
4. Bank Regions. There are two Bank Regions, see Table 29 and Table 30 for the M58WR016QT/B and see
Table 31 and Table 32 for the M58WR032QT/B.
90/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Table 42.
Common Flash Interface
Bank and erase block region 2 information(1)
TOP DEVICES
BOTTOM DEVICES
Description
Offset
Data
Offset
(P+28)h = 61h
01h
(P+30)h = 69h
(P+29)h = 62h
00h
(P+31)h = 6Ah
Data
03h(2)
(P+2A)h = 63h
(P+2B)h = 64h
(P+2C)h = 65h
11h
00h
00h
(P+32)h = 6Bh
(P+33)h = 6Ch
(P+34)h = 6Dh
07h(3) Number of identical banks within bank region 2
00h
11h
Number of program or erase operations allowed in
bank region 2:
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase operations
00h
Number of program or erase operations allowed in
other banks while a bank in this region is
programming
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase operations
00h
Number of program or erase operations allowed in
other banks while a bank in this region is erasing
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase operations
Types of erase block regions in Bank region 2
n = number of erase block regions with contiguous
same-size erase blocks.
Symmetrically blocked banks have one blocking
region.(4)
(P+2D)h = 66h
02h
(P+35)h = 6Eh
01h
(P+2E)h = 67h
06h
(P+36)h = 6Fh
07h
(P+2F)h = 68h
00h
(P+37)h = 70h
00h
(P+30)h = 69h
00h
(P+38)h = 71h
00h
(P+31)h = 6Ah
01h
(P+39)h = 72h
01h
(P+32)h = 6Bh
64h
(P+3A)h = 73h
64h
(P+33)h = 6Ch
00h
(P+3B)h = 74h
00h
(P+34)h = 6Dh
01h
(P+3C)h = 75h
01h
Bank Region 2 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase
blocks in each bank
Bits 16-31: n×256 = number of bytes in erase block
region
Bank Region 2 (Erase Block Type 1)
Minimum block erase cycles × 1000
Bank Region 2 (Erase Block Type 1): BIts per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
91/110
Common Flash Interface
Table 42.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Bank and erase block region 2 information(1) (continued)
TOP DEVICES
BOTTOM DEVICES
Description
Offset
Data
(P+35)h = 6Eh
03h
(P+36)h = 6Fh
07h
(P+37)h = 70h
00h
(P+38)h = 71h
20h
(P+39)h = 72h
00h
(P+3A)h = 73h
64h
(P+3B)h = 74h
00h
(P+3C)h = 75h
(P+3D)h = 76h
Offset
(P+3D)h = 76h
Data
03h
Bank Region 2 (Erase Block Type 1): Page mode
and synchronous mode capabilities (defined in
Table 39)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n×256 = number of bytes in erase block
region
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
01h
Bank Region 2 (Erase Block Type 2): BIts per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank Region 2 (Erase Block Type 2): Page mode
and synchronous mode capabilities (defined in
Table 39)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+3E)h = 77h
(P+3E)h = 77h
Feature Space definitions
(P+3F)h = 78h
(P+3F)h = 78h
Reserved
1. The variable P is a pointer which is defined at CFI offset 15h.
2. Applies to the M58WR016QT/B only.
3. Applies to the M58WR032QT/B only.
4. Bank Regions. There are two Bank Regions, see Table 29 and Table 30 for the M58WR016QT/B and see
Table 31 and Table 32 for the M58WR032QT/B.
92/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Appendix C
Flowcharts and pseudo codes
Flowcharts and pseudo codes
Figure 20. Program flowchart and pseudo code
Start
program_command (addressToProgram, dataToProgram) {:
"
writeToFlash (addressToProgram, 0x40);
/*writeToFlash (addressToProgram, 0x10);*/
/*see note (3)*/
"
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write 40h or 10h (3)
Write Address
& Data
do {
status_register=readFlash (addressToProgram);
"see note (3)";
/* E or G must be toggled*/
Read Status
Register (3)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06170b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
93/110
Flowcharts and pseudo codes
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 21. Double Word Program flowchart and pseudo code
Start
Write 35h
double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (addressToProgram1, 0x35);
/*see note (4)*/
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
Write Address 1
& Data 1 (3, 4)
Write Address 2
& Data 2 (3)
do {
status_register=readFlash (addressToProgram) ;
"see note (4)"
/* E or G must be toggled*/
Read Status
Register (4)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06171b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
4. Any address within the bank can equally be used.
94/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Flowcharts and pseudo codes
Figure 22. Quadruple Word Program flowchart and pseudo code
Start
quadruple_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2,
addressToProgram3, dataToProgram3,
addressToProgram4, dataToProgram4)
{
writeToFlash (addressToProgram1, 0x56);
/*see note (4) */
Write 56h
Write Address 1
& Data 1 (3, 4)
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 2
& Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
writeToFlash (addressToProgram3, dataToProgram3) ;
/*see note (3) */
Write Address 3
& Data 3 (3)
writeToFlash (addressToProgram4, dataToProgram4) ;
/*see note (3) */
Write Address 4
& Data 4 (3)
/*Memory enters read status state after
the Program command*/
do {
status_register=readFlash (addressToProgram) ;
/"see note (4) "/
/* E or G must be toggled*/
Read Status
Register (4)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06977b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
4. Any address within the bank can equally be used.
95/110
Flowcharts and pseudo codes
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 23. Program Suspend & Resume flowchart and pseudo code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
program has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR2 = 1
NO
Program Complete
if (status_register.SR2==0) /*program completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
YES
Read Data
}
else
Write FFh
{ writeToFlash (bank_address, 0xFF) ;
Read data from
another address
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write D0h
writeToFlash (bank_address, 0x70) ;
/*read status register to check if program has completed */
Write 70h(1)
}
Program Continues with
Bank in Read Status
Register Mode
}
AI10117b
1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
96/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Flowcharts and pseudo codes
Figure 24. Block Erase flowchart and pseudo code
Start
erase_command ( blockToErase ) {
writeToFlash (blockToErase, 0x20) ;
/*see note (2) */
Write 20h (2)
writeToFlash (blockToErase, 0xD0) ;
/* only A12-Amax(3) are significant */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
status_register=readFlash (blockToErase) ;
/* see note (2) */
/* E or G must be toggled*/
Read Status
Register (2)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1)
YES
Command
Sequence Error (1)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
YES
SR4, SR5 = 1
if ( (status_register.SR4==1) && (status_register.SR5==1) )
/* command sequence error */
error_handler ( ) ;
NO
SR5 = 0
NO
Erase Error (1)
if ( (status_register.SR5==1) )
/* erase error */
error_handler ( ) ;
YES
SR1 = 0
NO
Erase to Protected
Block Error (1)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI10185
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can be used also.
3. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.
97/110
Flowcharts and pseudo codes
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 25. Erase Suspend & Resume flowchart and pseudo code
Start
erase_suspend_command ( ) {
writeToFlash (bank_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
erase has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR6 = 1
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */
{ writeToFlash (bank_address, 0xFF) ;
Write FFh
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Read Data
YES
Write FFh
}
else
{ writeToFlash (bank_address, 0xFF) ;
read_program_data ( );
Read data from another block
or
Program/Protection Register Program
or
Block Lock/Unlock/Lock-Down
/*read or program data from another block*/
writeToFlash (bank_address, 0xD0) ;
/*write 0xD0 to resume erase*/
Write D0h
writeToFlash (bank_address, 0x70) ;
/*read status register to check if erase has completed */
Write 70h(1)
}
}
Erase Continues with
Bank in Read Status
Register Mode
AI10116b
1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
98/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Flowcharts and pseudo codes
Figure 26. Locking operations flowchart and pseudo code
Start
locking_operation_command (address, lock_operation) {
writeToFlash (address, 0x60) ; /*configuration setup*/
/* see note (1) */
Write 60h (1)
if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;
Write
01h, D0h or 2Fh
writeToFlash (address, 0x90) ;
/*see note (1) */
Write 90h (1)
Read Block
Lock States
Locking
change
confirmed?
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
/*Check the locking state (see Read Block Signature table )*/
NO
YES
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/
/*see note (1) */
Write FFh (1)
}
End
AI06176b
1. Any address within the bank can equally be used.
99/110
Flowcharts and pseudo codes
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Figure 27. Protection Register Program flowchart and pseudo code
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0xC0) ;
/*see note (3) */
Write C0h (3)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (addressToProgram) ;
/* see note (3) */
/* E or G must be toggled*/
Read Status
Register (3)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06177b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
100/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Flowcharts and pseudo codes
Figure 28. Enhanced Factory Program flowchart
SETUP PHASE
VERIFY PHASE
Start
Write PD1
Address WA1(1)
Write 30h
Address WA1
Write D0h
Address WA1
Read Status
Register
Read Status
Register
SR0 = 0?
NO
Check SR4, SR3
and SR1 for program,
VPP and Lock Errors
SR7 = 0?
Exit
PROGRAM PHASE
YES
Write PD2
Address WA2(1)
YES
SR0 = 0?
NO
NO
YES
Read Status
Register
Write PD1
Address WA1
SR0 = 0?
Read Status
Register
NO
YES
NO
SR0 = 0?
Write PDn
Address WAn(1)
YES
Write PD2
Address WA2(1)
Read Status
Register
Read Status
Register
SR0 = 0?
NO
YES
SR0 = 0?
NO
Write FFFFh
Address =/ Block WA1
YES
EXIT PHASE
Write PDn
Address WAn(1)
Read Status
Register
Read Status
Register
SR7 = 1?
NO
YES
SR0 = 0?
NO
Check Status
Register for Errors
YES
Write FFFFh
Address =/ Block WA1
End
AI06160
1. Address can remain Starting Address WA1 or be incremented.
101/110
Flowcharts and pseudo codes
C.1
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Enhanced Factory Program pseudo code
efp_command(addressFlow,dataFlow,n)
/* n is the number of data to be programmed */
{
/* setup phase */
writeToFlash(addressFlow[0],0x30);
writeToFlash(addressFlow[0],0xD0);
status_register=readFlash(any_address);
if (status_register.SR7==1){
/*EFP aborted for an error*/
if (status_register.SR4==1) /*program error*/
error_handler();
if (status_register.SR3==1) /*VPP invalid error*/
error_handler();
if (status_register.SR1==1) /*program to protect block error*/
error_handler();
}
else{
/*Program Phase*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
} while (status_register.SR0==1)
/*Ready for first data*/
for (i=0; i++; i< n){
writeToFlash(addressFlow[i],dataFlow[i]);
/* status register polling*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
} while (status_register.SR0==1);
/* Ready for a new data */
}
writeToFlash(another_block_address,FFFFh);
/* Verify Phase */
for (i=0; i++; i< n){
writeToFlash(addressFlow[i],dataFlow[i]);
/* status register polling*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
} while (status_register.SR0==1);
/* Ready for a new data */
}
writeToFlash(another_block_address,FFFFh);
/* exit program phase */
/* Exit Phase */
/* status register polling */
do{
status_register=readFlash(any_address);
/* E or G must be toggled */
} while (status_register.SR7==0);
if (status_register.SR4==1) /*program failure error*/
error_handler();
if (status_register.SR3==1) /*VPP invalid error*/
error_handler();
if (status_register.SR1==1) /*program to protect block error*/
error_handler();
}
}
102/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Flowcharts and pseudo codes
Figure 29. Quadruple Enhanced Factory Program flowchart
SETUP PHASE
LOAD PHASE
Start
Write 75h
Address WA1
FIRST
LOAD PHASE
Write PD1
Address WA1
Read Status
Register
Write PD1
Address WA1(1)
Write PD2
Address WA2(2)
Write PD3
Address WA3(2)
NO
SR7 = 0?
YES
Write PD4
Address WA4(2)
EXIT PHASE
Check SR4, SR3
and SR1 for program,
VPP and Lock Errors
PROGRAM AND
VERIFY PHASE
Read Status
Register
Write FFFFh
Address =
/ Block WA1
Exit
NO
SR0 = 0?
YES
Check SR4 for
Programming Errors
End
Last Page?
NO
YES
AI06178b
1. Address can remain Starting Address WA1 (in which case the next Page is programmed) or can be any address in the
same block.
2. The address is only checked for the first Word of each Page as the order to program the Words is fixed, so subsequent
Words in each Page can be written to any address.
103/110
Flowcharts and pseudo codes
C.2
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Quadruple Enhanced Factory Program Pseudo Code
quad_efp_command(addressFlow,dataFlow,n)
/* n is the number of pages to be programmed.*/
{
/* Setup phase */
writeToFlash(addressFlow[0],0x75);
for (i=0; i++; i< n){
/*Data Load Phase*/
/*First Data*/
writeToFlash(addressFlow[i],dataFlow[i,0]);
/*at the first data of the first page, Quad-EFP may be aborted*/
if (First_Page) {
status_register=readFlash(any_address);
if (status_register.SR7==1){
/*EFP aborted for an error*/
if (status_register.SR4==1) /*program error*/
error_handler();
if (status_register.SR3==1) /*VPP invalid error*/
error_handler();
if (status_register.SR1==1) /*program to protect block
error*/
error_handler();
}
}
/*2nd data*/
writeToFlash(addressFlow[i],dataFlow[i,1]);
/*3rd data*/
writeToFlash(addressFlow[i],dataFlow[i,2]);
/*4th data*/
writeToFlash(addressFlow[i],dataFlow[i,3]);
/* Program&Verify Phase */
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
}while (status_register.SR0==1)
}
/* Exit Phase */
writeToFlash(another_block_address,FFFFh);
/* status register polling */
do{
status_register=readFlash(any_address);
/* E or G must be toggled */
} while (status_register.SR7==0);
if (status_register.SR1==1) /*program to protected block error*/
error_handler();
if (status_register.SR3==1) /*VPP invalid error*/
error_handler();
if (status_register.SR4==1) /*program failure error*/
error_handler();
}
}
104/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Appendix D
Table 43.
Command interface state tables
Command interface state tables
Command interface states - modify table, next state(1)
Command Input
Current CI State
Read
Array(2)
(FFh)
Ready
Ready
Block
DWP,
Erase,
EFP
QWP
Bank Erase Setup
(3)(4)
Setup
(3)(4)
(30h)
(10/40h) (35h, 56h) Setup
(20h, 80h)
QuadEFP
Setup
(75h)
Program
Setup
QuadEFP
Setup
WP
setup(3)(4)
Lock/CR Setup
Program
Setup
Erase
Setup
EFP
Setup
Erase Confirm
P/E Resume,
Block Unlock
confirm, EFP
Confirm (D0h)
Read
Program/
Read
Clear Electronic
Erase
Status Status signature,
Suspend Register Register Read CFI
(B0h)
(70h) (5)(50h)
Query
(90h, 98h)
Ready
Ready (Lock Error)
Ready
Ready (Lock Error)
Setup
OTP
OTP Busy
Busy
Setup
Program
Erase
Program Busy
Busy
Program Suspended
Program Busy
Program Suspended
Setup
Ready (error)
Erase Busy
Ready (error)
Busy
Busy
Suspend
Lock/CR Setup in
Erase Suspend
Setup
Quad
EFP
1.
Erase
Suspended
Erase Busy
Erase
Suspended
Program
in Erase
Suspend
Erase Suspended
Setup
EFP
Program Busy
Suspend
Suspend
Program
in Erase
Suspend
Program
Suspended
Program Busy
Erase Busy
Erase Busy
Erase Suspended
Program Busy in Erase Suspend
Program
Suspend in
Erase
Suspend
Program Busy in Erase Suspend
Program Busy in Erase
Suspend
Program Suspend in Erase Suspend
Program Busy in
Erase Suspend
Program Suspend in Erase Suspend
Erase Suspend (Lock Error)
Erase Suspend
Erase Suspend (Lock Error)
EFP Busy
Ready (error)
Ready (error)
(6)
Busy
EFP Busy
Verify
EFP Verify(6)
Setup
Quad EFP Busy(6)
Busy
Quad EFP Busy(6)
CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory
Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.
2.
At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output.
3.
The two cycle command should be issued to the same bank address.
4.
If the P/E.C. is active, both cycles are ignored.
5.
The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.
6.
EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’.EFP and Quad EFP are busy if Block Address is first EFP
Address. Any other commands are treated as data.
105/110
Command interface state tables
Table 44.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Command interface states - modify table, next output state
Command Input(1) (2)
Current CI State
Erase Confirm
WP
Clear
Block Erase,
Quad- P/E Resume, Program/ Read
DWP,
EFP
Read
(4)
status
Status
Erase
Bank Erase
EFP Block Unlock
QWP
(3) Setup
Setup
Array (
(5)
Setup confirm, EFP Suspend Register Register(6)
Setup(4)(5) Setup(4)(5)
FFh)
(30h)
Confirm
(70h)
(B0h)
(75h)
(35h,
56h)
(20h,
80h)
(50h)
(10/40h)
(D0h)
Read
Electronic
signature,
Read CFI
Query
(90h, 98h)
Program Setup
Erase Setup
OTP Setup
Program in Erase
Suspend
EFP Setup
EFP Busy
Status Register
EFP Verify
Quad EFP Setup
Quad EFP Busy
Lock/CR Setup
Lock/CR Setup in
Erase Suspend
Status
Register
OTP Busy
Ready
Program Busy
Erase Busy
Array
Status Register
Program/Erase
Output Unchanged
Status
Output
Register Unchanged
Electronic
Signature/CFI
Program Busy in
Erase Suspend
Program Suspend
in Erase Suspend
1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple
Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase
Controller.
2. The output state shows the type of data that appears at the outputs if the bank address is the same as the command
address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI Query mode,
depending on the command issued. Each bank remains in its last output state until a new command is issued. The next
state does not depend on the bank’s output state.
3. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined
data output.
4. The two cycle command should be issued to the same bank address.
5. If the P/E.C. is active, both cycles are ignored.
6. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.
106/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Table 45.
Command interface state tables
Command interface states - lock table, next state
Command Input(1)
Current CI State
Ready
Lock/CR Setup
Lock/CR
Setup(2)
(60h)
OTP
Setup(2)
(C0h)
Lock/CR
Setup
OTP Setup
Block Lock
Confirm
(01h)
Block LockDown
Confirm (2Fh)
Set CR
Confirm
(03h)
EFP Exit,
Quad EFP
Exit(3)
Illegal
Command
(4)
P/E. C.
Operation
Completed
Ready
Ready (Lock error)
Ready
N/A
Ready (Lock error)
N/A
Setup
N/A
OTP
OTP Busy
Busy
Program
Ready
Setup
Program Busy
N/A
Busy
Program Busy
Ready
Suspend
Program Suspended
N/A
Setup
Ready (error)
N/A
Busy
Erase Busy
Ready
Erase
Suspend
Program in
Erase
Suspend
Lock/CR
Setup in
Erase
Suspend
Erase Suspended
N/A
Setup
Program Busy in Erase Suspend
N/A
Busy
Program Busy in Erase Suspend
Erase
Suspended
Suspend
Program Suspend in Erase Suspend
N/A
Lock/CR Setup in
Erase Suspend
Erase Suspend (Lock error)
Erase Suspend
Setup
EFP
Erase Suspend (Lock
error)
N/A
Ready (error)
N/A
Busy
EFP Busy(5)
EFP Verify
EFP
Busy(5)
N/A
Verify
EFP Verify(5)
Ready
EFP
Verify(5)
Ready
Quad EFP Busy(5)
Setup
N/A
QuadEFP
Busy
Quad EFP Busy(5)
Ready
Quad EFP
Busy(5)
Ready
1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple
Enhanced Factory Program, P/E. C. = Program/Erase Controller.
2. If the P/E.C. is active, both cycles are ignored.
3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.
4. Illegal commands are those not defined in the command set.
5. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’. EFP and Quad EFP are busy if Block
Address is first EFP Address. Any other commands are treated as data.
107/110
Command interface state tables
Table 46.
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Command interface states - lock table, next output state
Command Input(1)
Current CI State
Lock/CR
Setup(2)
(60h)
OTP
Setup(2)
(C0h)
Block
Lock
Confirm
(01h)
Block LockDown Confirm
(2Fh)
Set CR
Confirm
(03h)
EFP Exit,
Quad
EFP
Exit(3)
Illegal
Command
(4)
P/E. C.
Operation
Completed
Program Setup
Erase Setup
OTP Setup
Program in Erase
Suspend
Output
Unchanged
Status Register
EFP Setup
EFP Busy
EFP Verify
Quad EFP Setup
Quad EFP Busy
Lock/CR Setup
Lock/CR Setup in
Erase Suspend
OTP Busy
Status Register
Array
Status Register
Output
Unchanged
Status Register
Output Unchanged
Array
Output
Unchanged
Output
Unchanged
Status Register
Output Unchanged
Array
Output
Unchanged
Output
Unchanged
Ready
Program Busy
EraseBusy
Program/Erase
Program Busy in
Erase Suspend
Program Suspend
in Erase Suspend
1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP =
Quadruple Enhanced Factory Program, P/E. C. = Program/Erase Controller.
2. If the P/E.C. is active, both cycles are ignored.
3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.
4. Illegal commands are those not defined in the command set.
108/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
17
Revision history
Revision history
Table 47.
Document revision history
Date
Revision
15-Sep-2004
0.1
Changes
First Issue
14-Apr-2006
1
Document status promoted from Target Specificaton to full
Datasheet.
Small text changes. Address modified for Clear Status Register
command in Table 6: Standard commands.
Test condition modified for IDD3 and IDD7 in Table 19: DC
characteristics - currents. VPP1 min modified and VLKO value moved
from Min to Max in Table 20: DC characteristics - voltages.
tWHQV removed from Figure 16, Table 23, Figure 17 and Table 24.
Note 3 modified. Data modified at address offset 31h in Table 36.
Figure 23: Program Suspend & Resume flowchart and pseudo code
and Figure 25: Erase Suspend & Resume flowchart and pseudo
code modified.
12-Nov-2007
2
Applied Numonyx branding.
109/110
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
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