Mitsubishi M5M4V4265CJ-6 Edo (hyper page) mode 4194304-bit (262144-word by 16-bit) dynamic ram Datasheet

MITSUBISHI
LSIsLSIs
MITSUBISHI
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
(HYPER
PAGE)
MODE
4194304-BIT
(262144-WORD
BY 16-BIT)
DYNAMIC
RAM
EDOEDO
(HYPER
PAGE)
MODE
4194304-BIT
(262144-WORD
BY 16-BIT)
DYNAMIC
RAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with EDO
mode fuction, fabricated with the high performance CMOS
process, and is ideal for the buffer memory systems of personal
computer graphics and HDD where high speed, low power
dissipation, and low costs are essential. The use of double-layer
metalization process technology and a single-transistor dynamic
storage stacked capacitor cell provide high circuit density at
reduced costs. The lower supply (3.3V) operation, due to the
optimization of transistor structure, provides low power dissipation
while maintaining high speed operation. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application. This device has 2CAS and 1W
terminals with a refresh cycle of 512 cycles every 8.2ms.
FEATURES
RAS
CAS
Address
access
access access
time
time
time
(max.ns) (max.ns) (max.ns)
Type name
M5M4V4265CXX-5,-5S
M5M4V4265CXX-6,-6S
M5M4V4265CXX-7,-7S
50
60
70
13
15
20
Power
OE
Cycle
dissipaaccess
time
tion
time
(max.ns) (min.ns) (typ.mW)
25
30
35
13
15
20
90
110
130
408
363
333
XX=TP,J
Standard 40 pin SOJ, 44 pin TSOP (II)
Single 3.3±0.3V supply
Low stand-by power dissipation
CMOS Input level
1.8mW (Max)
CMOS Input level
360µW (Max) *
Operating power dissipation
M5M4V4265CXX-5,-5S
486mW (Max)
M5M4V4265CXX-6,-6S
432mW (Max)
M5M4V4265CXX-7,-7S
396mW (Max)
Self refresh capability *
Self refresh current
100µA (Max)
Extended refresh capability
Extended refresh current
100µA (Max)
EDO mode (512-column random access), Read-modify-write, RASonly refresh, CAS before RAS refresh, Hidden refresh capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A0~A8)
512 refresh cycles every 128ms (A0~A8) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S,
-7S : option) only
PIN CONFIGURATION (TOP VIEW)
(3.3V)VCC
1
40
VSS(0V)
DQ1
2
39
DQ16
DQ2
3
38
DQ15
DQ3
4
37
DQ14
DQ4
5
36
DQ13
(3.3V)VCC
6
35
VSS(0V)
DQ5
7
34
DQ12
DQ6
8
33
DQ11
DQ7
9
32
DQ10
DQ8 10
31
DQ9
NC 11
30
NC
NC 12
29
LCAS
W 13
28
UCAS
RAS 14
27
OE
NC 15
26
A8
A0 16
25
A7
A1 17
24
A6
A2 18
23
A5
A3 19
22
A4
(3.3V)VCC 20
21
VSS(0V)
Outline 40P0K (400mil SOJ)
(3.3V)VCC
1
44
VSS(0V)
DQ1
2
43
DQ16
DQ2
3
42
DQ15
DQ3
4
41
DQ14
DQ4
5
40
DQ13
(3.3V)VCC
6
39
VSS(0V)
DQ5
7
38
DQ12
DQ6
8
37
DQ11
DQ7
9
36
DQ10
DQ8 10
35
DQ9
NC 13
32
NC
NC 14
31
LCAS
W 15
30
UCAS
16
29
OE
NC 17
28
A8
A0 18
27
A7
A1 19
26
A6
A2 20
25
A5
A3 21
24
A4
(3.3V)VCC 22
23
VSS(0V)
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame buffer
memory for CRT
PIN DESCRIPTION
Pin name
A0~A8
DQ1~DQ16
RAS
LCAS
1
Function
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
UCAS
Upper byte control
column address strobe input
W
OE
VCC
VSS
Write control input
Output enable input
Power supply (+3.3V)
Ground (0V)
M5M4V4265CJ,TP-5,-5S:under development
RAS
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC : NO CONNECTION
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
In addition to EDO Mode, normal read, write and read-modifywrite operations the M5M4V4265CXX provides a number of other
functions, e.g., RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Operation
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
RAS only refresh
Hidden refresh
CAS before RAS (Extended *) refresh
Self refresh *
Stand-by
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
LCAS
ACT
NAC
ACT
ACT
NAC
ACT
NAC
ACT
ACT
ACT
DNC
UCAS
NAC
ACT
ACT
NAC
ACT
ACT
NAC
ACT
ACT
ACT
DNC
Input/Output
W
NAC
NAC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
DNC
DNC
DQ1~DQ8
DOUT
OPN
DOUT
DIN
DNC
DIN
OPN
DOUT
OPN
OPN
OPN
OE
ACT
ACT
ACT
NAC
NAC
NAC
DNC
ACT
DNC
DNC
DNC
DQ9~DQ16
OPN
DOUT
DOUT
DNC
DIN
DIN
OPN
DOUT
OPN
OPN
OPN
Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open
BLOCK DIAGRAM
VCC (3.3V)
ROW ADDRESS
STROBE INPUT RAS
LOWER BYTE CONTROL
COLUMN ADDRESS LCAS
STROBE INPUT
CLOCK GENERATOR
CIRCUIT
LOWER
UPPER BYTE CONTROL UCAS
COLUMN ADDRESS
STROBE INPUT
WRITE CONTROL
INPUT
VSS (0V)
(8)LOWER
DATA IN
BUFFER
UPPER
DQ1
DQ2
W
LOWER DATA
INPUTS /
OUTPUTS
DQ8
(8)LOWER
DATA OUT
BUFFER
VCC (3.3V)
VSS (0V)
A0~A8
COLUMN DECODER
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
(8)UPPER
DATA IN
BUFFER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
ROW &
COLUMN
ADDRESS
BUFFER
ROW
A 0~
A8 DECODER
MEMORY CELL
(4,194,304 BITS)
(8)UPPER
DATA OUT
BUFFER
DQ9
DQ10
DQ16
UPPER DATA
INPUTS /
OUTPUTS
VCC (3.3V)
VSS (0V)
OE
2
M5M4V4265CJ,TP-5,-5S:under development
OUTPUT ENABLE
INPUT
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
VO
IO
Pd
Topr
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
Ratings
-0.5~4.6
-0.5~4.6
-0.5~4.6
50
1000
0~70
-65~150
With respect to VSS
Ta=25˚C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted)
Symbol
VCC
VSS
VIH
VIL
Parameter
Min
3.0
0
2.0
-0.3
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
Limits
Nom
3.3
0
Max
3.6
0
Unit
V
V
V
mA
mW
˚C
˚C
(Note 1)
Unit
VCC+0.3
0.8
V
V
V
V
Note 1 : All voltage values are with respect to VSS.
ELECTRICAL CHARACTERISTICS (Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted) (Note 2)
Symbol
VOH
VOL
IOZ
II
ICC1(AV)
Parameter
Test conditions
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from Vcc, operating
(Note 3,4,5)
IOH=-2mA
IOL=2mA
Q floating 0V≤VOUT≤VCC
0V≤VIN≤VCC+0.3V, Other inputs pins=0V
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
Min
2.4
0
-5
-5
Limits
Typ
RAS, CAS cycling
tRC=tWC=min.
output open
RAS= CAS =VIH, output open
ICC2
Supply current from VCC, stand-by
(Note 6) RAS= CAS≥VCC -0.2V
output open
M5M4V4265C-5,-5S
ICC3(AV)
ICC4(AV)
ICC6(AV)
ICC8(AV) *
ICC9(AV) *
Average supply current
M5M4V4265C-6,-6S
from Vcc, RAS only
refresh mode (Note 3,5) M5M4V4265C-7,-7S
RAS cycling, CAS=VIH
tRC=min.
output open
M5M4V4265C-5,-5S
RAS=VIL, CAS cycling
tPC=min.
output open
Average supply current
from Vcc EDO mode
(Note 3,4,5)
Average supply current
from Vcc
CAS before RAS refresh
mode
(Note 3,5)
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
Average supply current
from VCC
Extended-refresh mode
(Note 6)
Average supply current from VCC
Self-refresh mode
(Note 6)
CAS before RAS refresh cycling
tRC=min.
output open
M5M4V4265CJ,TP-5,-5S:under development
Unit
V
V
µA
µA
mA
2
0.5
mA
0.1 *
125
110
95
125
110
95
115
100
85
mA
mA
mA
RAS cycling CAS≤0.2V or CAS
before RAS refresh cycling
RAS≤0.2V or ≥VCC-0.2V
CAS≤0.2V or ≥VCC-0.2V
W≤0.2V or≥VCC-0.2V
OE≤0.2V or ≥VCC-0.2V
A0~A8 ≤ 0.2V or ≥VCC-0.2V,
DQ=open
tRC=250µs, tRAS=tRAS min~1µs
100
µA
RAS=CAS≤0.2V
output open
100
µA
Note 2 : Current flowing into an IC is positive, out is negative.
3 : ICC1(AV), ICC3(AV), ICC4(AV), and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4 : ICC1(AV) and ICC4(AV) are dependent on output loading. Specified values are obtained with the output open.
5 : Column Address can be changed once or less while RAS=VIL and CAS=VIH.
3
Max
VCC
0.4
5
5
135
120
110
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAPACITANCE (Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted)
Symbol
CI (A)
CI (CLK)
CI / O
Parameter
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
Test conditions
Min
Limits
Typ
VI=VSS
f=1MHz
VI=25mVrms
Max
5
7
7
Unit
pF
pF
pF
SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=3.3±0.3V, Vss=0V, unless otherwise noted, see notes 6,14,15)
Limits
Symbol
Parameter
M5M4V4265C-5,-5S
Min
tCAC
tRAC
tAA
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after WE high
Output disable time after CAS high
Output disable time after RAS high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 13)
(Note 13)
(Note 7)
(Note 12)
(Note 12)
(Note 12,13)
(Note 12,13)
Max
13
50
25
28
13
5
5
5
M5M4V4265C-6,-6S
Min
Max
15
60
30
33
15
5
5
5
13
13
13
13
M5M4V4265C-7,-7S
Min
Max
20
70
35
38
20
5
5
5
15
15
15
15
20
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6 : An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS
inactivity before proper device operation is achieved.
7 : Measured with a load circuit equivalent to 50pF, VOH (IOH=-2mA) and VOL(IOL=2mA). The reference levels for measuring of output signals are
2.0V(VOH) and 0.8V(VOL).
8 : Assumes that tRCD≥tRCD(max) and tASC≥tASC(max) and tCP≥tCP(max).
9 : Assumes that tRCD≤tRCD(max) and tRAD≤tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC
will increase by amount that tRCD exceeds the value shown.
10 : Assumes that tRAD≥tRAD(max) and tASC≤tASC(max).
11 : Assumes that tCP≤tCP(max) and tASC≥tASC(max).
12 : tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT≤ ±5µA ) and is not
reference to VOH(min) or VOL(max).
13 : Output is disabled after both RAS and CAS go to high.
4
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and EDO Mode Cycles)
(Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted, see notes 14,15)
Limits
Symbol
Parameter
M5M4V4265C-5,-5S
Min
tREF
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tT
Refresh cycle time
Refresh cycle time *
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, RAS high to data
Delay time, CAS high to data
Delay time, OE high to data
Transition time
Note 14 : The timing requirements are assumed tT=2ns.
(Note 16)
(Note 17)
(Note 18)
(Note 19)
(Note 19)
(Note 20)
(Note 20)
(Note 20)
(Note 21)
30
18
5
0
8
13
0
0
8
8
0
0
13
13
13
1
Max
8.2
128
32
25
10
50
M5M4V4265C-6,-6S
Min
Max
8.2
128
40
20
5
0
10
15
0
0
10
10
0
0
15
15
15
1
45
30
13
50
M5M4V4265C-7,-7S
Min
50
20
5
0
10
15
0
0
10
10
0
0
20
20
20
1
Max
8.2
128
50
35
13
50
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 15 : VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Note 16 : tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
Note 17 : tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA.
Note 18 : tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by tCAC.
Note 19 : Either tDZC or tDZO must be satisfied.
Note 20 : Either tRDD or tCDD or tODD must be satisfied.
Note 21 : tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Limits
Symbol
tRC
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tCAL
tORH
tOCH
Parameter
M5M4V4265C-5,-5S
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
Column address to CAS hold time
RAS hold time after OE low
CAS hold time after OE low
Note 22 : Either tRCH or tRRH must be satisfied for a read cycle.
5
M5M4V4265CJ,TP-5,-5S:under development
(Note 22)
(Note 22)
Min
90
50
8
40
13
0
0
0
25
13
13
13
Max
10000
10000
M5M4V4265C-6,-6S
Min
110
60
10
48
15
0
0
0
30
18
15
15
Max
10000
10000
M5M4V4265C-7,-7S
Min
130
70
13
55
20
0
0
0
35
23
20
20
Unit
Max
10000
10000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
Parameter
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
M5M4V4265C-5,-5S M5M4V4265C-6,-6S
(Note 24)
Min
90
50
8
40
13
0
8
8
8
8
0
8
Max
10000
10000
Min
110
60
10
48
15
0
10
10
10
10
0
10
Max
10000
10000
M5M4V4265C-7,-7S
Min
130
70
10
55
20
0
13
13
13
13
0
13
Unit
Max
10000
10000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read-Write and Read-Modify-Write Cycles
Limits
Symbol
Parameter
Min
109
75
38
70
38
0
28
65
40
13
Max
M5M4V4265C-6,-6S
Min
133
89
44
82
44
0
32
77
47
15
Max
M5M4V4265C-7,-7S
Min
161
107
57
99
57
0
42
92
57
20
Unit
Max
ns
(Note 23)
ns
10000
10000
10000
RAS low pulse width
ns
tCAS
10000
10000
10000
CAS low pulse width
ns
tCSH
CAS hold time after RAS low
tRSH
ns
RAS hold time after CAS low
ns
tRCS
Read setup time before CAS low
ns
tCWD
(Note 24)
Delay time, CAS low to W low
tRWD
ns
(Note 24)
Delay time, RAS low to W low
tAWD
ns
(Note 24)
Delay time, address to W low
tOEH
ns
OE hold time after W low
Note 23 : tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
Note 24 : tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins
will remain high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min)
tRWC
tRAS
Read write/read modify write cycle time
M5M4V4265C-5,-5S
(for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.
6
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Cycle
(Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W)
(Note 25)
Limits
Symbol
tHPC
tHPRWC
tDOH
tRAS
tCP
tCPRH
tCPWD
tCHOL
tOEPE
tWPE
tHCWD
tHAWD
tHPWD
tHCOD
tHAOD
tHPOD
Parameter
(Note 26)
Hyper page mode read/write cycle time
Hyper page mode read write/read modify write cycle time
Output hold time from CAS low
(Note 27)
RAS low pulse width for read or write cycle
(Note 28)
CAS high pulse width
RAS hold time after CAS precharge
(Note 24)
Delay time, CAS precharge to W low
Hold time to maintain the data Hi-Z until CAS access
OE pulse width (Hi-Z control)
W pulse width (Hi-Z control)
Delay time, CAS low to W low after read
Delay time, Address to W low after read
Delay time, CAS precharge to W low after read
Delay time, CAS low to OE high after read
Delay time, Address to OE high after read
Delay time, CAS precharge to OE high after read
M5M4V4265C-5,-5S
Min
20
57
5
65
8
28
43
7
7
7
28
40
43
13
25
28
Max
100000
13
M5M4V4265C-6,-6S
Min
25
66
5
77
10
33
50
7
7
7
32
47
50
15
30
33
Max
100000
16
M5M4V4265C-7,-7S
Min
30
79
5
92
10
Unit
Max
100000
16
38
60
7
7
7
42
57
60
20
35
38
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 25 : All previously specified timing requirements and switching characteristics are applicable to their respective EDO mode cycle.
Note 26 : tHPC(min) is specified in the case of read-only and early write-only in EDO mode.
Note 27 : tRAS(min) is specified as two cycles of CAS input are performed.
Note 28 : tCP(max) is specified as a reference point only.
CAS before RAS Refresh Cycle
(Note 29)
Limits
Symbol
tCSR
tCHR
tCAS
Parameter
CAS setup time before RAS low
CAS hold time after RAS low
CAS low pulse width
M5M4V4265C-5,-5S
Min
5
10
17
Max
M5M4V4265C-6,-6S
Min
5
10
17
Max
M5M4V4265C-7,-7S
Min
5
15
22
Unit
Max
ns
ns
ns
Note 29 : Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Self Refresh Cycle *
(Note 30)
Limits
Symbol
tRASS
tRPS
tCHS
Parameter
CBR self refresh RAS low pulse width
CBR self refresh RAS high precharge time
CBR self refresh CAS hold time
7
M5M4V4265CJ,TP-5,-5S:under development
M5M4V4265C-5,-5S
Min
100
90
-50
Max
M5M4V4265C-6,-6S
Min
100
110
-50
Max
M5M4V4265C-7,-7S
Min
100
130
-50
Unit
Max
µs
ns
ns
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Timing Diagrams
Read Cycle
(Note 31)
tRC
tRAS
RAS
tRP
VIH
VIL
tRPC
tCSH
tCRP
tRCD
tRSH
tCAS
tCRP
VIH
LCAS/UCAS
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAL
tCAL
tRAH
tASC
ROW
ADDRESS
tASR
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tRRH
tRCS
tRCH
W
VIH
VIL
tDZC
tCDD
DQ1~DQ16
(INPUTS)
VIH
Hi-Z
VIL
tCAC
tREZ
tAA
tOHR
tCLZ
VOH
DQ1~DQ16
(OUTPUTS) VOL
Hi-Z
tWEZ
tOFF
tOHC
Hi-Z
tOEA
DATA VALID
tRAC
tDZO
tOEA
tOCH
OE
VIH
VIL
tORH
Note 31
Indicates the don't care input.
VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max)
Indicates the invalid output.
8
M5M4V4265CJ,TP-5,-5S:under development
tOEZ
tODD
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Read Cycle
tRC
tRP
tRAS
RAS
VIH
tRPC
VIL
tCSH
tCRP
LCAS
(or UCAS)
tRCD
tRSH
tCRP
VIH
VIL
tCPN
tCAS
UCAS
(or LCAS)
VIH
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAH
tRAL
tCAL
tASC
ROW
ADDRESS
tASR
tCAH
ROW
ADDRESS
COLUMN
ADDRESS
tRRH
tRCS
W
tRCH
VIH
VIL
DQ1~DQ8
VIH
(or DQ9~DQ16)
VIL
(INPUTS)
DQ1~DQ8
VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
Hi-Z
tCDD
tDZC
DQ9~DQ16 VIH
(or DQ1~DQ8)
VIL
(INPUTS)
Hi-Z
tREZ
tCAC
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
tWEZ
tOHR
tAA
tCLZ
tOFF
tOHC
Hi-Z
Hi-Z
DATA VALID
tRAC
tDZO
tOEZ
tOEA
tOCH
OE
VIH
VIL
tORH
9
M5M4V4265CJ,TP-5,-5S:under development
tODD
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Early Write Cycle
tWC
tRP
tRAS
RAS
VIH
tRPC
VIL
tCSH
tCRP
tRCD
tRSH
tCAS
tCRP
VIH
LCAS/UCAS
VIL
tASR
A0~A8
VIH
VIL
tRAH
tASC
ROW
ADDRESS
COLUMN
ADDRESS
tWCS
W
tDH
VIH
VIL
VIH
VIL
10
tWCH
VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
OE
ROW
ADDRESS
VIH
tDS
DQ1~DQ16
(INPUTS)
tASR
tCAH
M5M4V4265CJ,TP-5,-5S:under development
DATA VALID
Hi-Z
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Early Write Cycle
tWC
tRP
tRAS
RAS
VIH
VIL
tCSH
tCRP
LCAS
(or UCAS)
tRPC
tRCD
tRSH
tCRP
VIH
VIL
tCAS
UCAS
(or LCAS)
VIH
VIL
tASR
A0~A8
VIH
VIL
tRAH
tASC
COLUMN
ADDRESS
ROW
ADDRESS
tWCS
W
tASR
tCAH
ROW
ADDRESS
tWCH
VIH
VIL
DQ1~DQ8
VIH
(or DQ9~DQ16)
VIL
(INPUTS)
DQ1~DQ8
VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
Hi-Z
tDS
DQ9~DQ16 VIH
(or DQ1~DQ8)
VIL
(INPUTS)
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
OE
VIH
VIL
11
M5M4V4265CJ,TP-5,-5S:under development
tDH
DATA VALID
Hi-Z
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Delayed Write Cycle
tWC
tRAS
RAS
tRP
VIH
VIL
tRPC
tCSH
tRCD
tCRP
tRSH
tCAS
tCRP
VIH
LCAS/UCAS
VIL
tASR
A0~A8
VIH
VIL
tRAH
tCAH
tASC
tASR
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
tCWL
tRWL
tWP
tRCS
W
VIH
VIL
tWCH
tDZC
DQ1~DQ16
(INPUTS)
VIH
tDS
Hi-Z
tDH
DATA
VALID
VIL
tCLZ
DQ1~DQ16 VOH
(OUTPUTS) VOL
Hi-Z
Hi-Z
tDZO
tOEH
tOEZ
tODD
OE
VIH
VIL
12
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Delayed Write Cycle
tWC
tRP
tRAS
RAS
VIH
VIL
tCSH
tCRP
tRPC
tRCD
tRSH
tCRP
LCAS
(or UCAS)
VIH
VIL
tCAS
UCAS
(or LCAS)
VIH
VIL
tASR
A0~A8
VIH
VIL
tRAH
tCAH
tASC
tASR
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
tCWL
tRWL
tWP
tRCS
W
VIH
VIL
DQ1~DQ8
VIH
(or DQ9~DQ16)
VIL
(INPUTS)
DQ1~DQ8
VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
Hi-Z
tWCH
tDZC
DQ9~DQ16 VIH
(or DQ1~DQ8)
(INPUTS)
VIL
tDS
Hi-Z
tDH
DATA
VALID
tCLZ
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
Hi-Z
Hi-Z
tDZO
tOEH
tOEZ
tODD
OE
VIH
VIL
13
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRP
tRAS
RAS
VIH
VIL
tCSH
tCRP
tRPC
tRCD
tRSH
tCRP
tCAS
VIH
LCAS/UCAS
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAH
COLUMN
ADDRESS
ROW
ADDRESS
tCWL
tRWL
tWP
VIH
VIL
tDZC
DQ1~DQ16
(INPUTS)
ROW
ADDRESS
tAWD
tCWD
tRWD
tRCS
W
tASR
tCAH
tASC
tDH
tDS
VIH
Hi-Z
DATA VALID
VIL
tCAC
tAA
tCLZ
DQ1~DQ16 VOH
(OUTPUTS) VOL
Hi-Z
tRAC
tDZO
OE
VIH
VIL
14
M5M4V4265CJ,TP-5,-5S:under development
Hi-Z
DATA
VALID
tOEA
tODD
tOEZ
tOEH
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Read-Write, Read-Modify-Write Cycle
tRWC
tRP
tRAS
RAS
VIH
VIL
tCSH
tRPC
tRCD
tRSH
tCRP
LCAS
(or UCAS)
tCRP
VIH
VIL
tCAS
UCAS
(or LCAS)
VIH
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAH
tCAH
tASC
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
tAWD
tCWD
tRWD
tRCS
W
tASR
tCWL
tRWL
tWP
VIH
VIL
DQ1~DQ8
VIH
(or DQ9~DQ16)
VIL
(INPUTS)
DQ1~DQ8
VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
Hi-Z
tDH
tDS
tDZC
DQ9~DQ16 VIH
(or DQ1~DQ8)
VIL
(INPUTS)
Hi-Z
DATA VALID
tCAC
tAA
tCLZ
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
Hi-Z
tRAC
tODD
tDZO
OE
VIH
VIL
15
M5M4V4265CJ,TP-5,-5S:under development
Hi-Z
DATA
VALID
tOEA
tOEZ
tOEH
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle
tRAS
RAS
tRP
VIH
VIL
tCSH
tRCD
tCRP
tCAS
tHPC
tCAS
tCP
tRSH
tCAS
tCP
VIH
LCAS/UCAS
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAH
tCPRH
tASC
ROW
ADDRESS
tASC
tCAH
tASC
tCAH
COLUMN-1
COLUMN-2
tCAL
tCAL
ROW
ADDRESS
COLUMN-3
tRCS
W
tASR
tCAH
tRAL
tCAL
tRRH
tRCH
VIH
VIL
tWEZ
tDZC
DQ1~DQ16
(INPUTS)
tRDD
tCDD
Hi-Z
VIH
tCAC
VIL
tCAC
tAA
tCLZ
DQ1~DQ16 VOH
(OUTPUTS) VOL
DATA
VALID-1
tDOH
DATA
VALID-2
tCPA
tOEA
tOCH
OE
tAA
tDOH
Hi-Z
tRAC
tDZO
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tCPA
tOEZ
VIH
VIL
tODD
16
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Read Cycle
tRP
tRAS
RAS
VIH
VIL
tHPC
tCSH
tCRP
LCAS
(or UCAS)
tCP
tRCD
tCAS
tRSH
tCP
VIH
VIL
tCAS
UCAS
(or LCAS)
VIH
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAH
tCPRH
tCAH
tASC
ROW
ADDRESS
tASC
tCAH
COLUMN-1
COLUMN-2
tCAL
tCAL
tASC
ROW
ADDRESS
COLUMN-3
tRAL
tRRH
tCAL
tRCH
VIH
VIL
tDZC
DQ1~DQ8
VIH
(or DQ9~DQ16)
VIL
(INPUTS)
Hi-Z
tCAC
tREZ
tAA
DQ1~DQ8
VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
tOHR
Hi-Z
DATA
VALID-2
tCLZ
DQ9~DQ16 VIH
(or DQ1~DQ8)
(INPUTS)
VIL
tRDD
tCPA
tDZC
tCDD
Hi-Z
tCAC
tAA
tCAC
tAA
tDOH
tCLZ
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
Hi-Z
tRAC
tDZO
tOEA
tWEZ
tOFF
tOHC
DATA
VALID-3
DATA
VALID-1
tOCH
OE
tASR
tCAH
tRCS
W
tCRP
tCAS
tCPA
tOEZ
VIH
VIL
tODD
17
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Early Write Cycle
tRAS
RAS
tRP
VIH
VIL
tCSH
tRCD
tCRP
tCAS
tHPC
tCAS
tCP
tCP
tRSH
tCAS
tCRP
VIH
LCAS/UCAS
VIL
tCAL
tASR
A0~A8
VIH
VIL
tRAH
ROW
ADDRESS
tASC
COLUMN-1
tWCS
W
VIH
VIL
VIH
VIL
18
tCAH
COLUMN-2
tWCH
tWCS
tDH
tDS
tWCH
tCAH
COLUMN-3
tWCS
tWCH
VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
OE
tASC
VIH
tDS
DQ1~DQ16
(INPUTS)
tCAH
tCAL
tASC
M5M4V4265CJ,TP-5,-5S:under development
DATA
VALID-1
tDH
DATA
VALID-2
Hi-Z
tDS
tDH
DATA
VALID-3
tASR
ROW
ADDRESS
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Early Write Cycle
tRAS
RAS
tRP
VIH
VIL
tHPC
tCSH
tRSH
tCRP
LCAS
(or UCAS)
VIH
VIL
tRCD
UCAS
(or LCAS)
tCAS
tCAS
tCP
tCAS
tCP
VIH
VIL
tCAL
tASR
A0~A8
VIH
VIL
tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN-1
tWCS
W
tWCH
tCAH
tASC
COLUMN-2
tWCS
tWCH
tCAH
tASC
COLUMN-3
tWCS
tWCH
tDS
tDH
VIL
DQ1~DQ8
VIH
(or DQ9~DQ16)
VIL
(INPUTS)
tDH
DATA
VALID-1
DATA
VALID-3
DQ1~DQ8
VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
Hi-Z
tDS
DQ9~DQ16 VIH
(or DQ1~DQ8)
VIL
(INPUTS)
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
VIH
VIL
19
tCAL
VIH
tDS
OE
tCRP
M5M4V4265CJ,TP-5,-5S:under development
tDH
DATA
VALID-2
Hi-Z
tASR
ROW
ADDRESS
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read-Write, Read-Modify-Write Cycle
tRAS
RAS
tRP
VIH
VIL
tCSH
tCRP
tCAS
tRCD
tHPRWC
tCAS
tCP
tRWL
tCRP
VIH
LCAS/UCAS
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAH
tASC
ROW
ADDRESS
tASC
tCAH
tAWD
tCWD
tRCS
VIL
tCPWD
tDS
tDZC
VIH
Hi-Z
VIL
tCAC
tAA
tDH
Hi-Z
DATA
VALID-1
VIH
VIL
20
M5M4V4265CJ,TP-5,-5S:under development
tDH
DATA
VALID-2
tCAC
tAA
tCLZ
Hi-Z
Hi-Z
DATA
VALID-1
tRAC
tDZO
tDS
tDZC
tCLZ
DQ1~DQ16 VOH
(OUTPUTS) VOL
OE
tWP
VIH
tRWD
DQ1~DQ16
(INPUTS)
tASR
ROW
ADDRESS
tAWD
tCWD
tCWL
tWP
W
tCWL
COLUMN-2
COLUMN-1
tRCS
tCAH
tOEA
tCPA
tODD
tOEZ
Hi-Z
DATA
VALID-2
tDZO
tOEA
tODD
tOEH
tOEZ
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Read-Write, Read-Modify-Write Cycle
tRAS
RAS
tRP
VIH
VIL
tCSH
tRWL
tCRP
LCAS
(or UCAS)
VIH
VIL
tCAS
tRCD
tCP
UCAS
(or LCAS)
VIH
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAH
tASC
ROW
ADDRESS
tASC
tCAH
tCAH
tCWL
tASR
ROW
ADDRESS
COLUMN-2
COLUMN-1
tAWD
tCWD
tRCS
tAWD
tCWD
tCWL
tWP
W
tCRP
tHPRWC
tCAS
tRCS
tWP
VIH
VIL
tRWD
tCPWD
DQ1~DQ8
VIH
(or DQ9~DQ16)
VIL
(INPUTS)
DQ1~DQ8
VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
Hi-Z
tDS
tDZC
DQ9~DQ16 VIH
(or DQ1~DQ8)
VIL
(INPUTS)
Hi-Z
tDH
Hi-Z
DATA
VALID-1
tCAC
tAA
OE
VIH
VIL
21
M5M4V4265CJ,TP-5,-5S:under development
DATA
VALID-2
tCAC
tCLZ
Hi-Z
Hi-Z
DATA
VALID-1
tRAC
tDZO
tDH
tAA
tCLZ
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
tDS
tDZC
tOEA
tCPA
tODD
tOEZ
Hi-Z
DATA
VALID-2
tDZO
tOEA
tODD
tOEH
tOEZ
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (1)
tRAS
tRP
tRWL
RAS
VIH
VIL
tHPC
tCSH
tCRP
tRCD
tCAS
tCP
tCAS
tCAS
tCP
tCWL
VIH
LCAS/UCAS
tCRP
tHPRWC
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAH
ROW
ADDRESS
tASC
tCAH
tASC
COLUMN-1
tCAH
COLUMN-2
tRCS
tASR
ROW
ADDRESS
COLUMN-3
tCPWD
tAWD
tCWD
tCAL
VIL
tDH
tDS
VIH
VIL
tDZC
DATA
VALID-2
tCAC
tAA
DQ1~DQ16 VOH
(OUTPUTS) VOL
DATA
VALID-3
tCLZ
DATA
VALID-3
DATA
VALID-1
tRAC
tDZO
tCPA
tOEA
tDZO
tOEA tOEZ
tOEZ
VIH
tOCH
VIL
tODD
22
M5M4V4265CJ,TP-5,-5S:under development
tDH
tCAC
tWEZ
Hi-Z
tDS
tAA
tCLZ
OE
tWP
VIH
tDZC
DQ1~DQ16
(INPUTS)
tCAH
tWCH
tWCS
tCAL
W
tASC
tODD
tOEH
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (2)
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
tCP
tASC
A0~A8
VIH
tCAS
tCAS
tASC
tCAH
COLUMN-1
tASC
tCAH
COLUMN-2
tCAH
COLUMN-3
VIL
tCAL
tRCH
tCAL
tWCH
tWCS
W
VIH
VIL
tHCWD
tHAWD
tDH
tHPWD
DQ1~DQ16
(INPUTS)
VIH
Hi-Z
VIL
tDZC
tDS
Hi-Z
DATA
VALID-2
tCAC
tCAC
tAA
tAA
tCPA
tCPA
tWEZ
tCLZ
DQ1~DQ16 VOH
(OUTPUTS) VOL
tHCOD
tHAOD
tHPOD
OE
VIH
VIL
23
M5M4V4265CJ,TP-5,-5S:under development
Hi-Z
DATA
VALID-1
tOEZ
DATA
VALID-3
tDZC
tODD
tOEA
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by OE)
tRP
tRAS
RAS
VIH
VIL
tHPC
tCSH
tCRP
tRCD
tCP
tCAS
tRSH
tCAS
tCP
tCRP
tCAS
VIH
LCAS/UCAS
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAH
tCPRH
tCAH
tASC
ROW
ADDRESS
tASC
COLUMN-1
tASC
tCAH
tASR
tCAH
ROW
ADDRESS
COLUMN-3
COLUMN-2
tRAL
tRCS
tRRH
tRCH
W
VIH
VIL
tWEZ
tDZC
DQ1~DQ16
(INPUTS)
tRDD
tCDD
VIH
Hi-Z
VIL
tCAC
tAA
tCLZ
DQ1~DQ16 VOH
(OUTPUTS) VOL
Hi-Z
tRAC
tDZO
OE
VIH
tCAC
tCAC
tAA
tAA
tDOH
DATA
VALID-1
DATA
VALID-1
tOEZ
tCPA
tOEA
tOCH
tOEA
tCLZ
DATA
VALID-2
Hi-Z
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tCPA
tOEZ
tCHOL
tOEZ
VIL
tOEPE
24 M5M4V4265CJ,TP-5,-5S:under development
tOEPE
tODD
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by W)
tRAS
RAS
tRP
VIH
VIL
tCSH
tCRP
tRSH
tHPC
tRCD
tCAS
tCP
tCAS
tCP
tCRP
tCAS
VIH
LCAS/UCAS
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAH
tCAH
tASC
ROW
ADDRESS
COLUMN-1
tCAH
tCPRH
tASC
tCAH
COLUMN-2
COLUMN-3
tASC
tRAL
tRCS
W
tRCH
tRCS
ROW
ADDRESS
tRRH
tRCH
VIH
VIL
VIH
tRDD
tCDD
Hi-Z
VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
tWEZ
tWPE
tDZC
DQ1~DQ16
(INPUTS)
tASR
tCAC
tCAC
tAA
tAA
tCLZ
tDOH
Hi-Z
DATA
VALID-1
tRAC
tDZO
tAA
tWEZ
DATA
VALID-2
tCPA
tOEA
tCAC
tCLZ
Hi-Z
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tCPA
tOEZ
tOCH
OE
VIH
VIL
tODD
25
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
tRC
tRAS
RAS
tRP
VIH
VIL
tRPC
tCRP
tCRP
VIH
LCAS/UCAS
VIL
tASR
A0~A8
VIH
VIL
W
DQ1~DQ16
(INPUTS)
ROW
ADDRESS
ROW
ADDRESS
VIH
VIL
VIH
VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
OE
tASR
tRAH
VIH
VIL
26
M5M4V4265CJ,TP-5,-5S:under development
Hi-Z
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle, Extended Refresh Cycle *
tRC
tRP
RAS
tRC
tRAS
tRAS
tRP
VIH
VIL
tRPC tCSR
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
VIH
LCAS/UCAS
VIL
tCPN
tASR
A0~A8
VIH
ROW
ADDRESS
VIL
tRRH
tRCS
tRCH
W
DQ1~DQ16
(INPUTS)
VIH
VIL
VIH
VIL
tREZ
tOHR
tOFF
tOHC
DQ1~DQ16 VOH
(OUTPUTS)
VOL
Hi-Z
tOEZ
OE
VIH
VIL
27
M5M4V4265CJ,TP-5,-5S:under development
COLUMN
ADDRESS
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 32)
tRC
tRAS
RAS
tRC
tRP
tRAS
tRP
VIH
VIL
tCRP
tRCD
tRSH
tCHR
VIH
LCAS/UCAS
VIL
tRAD
tASR
A0~A8
VIH
VIL
tRAH
tASC
ROW
ADDRESS
tASR
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tRCS
tRAL
tRRH
VIH
W
VIL
tCDD
tDZC
tRDD
DQ1~DQ16
(INPUTS)
VIH
Hi-Z
VIL
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
DQ1~DQ16 VOH
(OUTPUTS)
VOL
Hi-Z
Hi-Z
DATA VALID
tRAC
tDZO
OE
tOEA
tORH
tOEZ
tODD
VIH
VIL
Note 32 : Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
28
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Self Refresh Cycle * (Note 30)
tRASS
tRP
RAS
tRPS
VIH
VIL
tRPC
tRPC
tCSR
tCHS
tCRP
VIH
LCAS/UCAS
VIL
tCPN
tASR
A0~A8
VIH
ROW
ADDRESS
VIL
tRRH
tRCS
tRCH
W
VIH
VIL
tRDD
tCDD
DQ1~DQ16
(INPUTS)
VIH
Hi-Z
VIL
tREZ
tOHR
tOFF
tOHC
DQ1~DQ16 VOH
(OUTPUTS) VOL
Hi-Z
tOEZ
tODD
OE
VIH
VIL
29
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Note 30 : Self refresh sequence
Two refreshing methods should be used properly depending on
the low pulse width (tRASS) of RAS signal during self refresh
period.
1. Distributed refresh during Read/Write operation
(A) Timing Diagram
Read / Write Cycle
Self Refresh Cycle
tRASS≥100µs
tNSD
Read / Write Cycle
tSND
RAS
last
refresh cycle
first
refresh cycle
Table 2
Read / Write
Self Refresh
Self Refresh
Read / Write
CBR distributed
refresh
tNSD≤250µs
tSND≤250µs
RAS only
distributed refresh
tNSD≤16µs
tSND≤16µs
Read / Write Cycle
(B) Definition of distributed refresh
tREF
tREF / 512
tREF / 512
RAS
refresh
cycle
read/write
cycles
refresh
cycle
Definition of CBR distributed refresh
(Including extended refresh)
The CBR distributed refresh performs more than 512
constant period (250µs max.) CBR cycles within 128 ms.
Definition of RAS only distributed refresh
All combinations of nine row address signals (A0 ~ A 8) are
selected during 512 constant period (16µs max.) RAS only
refresh cycles within 8.2 ms.
Note:
Hidden refresh may be used instead of CBR refresh.
RAS/CAS refresh may be used instead of RAS only refresh.
1.1 CBR distributed refresh
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the last
CBR refresh cycle during read/write operation period to the falling
edge of RAS signal at the start of self refresh operation should be
set within tNSD (shown in table 2).
30
M5M4V4265CJ,TP-5,-5S:under development
refresh
cycle
read/write
cycles
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end
of self refresh operation to the falling edge of RAS signal in the
first CBR refresh cycle during read/write operation period should
be set within tSND (shown in table 2).
1.2 RAS only distributed refresh
Switching from read/write operation to self refresh operation.
The time interval t NSD from the falling edge of RAS signal in the
last RAS only refresh cycle during read/write operation period to
the falling edge of RAS signal at the start of self refresh
operation should be set within 16µs.
Switching from self refresh operation to read/write operation.
The time interval tSND from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the first CBR refresh cycle during read/write operation period
should be set within 16µs.
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
2. Burst refresh during Read/Write operation
(A) Timing diagram
Read / Write
Self Refresh
tRASS≥100µs
tNSB
Read / Write
tSNB
RAS
first
refresh cycles
refresh cycles
511 cycles
refresh cycles
511 cycles
last
refresh cycles
Table 3
Read / Write Cycle
CBR burst
refresh
Read / Write
Self Refresh
Self Refresh
Read / Write
tNSB≤8.2ms
tSNB≤8.2ms
RAS only
burst refresh
tNSB+tSNB≤8.2ms
(B) Definition of burst refresh
8.2ms
RAS
refresh cycles
512 cycles
read/write cycles
Definition of CBR burst refresh
The CBR burst refresh performs more than 512 continuous
CBR cycles within 8.2 ms.
Definition of RAS only burst refresh
All combination of nine row address signals (A0~A8) are
selected during 512 continuous RAS only refresh cycles
within 8.2 ms.
2.1 CBR burst refresh
Switching from read/write operation to self refresh operation.
The time interval tNSB from the falling edge of RAS signal in the
first CBR refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within 8.2 ms.
Switching from self refresh operation to read/write operation.
The time interval tSNB from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the last CBR refresh cycle during read/write operation period
should be set within 8.2 ms.
31
M5M4V4265CJ,TP-5,-5S:under development
2.2 RAS only burst refresh
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the first
RAS only refresh cycle during read/write operation period
to the falling edge of RAS signal at the start of self refresh
operation should be set within tNSB (shown in table 3).
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end
of self refresh operation to the falling edge of RAS signal in the
last RAS only refresh cycle during read/write operation period
should be set within tSNB (shown in table 3).
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