MITSUBISHI LSIs M5M51008CP,FP,VP,RV,KV,KR -55H, -70H, -55X, -70X 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM DESCRIPTION The M5M51008CP,FP,VP,RV,KV,KR are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor (TFT) load cells and CMOS periphery result in a high density and low power static RAM. They are low standby current and low operation current and ideal for the battery back-up application. The M5M51008CVP,RV,KV,KR are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD). Two types of devices are available. M5M51008CVP,KV(normal lead bend type package), M5M51008CRV,KR(reverse lead bend type package).Using both types of devices, it becomes very easy to design a printed circuit board. Access time (max) M5M51008CP,FP,VP,RV,KV,KR-55H 55ns M5M51008CP,FP,VP,RV,KV,KR-70H 70ns M5M51008CP,FP,VP,RV,KV,KR-55X 55ns M5M51008CP,FP,VP,RV,KV,KR-70X 70ns Power supply current Active (1MHz) (max) 15mA (1MHz) ADDRESS INPUTS DATA INPUTS/ OUTPUTS FEATURES Type name PIN CONFIGURATION (TOP VIEW) stand-by (max) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC ADDRESS A15 INPUT CHIP SELECT S2 INPUT WRITE CONTROL W INPUT A13 A8 ADDRESS INPUTS A9 A11 OUTPUT ENABLE OE INPUT ADDRESS A10 INPUT CHIP SELECT S1 INPUT DQ8 DQ7 DQ6 DATA INPUTS/ DQ5 OUTPUTS DQ4 Outline 32P4(P), 32P2M-A(FP) 20µA (Vcc=5.5V) 8µA (Vcc=5.5V) 0.1µA (Vcc=3.0V typ) Low stand-by current 0.1µA (typ.) Directly TTL compatible : All inputs and outputs Easy memory expansion and power down by S1,S2 Data hold on +2V power supply Three-state outputs : OR - tie capability OE prevents data contention in the I/O bus Common data I/O Package M5M51008CP ············ 32pin 600mil DIP M5M51008CFP ············ 32pin 525mil SOP M5M51008CVP,RV ············ 32pin 8 X 20 mm 2 TSOP M5M51008CKV,KR ············ 32pin 8 X 13.4 mm 2 TSOP NC 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 DQ1 13 DQ2 14 DQ3 15 GND 16 A11 A9 A8 A13 W S2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 32 2 31 3 30 4 29 5 28 6 27 7 26 M5M51008CVP,KV 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 OE A10 S1 DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3 APPLICATION Outline 32P3H-E(VP), 32P3K-B(KV) Small capacity memory units A4 A5 A6 16 17 15 18 14 19 A7 A12 A14 A16 NC VCC A15 S2 W A13 A8 A9 A11 13 20 12 21 11 22 23 10 9 M5M51008CRV,KR 24 8 25 7 26 6 27 5 28 4 29 3 30 2 31 1 32 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8 S1 A10 OE Outline 32P3H-F(RV), 32P3K-C(KR) NC : NO CONNECTION MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M51008CP,FP,VP,RV,KV,KR -55H, -70H, -55X, -70X 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM FUNCTION The operation mode of the M5M51008C series are determined by a combination of the device control inputs S1,S2,W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S 1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W,S1 or S2, whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state(S1=L,S2=H). When setting S1 at a high level or S 2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high- impedance state, allowing OR-tie with other chips and memory expansion by S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as I CC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the nonselected mode. FUNCTION TABLE S1 X H L L L S2 L X H H H W X X L H H Mode DQ OE X Non selection High-impedance X Non selection High-impedance Din X Write Dout L Read High-impedance H ICC Stand-by Stand-by Active Active Active BLOCK DIAGRAM * A4 8 A5 7 A6 6 A7 5 * 16 15 14 13 A12 4 12 A14 3 11 A16 2 10 A15 31 7 A13 28 4 A0 12 20 A1 11 19 A2 10 18 9 17 131072 WORDS X 8 BITS (512 ROWS X128 COLUMNS X 16BLOCKS) 21 13 DQ1 22 14 DQ2 23 15 DQ3 25 17 DQ4 26 18 DQ5 27 19 DQ6 28 20 DQ7 29 21 DQ8 5 WRITE 29 W CONTROL INPUT 30 22 S1 6 30 S2 32 OUTPUT 24 OE ENABLE INPUT 8 32 VCC 24 16 GND (0V) DATA INPUTS/ OUTPUTS ADDRESS INPUTS A3 A10 23 31 A8 27 3 A9 26 2 A11 25 1 CLOCK GENERATOR CHIP SELECT INPUTS * Pin numbers inside dotted line show those of TSOP MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs M5M51008CP,FP,VP,RV,KV,KR -55H, -70H, -55X, -70X 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Ratings – 0.3*~7 – 0.3*~Vcc + 0.3 Conditions With respect to GND Unit V V V mW °C °C 0~Vcc 700 Ta=25°C 0~70 – 65~150 * –3.0V in case of AC ( Pulse width ≤ 50ns ) DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=5V±10%, unless otherwise noted) Symbol Parameter Test conditions VIH High-level input voltage Min 2.2 VIL Low-level input voltage –0.3* VOH High-level output voltage Limits Typ Max Unit Vcc + 0.3 V 0.8 V IOH= –1.0mA 2.4 V IOH= –0.1mA Vcc – 0.5 V VOL Low-level output voltage IOL=2mA 0.4 V II Input current VI=0~Vcc ±1 µA IO Output current in off-state S1=VIH or S2=VIL or OE=VIH VI/O=0~VCC ±1 µA ICC1 Active supply current (AC, MOS level) S1 ≤ VCC–0.2V, S2 ≥ VCC–0.2V other inputs ≤ 0.2V or ≥ VCC–0.2V Output-open(duty 100%) ICC2 ICC3 ICC4 Active supply current (AC, TTL level) S1=VIL,S2=VIH, other inputs=VIH or VIL Output-open(duty 100%) 1) S2 ≤ 0.2V, other inputs=0~VCC 2) S1 ≥ VCC–0.2V, S2 ≥ VCC–0.2V, other inputs=0~VCC Stand-by current -H -X 55ns 80 70ns 70 1MHz 15 55ns 85 70ns 70 1MHz 15 ~25°C 2 ~40°C 6 ~70°C 20 ~25°C 1 ~40°C 3 ~70°C 8 S1=VIH or S2=VIL, other inputs=0~VCC Stand-by current 3 mA mA µA mA * –3.0V in case of AC ( Pulse width ≤ 50ns ) CAPACITANCE (Ta=0~70°C, Vcc=5V±10% unless otherwise noted) Symbol CI CO Parameter Input capacitance Output capacitance Test conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz Min Limits Typ Max 6 10 Unit pF pF Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc = 5V, Ta = 25°C MITSUBISHI ELECTRIC 3 MITSUBISHI LSIs M5M51008CP,FP,VP,RV,KV,KR -55H, -70H, -55X, -70X 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, 5V±10% unless otherwise noted ) (1) MEASUREMENT CONDITIONS Input pulse level ............... VIH=2.4V,VIL=0.6V (-70H,-70X) VIH=3.0V,VIL=0.0V (-55H,-55X) Input rise and fall time ...... 5ns Reference level ................ VOH=VOL=1.5V Output loads ..................... Fig.1, CL=30pF (-55H,-70H,-55X,-70X) CL=5pF (for ten,tdis) Transition is measured ± 500mV from steady state voltage. (for ten,tdis) VCC 1.8kΩ DQ 990Ω CL ( Including scope and JIG ) Fig.1 Output load (2) READ CYCLE Limits Symbol tCR ta(A) ta(S1) ta(S2) ta(OE) tdis(S1) tdis(S2) tdis(OE) ten(S1) ten(S2) ten(OE) tV(A) Parameter -55H,-55X Min Max 55 55 55 55 30 20 20 20 5 5 5 5 Read cycle time Address access time Chip select 1 access time Chip select 2 access time Output enable access time Output disable time after S1 high Output disable time after S2 low Output disable time after OE high Output enable time after S1 low Output enable time after S2 high Output enable time after OE low Data valid time after address -70H,-70X Min Max 70 70 70 70 35 25 25 25 10 10 5 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Symbol tCW tw(W) tsu(A) tsu(A-WH) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Limits -55H,-55X -70H,-70X Min Max Min Max 55 70 45 55 0 0 50 65 50 65 50 65 25 30 0 0 0 0 20 25 20 25 5 5 5 5 Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to W Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low MITSUBISHI ELECTRIC Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 4 MITSUBISHI LSIs M5M51008CP,FP,VP,RV,KV,KR -55H, -70H, -55X, -70X 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM (4) TIMING DIAGRAMS Read cycle tCR A0~16 ta(A) tv (A) ta (S1) S1 (Note 3) tdis (S1) S2 (Note 3) ta (S2) (Note 3) tdis (S2) ta (OE) (Note 3) ten (OE) OE (Note 3) tdis (OE) (Note 3) ten (S1) ten (S2) DQ1~8 DATA VALID W = "H" level Write cycle (W control mode) tCW A0~16 tsu (S1) S1 (Note 3) (Note 3) S2 tsu (S2) (Note 3) (Note 3) tsu (A-WH) OE tsu (A) tw (W) trec (W) W tdis (W) ten(OE) ten (W) tdis (OE) DQ1~8 DATA IN STABLE tsu (D) MITSUBISHI ELECTRIC th (D) 5 MITSUBISHI LSIs M5M51008CP,FP,VP,RV,KV,KR -55H, -70H, -55X, -70X 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM Write cycle ( S1 control mode) tCW A0~16 tsu (A) tsu (S1) trec (W) S1 S2 (Note 3) (Note 3) (Note 5) W (Note 4) (Note 3) (Note 3) tsu (D) th (D) DATA IN STABLE DQ1~8 Write cycle (S2 control mode) tCW A0~16 S1 (Note 3) (Note 3) tsu (A) tsu (S2) trec (W) S2 (Note 5) W (Note 4) (Note 3) (Note 3) tsu (D) DQ1~8 th (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". 4: Writing is executed while S2 high overlaps S1 and W low. 5: When the falling edge of W is simultaneously or prior to the falling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. 6: Don't apply inverted phase signal externally when DQ pin is output mode. MITSUBISHI ELECTRIC 6 MITSUBISHI LSIs M5M51008CP,FP,VP,RV,KV,KR -55H, -70H, -55X, -70X 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS (Ta=0~70°C, unless otherwise noted) Symbol VCC (PD) Parameter Test conditions Min 2.0 2.2 Power down supply voltage VI (S1) Chip select input S1 VI (S2) Chip select input S2 2.2V≤Vcc(PD) 2V≤Vcc(PD)≤2.2V 4.5V≤Vcc(PD) Vcc(PD)<4.5V Limits Typ Power down supply current V Vcc(PD) 0.8 0.2 VCC = 3V 1) S2 ≤ 0.2V, other inputs = 0~3V 2) S1 ≥ VCC–0.2V, S2 ≥ VCC–0.2V other inputs = 0~3V Unit V ~25°C ICC (PD) Max V 1 -H ~40°C 3 ~70°C 10 ~25°C 0.5 -X ~40°C 1.5 ~70°C 4 µA (2) TIMING REQUIREMENTS (Ta=0~70°C, unless otherwise noted ) Symbol tsu (PD) trec (PD) Parameter Test conditions Power down set up time Power down recovery time Min 0 5 Limits Typ Max Unit ns ms (3) POWER DOWN CHARACTERISTICS S1 control mode VCC t su (PD) 4.5V 4.5V t rec (PD) 2.2V 2.2V S1 ≥ VCC – 0.2V S1 S2 control mode VCC S2 t su (PD) 4.5V 4.5V t rec (PD) 0.2V 0.2V S2 ≤ 0.2V MITSUBISHI ELECTRIC 7