Mitsubishi M5M5256DRV-85VXL-W 262144-bit (32768-word by 8-bit) cmos static ram Datasheet

'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-W,-85VLL-W,
-70VXL-W,-85VXL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURE
Type
M5M5256DFP,VP,RV-70VLL
Access Power supply current
time
Active Stand-by
(max)
(max)
(max)
70ns
12µA
M5M5256DFP,VP,RV-85VLL
(Vcc=3.6V)
85ns
25mA
(Vcc=3.6V)
2.4µA
M5M5256DFP,VP,RV-70VXL
70ns
(Vcc=3.6V)
M5M5256DFP,VP,RV-85VXL
85ns
(Vcc=3.0V,
Typical)
0.05µA
•Single +3.3±0.3V power supply
•No clocks, no refresh
•Data-Hold on +2.0V power supply
•Directly TTL compatible : all inputs and outputs
•Three-state outputs : OR-tie capability
•/OE prevents data contention in the I/O bus
•Common Data I/O
•Battery backup capability
•Low stand-by current··········0.05µA(typ.)
A14
A12
1
2
A7
3
A6
4
A5
5
A4
6
7
A3
A2
8
A1
9
A0
10
DQ1 11
DQ2 12
DQ3 13
GND 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/W
A13
A8
A9
A11
/OE
A10
/S
DQ8
DQ7
DQ6
DQ5
DQ4
Outline 28P2W-C (DFP)
22 /OE
23 A11
24 A9
25 A8
26 A13
27 /W
28Vcc
1 A14
2 A12
3 A7
4 A6
5 A5
6 A4
7 A3
M5M5256DVP
-W
A10 21
/S 20
DQ8 19
DQ7 18
DQ6 17
DQ5 16
DQ415
GND 14
DQ3 13
DQ2 12
DQ1 11
A0 10
A1 9
A2 8
Outline 28P2C-A (DVP)
PACKAGE
M5M5256DFP
: 28 pin 450 mil SOP
M5M5256DVP,RV : 28pin 8 X 13.4 mm2
PIN CONFIGURATION (TOP VIEW)
M5M5256DFP
-W
The M5M5256DFP,VP,RV is 262,144-bit CMOS static RAMs
organized as 32,768-words by 8-bits which is fabricated using
high-performance 3 polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery results in a high
density and low power static RAM. Stand-by current is small
enough for battery back-up application. It is ideal for the memory
systems which require simple interface.
Especially the M5M5256DVP,RV are packaged in a 28-pin thin
small outline package.Two types of devices are available,
M5M5256DVP(normal lead bend type package),
M5M5256DRV(reverse lead bend type package). Using both types of
devices, it becomes very easy to design a printed circuit board.
TSOP
APPLICATION
Small capacity memory units
7 A3
6 A4
5 A5
4 A6
3 A7
2 A12
1 A14
28 Vcc
27 /W
26 A13
25 A8
24 A9
23 A11
22 /OE
M5M5256DRV
-W
A2 8
A1 9
A0 10
DQ1 11
DQ2 12
DQ3 13
GND 14
DQ4 15
DQ5 16
DQ6 17
DQ7 18
DQ8 19
/S 20
A10 21
Outline 28P2C-B (DRV)
MITSUBISHI
ELECTRIC
1
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-W,-85VLL-W,
-70VXL-W,-85VXL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5256DP,KP,FP,VP,RV is
determined by a combination of the device control inputs /S,
/W and /OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
/W, /S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable /OE directly controls the output stage. Setting the
/OE at a high level,the output stage is in a high-impedance
state, and the data bus contention problem in the write cycle
is eliminated.
A read cycle is executed by setting /W at a high level and
/OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at +2V
power supply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
FUNCTION TABLE
/S
/W
/OE
Mode
DQ
Icc
H
X
X
Non selection
High-impedance
Stand-by
L
L
X
Write
DIN
Active
L
H
L
Read
DOUT
Active
L
H
H
High-impedance
Active
1
X 8BIT
A 12
22
A7
3
A6
4
A5
5
A4
6
A3
7
8
A1
9
A0
10
A 10
21
A 11
23
A9
24
WRITE CONTROL
INPUT /W
27
CHIP SELECT
INPUT
20
/S
OUTPUT ENABLE
/OE
INPUT
COLUMN
DECODER
A2
(512 ROWS X
512 COLUMNS)
CLOCK
GENERATOR
22
OUTPUT BUFFER
A 14
11
DQ1
12
DQ2
13
DQ3
15
DQ4
16
DQ5
17
DQ6
18
DQ7
19
DQ8
28
VCC
(3.3V)
14
GND
(0V)
DATA I/O
DATA INPUT
BUFFER
32768 WORD
ROW DECODER
26
ADDRESS INPUT
BUFFER
25
A 13
ADDRESS INPUT
BUFFER
ADDRESS
INPUT
A8
SENSE ANPLIFIER
BLOCK DIAGRAM
MITSUBISHI
ELECTRIC
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-W,-85VLL-W,
-70VXL-W,-85VXL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply voltage
Vcc
VI
VO
Pd
Topr
Tstg
Conditions
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Ratings
-0.3*~4.6
-0.3*~Vcc+0.3
With respect to GND
Unit
V
V
V
mW
(Max 4.6)
0~Vcc
700
-20~70
-65~150
Ta=25°C
°C
°C
* -3.0V in case of AC ( Pulse width ≤ 30ns )
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
(Ta=-20~70°C, Vcc=3.3±0.3V, unless otherwise noted)
Limits
Test conditions
Min
Typ
Max
Unit
VIH
High-level input voltage
2.0
Vcc
+0.3
V
VIL
Low-level input voltage
-0.3*
0.6
V
VOH1
High-level output voltage 1 IOH=-0.5mA
2.4
V
VOH2
High-level output voltage 2 IOH=-0.05mA
Vcc
-0.5
V
VOL
II
Low-level output voltage
IOL=1mA
0.4
V
Input current
VI=0~Vcc
±1
uA
IO
Output current in off-state
/S=VIH or or /OE=VIH,
VI/O=0~Vcc
±1
uA
Icc1
Active supply current
Min.
/S≤0.2V,
cycle
Other inputs<0.2V or >Vcc-0.2V
1MHz
Output-open Min. cycle
Icc2
(AC, MOS level )
Active supply current
(AC, TTL level )
/S=VIL,
other inputs=VIH or VIL
Output-open Min. cycle
Icc3
Stand-by current
/S≥Vcc-0.2V,
other inputs=0~Vcc
Icc4
Stand-by current
/S=VIH,other inputs=0~Vcc
13
25
mA
1.5
3
Min.
cycle
14
25
1MHz
1.5
3
mA
-VLL
12
-VXL
0.05
2.4
0.33
uA
mA
* -3.0V in case of AC ( Pulse width ≤ 30ns )
CAPACITANCE
Symbol
CI
CO
(Ta=-20~70°C, Vcc=3.3±0.3V, unless otherwise noted)
Parameter
Input capacitance
Output capacitance
Test conditions
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Min
Limits
Typ Max
6
8
Unit
pF
pF
Note 0: Direction for current flowing into an IC is positive (no mark).
1: Typical value is one at Ta = 25°C.
2: CI, CO are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-W,-85VLL-W,
-70VXL-W,-85VXL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(1) MEASUREMENT CONDITIONS
(Ta = -20~70°C, Vcc=3.3±0.3V, unless otherwise noted )
Input pulse level···················VIH=2.2V,VIL=0.4V
Input rise and fall time··········5ns
Reference level····················VOH=VOL=1.5V
Output loads·························Fig.1,CL=30pF (-70VLL,-70VXL )
CL=50pF (-85VLL,-85VXL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
DQ
(Including
scope and JIG)
CL
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tV(A)
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after /S high
Output disable time after /OE high
Output enable time after /S low
Output enable time after /OE low
Data valid time after address
Limits
-70VLL, VXL -85VLL, VXL
Min Max Min Max
70
85
70
85
70
85
35
45
25
25
25
25
5
10
5
10
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Limits
-70VLL, VXL -85VLL, VXL Unit
Min Max Min Max
ns
tCW
70
85
Write cycle time
tw(W)
ns
Write pulse width
55
60
tsu(A)
ns
Address setup time
0
0
tsu(A-WH) Address setup time with respect to /W high 65
ns
70
tsu(S)
ns
Chip select setup time
65
70
tsu(D)
ns
Data setup time
30
35
th(D)
ns
Data hold time
0
0
trec(W)
ns
Write recovery time
0
0
tdis(W)
ns
Output disable time from /W low
25
25
tdis(OE) Output disable time from /OE high
ns
25
25
ten(W)
ns
Output enable time from /W high
5
10
ten(OE)
ns
Output enable time from /OE low
5
10
Symbol
Parameter
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-W,-85VLL-W,
-70VXL-W,-85VXL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~14
ta(A)
tv (A)
ta (S)
/S
(Note 3)
ta (OE)
tdis (S)
(Note 3)
tdis (OE)
(Note 3)
ten (OE)
/OE
(Note 3)
ten (S)
DATA VALID
DQ1~8
/W = "H" level
Write cycle (/W control mode)
tCW
A0~14
tsu (S)
/S
(Note 3)
(Note 3)
tsu (A-WH)
/OE
tsu (A)
tw (W)
trec (W)
/W
tdis (W)
tdis (OE)
ten (W)
ten(OE)
DATA IN
STABLE
DQ1~8
(Note 3)
(Note 3)
tsu (D)
MITSUBISHI
ELECTRIC
th (D)
5
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-W,-85VLL-W,
-70VXL-W,-85VXL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( /S control mode)
tCW
A0~14
tsu (A)
tsu (S)
trec (W)
/S
(Note 5)
/W
(Note 4)
(Note 3)
DQ1~8
tsu (D)
th (D)
(Note 3)
DATA IN
STABLE
Note 3 : Hatching indicates the state is "don't care".
4 : Writing is executed in overlap of /S and /W low.
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inverted phase signal externally when DQ pin is output mode.
7 : ten, tdis are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
6
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-W,-85VLL-W,
-70VXL-W,-85VXL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Symbol
(Ta = -20~70°C, Vcc=3.3±0.3V, unless otherwise noted)
Parameter
Test conditions
Vcc (PD)
Power down supply voltage
VI (/S)
Chip select input /S
Icc (PD)
Power down supply current
Vcc = 3V,/S≥Vcc-0.2V,
Other inputs=0~Vcc
Min
2
2
Limits
Typ Max
Unit
V
V
10
-VLL
(Note 7)
-VXL
0.05
2
uA
(Note 8)
Note7: ICC (PD) = 1uA in case of Ta = 25°C
Note8: ICC (PD) = 0.2uA in case of Ta = 25°C
(2) TIMING REQUIREMENTS (Ta = -20~70°C, Vcc=3.3±0.3V, unless otherwise noted )
Symbol
tsu (PD)
trec (PD)
Parameter
Test conditions
Power down set up time
Power down recovery time
Min
Limits
Typ Max
Unit
ns
ns
0
tCR
(3) POWER DOWN CHARACTERISTICS
/S control mode
Vcc
tsu (PD)
3.0V
3.0V
2.0V
2.0V
/S
trec (PD)
/S≥Vcc-0.2V
MITSUBISHI
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