STMicroelectronics M74HC646M1R Hc648 octal bus transceiver/register 3-state, inv. hc646 octal bus transceiver/register 3-state Datasheet

M74HC646
M74HC648
HC646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
HC648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)
.
.
.
.
.
.
.
.
HIGH SPEED
fMAX = 73 MHz (TYP.) AT VCC = 5 V
LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
IOH= IOL = 6 mA (MIN.)
BALANCED PROPAGATION DELAYS
tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS646/648
DESCRIPTION
The M74HC646/648 are high speed CMOS OCTAL
BUS TRANSCEIVERS AND REGISTERS, (32
STATE) fabricated in silicon gate C MOS technology. They have the same high speed performance
of LSTTL combined with true CMOS low power consumption.
These devices consist of bus transceiver circuits
with 3-state output, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data
directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the
registers on the low-to-high transition of the appropriate clock pin (Clock AB - or Clock BA). Enable (G)
and direction (DIR) pins are provided to control the
transceiver functions. In the transceiver mode, data
present at the high-impedance port may be stored
in either register or in both.
The select controls (Select AB select BA) can multiplex stored and real-time (transparent mode) data.
The direction control determines which bus will receive data when enable G is active (low).
In the isolation mode (enable G high), ”A” data may
be stored in one register and/or ”B” data may be
stored in the other register. When an output function
is disabled, the input function is still enabled and
may be used to store and transmit data. Only one
of the two buses, A or B, may be driven at a time.
All inputs are equipped with protection circuits
October 1993
B1R
(Plastic Package)
M1R
(Micro Package)
ORDER CODES :
M74HCXXXM1R
M74HCXXXB1R
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
GAB, GAB, CAB,
SAB, SBA, CBA
A, B
1/12
M74HC646/648
LOGIC DIAGRAM (HC648)
Note : In case of M54/74HC646 output inverter marked * at A bus and B bus are eliminated.
TIMING CHART
2/12
M74HC646/648
TRUTH TABLE
HC646 (The truth table for HC648 is the same as this, but with the outputs inverted)
G
DIR CAB CBA SAB SBA
X
H
X*
X
Z
Z
X
INPUTS
INPUTS
Both the A and B bus are used for inputs to the
internal flip-flops. Data at the bus will be stored on
low to high transition of the clock inputs
X*
L
X
INPUTS
L
OUTPUTS
L
The A bus are inputs and the B bus are outputs
The data at the A bus are displayed at the B bus
H
H
X*
L
X
L
H
L
H
The data at the A bus are displayed at the B bus.
The data of the A bus are stored to the internal
flip-flop on low to high transition of th clock pulse.
X*
H
X
X
Qn
X*
H
X
The data stored to the internal flip-flop are dispayed
at the B bus
The data at the A bus are stored to the internal flipflop on low to high transition of the clock pulse. The
states of the internal flip-flops output directly to the
B bus
X
X*
L
X
L
X
L
L
X*
x*
FUNCTION
Both the A bus and the B bus are inputs
X
H
X
B
INPUTS
X
X
X
L
X
A
INPUTS
X
The output functions of the A and B bus are disabled
L
L
H
H
OUTPUTS
INPUTS
The B bus are inputs and the A bus are outputs
L
H
L
L
H
L
The data at the B bus are displayed at the A bus
H
H
The data at the B bus are displayed at the A bus.
The data of the B bus are stored to the internal flipflop on low to high transition of the clock pulse
X
H
Qn
X
The data stored to the internal flip-flops are
displayed at the A bus
X
H
L
H
L
H
the data at the B bus are stored to the internal flipflop on low to high transition of the clock pulse. The
states of the internal flip-flops output directly to the
A bus
X
: DON’T CARE
Z
: HIGH IMPEDANCE
Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS
*
: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO HIGH TRANSITION OF
THE CLOCK INPUTS
3/12
M74HC646/648
PIN DESCRIPTION
PIN No
1
2
3
4, 5, 6, 7, 8, 9, 10, 11
20, 19, 18, 17, 16, 15, 14, 13
21
22
23
12
24
SYMBOL
CLOCK AB
SELECT AB
GAB
A1 to A8
B1 to B8
G
SELECT BA
CLOCK BA
GND
VCC
NAME AND FUNCTION
A to B Clock Input (LOW to HIGH, Edge-Trigged)
Select A to B Source Input
Direction Control Input
A data Inputs/Outputs
B Data Inputs/Outputs
Output Enable Input (Active LOW)
Select B to A Source Input
B to A Clock Input (LOW to HIGH, Edge-Triggered)
Ground (0V)
Positive Supply Voltage
IEC LOGIC SYMBOLS
HC646
4/12
HC648
M74HC646/648
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VCC
VI
Supply Voltage
DC Input Voltage
-0.5 to +7
-0.5 to VCC + 0.5
V
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
IOK
DC Input Diode Current
DC Output Diode Current
± 20
± 20
mA
mA
IO
DC Output Source Sink Current Per Output Pin
± 35
mA
DC VCC or Ground Current
± 70
mA
500 (*)
mW
ICC or IGND
Parameter
PD
Power Dissipation
Tstg
TL
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
300
o
o
C
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
VI
Input Voltage
VO
Top
Output Voltage
Operating Temperature
tr, tf
Input Rise and Fall Time
Value
2 to 6
Unit
V
0 to VCC
V
0 to VCC
-40 to +85
o
V
C
VCC = 2 V
0 to 1000
ns
VCC = 4.5 V
VCC = 6 V
0 to 500
0 to 400
5/12
M74HC646/648
DC SPECIFICATIONS
Test Conditions
Symbol
VIH
V IL
V OH
Parameter
High Level Input Voltage
Low Level Input
Voltage
High Level Output Voltage
1.5
1.5
4.5
6.0
3.15
4.2
3.15
4.2
0.5
0.5
4.5
1.35
1.35
6.0
1.8
1.8
2.0
4.5
2.0
VI =
IO=-20 µA
VIH
or
V IL IO=-6.0 mA
IO=-7.8 mA
4.5
VI =
IO= 20 µA
VIH
or
V IL IO= 6.0 mA
IO= 7.8 mA
VI = VCC or GND
4.5
6.0
1.9
4.4
2.0
4.5
1.9
4.4
5.9
6.0
5.9
4.18
5.68
4.31
5.8
4.13
5.63
Unit
V
2.0
4.5
6.0
Low Level Output Voltage
-40 to 85 oC
Min. Max.
2.0
6.0
VOL
Value
TA = 25 oC
Min. Typ. Max.
VCC
(V)
V
V
0.0
0.1
0.1
0.0
0.0
0.1
0.1
0.1
0.1
0.17
0.26
0.37
0.18
0.26
±0.1
0.37
±1
µA
V
Input Leakage Current
6.0
6.0
IOZ
3 State Output Off State Current
6.0
VI = VIH or VIL
VO = VCC or GND
±0.5
±5.0
µA
ICC
Quiescent Supply Current
6.0
VI = VCC or GND
4
40
µA
II
AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns)
Test Conditions
Symbol
Parameter
tTLH
tTHL
Output Transition Time
tPLH
tPHL
Propagation Delay Time
(BUS - BUS)
VCC
(V)
CL
(pF)
2.0
4.5
50
6.0
2.0
4.5
6.0
2.0
4.5
6.0
tPLH
tPHL
Propagation Delay Time
(CLOCK - BUS)
2.0
4.5
6.0
2.0
4.5
6.0
6/12
Value
TA = 25 oC
Min. Typ. Max.
25
60
7
12
-40 to 85 oC
Min. Max.
75
15
Unit
ns
6
74
21
18
91
10
150
30
26
190
13
190
38
32
240
26
22
38
32
48
41
50
98
28
210
42
265
53
ns
150
24
116
33
36
250
50
45
315
63
ns
28
43
54
50
150
ns
ns
M74HC646/648
AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns)
Symbol
tPLH
tPHL
Parameter
Propagation Delay Time
(SELECT - BUS)
Test Conditions
VCC CL
(V) (pF)
2.0
4.5
6.0
2.0
4.5
6.0
tPZL
tPZH
3-State Output Enable Time
(G, DIR)
tPLZ
tPHZ
Output Disable Time
(G, DIR)
fMAX
Maximum Clock Frequency
tW(H)
tW(L)
ts
th
CIN
CI/O
CPD (*)
Minimum Clock Pulse Width
Minimum Set-up Time
Minimum Hold Time
Input Capacitance
Bus Terminal Capacitance
Power Dissipation Capacitance
2.0
4.5
6.0
2.0
4.5
50
Value
TA = 25 C
-40 to 85 oC
Min. Typ. Max. Min. Max.
81
170
215
23
34
43
o
150
50
RL = 1 KΩ
150
RL = 1 KΩ
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
50
RL = 1 KΩ
50
50
50
6
30
35
20
98
28
24
29
210
42
36
37
265
53
45
84
24
20
102
29
175
35
30
215
43
220
44
37
270
54
25
60
37
175
46
220
23
20
35
30
44
37
19
67
79
ns
ns
ns
ns
ns
MHz
30
7
6
16
75
15
13
50
95
19
16
65
4
3
10
9
5
5
5
13
11
5
5
5
ns
10
10
pF
pF
50
for HC646
for HC648
4.8
24
28
Unit
5
10
39
38
ns
ns
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC/8 (per bit)
7/12
M74HC646/648
SWITCHING CHARACTERISTICS TEST CIRCUIT AND WAVEFORM
WAVEFORM 1
WAVEFORM 2
WAVEFORM 3
WAVEFORM 5
WAVEFORM 4
8/12
M74HC646/648
TEST WAVEFORM ICC (Opr.)
* INPUT TRANSITION TIME IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICSTEST.
9/12
M74HC646/648
Plastic DIP24 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
a1
0.63
0.025
b
0.45
0.018
b1
0.23
b2
0.31
1.27
D
E
0.009
0.012
0.050
32.2
15.2
16.68
1.268
0.598
0.657
e
2.54
0.100
e3
27.94
1.100
F
MAX.
14.1
0.555
I
4.445
0.175
L
3.3
0.130
P043A
10/12
M74HC646/648
SO24 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
A
a1
MIN.
TYP.
MAX.
2.65
0.10
0.104
0.20
a2
0.004
0.007
2.45
0.096
b
0.35
0.49
0.013
0.019
b1
0.23
0.32
0.009
0.012
C
0.50
0.020
c1
45° (typ.)
D
15.20
15.60
0.598
0.614
E
10.00
10.65
0.393
0.420
e
1.27
0.05
e3
13.97
0.55
F
7.40
7.60
0.291
0.299
L
0.50
1.27
0.19
0.050
S
8° (max.)
L
s
e3
b1
e
a1
b
A
a2
C
c1
E
D
13
1
12
F
24
11/12
M74HC646/648
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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12/12
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