Megawin MA007AF 3-in-1 8-bit serial to parallel latch Datasheet

MA007A
3-in-1 8-bit serial to parallel latch
Features
• Three 8-bit serial input
• Three 8-bit parallel output
• Operation voltage: 2.0V to 5.7V
• Storage register with 3-state outputs
• Shift register with direct clear
• 5 MHz (typical) shift out frequency
• Output capability:
♦ Parallel outputs; bus driver
♦ Serial output; standard
Selection Information
Package / Dice
Parallel Output
Sink Current
MA007AH
Dice
MA007AP
44-PLCC
MA007AD
48-LQFP
MA007AF
44-PQFP
24 pins
20mA
Application Field
Serial-to-parallel data conversion
Remote control holding register
This document contains information on a new product under development by MEGAWIN. MEGAWIN reserves the right to change or discontinue
this product without notice.
© MEGAWIN Technology Co., Ltd. 2006 All rights reserved.
2005/11 version A1
MEGAWIN
General Description
The MA007 are high-speed Si-gate CMOS
together, the shift register will always be one clock
devices. There are three groups 8-stage serial
pulse ahead of the storage register. The shift
shift register with a storage register and 3-state
register has a serial input (DINx) and a serial
outputs in MA007. The shift register and storage
standard output (DOUTx) for cascading. It is also
register have separate clocks. Data is shifted on
provided with asynchronous reset (active LOW)
the positive-going transitions of the SCLK input.
for all 8 stages shift register. The storage register
The data in each register is transferred to the
has 8 parallel 3-state bus driver outputs. Data in
storage register on a positive-going transition of
the storage register appears at the output
the PCLK input. If both clocks are connected
whenever the output enable input (/OE) is LOW.
Pad Description
Pad No.
1
2
3
4
5, 6, 7
10, 9, 8
20 to 13
29 to 22
38 to 31
12, 30, 40
11, 21, 39, 41
2
Pad Name
/OE
PCLK
/SCLR
SCLK
DIN0, DIN1, DIN2
DOUT0, DOUT1, DOUT2
Q20 to Q27
Q10 to Q17
Q00 to Q07
VCC
GND
I/O
I
I
I
I
I
O
O
O
O
P
P
Description
Output enable (active LOW)
Parallel register clock input
Serial register reset (active LOW)
Shift register clock input
Serial data input
Serial data output
Parallel data group 2 output
Parallel data group 1 output
Parallel data group 0 output
Positive supply voltage
Power ground (0 V)
MA007A Technical Summary
MEGAWIN
Block Diagram
7
6
5
Din0
Din1
Din2
4
3
2
1
8-STAGE SHIFT
REGISTER
8-STAGE SHIFT
REGISTER
8-STAGE SHIFT
REGISTER
SCLK
/SCLR
PCLK
/OE
Dout0 10
Dout1 9
Dout2 8
8-BIT STORAGE
REGISTER
8-BIT STORAGE
REGISTER
8-BIT STORAGE
REGISTER
3-STATE OUTPUTS
3-STATE OUTPUTS
3-STATE OUTPUTS
Q27
Q26
Q25
Q24
Q23
Q22
Q21
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
MA007A Technical Summary
Q20
Q17
Q16
Q15
Q14
Q13
Q12
Q11
Q10
Q07
Q06
Q05
Q04
Q03
Q02
Q01
Q00
MEGAWIN
3
Function Description
FUNCTION TABLE
INPUTS
OUTPUTS
FUNCTON
SCLK PCLK /OE /SCLR DINx
DOUTx
QxN
X
X
L
L
X
L
NC
X
↑
L
L
X
L
L
Empty shift register loaded into storage register
X
X
H
L
X
L
Z
Shift register clear. Parallel outputs in high-impedance
OFF-state
A LOW level on /SCLR only affects the shift registers
↑
X
L
H
H
Qx6’
NC
Logic high level shifted into shift register stage 0.
Contents of all shift register stages shifted through, e.g.
previous state of stage 6 (internal Qx6’) appears on the
serial output (DOUTx)
X
↑
L
H
X
NC
Qxn’
Contents of shift register stages (internal Qxn’) are
transferred to the storage register and parallel output
stages
↑
↑
L
H
X
Qx6’
Qxn’
Contents of shift register shifted through. Previous
contents of the shift register are transferred to the
storage register and the parallel output stages.
Notes
H = HIGH voltage level; L = LOW voltage level
↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW
Z = high-impedance OFF-state; NC = no change
X = don’t care.
4
MA007A Technical Summary
MEGAWIN
Application Circuit
1
2
3
4
VCC
5
D
6
VCC
R7
V+ (Ext)
1K
VCC
D
VCC
Q7
8550D
Q8
8550D
R8
1K
Label_C1
Label_C2
+ C2
470uF
C3
0.1uF
VCC
SPK1
VCC
VCC
8 Ohm
SPK1
C
Q2
8050S
R3
620
U1
MLC031A/021A/017A_COB
VCC
IC_VCC
D6
D5
IC_VCC
R1
680K
@4MHz
Li-Battery
3.0V
C4
47uF
1N60P
C8
0.1uF
X1
C5
100pF
Q1
8050S
R2
8.2K
P0.0
32.768KHz
C6
20pF
1
2
3
4
5
6
7
8
9
VDD
OSCO
OSCI
GND
RES
TEST
X32O
X32I
P0.0
SPK2
AVDD
SPK1
AGND
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
36
35
34
33
32
31
30
29
28
27
C9
VCC
C11
SPK1
11
12
13
14
15
16
17
18
19
20
0.1uF
0.1uF
C7
20pF
Dout2
Dout1
Dout0
GND
OPT
VCC
GND
Q00
Q01
Q02
Q03
Q04
Q05
Q06
Q07
GND
VCC
Q27
Q26
Q25
Q24
Q23
Q22
Q21
Q20
VCC
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
GND
OE
PCLK
SCLR
SCLK
Din0
Din1
Din2
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Q6
8550D
R6
C
1K
VCC
C12
0.1uF
R10
R11
R12
R13
R14
R15
R16
R17
R20
R21
R22
R23
R24
R25
R26
R27
LED
LED
LED
LED
100 * 8
VCC
100 * 8
B
MA007A_COB
Label_C1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
B
8
9
10
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P1.0
P1.1
1N4148
1K
U2
1
2
3
4
5
6
7
Q5
8550D P1.1
R5
P1.0
P1.0
P1.1
R30
R31
R32
R33
R34
R35
R36
R37
LED
Label_C2
LED
100 * 8
A
A
Title
Size
Number
Revision
B
Date:
File:
1
MEGAWIN
2
3
4
MA007A Technical Summary
5
28-Mar-2005
Sheet of
E:\User\Feng\Project\DataSheet\MA007A\LED_Clock_ASIC2_AP.DDB
Drawn By:
6
5
GND
Q00
Q01
Q02
Q03
Q04
Q05
Q06
Q07
VCC
Q10
Q11
Q12
Q13
38
37
36
35
34
33
32
31
30
29
28
27
26
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VCC
Q27
Q26
Q25
Q24
Q23
Q22
Q21
Q20
GND
Q17
Q16
Q15
Q14
2
3
4
5
Din1
6
Din2
7
Dout2
8
Dout1
9
6
39
1
Din0
(0,0)
VCC
SCLK
40
GND
PCLK
/SCLR
GND
/OE
41
Dout0
Pad Assignment
MA007A Technical Summary
MEGAWIN
Absolute Maximum Rating
PARAMETER
Supply Voltage to Ground Potential
Applied Input / Output Voltage
Power Dissipation
Ambient Operating Temperature
Storage Temperature
RATING
-0.3 to +6.0
-0.3 to +6.0
500
0 to +70
-55 to +150
UNIT
V
V
mW
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC Characteristics
(VCC-GND = 5.0V, Ta = 25° C; unless otherwise specified)
PARAMETER
Op. Voltage
SYM.
VCC
CONDITIONS
-
MIN.
2.0
TYP.
5.0
MAX.
6.0
UNIT
V
Op. Current
IOP
Input High Voltage
VIH
No load (Ext.-V)
-
4.0
16.0
μA
-
0.7 VDD
-
VDD
V
Input Low Voltage
VIL
-
0
-
DOUTx sink current
IOL0
VOL = 0.4V
-
3.0
4.5
mA
DOUTx drive current
IOH0
VOH = 4.5V
-
1.5
2.5
mA
Qx0 to Qx7 sink current
IOL1
Qx0 to Qx7 drive current
IOH1
0.3VDD
V
VOL = 0.4V
-
18
27
mA
VOL = 0.4V, VCC = 6.0V
-
20
32
mA
VOH = 4.5V
-
2.7
3.5
mA
VOH = 5.4V, VCC = 6.0V
-
3.0
5.0
mA
All output sink current
IOL2
VOL = 0.4V
-
16
24
mA
All output drive current
IOH2
VOH = 4.5V
-
8
12
mA
Total output sink current
IOL3
VOL = 0.4V
-
384
576
mA
Total output drive current
IOH3
VOH = 4.5V
-
192
288
mA
MEGAWIN
MA007A Technical Summary
7
AC Characteristics
(VCC-GND = 5.0V, Ta = 25° C; unless otherwise specified)
PARAMETER
Maximum clock pulse
frequency (SCLK, PCLK)
Propagation delay
Setup Time
SYM.
FMAX
TPHL1
TPLH1
TPHL2
TPLH2
TPHL3
CONDITIONS
MIN.
TYP.
MAX.
UNIT
50 % duty cycle
-
2.5
5
MHz
SCLK to DOUTx, CL = 15 pF
-
95
195
nS
PCLK to QXn, CL = 15 pF
-
100
200
nS
/SCLR to DOUTx, CL = 15 pF
-
100
200
nS
TSU1
Din to SCLK
10
-
-
nS
TSU2
SCLK to PCLK
100
-
-
nS
TSU3
SCLK to PCLK
-
5
10
nS
TW1
SCLK
25
-
-
nS
TW2
PCLK
25
-
-
nS
TW3
/SCLR
25
-
-
nS
Tri-state output enable time
TPZH
TPZL
/OE to QXn
-
100
200
nS
Tri-state output disable time
TPHZ
TPLZ
/OE to QXn
-
100
200
nS
Din to SCLK
5
-
-
nS
/SCLR to SCLK
10
-
-
nS
Pulse Width
Hold time
Removal time
8
TH
TREM
MA007A Technical Summary
MEGAWIN
System Timing
SCLK to DOUTx Propagation Delay Waveforms
1/FMAX
SCLK
50%
TW1
TPLH1
TPHL1
DOUTx
PCLK to QXn Propagation Delay and Setup Time Waveforms
1/FMAX
SCLK
TSU2
PCLK
50%
TW2
TPLH2
TPHL2
QXn
MEGAWIN
MA007A Technical Summary
9
SCLK and PCLK are connected together to QXn-1 Propagation Delay and Setup Time
Waveforms
1/FMAX
SCLK
TSU3
PCLK
50%
TW2
TPLH2
TPHL2
QXn-1
PCLK to QXn Propagation Delay and Setup Time Waveforms
/SCLR
TW3
TREM
SCLK
TSU1
TH
DINx
50%
TPHL3
DOUTx
10
MA007A Technical Summary
MEGAWIN
Tri-state Enable/Disable Time Waveforms
/OE
TPZL
QXn
Low-to-Off
Off-to-Low
TPLZ
TPHZ
TPZH
QXn
High-to-Off
Off-to-High
Outputs
Enable
MEGAWIN
Outputs
Disable
MA007A Technical Summary
Outputs
Enable
11
Package Information
MA007AE 48 Pin PDIP (600mil) Configuration
Din0
1
48
SCLK
Din1
2
47
/SCLR
PCLK
Din2
3
46
Dout2
4
45
/OE
Dout1
5
44
GND
Dout0
6
43
VCC
GND
7
42
GND
VCC
8
41
Q00
Q27
9
40
Q01
Q26
10
39
Q02
Q25
11
38
Q03
Q24
12
37
Q04
Q23
13
36
Q05
Q22
14
35
Q06
Q21
15
34
Q07
Q20
16
33
VCC
GND
17
32
Q10
Q17
18
31
Q11
Q16
19
30
Q12
Q15
20
29
Q13
Q14
21
28
NC
NC
22
27
NC
NC
23
26
NC
NC
24
25
NC
48-PDIP (600 mil)
48 Pin PDIP Package Dimension
12
MA007A Technical Summary
MEGAWIN
/SCLR
PCLK
/OE
GND
43
42
41
40
2
Din0
Din1
3
SCLK
Din2
4
44
Dout2
5
1
Dout0
Dout1
6
MA007AP 44 Pin PLCC Configuration
GND
7
39
VCC
VCC
8
38
GND
Q27
9
37
Q26
10
36
Q00
Q01
Q25
11
35
Q02
Q24
12
34
Q03
Q23
13
33
Q04
Q22
14
32
Q05
Q21
15
31
Q06
Q20
16
30
Q07
GND
17
29
VCC
Q10
NC
28
NC
27
23
Q14
26
22
Q15
NC
21
Q16
Q11
Q12
Q13
20
Q17
25
19
24
18
44 Pin PLCC Package Dimension
MEGAWIN
MA007A Technical Summary
13
Din0
/SCLR
PCLK
/OE
GND
40
39
38
37
Din1
43
SCLK
Din2
44
41
Dout2
45
42
Dout0
Dout1
46
GND
47
48
MA007AD 48 Pin LQFP Configuration
VCC
1
36
VCC
Q27
2
35
GND
Q26
3
34
Q25
4
33
Q00
Q01
Q24
5
32
Q02
Q23
6
31
Q03
Q22
7
30
Q04
Q21
8
29
Q05
Q20
9
28
Q06
GND
10
27
Q07
Q17
11
26
VCC
Q16
12
25
Q10
24
Q11
NC
Q12
Q13
23
22
NC
NC
21
NC
20
17
NC
NC
16
Q14
NC
15
Q15
19
14
18
13
48 Pin LQFP Package Dimension
14
MA007A Technical Summary
MEGAWIN
Q01
Q02
Q03
Q04
Q05
Q06
Q07
VCC
43
41
40
39
38
37
36
35
34
42
VCC
GND
Q00
44
MA007AF 44 Pin PQFP Configuration
GND
1
33
Q10
/OE
2
32
Q11
PCLK
3
31
Q12
/SCLR
4
30
Q13
SCLK
5
29
NC
Din0
6
28
NC
Din1
7
27
NC
Din2
8
26
Q14
Dout2
9
25
Q15
Dout1
10
24
Q16
Dout0
11
23
Q17
15
16
17
18
19
20
21
VCC
Q27
Q26
Q25
Q24
Q23
Q22
Q21
GND
Q20
22
14
GND
13
12
44 Pin PQFP Package Dimension
MEGAWIN
MA007A Technical Summary
15
Notes:
Vision History
VERSION
DATE
A1
Nov. 2005
16
PAGE
DESCRIPTION
Initial issue.
MA007A Technical Summary
MEGAWIN
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