MA009A 24-bit I/O extender with interrupt function Features • Operation voltage: 2.0V to 5.7V • Low standby current (1uA, typ.) • 2 Mbps, 3-wire serial interface • 8 chip addresses are provided • 24 input/output pins ♦ 16 input pins with pull-high disable/enable and interrupt function ♦ 16 output pins with CMOS/NMOS, large/small sink capability Selection Information Package / Dice Parallel Input Parallel Output Parallel I/O Max. Sink Current MA009AH Dice MA009AP 44-PLCC MA009AD 48-LQFP MA009AF 44-PQFP 8 pins 8 pins 8 pins 20mA Application Field System I/O port LED status indicator This document contains information on a new product under development by MEGAWIN. MEGAWIN reserves the right to change or discontinue this product without notice. © MEGAWIN Technology Co., Ltd. 2006 All rights reserved. 2006/09 version A1 MEGAWIN General Description The MA009 is high-speed Si-gate CMOS devices output. The MA009 is controlled through a 3-wire that provide a general purpose I/O peripheral. The serial interface, and can be set as one of eight chip MA009 provides microcontroller eight input pins addresses by pin option. The device is optimized plus eight I/O pins and eight output pins. Each for use in many commercial and industrial input pin can be configured as interrupt source and applications where high density, low pin count, output pin can be configured as CMOS/NMOS low voltage, and low power are essential. Pad Description Pad No. Pad Name 1, 8, 9 2, 3, 4 5 6 7 10 20 to 13 29 to 22 38 to 31 NC A0, A1, A2 12, 30, 40, 41 11, 21, 39 2 C/DB SCLK Sin INTB P20 to P27 P10 to P17 P00 to P07 VCC GND I/O I I I I I O O O O P P Description No connection Chip Address bit0, bit1, bit2 Serial interface, command/data selector Serial interface, serial clock Serial interface, serial command/data input Input port interrupt event indicator Output Port 2 Input/Output Port 1 Input Port 0 Positive supply voltage Power ground (0 V) MA009A Technical Summary MEGAWIN Block Diagram C/DB Input Port P0 SCLK P0 Sin Serial to Parallel Converting Logic Control Logic I/O Port P1 Output Port P2 P1 P2 INTB A0 ~ A2 MEGAWIN Vdd MA009A Technical Summary Vss 3 Function Description There are three 8-bit I/O ports (P0 is pure input port, P1 is I/O port and P2 is pure output port) and one interrupt output pin (INTB) in MA009. The MA009 operates as a slave that sends and receives data through a 3-wire interface. The interface uses a command/data select line (C/DB); serial command/data line (Sin) and a serial clock line (SCLK) to achieve bidirectional communication between master(s) and slave(s). The master (such as microcontroller) should send serial clock and serial command to configure or to get data from MA009. The serial communication waveform are shown as below: COMMAND WRITE PERIOD COMMAND DATA C/DB SCLK Sin MSB LSB Command Write Period Waveform (command should be ready in rising edge) COMMAND READ PERIOD COMMAND DATA C/DB SCLK Sin MSB LSB Command Read Period Waveform (master can get data in falling edge) 4 MA009A Technical Summary MEGAWIN Control Registers Definition The default value of all the control register is 0 after power on. Chip Address Name C_ADDR Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 A02 Bit 1 A01 Bit 0 A00 Chip address register. Only the contents of chip address register are same as chip address pin A2, A1 and A0, all command could be enabled. This function will make the master to connect more than one MA009 easily. Input Port 0 Name P0 Bit 7 P07 Bit 6 P06 Bit 5 P05 Bit 4 P04 Bit 3 P03 Bit 2 P02 Bit 1 P01 Bit 0 P00 Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 PR01 Bit 0 PR00 Port P0 input status register. Name P0PR Bit 7 - Bit 6 - Port P0 pull high control register. P0PR.0: P0.0 ~ P0.3 pull high control, 0: enable (large resistance, 350K), 1: disable P0PR.1: P0.4 ~ P0.7 pull high control, 0: enable (large resistance, 350K), 1: disable Name P0PSR Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 PS01 Bit 0 PS00 Port P0 strong pull high selection register. P0PSR.0: P0.0 ~ P0.3 strong pull high selection, 0: disable, 1: enable (small resistance, 50K) P0PSR.1: P0.4 ~ P0.7 strong pull high selection, 0: disable, 1: enable (small resistance, 50K) Name P0IEN Bit 7 IE07 Bit 6 IE06 Bit 5 IE05 Bit 4 IE04 Bit 3 IE03 Bit 2 IE02 Bit 1 IE01 Bit 0 IE00 Port P0 interrupts enable register. P0IEN.0 ~ P0IEN.7: P0.0 ~ P0.7 falling edge interrupts control, 0: disable, 1: enable Name P0EVT Bit 7 ST07 Bit 6 ST06 Bit 5 ST05 Bit 4 ST04 Bit 3 ST03 Bit 2 ST02 Bit 1 ST01 Bit 0 ST00 Port P0 interrupts events status register. When a falling edge signal is occurs in any interrupt enabled (the bit 0 or bit 1 of P0IEN is set to 1) pins of port P0, the corresponding bit of P0EVT will be set to 1. The interrupt will be generated from the INTB (1!0) pin in this condition, and the mater (for example, a microcontroller) can read the interrupt status from P0EVT. The master can send EVTCLR (13H) command to MA009 to clear the P0EVT after the interrupt event is processed. This MEGAWIN MA009A Technical Summary 5 function will make the mater to expand interrupt pins very easily. I/O Port 1 Name P1 Bit 7 P17 Bit 6 P16 Bit 5 P15 Bit 4 P14 Bit 3 P13 Bit 2 P12 Bit 1 P11 Bit 0 P10 Bit 4 - Bit 3 - Bit 2 - Bit 1 CR11 Bit 0 CR10 Bit 2 - Bit 1 PO11 Bit 0 PO10 Port P1 input or output status register. Name P1CR Bit 7 - Bit 6 - Bit 5 - Port P1 I/O control register. P1CR.0: P1.0 ~ P1.3 is input or output, 0: input, 1: output P1CR.1: P1.4 ~ P1.7 is input or output, 0: input, 1: output Name P1POR Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Port P1 pull high/output mode control register. If P1CR.x == 0 (input mode) P1POR.0: P1.0 ~ P1.3 pull high control, 0: enable (large resistance, 350K), 1: disable P1POR.1: P1.4 ~ P1.7 pull high control, 0: enable (large resistance, 350K), 1: disable If P1CR.x == 1 (output mode) P1POR.0: P1.0 ~ P1.3 CMOS/NMOS selector, 0: CMOS, 1: NMOS P1POR.1: P1.4 ~ P1.7 CMOS/NMOS selector, 0: CMOS, 1: NMOS Name P1PSR Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 PS11 Bit 0 PS10 Port P1 strong pull high selection register. If P1CR.x == 0 (input mode) P1PSR.0: P1.0 ~ P1.3 strong pull high control, 0: disable, 1: enable (small resistance, 50K) P1PSR.1: P1.4 ~ P1.7 strong pull high control, 0: disable, 1: enable (small resistance, 50K) Name P1SCR Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 SC11 Bit 0 SC10 Port P1 sink control register. If P1CR.x == 1 (output mode) P1SCR.0: P1.0 ~ P1.3 output sink ability control, 0: weak, 1: strong (large sink current) P1SCR.1: P1.4 ~ P1.7 output sink ability control, 0: weak, 1: strong (large sink current) 6 MA009A Technical Summary MEGAWIN Name P1IEN Bit 7 IE17 Bit 6 IE16 Bit 5 IE15 Bit 4 IE14 Bit 3 IE13 Bit 2 IE12 Bit 1 IE11 Bit 0 IE10 Port P1 interrupts enable register. If P1CR.x == 0 (input mode) P1IEN.0 ~ P1IEN.7: P1.0 ~ P1.7 falling edge interrupts control, 0: disable, 1: enable Name P1EVT Bit 7 ST17 Bit 6 ST16 Bit 5 ST15 Bit 4 ST14 Bit 3 ST13 Bit 2 ST12 Bit 1 ST11 Bit 0 ST10 Port P1 interrupts events status register. This function is same as port P0. When a falling edge signal is occurs in any interrupt enabled (the bit 0 or bit 1 of P1IEN is set to 1) pins of port P1, the corresponding bit of P1EVT will be set to 1. The interrupt will be generated from the INTB (1!0) pin in this condition, and the mater (for example, a microcontroller) can read the interrupt status from P1EVT. The master can send EVTCLR (13H) command to MA009 to clear the P1EVT after the interrupt event is processed. Output Port 2 Name P2 Bit 7 P27 Bit 6 P26 Bit 5 P25 Bit 4 P24 Bit 3 P23 Bit 2 P22 Bit 1 P21 Bit 0 P20 Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 OR21 Bit 0 OR20 Bit 1 SC21 Bit 0 SC20 Port P2 output status register. Name P2OR Bit 7 - Bit 6 - Port P2 output mode control register P2OR.0: P2.0 ~ P2.3 CMOS/NMOS selector, 0: CMOS, 1: NMOS P2OR.1: P2.4 ~ P2.7 CMOS/NMOS selector, 0: CMOS, 1: NMOS Name P2SCR Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Port P2 sink control register. P2SCR.0: P2.0 ~ P2.3 output sink ability control, 0: weak, 1: strong (large sink current) P2SCR.1: P2.4 ~ P2.7 output sink ability control, 0: weak, 1: strong (large sink current) Name P2PR Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 PR21 Bit 0 PR20 Port P2 pull high control register. P2PR.0: P2.0 ~ P2.3 pull high control, 0: enable (large resistance, 350K), 1: disable P2PR.1: P2.4 ~ P2.7 pull high control, 0: enable (large resistance), 1: disable MEGAWIN MA009A Technical Summary 7 Command Definition Instruction OPCODE Operand1 C_RES FEFFH C_EVTCLR 13H W_ADDR FDH 8-bit data Input port P0 W_P0PR 04H 8-bit data W_P0PSR 0AH 8-bit data W_P0IEN R_P0 R_P0PR R_P0PSR 10H 3DH 34H 3AH 8-bit data R_P0EVT 43H I/O port P1 W_P1 W_P1CR 0EH 02H 8-bit data 8-bit data W_P1POR 05H 8-bit data W_P1PSR W_P1SCR W_P1IEN R_P1 R_P1CR R_P1POR R_P1PSR R_P1SCR R_P1EVT Output port P2 W_P2 0BH 08H 11H 3EH 32H 35H 3BH 38H 44H 8-bit data 8-bit data 8-bit data 0FH 8-bit data W_P2OR 06H 8-bit data W_P2SCR W_P2PR R_P2OR R_P2SCR R_P2PR 09H 0CH 36H 39H 3CH 8-bit data 8-bit data Data 8-bit data (R) 8-bit data (R) 8-bit data (R) 8-bit data (R) Comments Software chip reset, all register value will be reset to 0 (default value). Clear all event, P0EVT and P1EVT will be cleared. Write chip address, must match the pin status of A2 ~A0 to enable MA009. Write P0PR (pull high control register) Write P0PSR (strong pull high selection register) Write P0IEN (interrupts enable register) Read P0 Read P0PR Read P0PSR Read P0EVT (interrupts events status register) 8-bit data (R) 8-bit data (R) 8-bit data (R) 8-bit data (R) 8-bit data (R) 8-bit data (R) Write P1 Write P1CR (I/O control register) Write P1POR (pull high/output mode control register) Write P1PSR Write P1SCR (sink control register) Write P1IEN Read P1 Read P1CR Read P1POR Read P1PSR Read P1SCR Read P1EVT 8-bit data (R) 8-bit data (R) 8-bit data (R) Write P2 Write P2OR (output mode control register) Write P2SCR Write P2PR Read P2OR Read P2SCR Read P2PR The command should be sent from MSB to LSB, and the signal must be stable in clock rising edge. 8 MA009A Technical Summary MEGAWIN Command waveform example: If we want to set the P0.0~P0.3 as interrupt source, then we can write 0FH into P0IEN register. All the signals are sent MA009 by master(s) in this case. COMMAND WRITE PERIOD COMMAND DATA C/DB SCLK Sin MSB LSB MSB LSB If we want to read the interrupt status, then we can send 43H to MA009. The last 8-bit data is sent by MA009 in this case. COMMAND READ PERIOD COMMAND DATA C/DB SCLK Sin MSB MEGAWIN LSB MSB MA009A Technical Summary LSB 9 Application Circuit Vdd Vdd 0.1uF SCLK SDATA I/O SCLK Sin C/DB INT INTB Vcc P1.0 P1.1 P1.2 I/O 0 I/O 1 I/O 2 P0.0 P0.1 P0.2 P0.3 Input 0 Input 1 Vdd A2 A1 A0 GND 10 P2.0 P2.1 P2.2 ... P2.7 MA009 uC ... MA009A Technical Summary MEGAWIN GND P00 P01 P02 P03 P04 P05 P06 P07 P11 P12 P13 39 38 37 36 35 34 33 32 31 30 29 28 27 26 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VCC P26 P25 P24 P23 P22 P21 P20 GND VCC P10 VCC 2 40 GND A0 A1 VCC NC 1 41 INTB Pad Assignment SCLK 6 Sin 7 NC 8 NC 9 (0,0) MEGAWIN MA009A Technical Summary P14 5 P15 C/DB P16 4 P17 A2 P27 3 11 Absolute Maximum Rating PARAMETER Supply Voltage to Ground Potential Applied Input / Output Voltage Power Dissipation Ambient Operating Temperature Storage Temperature RATING -0.3 to +6.0 -0.3 to +6.0 500 0 to +70 -55 to +150 UNIT V V mW °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Characteristics (VCC-GND = 5.0V, Ta = 25° C; unless otherwise specified) PARAMETER Op. Voltage SYM. VCC CONDITIONS - MIN. 2.0 TYP. 5.0 MAX. 6.0 UNIT V Op. Current IOP No load (Ext.-V) - 4.0 16.0 μA Standby Current ISTB No load (Ext.-V) - 0.5 2.0 μA Input High Voltage VIH - 0.7 VDD - VDD V Input Low Voltage VIL - 0 - P1.0 to P2.7, INTB normal sink IOL0 VOL = 0.4V - 3.0 4.5 mA INTB drive current IOH0 VOH = 4.5V - 1.5 2.5 mA P1.0 to P2.7 large sink current IOL1 VOL = 0.4V - 18 27 mA VOL = 0.4V, VCC = 6.0V - 20 32 mA VOH = 4.5V - 2.7 3.5 mA 0.3VDD V current P1.0 to P2.7 drive current IOH1 VOH = 5.4V, VCC = 6.0V - 3.0 5.5 mA All output (P1.0 to P2.7) large sink current IOL2 VOL = 0.4V - 16 24 mA All output (P1.0 to P2.7) drive IOH2 VOH = 4.5V - 8 12 mA Total output large sink current IOL3 VOL = 0.4V - 256 384 mA Total output drive current IOH3 VOH = 4.5V - 128 192 mA Internal Pull-high Resistor (L) RPH0 Weak pull high - 350K - Ω Internal Pull-high Resistor (S) RPH1 Strong pull high, P0, P1 only - 50K - Ω current 12 MA009A Technical Summary MEGAWIN AC Characteristics (VCC-GND = 5.0V, Ta = 25° C; unless otherwise specified) PARAMETER Maximum clock pulse frequency (SCLK) SYM. FMAX CONDITIONS 50 % duty cycle MIN. TYP. MAX. UNIT - 2.5 5 MHz Pulse Width TW SCLK 100 -2 - nS Command Setting Time TCS C/DB to SCLK 60 -2 - nS Data Setting Time TDS1 C/DB to SCLK (Write Mode) 30 -2 - nS TDS2 C/DB to SCLK (Read Mode) 30 -2 - nS TSU1 Sin to SCLK (Command) 20 -2 - nS TSU2 Sin to SCLK (Data) 20 -2 - nS TH SCLK to Sin 10 -2 - nS TSW Vdd = 2.4V - 15 nS TV Vdd = 2.4V - 10 nS Setup Time Hold time Input/Output Switch Time Output Valid Time Output Hold Time Software Reset Recovery Time THO Vdd = 2.4V 20 - nS TSREC Vdd = 2.4V 90 - nS System Timing Command Write Setup Time Waveforms COMMAND WRITE PERIOD COMMAND C/DB DATA TCS TDS1 TW SCLK TSU1 TSU2 TH Sin MEGAWIN Valid In Valid In MA009A Technical Summary 13 Command Read Setup Time Waveforms COMMAND READ PERIOD COMMAND DATA C/DB TDS2 SCLK THO TV Sin Valid In Valid Out Command Reset Recovery Time Waveforms SOFTWARE RESET PERIOD COMMAND C/DB SCLK TSREC Sin MSB 14 LSB MA009A Technical Summary MEGAWIN Package Information MA009AE 48 Pin PDIP (600mil) Configuration C/DB 1 48 A2 SCLK 2 47 A1 Sin 3 46 A0 NC 4 45 NC NC 5 44 VCC INTB 6 43 VCC GND 7 42 GND VCC 8 41 P00 P27 9 40 P01 P26 10 39 P02 P25 11 38 P03 P24 12 37 P04 P23 13 36 P05 P22 14 35 P06 P21 15 34 P07 P20 16 33 VCC GND 17 32 P10 P17 18 31 P11 P16 19 30 P12 P15 20 29 P13 P14 21 28 NC NC 22 27 NC NC 23 26 NC NC 24 25 NC 48-PDIP (600 mil) 48 Pin PDIP Package Dimension MEGAWIN MA009A Technical Summary 15 A2 A1 A0 NC VCC 43 42 41 40 C/DB 1 44 Sin SCLK 4 2 NC 5 3 INTB NC 6 MA009AP 44 Pin PLCC Configuration GND 7 39 VCC VCC 8 38 GND P27 9 37 P26 10 36 P00 P01 P25 11 35 P02 P24 12 34 P03 P23 13 33 P04 P22 14 32 P05 P21 15 31 P06 P20 16 30 P07 GND 17 29 VCC P10 NC 28 NC 27 23 P14 26 22 P15 NC 21 P16 P11 P12 P13 20 P17 25 19 24 18 44 Pin PLCC Package Dimension 16 MA009A Technical Summary MEGAWIN A2 A1 A0 NC VCC 40 39 38 37 C/DB 42 41 Sin SCLK 43 NC 45 44 INTB NC 46 GND 48 47 MA009AD 48 Pin LQFP Configuration VCC 1 36 VCC P27 2 35 GND P26 3 34 P25 4 33 P00 P01 P24 5 32 P02 P23 6 31 P03 P22 7 30 P04 P21 8 29 P05 P20 9 28 P06 GND 10 27 P07 P17 11 26 VCC P16 12 25 P10 24 P11 NC P12 P13 23 22 NC NC 21 NC 20 17 NC NC 16 P14 NC 15 P15 19 14 18 13 48 Pin LQFP Package Dimension MEGAWIN MA009A Technical Summary 17 P01 P02 P03 P04 P05 P06 P07 VCC 43 41 40 39 38 37 36 35 34 42 VCC GND P00 44 MA009AF 44 Pin PQFP Configuration VCC 1 33 P10 NC 2 32 P11 A0 3 31 P12 A1 4 30 P13 A2 5 29 NC C/DB 6 28 NC SCLK 7 27 NC 8 26 p14 NC 9 25 P15 NC 10 24 P16 INTB 11 23 P17 Sin 16 17 18 19 20 P27 P26 P25 P24 P23 P22 P21 P20 15 VCC GND 14 GND 22 13 21 12 44 Pin PQFP Package Dimension 18 MA009A Technical Summary MEGAWIN Vision History VERSION DATE A1 Sep. 2006 MEGAWIN PAGE DESCRIPTION Initial issue. MA009A Technical Summary 19