MAC97 Series Preferred Device Sensitive Gate Triacs Silicon Bidirectional Thyristors Designed for use in solid state relays, MPU interface, TTL logic and any other light industrial or consumer application. Supplied in an inexpensive TO−92 package which is readily adaptable for use in automatic insertion equipment. http://onsemi.com Features TRIACS 0.8 AMPERE RMS 200 thru 600 VOLTS • One−Piece, Injection−Molded Package • Blocking Voltage to 600 Volts • Sensitive Gate Triggering in Four Trigger Modes (Quadrants) for all • • possible Combinations of Trigger Sources, and especially for Circuits that Source Gate Drives All Diffused and Glassivated Junctions for Maximum Uniformity of Parameters and Reliability Pb−Free Packages are Available* MT2 MT1 G MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Peak Repetitive Off-State Voltage (TJ = −40 to +110°C) (Note 1) Sine Wave 50 to 60 Hz, Gate Open MAC97A4 MAC97A6 MAC97A8 VDRM, VRRM On-State RMS Current Full Cycle Sine Wave 50 to 60 Hz (TC = +50°C) IT(RMS) 0.6 A Peak Non−Repetitive Surge Current One Full Cycle, Sine Wave 60 Hz (TC = 110°C) ITSM 8.0 A I2t 0.26 A2s Peak Gate Voltage (t v 2.0 ms, TC = +80°C) VGM 5.0 V Peak Gate Power (t v 2.0 ms, TC = +80°C) PGM 5.0 W Average Gate Power (TC = 80°C, t v 8.3 ms) PG(AV) 0.1 W Peak Gate Current (t v 2.0 ms, TC = +80°C) IGM 1.0 A Operating Junction Temperature Range TJ −40 to +110 °C Storage Temperature Range Tstg −40 to +150 °C Circuit Fusing Considerations (t = 8.3 ms) Value Unit 200 400 600 1 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 September, 2005 − Rev. 9 MARKING DIAGRAMS V 1 2 TO−92 (TO−226AA) CASE 029 STYLE 12 MAC 97Ax AYWWG G 3 MAC97Ax = Device Code x = 4, 6, or 8 A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT 1 Main Terminal 1 2 Gate 3 Main Terminal 2 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MAC97/D MAC97 Series THERMAL CHARACTERISTICS Symbol Max Unit Thermal Resistance, Junction−to−Case Characteristic RqJC 75 °C/W Thermal Resistance, Junction−to−Ambient RqJA 200 °C/W TL 260 °C Maximum Lead Temperature for Soldering Purposes for 10 Seconds ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted; Electricals apply in both directions) Characteristic Symbol Min Typ Max Unit − − − − 10 100 mA mA − − 1.9 V OFF CHARACTERISTICS Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) IDRM, IRRM TJ = 25°C TJ = +110°C ON CHARACTERISTICS Peak On−State Voltage (ITM = ".85 A Peak; Pulse Width v 2.0 ms, Duty Cycle v 2.0%) VTM Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 W) MT2(+), G(+) MT2(+), G(−) MT2(−), G(−) MT2(−), G(+) IGT Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 100 W) MT2(+), G(+) All Types MT2(+), G(−) All Types MT2(−), G(−) All Types MT2(−), G(+) All Types VGT Gate Non−Trigger Voltage (VD = 12 V, RL = 100 W, TJ = 110°C) All Four Quadrants mA − − − − − − − − 5.0 5.0 5.0 7.0 V − − − − .66 .77 .84 .88 2.0 2.0 2.0 2.5 VGD 0.1 − − V Holding Current (VD = 12 Vdc, Initiating Current = 200 mA, Gate Open) IH − 1.5 10 mA Turn-On Time (VD = Rated VDRM, ITM = 1.0 A pk, IG = 25 mA) tgt − 2.0 − ms dV/dt(c) − 5.0 − V/ms dv/dt − 25 − V/ms DYNAMIC CHARACTERISTICS Critical Rate−of−Rise of Commutation Voltage (VD = Rated VDRM, ITM = .84 A, Commutating di/dt = .3 A/ms, Gate Unenergized, TC = 50°C) Critical Rate of Rise of Off−State Voltage (VD = Rated VDRM, TC = 110°C, Gate Open, Exponential Waveform http://onsemi.com 2 MAC97 Series Voltage Current Characteristic of Triacs (Bidirectional Device) + Current Symbol Parameter VTM VDRM Peak Repetitive Forward Off State Voltage IDRM Peak Forward Blocking Current VRRM Peak Repetitive Reverse Off State Voltage IRRM Peak Reverse Blocking Current VTM Maximum On State Voltage IH Holding Current on state IH IRRM at VRRM off state IH Quadrant 3 MainTerminal 2 − VTM Quadrant Definitions for a Triac MT2 POSITIVE (Positive Half Cycle) + (+) MT2 Quadrant II (+) MT2 (−) IGT GATE Quadrant I (+) IGT GATE MT1 MT1 REF REF IGT − + IGT (−) MT2 Quadrant III Quadrant 1 MainTerminal 2 + (−) MT2 Quadrant IV (+) IGT GATE (−) IGT GATE MT1 MT1 REF REF − MT2 NEGATIVE (Negative Half Cycle) All polarities are referenced to MT1. With in−phase signals (using standard AC lines) quadrants I and III are used. http://onsemi.com 3 + Voltage IDRM at VDRM MAC97 Series 110 100 100 I T(RMS) , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE (° C) T = 30° 60° 90 DC 90° 80 180° 70 120° 60 a 50 a 40 30 a = CONDUCTION ANGLE 0.1 0.2 0.3 60° 90 0.4 0.5 0.6 0.7 0.8 90° DC 80 180° 70 120° 60 a 50 40 20 0 T = 30° a 30 a = CONDUCTION ANGLE 0 0.05 0.1 0.15 0.2 0.25 0.3 IT(RMS), RMS ON−STATE CURRENT (AMPS) IT(RMS), RMS ON−STATE CURRENT (AMPS) Figure 1. RMS Current Derating Figure 2. RMS Current Derating 1.2 0.35 0.4 5.2 6.0 6.0 4.0 a 1.0 DC a 0.8 TJ = 110°C 180° 2.0 a = CONDUCTION ANGLE 25°C 120° 0.6 1.0 0.4 ITM , INSTANTANEOUS ON-STATE CURRENT (AMP) P (AV), MAXIMUM AVERAGE POWER DISSIPATION (WATTS) TC, MAXIMUM ALLOWABLE CASE TEMPERATURE (° C) 110 90° 60° 0.2 T = 30° 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 IT(RMS), RMS ON−STATE CURRENT (AMPS) Figure 3. Power Dissipation 0.6 0.4 0.2 0.1 0.06 0.04 0.02 0.01 0.006 0.4 1.2 2.0 2.8 3.6 4.4 VTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) Figure 4. On−State Characteristics http://onsemi.com 4 R (t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) MAC97 Series 10 I TSM , PEAK SURGE CURRENT (AMPS) 1.0 5.0 ZQJC(t) = RQJC(t) @ r(t) 0.1 3.0 TJ = 110°C f = 60 Hz 2.0 0.01 0.1 1.0 10 1S103 100 Surge is preceded and followed by rated current. 1.0 1.0 1S104 2.0 3.0 5.0 Figure 5. Transient Thermal Response 30 50 100 Figure 6. Maximum Allowable Surge Current 100 1.2 VGT, GATE TRIGGER VOLTAGE (V) IGT, GATE TRIGGER CURRENT (mA) 10 NUMBER OF CYCLES t, TIME (ms) Q4 10 Q3 Q2 Q1 1 0 −40 −25 −10 5 20 35 50 80 65 95 1.1 Q4 1.0 Q3 0.9 Q2 0.8 Q1 0.7 0.6 0.5 0.4 0.3 −40 −25 110 −10 5 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 7. Typical Gate Trigger Current versus Junction Temperature Figure 8. Typical Gate Trigger Voltage versus Junction Temperature 100 110 10 10 IH , HOLDING CURRENT (mA) IL , LATCHING CURRENT (mA) CYCLE Q2 Q3 Q4 1 Q1 0 −40 −25 −10 5 20 35 50 65 80 95 MT2 Negative 1 MT2 Positive 0.1 −40 −25 110 −10 5 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 9. Typical Latching Current versus Junction Temperature Figure 10. Typical Holding Current versus Junction Temperature http://onsemi.com 5 110 MAC97 Series LL 200 VRMS ADJUST FOR ITM, 60 Hz VAC MEASURE I TRIGGER TRIGGER CONTROL CHARGE 1N4007 CHARGE CONTROL NON-POLAR CL RS CS MT2 1N914 51 W − ADJUST FOR + dV/dt(c) 200 V MT1 G Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information. Figure 11. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage (dV/dt)c ORDERING & SHIPPING INFORMATION U.S. Europe Equivalent Shipping Description of TO92 Tape Orientation MAC97A6RL1 Radial Tape & Reel (2K/Reel) Flat side of TO92 & adhesive tape visible MAC97A6RL1G Radial Tape & Reel (2K/Reel) (Pb−Free) Flat side of TO92 & adhesive tape visible MAC97A8RLRM MAC97A8RL1 Radial Tape & Reel (2K/Reel) Flat side of TO92 & adhesive tape visible MAC97A8RLRMG MAC97A8RL1G Radial Tape & Reel (2K/Reel) (Pb−Free) Flat side of TO92 & adhesive tape visible MAC97A4 Bulk in Box (5K/Box) N/A, Bulk MAC97A4G Bulk in Box (5K/Box) (Pb−Free) N/A, Bulk MAC97A6 Bulk in Box (5K/Box) N/A, Bulk MAC97A6G Bulk in Box (5K/Box) (Pb−Free) N/A, Bulk MAC97A8 Bulk in Box (5K/Box) N/A, Bulk MAC97A8G Bulk in Box (5K/Box) (Pb−Free) N/A, Bulk MAC97A6RLRF Radial Tape & Reel (2K/Reel) Round side of TO92 & adhesive tape on reverse side MAC97A6RLRFG Radial Tape & Reel (2K/Reel) (Pb−Free) Round side of TO92 & adhesive tape on reverse side MAC97A6RLRP Radial Tape & Reel (2K/Reel) Round side of TO92 & adhesive tape on reverse side MAC97A6RLRPG Radial Tape & Reel (2K/Reel) (Pb−Free) Round side of TO92 & adhesive tape on reverse side MAC97A8RLRP Radial Tape / Fan Fold Box (2K/Box) Round side of TO92 & adhesive tape visible MAC97A8RLRPG Radial Tape / Fan Fold Box (2K/Box) (Pb−Free) Round side of TO92 & adhesive tape visible †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 MAC97 Series TO−92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL H2A H2A H2B H2B H W2 H4 H5 T1 L1 H1 W1 W L T T2 F1 F2 P2 D P2 P1 P Figure 12. Device Positioning on Tape Specification Inches Symbol Item Millimeter Min Max Min Max D Tape Feedhole Diameter 0.1496 0.1653 3.8 4.2 D2 Component Lead Thickness Dimension 0.015 0.020 0.38 0.51 Component Lead Pitch 0.0945 0.110 2.4 2.8 .059 0.156 1.5 4.0 0.3346 0.3741 8.5 9.5 0 0.039 0 1.0 F1, F2 H Bottom of Component to Seating Plane H1 Feedhole Location H2A Deflection Left or Right H2B Deflection Front or Rear 0 0.051 0 1.0 H4 Feedhole to Bottom of Component 0.7086 0.768 18 19.5 H5 Feedhole to Seating Plane 0.610 0.649 15.5 16.5 L Defective Unit Clipped Dimension 0.3346 0.433 8.5 11 L1 Lead Wire Enclosure 0.09842 − 2.5 − P Feedhole Pitch 0.4921 0.5079 12.5 12.9 P1 Feedhole Center to Center Lead 0.2342 0.2658 5.95 6.75 P2 First Lead Spacing Dimension 0.1397 0.1556 3.55 3.95 0.06 0.08 0.15 0.20 − 0.0567 − 1.44 T Adhesive Tape Thickness T1 Overall Taped Package Thickness T2 Carrier Strip Thickness 0.014 0.027 0.35 0.65 W Carrier Strip Width 0.6889 0.7481 17.5 19 W1 Adhesive Tape Width 0.2165 0.2841 5.5 6.3 W2 Adhesive Tape Position 0.0059 0.01968 0.15 0.5 NOTES: 2. Maximum alignment deviation between leads not to be greater than 0.2 mm. 3. Defective components shall be clipped from the carrier tape such that the remaining protrusion (L) does not exceed a maximum of 11 mm. 4. Component lead to tape adhesion must meet the pull test requirements. 5. Maximum non−cumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches. 6. Holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive. 7. No more than 1 consecutive missing component is permitted. 8. A tape trailer and leader, having at least three feed holes is required before the first and after the last component. 9. Splices will not interfere with the sprocket feed holes. http://onsemi.com 7 MAC97 Series PACKAGE DIMENSIONS TO−92 (TO−226AA) CASE 029−11 ISSUE AL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. B R P L SEATING PLANE K DIM A B C D G H J K L N P R V D X X G J H V C SECTION X−X 1 N N INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.021 0.045 0.055 0.095 0.105 0.015 0.020 0.500 −−− 0.250 −−− 0.080 0.105 −−− 0.100 0.115 −−− 0.135 −−− MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.407 0.533 1.15 1.39 2.42 2.66 0.39 0.50 12.70 −−− 6.35 −−− 2.04 2.66 −−− 2.54 2.93 −−− 3.43 −−− STYLE 12: PIN 1. MAIN TERMINAL 1 2. GATE 3. MAIN TERMINAL 2 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 8 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MAC97/D