LATTICE MACH445-12

FINAL
COM’L: -12/15/20
MACH445-12/15/20
Lattice Semiconductor
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
■ 100-pin version of the MACH435 in PQFP
■ Up to 20 product terms per function, with XOR
■ 5 V, in-circuit programmable
■ Flexible clocking
■ JTAG, IEEE 1149.1 JTAG testing capability
— Four global clock pins with selectable edges
— Asynchronous mode available for each
macrocell
■ 8 “PAL33V16” blocks
■ 128 macrocells
■ 12 ns tPD
■ 83 MHz fCNT
■ 70 inputs with pull-up resistors
■ Input and output switch matrices for high
routability
■ 64 outputs
■ Fixed, predictable, deterministic delays
■ 192 flip-flops
■ JEDEC-file compatible with MACH435
— 128 macrocell flip-flops
— 64 input flip-flops
■ Zero-hold-time input register option
GENERAL DESCRIPTION
The MACH445 is a member of the high-performance
EE CMOS MACH 4 family. This device has approximately twelve times the macrocell capability of the
popular PAL22V10, with significant density and functional features that the PAL22V10 does not provide. It is
architecturally identical to the MACH435, with the
addition of JTAG and 5-V programming features.
The MACH445 consists of eight PAL blocks interconnected by a programmable central switch matrix. The
central switch matrix connects the PAL blocks to each
other and to all input pins, providing a high degree of
connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
Routability is further enhanced by an input switch matrix
and an output switch matrix. The input switch matrix
provides input signals with alternative paths into the
central switch matrix; the output switch matrix provides
flexibility in assigning macrocells to I/O pins.
The MACH445 has macrocells that can be configured
as synchronous or asynchronous. This allows
designers to implement both synchronous and
asynchronous logic together on the same device. The
two types of design can be mixed in any proportion,
since the selection on each macrocell affects only that
macrocell.
Up to 20 product terms per function can be assigned. It
is possible to allocate some product terms away from a
macrocell without losing the use of that macrocell for
logic generation.
The MACH445 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type, T-type, J-K, or S-R to help reduce
the number of product terms used. The flip-flop can also
be configured as a latch. The register type decision can
be made by the designer or by the software.
All macrocells can be connected to an I/O cell through
the output switch matrix. The output switch matrix
makes it possible to make significant design changes
while minimizing the risk of pinout changes.
Publication# 17468 Rev. E
Issue Date: May 1995
Amendment /0
2
4
4
Clock Generator
OE
CLK0/I0, CLK1/I1,
CLK2/I3, CLK3/I4
MACH445-12/15/20
4
Block G
8
I/O Cells
8
Output Switch
Matrix
I/O48–I/O55
4
8
Block H
Clock Generator
I/O56–I/O63
8
I/O Cells
8
16
16
16
Input Switch
Matrix
16
Macrocells
4
4
8
Clock Generator
17468E-1
Block F
I/O40–I/O47
8
I/O Cells
8
Output Switch
Matrix
16
Macrocells
16
66 X 90
AND Logic Array
and Logic Allocator
24
16
16
4
4
4
4
4
8
8
OE
Output Switch
Matrix
OE
4
OE
16
Input Switch
Matrix
16
4
33
24
Input Switch
Matrix
8
OE
Macrocells
OE
16
66 X 90
AND Logic Array
and Logic Allocator
24
16
16
4
Block D
Block E
I/O32–I/O39
8
I/O Cells
8
Output Switch
Matrix
16
Macrocells
16
66 X 90
AND Logic Array
and Logic Allocator
33
33
66 X 90
AND Logic Array
and Logic Allocator
16
Macrocells
16
Output Switch
Matrix
8
I/O Cells
8
I/O24–I/031
16
16
24
24
16
16
Input Switch
Matrix
4
4
33
66 X 90
AND Logic Array
and Logic Allocator
16
Macrocells
16
Output Switch
Matrix
Central Switch Matrix
4
4
8
8
OE
16
66 X 90
AND Logic Array
and Logic Allocator
Input Switch
Matrix
24
Input Switch
Matrix
33
16
16
OE
24
33
66 X 90
AND Logic Array
and Logic Allocator
16
Macrocells
16
Output Switch
Matrix
4
I/O Cells
8
Input Switch
Matrix
24
4
4
8
8
Block C
I/O16–I/O23
Input Switch
Matrix
33
33
16
16
Clock Generator
66 X 90
AND Logic Array
and Logic Allocator
16
Macrocells
16
Output Switch
Matrix
4
I/O Cells
8
Clock Generator
4
8
8
I/O Cells
8
Block B
I/O8–I/O15
Clock Generator
4
4
4
Block A
I/O0–I/O7
2
BLOCK DIAGRAM
I2, I5
Clock Generator
Clock Generator
CONNECTION DIAGRAM MACH445 (MACH435)
Top View
PQFP
BLOCK H
(62)
(61)
(60)
(59)
(58)
(57)
(56)
(55)
(54)
(41)
GND
GND
TD0
TRST*
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
GND
VCC
VCC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
ENABLE*
GND
GND
BLOCK G
(73)
(72)
(71)
(70)
(69)
(68)
(67)
(66)
(65)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
BLOCK F
(82)
(81)
(80)
(79)
(78)
(77)
(76)
(75)
92
91
90
89
88
87
86
85
84
83
82
81
(10) 100
(9) 99
(8) 98
(7) 97
(6) 96
(5) 95
(4) 94
(3) 93
1
2
3
4 (83)
5 (12)
6 (13)
7 (14)
8 (15)
9 (16)
10 (17)
11 (18)
12 (19)
13 (20)
14
15
16
17
18 (23)
19 (24)
20 (25)
21 (26)
22 (27)
23 (28)
24 (29)
25 (30)
26 (31)
27
28
29
30
31 (33)
32 (34)
33 (35)
34 (36)
35 (37)
36 (38)
37 (39)
38 (40)
39
40
41
42
43 (45)
44 (46)
45 (47)
46 (48)
47 (49)
48 (50)
49 (51)
50 (52)
GND
GND
TDI
I5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I0/CLK0
VCC
VCC
GND
GND
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
TMS
TCK
GND
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
VCC
GND
GND
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
BLOCK C
BLOCK B
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
GND
GND
VCC
I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
BLOCK A
BLOCK D
BLOCK E
17468E-2
PIN DESIGNATIONS
CLK/I
GND
I
I/O
VCC
=
=
=
=
=
Clock or Input
Ground
Input
Input/Output
Supply Voltage
MACH445-12/15/20
3
ORDERING INFORMATION
Commercial Products
Programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
MACH 445 -12
Y
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING
Blank = Shipped in Trays
DEVICE NUMBER
445
= 2nd Generation, 128 Macrocells, 100 Pins
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
PACKAGE TYPE
Y = 100-Pin Plastic Quad Flat Pack
(PQR100)
SPEED
-12 = 12 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
Valid Combinations
MACH445-12
MACH445-15
MACH445-20
4
C
YC
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device. Consult your local sales office to confirm availability of
specific valid combinations and to check on newly released combinations.
MACH445-12/15/20
FUNCTIONAL DESCRIPTION
The Clock Generator
The MACH445 consists of eight PAL blocks connected
by a central switch matrix. There are 64 I/O pins and 6
dedicated input pins feeding the central switch matrix.
These signals are distributed to the eight PAL blocks for
efficient design implementation. There are 4 global
clock pins that can also be used as dedicated inputs.
Each PAL block has a clock generator that can generate
four clock signals for use throughout the PAL block.
These four signals are available to all macrocells and
I/O cells in the PAL block, whether in synchronous or
asynchronous mode. The clock generator chooses the
four signals from the eight possible signals given by the
true and complement versions of the four global clock
pin signals.
All inputs and I/O pins have built-in pull-up resistors.
While it is always good design practice to tie unused
pins high, the pull-up resistors provide design security
and stability in the event that unused pins are left
disconnected.
The PAL Blocks
Each PAL block in the MACH445 (Figure 1) contains a
clock generator, a 90-product-term logic array, a logic
allocator, 16 macrocells, an output switch matrix, 8 I/O
cells, and an input switch matrix. The central switch
matrix feeds each PAL block with 33 inputs. This makes
the PAL block look effectively like an independent
“PAL33V16” with 8 to 16 buried macrocells.
In addition to the logic product terms, individual output
enable product terms and two PAL block initialization
product terms are provided. Each I/O pin can be
individually enabled. All flip-flops that are in the
synchronous mode within a PAL block are initialized
together by either of the PAL block nitialization
product terms.
The Central Switch Matrix and Input
Switch Matrix
The MACH445 central switch matrix is fed by the input
switch matrices in each PAL block. Each PAL block
provides 16 internal feedback signals, 8 registered input
signals, and 8 I/O pin signals to the input switch matrix.
Of these 32 signals, 24 decoded signals are provided to
the central switch matrix by the input switch matrix. The
central switch matrix distributes these signals back to
the PAL blocks in a very efficient manner that provides
for high performance. The design software automatically configures the input and central switch matrices
when fitting a design into the device.
The Product-Term Array
The MACH445 product-term array consists of 80
product terms for logic use, eight product terms for
output enable use, and two product terms for global PAL
block initialization. Each macrocell has a nominal
allocation of 5 product terms for logic, although the logic
allocator allows for logic redistribution. Each I/O pin has
its own individual output enable term. The initialization
product terms provide asynchronous reset or preset to
synchronous-mode macrocells in the PAL block.
The Logic Allocator
The logic allocator in the MACH445 takes the 80 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to 20
product terms in synchronous mode, or 18 product
terms in asynchronous mode. When product terms are
routed away from a macrocell, all 5 product terms may
be redirected, which precludes the use of the macrocell
for logic generation. It is possible to redirect only 4
product terms, leaving one for simple function generation. The design software automatically configures the
logic allocator when fitting the design into the device.
The logic allocator also provides an exclusive-OR gate.
This gate allows generation of combinatorial exclusiveOR logic, such as comparison or addition. It allows
registered exclusive-OR functions, such as CRC generation, to be implemented more efficiently. Emulating
all flip-flop types with a D-type flip-flop is also made
possible. Register type emulation is automatically
handled by the design software.
Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
MACH445-12/15/20
5
Table 9. Logic Allocation
Macrocell
Available Clusters
M0
C0, C1, C2
M1
C0, C1, C2, C3
M2
C1, C2, C3, C4
M3
C2, C3, C4, C5
M4
C3, C4, C5, C6
M5
C4, C5, C6, C7
M6
C5, C6, C7, C8
M7
C6, C7, C8, C9
M8
C7, C8, C9, C10
M9
C8, C9, C10, C11
M10
C9, C10, C11, C12
M11
C10, C11, C12, C13
M12
C11, C12, C13, C14
M13
C12, C13, C14, C15
M14
C13, C14, C15
M15
C14, C15
The flip-flop clock depends on the mode selected for
the macrocell. In synchronous mode, any of the PAL
block clocks generated by the Clock Generator can be
used. In asynchronous mode, the additional choice of
either edge of an individual product-term clock is
available.
The Macrocell and Output Switch Matrix
The MACH445 has 16 macrocells, half of which can
drive I/O pins; this selection is made by the output switch
matrix. Each macrocell can drive one of four I/O cells.
The allowed combinations are shown in Table 2. Please
refer to Figure 1 for macrocell and I/O pin
numbers.
Table 2. Output Switch Matrix Combinations
Macrocell
M0, M1
M2, M3
M4, M5
M6, M7
M8, M9
M10, M11
M12, M13
M14, M15
I/O Pin
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
6
The macrocells can be configured as registered,
latched, or combinatorial. In combination with the logic
allocator, the registered configuration can be any of the
standard flip-flop types. The macrocell provides internal
feedback whether configured with or without the flipflop, and whether or not the macrocell drives an I/O cell.
Routable to I/O Pins
I/O5, I/O6, I/O7, I/O0
I/O6, I/O7, I/O0, I/O1
I/O7, I/O0, I/O1, I/O2
I/O0, I/O1, I/O2, I/O3
I/O1, I/O2, I/O3, I/O4
I/O2, I/O3, I/O4, I/O5
I/O3, I/O4, I/O5, I/O6
I/O4, I/O5, I/O6, I/O7
Initialization can be handled as part of a bank of
macrocells via the PAL block initialization terms if in
synchronous mode, or individually if in asynchronous
mode. In synchronous mode, one of the PAL block
product terms is available each for preset and reset. The
swap function determines which product term drives
which function. This allows initialization polarity compatibility with the MACH 1 and 2 series. In asynchronous
mode, one product term can be used either to drive reset
or preset.
The I/O Cell
The I/O cell in the MACH445 consists of a three-state
buffer and an input flip-flop. The I/O cell is driven by one
of the macrocells, as selected by the output switch
matrix. Each I/O cell can take its input from one of eight
macrocells. The three-state buffer is controlled by an
individual product term. The input flip-flop can be
configured as a register or latch. Both the direct I/O
signal and the registered/latched signal are available to
the input switch matrix, and can be used simultaneously
if desired.
JTAG Testing
JTAG is the commonly used acronym for the IEEE
Standard 1149.1–1990. The JTAG standard defines
input and output pins, logic control functions, and
instructions. Lattice/Vantis has incorporated this standard into the MACH445 device.
Available Macrocells
M0, M1, M2, M3, M4, M5, M6, M7
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M14, M15, M0, M1, M2, M3, M4, M5
The JTAG standard was developed as a means of
providing both board-level and device-level testing.
MACH445-12/15/20
Five-Volt Programming
Zero-Hold-Time Input Register
Another benefit from the JTAG circuitry that we have
derived is the ability to use the JTAG port for five-volt
programming. This allows the device to be soldered to
the board before programming. Once the device is
attached, the delicate Plastic Quad Flat Pack, or PQFP,
leads are protected from programming and testing
operations that could potentially damage them. Programming and verification of the device is done serially
which is ideal for on-board programming since it only
requires the use of the Test Access Port. Use of the
programming Enable Pin (ENABLE*) is optional.
The MACH445 device has a zero-hold time (ZHT) fuse.
This fuse controls the time delay associated with loading
data into all I/O cell registers and latches in the
MACH445 device.
When programmed, the ZHT fuse increases the data
path setup delays to input storage elements, matching
equivalent delays in the clock path. When the fuse is
erased, the setup time to the input storage element is
minimized and the device timing is compatible with the
MACH435 device.
This feature facilitates doing worst-case designs for
which data is loaded from sources which have low (or
zero) minimum output propagation delays from clock
edges.
MACH445-12/15/20
7
CLK2/I3
CLK3/I4
CLK0/I0
CLK1/I1
16
Clock
Generator
M0
Macrocell
M0
C1
M1
Macrocell
M1
C2
M2
Macrocell
M2
C3
M3
Macrocell
M3
C4
M4
Macrocell
M4
C5
M5
Macrocell
M5
C6
M6
Macrocell
M6
M7
Macrocell
M7
M8
Macrocell
M8
C9
M9
Macrocell
M9
C10
M10
Macrocell
M10
C11
M11
Macrocell
C12
M12
Macrocell
M12
C13
M13
Macrocell
M13
C14
M14
Macrocell
M14
C15
M15
Macrocell
M15
C7
C8
Output Switch Matrix
C0
Logic Allocator
Central Switch Matrix
4
O0
I/O
Cell
I/O0
O1
I/O
Cell
I/O1
O2
I/O
Cell
I/O2
O3
I/O
Cell
I/O3
O4
I/O
Cell
I/O4
O5
I/O
Cell
I/O5
O6
I/O
Cell
I/O6
O7
I/O
Cell
I/O7
M11
17
16
24
Input
Switch
Matrix
16
17468E-3
Figure 1. MACH445 PAL Block
8
MACH445-12/15/20
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC +0.5 V
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . –0.5 V to VCC +0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to +70°C) . . . . . . . . . . . . . . . . . . . . 200 mA
Commercial (C) Devices
Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage (VCC) with
Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min
VIN = VIH or VIL
2.4
VOL
Output LOW Voltage
IOL = 24 mA, VCC = Min
VIN = VIH or VIL (Note 1)
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 2)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 2)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.25 V, VCC = Max (Note 3)
10
µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 3)
–100
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 3)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 3)
–100
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 4)
–160
mA
ICC
Supply Current
VIN = 0 V, Outputs Open (IOUT = 0 mA)
VCC = 5.0 V, f =25 MHz, TA = 25°C (Note 5)
V
0.5
V
2.0
V
–30
255
mA
CAPACITANCE (Note 6)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Unit
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT = 2.0 V
VCC = 5.0 V, TA = 25°C,
6
pF
f = 1 MHz
8
pF
Notes:
1.
2.
3.
4.
Total IOL for one PAL block should not exceed 128 mA.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded,
enabled, and reset.
6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
MACH445-12 (Com’l)
9
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
Parameter
Symbol
-12
Parameter Description
tPD
Input, I/O, or Feedback to
Combinatorial Output
tSA
Setup Time from Input, I/O, or
Feedback to Product Term Clock
Max
Unit
3
12
ns
D-type
5
ns
T-type
6
ns
ns
tHA
Register Data Hold Time Using Product Term Clock
5
tCOA
Product Term Clock to Output
4
tWLA
tWHA
fMAXA
Product Term, Clock Width
Maximum
Frequency
Using Product
Term Clock
(Note 2)
External Feedback
Internal Feedback (f CNTA)
tSS
Setup Time from Input, I/O, or Feedback
to Global Clock
8
ns
8
ns
D-type
52.6
MHz
T-type
50.0
MHz
D-type
58.8
MHz
T-type
55.6
MHz
62.5
MHz
D-type
7
ns
T-type
8
ns
tHS
Register Data Hold Time Using Global Clock
0
Global Clock to Output
2
Global Clock Width
tWHS
fMAXS
Maximum
Frequency
Using Global
Clock (Note 2)
External Feedback
Internal Feedback (f CNTS)
No Feedback (Note 3)
ns
HIGH
tCOS
tWLS
14
LOW
No Feedback (Note 3)
10
Min
ns
8
ns
LOW
6
ns
HIGH
6
ns
D-type
66.7
MHz
T-type
62.5
MHz
D-type
83.3
MHz
T-type
76.9
MHz
83.3
MHz
tSLA
Setup Time from Input, I/O, or Feedback to
Product Term Clock
5
ns
tHLA
Latch Data Hold Time Using Product Term Clock
5
ns
tGOA
Product Term Gate to Output
tGWA
Product Term Gate Width LOW (for LOW transparent)
or HIGH (for HIGH transparent)
6
ns
tSLS
Setup Time from Input, I/O, or Feedback to Global Gate
8
ns
tHLS
Latch Data Hold Time Using Global Gate
0
ns
tGOS
Gate to Output
tGWS
Global Gate Width LOW (for LOW transparent)
or HIGH (for HIGH transparent)
tICO
Input Register Clock to Combinatorial Output
16
10
MACH445-12 (Com’l)
6
ns
ns
ns
18
ns
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
(continued)
Parameter
Symbol
tICS
-12
Parameter Description
Min
Input Register Clock to Output Register Setup
tWICL
tWICH
fMAXIR
Input Register Clock Width
Maximum Input Register Frequency
1/(t WICL + t WICH )
Max
Unit
D-type
9
ns
T-type
10
ns
LOW
6
ns
HIGH
6
ns
83.3
MHz
tIGO
Input Latch Gate to Combinatorial Output
16
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
18
ns
tIGSA
Input Latch Gate to Output Latch Setup Using
Product Term Output Latch Gate
4
ns
tIGSS
Input Latch Gate to Output Latch Setup Using Global
Output Latch Gate
9
ns
tWIGL
Input Latch Gate Width LOW
6
ns
tAR
Asynchronous Reset to Registered or Latched Output
16
ns
tARW
Asynchronous Reset Width (Note 2)
12
ns
tARR
Asynchronous Reset Recovery Time (Note 2)
10
ns
tAP
Asynchronous Preset to Registered or Latched Output
16
ns
tAPW
Asynchronous Preset Width (Note 2)
tAPR
Asynchronous Preset Recovery Time (Note 2)
tEA
Input, I/O, or Feedback to Output Enable
2
12
ns
tER
Input, I/O, or Feedback to Output Disable
2
12
ns
14
ns
12
ns
8
ns
Input Register with Standard-Hold-Time Option
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input Latch
tSIR
Input Register Setup Time
2
ns
tHIR
Input Register Hold Time
3
ns
tSIL
Input Latch Setup Time
2
ns
tHIL
Input Latch Hold Time
3
ns
tSLLA
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Product Term Output Gate
4
ns
tSLLS
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Gate
9
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
MACH445-12 (Com’l)
16
ns
11
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
(continued)
Parameter
Symbol
-12
Parameter Description
Min
Max
Unit
20
ns
Input Register with Zero-Hold-Time Option
tPDL ❙
Input, I/O, or Feedback to Output Through
Transparent Input Latch
tSIR❙
Input Register Setup Time
❙
6
ns
Input Register Hold Time
0
ns
Input Latch Setup Time
6
ns
Input Latch Hold Time
0
ns
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Product Term Output Gate
16
ns
tSLLS ❙
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Gate
18
ns
tPDLL ❙
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
tHIR
tSIL❙
tHIL❙
tSLLA
❙
22
Notes:
1. See Switching Test Circuit at the end of this Data Book for test conditions.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
12
MACH445-12 (Com’l)
ns
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC) with
Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . –0.5 V to VCC +0.5 V
DC Output or
I/O Pin Voltage . . . . . . . . . . . . –0.5 V to VCC +0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to +70°C) . . . . . . . . . . . . . . . . . . . . 200 mA
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min
VIN = VIH or VIL
2.4
VOL
Output LOW Voltage
IOL = 24 mA, VCC = Min
VIN = VIH or VIL (Note 1)
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 2)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 2)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.25 V, VCC = Max (Note 3)
10
µA
IIL
–100
µA
10
µA
–100
µA
–160
mA
V
0.5
2.0
V
V
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 3)
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 3)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 3)
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 4)
–30
ICC
Supply Current
VIN = 0 V, Outputs Open
(IOUT = 0 mA), VCC = 5.0 V,
f =25 MHz TA = 25°C (Note 5)
255
mA
CAPACITANCE (Note 6)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Unit
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT = 2.0 V
VCC = 5.0 V, TA = 25°C,
6
pF
f = 1 MHz
8
pF
Notes:
1.
2.
3.
4.
Total IOL for one PAL block should not exceed 128 mA.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded,
enabled, and reset. An actual ICC value can be calculated by using the “Typical Dynamic ICC Characteristics” Chart towards the
end of this data sheet.
6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
MACH445-15/20 (Com’l)
13
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
-15
Parameter
Symbol Parameter Description
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 2)
tSA
Setup Time from Input, I/O, or
Feedback to Product Term Clock
tHA
Register Data Hold Time Using Product Term Clock
tCOA
Product Term Clock to Output (Note 2)
tWLA
Min
Max
Min
Max
Unit
3
15
3
20
ns
D-type
8
10
ns
T-type
9
11
ns
8
10
ns
4
Product Term, Clock Width
tWHA
-20
18
4
22
ns
LOW
9
12
ns
HIGH
9
12
ns
D-type
38.5
31.2
MHz
T-type
37
30.3
MHz
D-type
47.6
37
MHz
T-type
45.4
35.7
MHz
55.6
41.7
MHz
D-type
10
13
ns
T-type
11
14
ns
0
ns
External Feedback 1/(t SA + t COA )
fMAXA
tSS
Maximum
Frequency
Using Product
Term Clock
(Note 3)
Internal Feedback (f CNTA)
No Feedback
(Note 4)
1/(t WLA + t WHA )
Setup Time from Input, I/O, or Feedback
to Global Clock
tHS
Register Data Hold Time Using Global Clock
0
tCOS
Global Clock to Output (Note 2)
2
tWLS
10
2
12
ns
LOW
6
8
ns
HIGH
6
8
ns
D-type
50
40
MHz
T-type
47.6
38.5
MHz
D-type
66.6
50
MHz
T-type
62.5
47.6
MHz
83.3
62.5
MHz
Global Clock Width
tWHS
External Feedback 1/(t
fMAXS
Maximum
Frequency
Using Global
Clock (Note 3)
Internal Feedback (f CNTS)
No Feedback
(Note 4)
14
SS + t COS )
1/(t WLS + t WHS )
tSLA
Setup Time from Input, I/O, or Feedback to
Product Term Clock
8
10
ns
tHLA
Latch Data Hold Time Using Product Term Clock
8
10
ns
tGOA
Product Term Gate to Output (Note 2)
tGWA
Product Term Gate Width LOW (for LOW transparent)
or HIGH (for HIGH transparent)
9
12
ns
tSLS
Setup Time from Input, I/O, or Feedback to Global Gate
10
13
ns
tHLS
Latch Data Hold Time Using Global Gate
0
0
ns
tGOS
Gate to Output (Note 2)
tGWS
Global Gate Width LOW (for LOW transparent)
or HIGH (for HIGH transparent)
tICO
Input Register Clock to Combinatorial Output
19
22
11
MACH445-15/20 (Com’l)
6
12
8
20
ns
ns
ns
25
ns
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
(continued)
-15
Parameter
Symbol Parameter Description
tICS
Min
Input Register Clock to Output Register Setup
tWICL
-20
Max
Min
Max
Unit
D-type
15
20
ns
T-type
16
21
ns
LOW
6
8
ns
HIGH
6
8
ns
83.3
62.5
MHz
Input Register Clock Width
tWICH
fMAXIR
Maximum Input Register Frequency
1/(t WICL + t WICH )
tIGO
Input Latch Gate to Combinatorial Output
20
25
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
22
27
ns
tIGSA
Input Latch Gate to Output Latch Setup Using
Product Term Output Latch Gate
14
19
ns
tIGSS
Input Latch Gate to Output Latch Setup Using Global
Output Latch Gate
16
21
ns
tWIGL
Input Latch Gate Width LOW
6
8
ns
tAR
Asynchronous Reset to Registered or Latched Output
20
25
ns
tARW
Asynchronous Reset Width (Note 3)
15
20
ns
tARR
Asynchronous Reset Recovery Time (Note 3)
15
20
ns
tAP
Asynchronous Preset to Registered or Latched Output
20
25
ns
tAPW
Asynchronous Preset Width (Note 3)
15
tAPR
Asynchronous Preset Recovery Time (Note 3)
15
tEA
Input, I/O, or Feedback to Output Enable (Note 2)
2
15
2
20
ns
tER
Input, I/O, or Feedback to Output
2
15
2
20
ns
22
ns
Disable (Note 2)
20
ns
20
ns
Input Register with Standard-Hold-Time Option
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input Latch
tSIR
Input Register Setup Time
2
2
ns
tHIR
Input Register Hold Time
4
5
ns
tSIL
Input Latch Setup Time
2
2
ns
tHIL
17
Input Latch Hold Time
4
5
ns
tSLLA
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Product Term Output Gate
10
12
ns
tSLLS
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Gate
12
16
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
MACH445-15/20 (Com’l)
19
24
ns
15
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
(continued)
-15
Parameter
Symbol Parameter Description
Min
-20
Max
Min
Max
Unit
30
ns
Input Register with Zero-Hold-Time Option
tPDL ❙
Input, I/O, or Feedback to Output Through
Transparent Input Latch
tSIR❙
23
Input Register Setup Time
6
8
ns
❙
Input Register Hold Time
0
0
ns
❙
Input Latch Setup Time
6
8
ns
Input Latch Hold Time
0
0
ns
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Product Term Output Gate
16
20
ns
tSLLS ❙
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Gate
18
24
ns
tPDLL ❙
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
tHIR
tSIL
tHIL
❙
tSLLA
❙
25
32
Notes:
1. See Switching Test Circuit at the end of this Data Book for test conditions.
2. Parameters measured with 32 outputs switching.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
16
MACH445-15/20 (Com’l)
ns
TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS
VCC = 5.0 V, TA = 25°C
IOL (mA)
80
60
40
20
VOL (V)
–1.0 –0.8 –0.6 –0.4 –0.2
–20
.2
.4
.6
.8
1.0
–40
–60
–80
17468E-4
Output, LOW
IOH (mA)
25
1
2
3
4
5
VOH (V)
–3
–2
–1
–25
–50
–75
–100
–125
–150
17468E-5
Output, HIGH
II (mA)
20
VI (V)
–2
–1
–20
1
2
3
4
5
–40
–60
–80
–100
Input
MACH445-12/15/20
17468E-6
17
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25°C
325
MACH445
300
275
250
225
200
175
ICC (mA)
150
125
100
75
50
25
0
0
10
20
30
40
50
60
70
Frequency (MHz)
17468E-7
The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is
capable of being loaded, enabled, and reset.
Maximum frequency shown uses internal feedback and a D-type register.
18
MACH445-12/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol
Typ
Parameter Description
PQFP
Unit
θjc
Thermal impedance, junction to case
5
°C/W
θja
Thermal impedance, junction to ambient
38
°C/W
200 lfpm air
32
°C/W
400 lfpm air
28
°C/W
600 lfpm air
26
°C/W
800 lfpm air
24
°C/W
θjma
Thermal impedance, junction to
ambient with air flow
Plastic θjc Considerations
The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
MACH445-12/15/20
19
SWITCHING WAVEFORMS
Input, I/O, or
Feedback
VT
tPD
Combinatorial
Output
VT
17468E-8
Combinatorial Output
Input, I/O,
or Feedback
Input, I/O, or
Feedback
VT
tS
VT
tH
tSL
Gate
VT
Clock
tHL
tCO
Registered
Output
VT
tPDL
tGO
Latched
Out
VT
VT
17468E-10
17468E-9
Registered Output
Latched Output (MACH 2, 3, and 4)
tWH
Clock
Gate
VT
tGWS
tWL
17468E-12
17468E-11
Clock Width
Gate Width (MACH 2, 3, and 4)
Registered
Input
VT
tSIR
Input
Register
Clock
Registered
Input
tHIR
Input
Register
Clock
VT
tICO
Combinatorial
Output
VT
17468E-13
Output
Register
Clock
Registered Input (MACH 2 and 4)
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
20
VT
MACH445-12/15/20
VT
tICS
VT
17468E-14
Input Register to Output Register Setup
(MACH 2 and 4)
SWITCHING WAVEFORMS
Latched
In
VT
tSIL
tHIL
Gate
VT
tIGO
Combinatorial
Output
VT
17468E-15
Latched Input (MACH 2 and 4)
tPDLL
Latched
In
VT
Latched
Out
Input
Latch Gate
VT
tIGOL
tSLL
tIGS
VT
Output
Latch Gate
17468E-16
Latched Input and Output
(MACH 2, 3, and 4)
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
MACH445-12/15/20
21
SWITCHING WAVEFORMS
tWICH
Clock
Input
Latch
Gate
VT
VT
tWICL
tWIGL
17468E-18
17468E-17
Input Register Clock Width
(MACH 2 and 4)
Input Latch Gate Width
(MACH 2 and 4)
tARW
tAPW
Input, I/O, or
Feedback
Input, I/O,
or Feedback
VT
VT
tAR
Registered
Output
tAP
Registered
Output
VT
VT
tARR
Clock
tAPR
Clock
VT
VT
17468E-19
17468E-20
Asynchronous Reset
Asynchronous Preset
Input, I/O, or
Feedback
VT
tER
Outputs
tEA
VOH - 0.5V
VOL + 0.5V
VT
17468E-21
Output Disable/Enable
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
22
MACH445-12/15/20
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1
Output
Test Point
R2
CL
17468E-22
Commercial
Specification
tPD, tCO
tEA
tER
S1
CL
R1
R2
Closed
Measured
Output Value
1.5 V
Z → H: Open
Z → L: Closed
35 pF
H → Z: Open
L → Z: Closed
5 pF
1.5 V
300 Ω
390 Ω
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
*Switching several outputs simultaneously should be avoided for accurate measurement.
MACH445-12/15/20
23
fMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, fMAX is specified for
three types of synchronous designs.
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external
feedback or in conjunction with an equivalent speed device. This fMAX is designated “fMAX external.”
The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is
designated “fMAX internal”. A simple internal counter is a
good example of this type of design; therefore, this parameter is sometimes called “fCNT.”
The third type of design is a simple data path application. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (tS + tH). However,
a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum
clock period determines the period for the third fMAX, designated “fMAX no feedback.”
For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no
feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the
sum of the setup and hold times (tSIR + tHIR) or the sum of
the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified
as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will
be limited by tICS.
All frequencies except fMAX internal are calculated from
other measured AC parameters. fMAX internal is measured directly.
CLK
CLK
(SECOND
CHIP)
LOGIC
LOGIC
REGISTER
tS
t CO
tS
fMAX Internal (fCNT)
fMAX External; 1/(tS + tCO)
LOGIC
REGISTER
CLK
CLK
REGISTER
REGISTER
tS
tSIR
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
LOGIC
tHIR
fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
17468E-23
24
MACH445-12/15/20
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using our
advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in
bipolar parts. As a result, the device can be erased and
reprogrammed, a feature which allows 100% testing at
the factory.
Endurance Characteristics
Parameter
Symbol
tDR
N
Parameter Description
Min
Units
Test Conditions
10
Years
Max Storage
Temperature
Min Pattern Data Retention Time
20
Years
Max Operating
Temperature
Max Reprogramming Cycles
100
Cycles
Normal Programming
Conditions
MACH445-12/15/20
25
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
100 kΩ
1 kΩ
VCC
ESD
Protection
Input
VCC
VCC
100 kΩ
1 kΩ
Preload
Circuitry
Feedback
Input
17468E-24
I/O
26
MACH445-12/15/20
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state
will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the
Parameter
Symbol
wide range of ways VCC can rise to its steady state, two
conditions are required to insure a valid power-up reset.
These conditions are:
1. The VCC rise must be monotonic.
2. Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Descriptions
Max
Unit
tPR
Power-Up Reset Time
10
µs
tS
Input or Feedback Setup Time
tWL
Clock Width LOW
See
Switching
Characteristics
VCC
Power
4V
tPR
Registered
Output
tS
Clock
tWL
17468E-25
Power-Up Reset Waveform
MACH445-12/15/20
27
USING PRELOAD AND OBSERVABILITY
In order to be testable, a circuit must be both controllable
and observable. To achieve this, the MACH devices
incorporate register preload and observability.
Preloaded
HIGH
D
In preload mode, each flip-flop in the MACH device can
be loaded from the I/O pins, in order to perform
functional testing of complex state machines. Register
preload makes it possible to run a series of tests from a
known starting state, or to load illegal states and test for
proper recovery. This ability to control the MACH
device’s internal state can shorten test sequences,
since it is easier to reach the state of interest.
Q1
Q
AR
Preloaded
HIGH
The observability function makes it possible to see the
internal state of the buried registers during test by
overriding each register’s output enable and activating
the output buffer. The values stored in output and buried
registers can then be observed on the I/O pins. Without
this feature, a thorough functional test would be
impossible for any designs with buried registers.
D Q2
Q
AR
While the implementation of the testability features is
fairly straightforward, care must be taken in certain
instances to insure valid testing.
One case involves asynchronous reset and preset. If the
MACH registers drive asynchronous reset or preset
lines and are preloaded in such a way that reset or
preset are asserted, the reset or preset may remove the
preloaded data. This is illustrated in Figure 2. Care
should be taken when planning functional tests, so that
states that will cause unexpected resets and presets are
not preloaded.
Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into
registered mode. When this happens, all product terms
are forced to zero, which eliminates all combinatorial
data. For a straight combinatorial output, the correct
value will be restored after the preload or observe
function, and there will be no problem. If the function
implements a combinatorial latch, however, it relies on
feedback to hold the correct value, as shown in Figure 3.
As this value may change during the preload or observe
operation, you cannot count on the data being correct
after the operation. To insure valid testing in these
cases, outputs that are combinatorial latches should not
be tested immediately following a preload or observe
sequence, but should first be restored to a known state.
On
Preload
Mode
Off
Q1
AR
Q2
Figure 2. Preload/Reset Conflict
17468E-26
Set
All MACH 2 devices support both preload and
observability.
Contact individual programming vendors in order to
verify programmer support.
Reset
Figure 3. Combinatorial Latch
17468E-27
28
MACH445-12/15/20