Maxim MAX1238EEE 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial, 12-bit adc Datasheet

19-2333; Rev 2; 2/03
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
Applications
Features
♦ High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
♦ Single-Supply
2.7V to 3.6V (MAX1237/MAX1239)
4.5V to 5.5V (MAX1236/MAX1238)
♦ Internal Reference
2.048V (MAX1237/MAX1239)
4.096V (MAX1236/MAX1238)
♦ External Reference: 1V to VDD
♦ Internal Clock
♦ 4-Channel Single-Ended or 2-Channel Fully
Differential (MAX1236/MAX1237)
♦ 12-Channel Single-Ended or 6-Channel Fully
Differential (MAX1238/MAX1239)
♦ Internal FIFO with Channel-Scan Mode
♦ Low Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down Mode
♦ Software-Configurable Unipolar/Bipolar
♦ Small Packages
8-Pin µMAX (MAX1236/MAX1237)
16-Pin QSOP (MAX1238/MAX1239)
Hand-Held Portable Applications
Ordering Information
Medical Instruments
Battery-Powered Test Equipment
PART
Solar-Powered Remote Systems
TEMP
RANGE
PINI2C SLAVE INL
PACKAGE ADDRESS (LSB)
Received-Signal-Strength Indicators
MAX1236EUA
-40°C to +85°C
8 µMAX
0110100
±1
System Supervision
MAX1236KEUA* -40°C to +85°C
8 µMAX
0110000
±1
MAX1236LEUA* -40°C to +85°C
8 µMAX
0110010
±1
Selector Guide
PART
MAX1236EUA
INPUT
CHANNELS
4
MAX1236MEUA* -40°C to +85°C
8 µMAX
0110110
±1
-40°C to +85°C
8 µMAX
0110100
±1
MAX1237KEUA* -40°C to +85°C
8 µMAX
0110000
±1
MAX1237LEUA* -40°C to +85°C
8 µMAX
0110010
±1
4.5 to 5.5
MAX1237MEUA* -40°C to +85°C
8 µMAX
0110110
±1
*Future product—contact factory for availability.
INTERNAL
SUPPLY
REFERENCE
VOLTAGE (V)
(V)
4.096
MAX1237EUA
4
2.048
2.7 to 3.6
MAX1238EEE
12
4.096
4.5 to 5.5
MAX1239EEE
12
2.048
2.7 to 3.6
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
MAX1237EUA
Ordering Information continued at end of data sheet.
Pin Configurations appear at end of data sheet.
Typical Operating Circuit appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1236–MAX1239
General Description
The MAX1236–MAX1239 low-power, 12-bit, multichannel analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an
I2C-compatible 2-wire serial interface. These devices
operate from a single supply of 2.7V to 3.6V (MAX1237/
MAX1239) or 4.5V to 5.5V (MAX1236/MAX1238) and
require only 670µA at the maximum sampling rate of
94.4ksps. Supply current falls below 230µA for sampling rates under 46ksps. AutoShutdown™ powers
down the devices between conversions, reducing supply current to less than 1µA at low throughput rates.
The MAX1236/MAX1237 have four analog input channels each, while the MAX1238/MAX1239 have 12 analog input channels each. The fully differential analog
inputs are software configurable for unipolar or bipolar,
and single-ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to V DD . The MAX1237/
MAX1239 feature a 2.048V internal reference and the
MAX1236/MAX1238 feature a 4.096V internal reference.
The MAX1236/MAX1237 are available in an 8-pin µMAX
package. The MAX1238/MAX1239 are available in a 16pin QSOP package. The MAX1236–MAX1239 are guaranteed over the extended temperature range
(-40°C to +85°C). For pin-compatible 10-bit parts, refer to
the MAX1136–MAX1139 data sheet. For pin-compatible
8-bit parts, refer to the MAX1036–MAX1039 data sheet.
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
AIN0–AIN11,
REF to GND ............-0.3V to the lower of (VDD + 0.3V) and 6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current Into Any Pin .........................................±50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin µMAX (derate 4.5mW/°C above +70°C) .............362mW
16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX1237/MAX1239), VDD = 4.5V to 5.5V (MAX1236/MAX1238), VREF = 2.048V (MAX1237/MAX1239), VREF =
4.096V (MAX1236/MAX1238), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±1
LSB
DC ACCURACY (Note 1)
Resolution
12
Relative Accuracy
INL
(Note 2)
Differential Nonlinearity
DNL
No missing codes over temperature
Bits
Offset Error
Offset-Error Temperature
Coefficient
Relative to FSR
Gain Error
(Note 3)
Gain-Temperature Coefficient
Relative to FSR
±1
LSB
±4
LSB
0.3
ppm/°C
±4
LSB
0.3
ppm/°C
Channel-to-Channel Offset
Matching
±0.1
LSB
Channel-to-Channel Gain
Matching
±0.1
LSB
70
dB
-78
dB
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps)
Signal-to-Noise Plus Distortion
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Up to the 5th harmonic
78
dB
Full-Power Bandwidth
SINAD > 68dB
3
MHz
Full-Linear Bandwidth
-3dB point
5
MHz
CONVERSION RATE
Conversion Time (Note 4)
2
tCONV
Internal clock
External clock
7.5
10.6
_______________________________________________________________________________________
µs
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
(VDD = 2.7V to 3.6V (MAX1237/MAX1239), VDD = 4.5V to 5.5V (MAX1236/MAX1238), VREF = 2.048V (MAX1237/MAX1239), VREF =
4.096V (MAX1236/MAX1238), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
Throughput Rate
SYMBOL
fSAMPLE
CONDITIONS
MIN
51
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX1238/MAX1239)
51
External clock
MAX
ksps
800
Internal Clock Frequency
ns
2.8
tAD
UNITS
94.4
Track/Hold Acquisition Time
Aperture Delay (Note 5)
TYP
Internal clock, SCAN[1:0] = 01
External clock, fast mode
60
External clock, high-speed mode
30
MHz
ns
ANALOG INPUT (AIN0–AIN11)
Input-Voltage Range, SingleEnded and Differential (Note 6)
Input Multiplexer Leakage Current
Input Capacitance
Unipolar
0
VREF
Bipolar
0
±VREF/2
±0.01
ON/OFF leakage current, VAIN_ = 0 or VDD
CIN
±1
22
V
µA
pF
INTERNAL REFERENCE (Note 7)
Reference Voltage
VREF
Reference-Voltage Temperature
Coefficient
TA = +25°C
MAX1237/MAX1239
1.968
2.048
2.128
MAX1236/MAX1238
3.936
4.096
4.256
TCVREF
25
REF Short-Circuit Current
ppm/°C
2
REF Source Impedance
V
1.5
mA
kΩ
EXTERNAL REFERENCE
REF Input-Voltage Range
VREF
(Note 8)
REF Input Current
IREF
fSAMPLE = 94.4ksps
1
VDD
V
40
µA
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Input-High Voltage
VIH
Input-Low Voltage
VIL
Input Hysteresis
0.7 ✕ VDD
0.1 ✕ VDD
VHYST
Input Current
IIN
Input Capacitance
CIN
Output Low Voltage
VOL
V
0.3 ✕ VDD
V
±10
VIN = 0 to VDD
15
ISINK = 3mA
V
µA
pF
0.4
V
_______________________________________________________________________________________
3
MAX1236–MAX1239
ELECTRICAL CHARACTERISTICS (continued)
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1237/MAX1239), VDD = 4.5V to 5.5V (MAX1236/MAX1238), VREF = 2.048V (MAX1237/MAX1239), VREF =
4.096V (MAX1236/MAX1238), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Supply Voltage
Supply Current
Power-Supply Rejection Ratio
VDD
IDD
PSRR
MAX1237/MAX1239
2.7
3.6
MAX1236/MAX1238
4.5
5.5
fSAMPLE = 94.4ksps
external clock
Internal reference
900
1150
External reference
670
900
fSAMPLE = 40ksps
internal clock
Internal reference
530
External reference
230
fSAMPLE = 10ksps
internal clock
Internal reference
380
External reference
60
fSAMPLE =1ksps
internal clock
Internal reference
330
External reference
6
V
µA
Shutdown (internal REF off)
0.5
10
Full-scale input (Note 9)
±0.5
±0.2
LSB/V
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.7V to 3.6V (MAX1237/MAX1239), VDD = 4.5V to 5.5V (MAX1236/MAX1238), VREF = 2.048V (MAX1237/MAX1239), VREF =
4.096V (MAX1236/MAX1238), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency
fSCL
Bus Free Time Between a STOP (P)
and a START (S) Condition
tBUF
1.3
µs
Hold Time for START (S) Condition
tHD, STA
0.6
µs
Low Period of the SCL Clock
tLOW
1.3
µs
High Period of the SCL Clock
tHIGH
0.6
µs
Setup Time for a Repeated START
Condition (Sr)
tSU, STA
0.6
µs
Data Hold Time (Note 10)
tHD, DAT
0
Data Setup Time
tSU, DAT
100
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
900
ns
ns
tR
Measured from 0.3VDD - 0.7VDD
20 + 0.1CB
300
tF
Measured from 0.3VDD - 0.7VDD
20 + 0.1CB
300
ns
Setup Time for STOP (P) Condition
tSU, STO
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
50
ns
4
0.6
ns
_______________________________________________________________________________________
µs
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
(VDD = 2.7V to 3.6V (MAX1237/MAX1239), VDD = 4.5V to 5.5V (MAX1236/MAX1238), VREF = 2.048V (MAX1237/MAX1239), VREF =
4.096V (MAX1236/MAX1238), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.7
MHz
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 11)
Serial Clock Frequency
Hold Time, Repeated START
Condition (Sr)
fSCLH
(Note 12)
tHD, STA
160
ns
Low Period of the SCL Clock
tLOW
320
ns
High Period of the SCL Clock
tHIGH
120
ns
Setup Time for a Repeated START
Condition (Sr)
tSU, STA
160
ns
Data Hold Time
tHD, DAT
Data Setup Time
(Note 10)
0
150
ns
tSU, DAT
10
Rise Time of SCL Signal
(Current Source Enabled)
tRCL
20
80
ns
Rise Time of SCL Signal after
Acknowledge Bit
tRCL1
Measured from 0.3VDD - 0.7VDD
20
160
ns
Fall Time of SCL Signal
tFCL
Measured from 0.3VDD - 0.7VDD
20
80
ns
Rise Time of SDA Signal
tRDA
Measured from 0.3VDD - 0.7VDD
20
160
ns
Fall Time of SDA Signal
tFDA
Measured from 0.3VDD - 0.7VDD
20
160
ns
400
pF
10
ns
Setup Time for STOP (P) Condition
tSU, STO
Capacitive Load for Each Bus Line
CB
Pulse Width of Spike Suppressed
tSP
ns
160
(Notes 10 and 12)
0
ns
Note 1: For DC accuracy, the MAX1136/MAX1138 are tested at VDD = 5V and the MAX1137/MAX1139 are tested at VDD = 3V. All
devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a
0.01µF capacitor.
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVP-P.
Note 9: Measured as for the MAX1237/MAX1239

2N − 1
[VFS (3.6V) − VFS (2.7V)] ×

VREF 

(3.6V − 2.7V)
_______________________________________________________________________________________
5
MAX1236–MAX1239
TIMING CHARACTERISTICS (Figure 1) (continued)
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.7V to 3.6V (MAX1237/MAX1239), VDD = 4.5V to 5.5V (MAX1236/MAX1238), VREF = 2.048V (MAX1237/MAX1239), VREF =
4.096V (MAX1236/MAX1238), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C, see Tables 1–5 for programming notation.)
and for the MAX1236/MAX1238 where N is the number of bits and VREF.

2N − 1
[VFS (5.5V) − VFS (4.5V)] ×

VREF 

(5.5V − 4.5V)
Note 10: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 11: CB = total capacitance of one bus line in pF.
Note 12: fSCL must meet the minimum clock low time plus the rise/fall times.
Typical Operating Characteristics
(VDD = 3.3V (MAX1237/MAX1239), VDD = 5V (MAX1236/MAX1238), fSCL = 1.7MHz, (50% duty cycle), fSAMPLE = 94.4ksps, singleended, unipolar, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
0.8
0.4
0.1
0.2
0
0.1
0
-0.2
-0.2
-0.4
-0.3
-0.6
-0.4
-0.8
-0.5
500 1000 1500 2000 2500 3000 3500 4000
SDA = SCL = VDD
0.5
0.4
IDD (µA)
INTERNAL REFERENCE MAX1239/MAX1237
0.3
500
450
EXTERNAL REFERENCE MAX1238/MAX1236
0.2
400
350
5
20
35
50
TEMPERATURE (°C)
65
40k
50k
0.50
0.45
0.40
MAX1238
0.35
0.30
0.25
0.20
MAX1239
0.15
0.05
0
0
-40 -25 -10
30k
0.10
0.1
EXTERNAL REFERENCE MAX1239/MAX1237
300
6
0.6
SUPPLY CURRENT (µA)
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
20k
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1236 toc05
INTERNAL REFERENCE MAX1238/MAX1236
600
550
10k
FREQUENCY (Hz)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1236 toc04
800
650
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL OUTPUT CODE
SUPPLY CURRENT vs. TEMPERATURE
(MAX1238/MAX1239)
700
-140
-180
0
DIGITAL OUTPUT CODE
750
-120
-160
-1.0
0
-100
MAX1236 toc06
0.2
fSAMPLE = 94.4ksps
fIN = 10kHz
-80
AMPLITUDE (dBc)
0.6
INL (LSB)
DNL (LSB)
0.3
-60
MAX1236 toc02
0.4
FFT PLOT
1.0
MAX1236 toc01
0.5
MAX1236 toc03
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
SUPPLY CURRENT (µA)
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
80
2.7
3.2
3.7
4.2
4.7
INPUT VOLTAGE (V)
5.2
-40 -25 -10
5
20
35
50
TEMPERATURE (°C)
_______________________________________________________________________________________
65
80
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
B
1.0000
1.00002
1.00000
0.99998
0.9998
0.99996
MAX1239
0.9994
0.99994
0.9992
0.99992
-40 -25 -10
10 20 30 40 50 60 70 80 90 100
MAX1237/MAX1239
NORMALIZED TO
REFERENCE VALUE AT
VDD = 3.3V
0.99990
0.9990
5
20
35
50
65
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
80
VDD (V)
TEMPERATURE (°C)
CONVERSION RATE (ksps)
OFFSET ERROR vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
-0.1
1.6
1.2
OFFSET ERROR (LSB)
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
MAX1236 toc11
2.0
MAX1236 toc10
0
OFFSET ERROR (LSB)
1.00006
1.00004
1.0002
0.9996
0.8
0.4
0
-0.4
-0.8
-0.8
-1.2
-0.9
-1.6
-1.0
-2.0
-40 -25 -10
5
20
35
50
65
80
2.7
3.2
3.7
TEMPERATURE (°C)
4.2
4.7
5.2 5.5
VDD (V)
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
2.0
1.8
1.6
1.6
1.2
GAIN ERROR (LSB)
1.4
1.2
1.0
0.8
MAX1236 toc13
2.0
MAX1236 toc12
0
MAX1236/MAX1238
NORMALIZED TO
REFERENCE VALUE AT
VDD = 5V
1.00008
MAX1238
1.0004
MAX1236 toc09
1.0006
MAX1238
1.00010
MAX1236 toc08
NORMALIZED TO VALUE AT +25°C
1.0008
VREF (V)
A
1.0010
VREF NORMALIZED
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1236 toc07
800
750
700
650
600
550
500
450
400
350
300
250
200
GAIN ERROR (LSB)
AVERAGE IDD (µA)
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (EXTERNAL CLOCK)
0.8
0.4
0
-0.4
0.6
-0.8
0.4
-1.2
0.2
-1.6
-2.0
0
-40 -25
-10
5
20
35
50
TEMPERATURE (°C)
65
80
2.7
3.2
3.7
4.2
4.7
5.2 5.5
VDD (V)
_______________________________________________________________________________________
7
MAX1236–MAX1239
Typical Operating Characteristics (continued)
(VDD = 3.3V (MAX1237/MAX1239), VDD = 5V (MAX1236/MAX1238), fSCL = 1.7MHz, (50% duty cycle), fSAMPLE = 94.4ksps, singleended, unipolar, TA = +25°C, unless otherwise noted.)
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
MAX1236–MAX1239
Pin Description
PIN
MAX1236
MAX1237
MAX1238
MAX1239
NAME
DESCRIPTION
1, 2, 3
1, 2, 3
AIN0–AIN2
—
4–8
AIN3–AIN7
—
16, 15, 14
AIN8–AIN10
4
—
AIN3/REF
Analog Input 3/Reference Input or Output. Selected in the setup
register (see Tables 1 and 6).
—
13
AIN11/REF
Analog Input 11/Reference Input or Output. Selected in the setup
register (see Tables 1 and 6).
5
9
SCL
6
10
SDA
Data Input/Output
7
11
GND
Ground
8
12
VDD
Positive Supply. Bypass to GND with a 0.1µF capacitor.
Analog Inputs
Clock Input
A. F/S-MODE 2-WIRE SERIAL INTERFACE TIMING
tR
tF
t
SDA
tSU.DAT
tHD.DAT
tLOW
tHD.STA
tBUF
tSU.STA
tSU.STO
SCL
tHD.STA
tHIGH
tR
tF
S
A
Sr
P
S
B. HS-MODE 2-WIRE SERIAL INTERFACE TIMING
tRDA
tFDA
SDA
tSU.DAT
tHD.DAT
tLOW
tBUF
tHD.STA
tSU.STO
tSU.STA
SCL
tHD.STA
tHIGH
tRCL
tFCL
tRCL1
S
Sr
A
P
HS-MODE
Figure 1. 2-Wire Serial Interface Timing
8
_______________________________________________________________________________________
S
F/S-MODE
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
MAX1236–MAX1239
SDA
SCL
INPUT SHIFT REGISTER
VDD
CONTROL
LOGIC
SETUP REGISTER
GND
INTERNAL
OSCILLATOR
CONFIGURATION REGISTER
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11/REF
T/H
ANALOG
INPUT
MUX
12-BIT
ADC
OUTPUT SHIFT
REGISTER
AND RAM
REF
REFERENCE
4.096V (MAX1238)
2.048V (MAX1239)
MAX1238
MAX1239
Figure 2. MAX1238/MAX1239 Simplified Functional Diagram
Figure 2 shows the simplified internal structure for the
MAX1238/MAX1239.
VDD
IOL
Power Supply
VOUT
SDA
400pF
IOH
Figure 3. Load Circuit
Detailed Description
The MAX1236–MAX1239 analog-to-digital converters
(ADCs) use successive-approximation conversion techniques and fully differential input track/hold (T/H) circuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX1236/MAX1237 are
4-channel ADCs, and the MAX1238/MAX1239 are 12channel ADCs. These devices feature a high-speed, 2wire serial interface supporting data rates up to 1.7MHz.
The MAX1236–MAX1239 operates from a single supply
and consumes 670µA (typ) at sampling rates up to
94.4ksps. The MAX1237/MAX1239 feature a 2.048V
internal reference and the MAX1236/MAX1238 feature
a 4.096V internal reference. All devices can be configured for use with an external reference from 1V to VDD.
Analog Input and Track/Hold
The MAX1236–MAX1239 analog-input architecture contains an analog-input multiplexer (mux), a fully differential track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog input multiplexer connects C T/H between the analog input selected by
CS[3:0] (see the Configuration Setup Bytes section) and
GND (Table 3). In differential mode, the analog-input
multiplexer connects CT/H to the “+” and “-” analog
inputs selected by CS[3:0] (Table 4).
During the acquisition interval, the T/H switches are in
the track position and CT/H charges to the analog input
_______________________________________________________________________________________
9
clock pulse during the shifting out of the first byte of the
result. The conversion is performed during the next 12
clock cycles.
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on CT/H as a stable sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of a 12-bit resolution. This action
requires 12 conversion clock cycles and is equivalent
to transferring a charge of 11pF ✕ (VIN+ - VIN-) from
CT/H to the binary weighted capacitive DAC, forming a
digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source impedances,
connect a 100pF capacitor from the analog input to GND.
This input capacitor forms an RC filter with the source
impedance limiting the analog-input bandwidth. For larger source impedances, use a buffer amplifier to maintain
analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte, see the Slave Address section. The
T/H circuitry enters hold mode on the falling clock edge of
the acknowledge bit of the address byte (the ninth clock
pulse). A conversion, or series of conversions, are then
internally clocked and the MAX1236–MAX1239 holds
SCL low. With external clock mode, the T/H circuitry
enters track mode after a valid address on the rising
edge of the clock during the read (R/W = 1) bit. Hold
mode is then entered on the rising edge of the second
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capacitance. If the analog-input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the minimum time needed for the signal
to be acquired. It is calculated by:
tACQ ≥ 9 ✕ (RSOURCE + RIN) ✕ CIN
where RSOURCE is the analog-input source impedance,
RIN = 2.5kΩ, and CIN = 22pF. tACQ is 1.5/fSCL for internal
clock mode and tACQ = 2 / fSCL for external clock mode.
Analog Input Bandwidth
The MAX1236–MAX1239 feature input-tracking circuitry
with a 5MHz small-signal bandwidth. The 5MHz input
bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using
under sampling techniques. To avoid high-frequency
signals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
Analog Input Range and Protection
Internal protection diodes clamp the analog input to
VDD and GND. These diodes allow the analog inputs to
HOLD
ANALOG INPUT MUX
REF
CT/H
AIN0
AIN1
HOLD
AIN3/REF
TRACK
VDD/2
HOLD
AIN2
CAPACITIVE
DAC
TRACK
HOLD
TRACK
TRACK
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
CAPACITIVE
DAC
TRACK
GND
CT/H
HOLD
REF
MAX1236
MAX1237
Figure 4. Equivalent Input Circuit
10
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the
MAX1236–MAX1239 analog-input circuitry for singleended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are the
difference between the analog input selected by CS[3:0]
and GND (Table 3). In differential mode (SGL/ DIF = 0),
the digital conversion results are the difference between
the “+” and the “-” analog inputs selected by CS[3:0]
(Table 4).
Unipolar/Bipolar
When operating in differential mode, the BIP/UNI bit of
the set-up byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to VREF. A negative differential analog
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±VREF/2. The digital output code is binary in unipolar mode and two’s complement in bipolar
mode, see the Transfer Functions section.
In single-ended mode, the MAX1236–MAX1239 always operates in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to VREF.
2-Wire Digital Interface
The MAX1236–MAX1239 feature a 2-wire interface consisting of a serial data line (SDA) and serial clock line
(SCL). SDA and SCL facilitate bidirectional communication between the MAX1236–MAX1239 and the master at
rates up to 1.7MHz. The MAX1236–MAX1239 are slaves
that transfer and receive data. The master (typically a
microcontroller) initiates data transfer on the bus and
generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Operating Circuit). Series resistors (RS) are optional. They
protect the input architecture of the MAX1236–MAX1239
from high voltage spikes on the bus lines and minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX1236–MAX1239.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condition (S), a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A repeated START condition (Sr) can be used
in place of a STOP condition to leave the bus active and
the interface mode unchanged (see HS mode).
Sr
S
P
SDA
SCL
Figure 5. START and STOP Conditions
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX1236–MAX1239 (slave) generate acknowledge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse
(Figure 6). To generate a not-acknowledge, the receiver allows SDA to be pulled high before the rising edge
of the acknowledge-related clock pulse and leaves
SDA high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt
communication at a later time.
S
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
SCL
1
2
8
9
Figure 6. Acknowledge Bits
______________________________________________________________________________________
11
MAX1236–MAX1239
swing from (GND - 0.3V) to (VDD + 0.3V) without causing damage to the device. For accurate conversions,
the inputs must not go more than 50mV below GND or
above VDD.
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition followed by a slave
address. When idle, the MAX1236–MAX1239 continuously wait for a START condition followed by their slave
address. When the MAX1236–MAX1239 recognize their
slave address, they are ready to accept or send data.
Please refer to the table in the ordering information section for the factory programmed slave address of the
selected device. The least significant bit (LSB) of the
address byte (R/W) determines whether the master is
writing to or reading from the MAX1236–MAX1239
(R/W = 0 selects a write condition, R/W = 1 selects a
read condition). After receiving the address, the
MAX1236–MAX1239 (slave) issues an acknowledge by
pulling SDA low for one clock cycle.
0
1
HS-Mode
At power-up, the MAX1236–MAX1239 bus timing is set
for F/S-mode. The bus master selects HS-mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After successfully receiving the HS-mode master code, the MAX1236–
MAX1239 issue a not-acknowledge, allowing SDA to be
pulled high for one clock cycle (Figure 8). After the notacknowledge, the MAX1236–MAX1239 are in HS-mode.
The bus master must then send a repeated START followed by a slave address to initiate HS-mode communication. If the master generates a STOP condition, the
MAX1236–MAX1239 return to F/S-mode.
SLAVE ADDRESS
MAX1236/MAX1237
S
Bus Timing
At power-up, the MAX1236–MAX1239 bus timing is set
for fast-mode (F/S-mode), which allows conversion rates
up to 22.2ksps. The MAX1236–MAX1239 must operate
in high-speed mode (HS-mode) to achieve conversion
rates up to 94.4ksps. Figure 1 shows the bus timing for
the MAX1236–MAX1239’s 2-wire interface.
1
0
1
0
0
R/W
A
SDA
1
SCL
2
3
4
5
6
7
8
9
SEE ORDERING INFORMATION FOR SLAVE ADDRESS OPTIONS AND DETAILS.
Figure 7. MAX1236/MAX1237 Slave Address Byte
HS-MODE MASTER CODE
S
0
0
0
0
1
X
X
X
A
Sr
SDA
SCL
F/S-MODE
HS-MODE
Figure 8. F/S-Mode to HS-Mode Transfer
12
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
configuration byte (Table 3). The master can write either
one or two bytes to the slave in any order (setup byte,
then configuration byte; configuration byte, then setup
byte; setup byte or configuration byte only; Figure 9). If
the slave receives a byte successfully, it issues an
acknowledge. The master ends the write cycle by issuing a STOP condition or a repeated START condition.
When operating in HS-mode, a STOP condition returns
the bus into F/S-mode (see the HS-Mode section).
MASTER TO SLAVE
SLAVE TO MASTER
A. ONE-BYTE WRITE CYCLE
1
S
7
1 1
SLAVE ADDRESS
8
1
1
NUMBER OF BITS
SETUP OR
W A
A P or Sr
CONFIGURATION BYTE
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
B. TWO-BYTE WRITE CYCLE
1
S
7
1 1
SLAVE ADDRESS
8
SETUP OR
W A
CONFIGURATION BYTE
1
A
8
1
1
NUMBER OF BITS
SETUP OR
A P or Sr
CONFIGURATION BYTE
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
Figure 9. Write Cycle
Table 1. Setup Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
REG
SEL2
SEL1
SEL0
CLK
BIP/UNI
RST
X
BIT
NAME
7
REG
6
SEL2
5
SEL1
4
SEL0
3
CLK
2
BIP/UNI
1
RST
0
X
DESCRIPTION
Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).
Three bits select the reference voltage and the state of AIN_/REF (Table 6). Default to 000 at
power-up.
1 = external clock, 0 = internal clock. Default to 0 at power-up.
1 = bipolar, 0 = unipolar. Default to 0 at power-up (see the Unipolar/Bipolar section).
1= no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t care, can be set to 1 or 0.
______________________________________________________________________________________
13
MAX1236–MAX1239
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by seven address bits (Figure
7) and a write bit (R/W = 0). If the address byte is successfully received, the MAX1236–MAX1239 (slave)
issues an acknowledge. The master then writes to the
slave. The slave recognizes the received byte as the
set-up byte (Table 1) if the most significant bit (MSB) is
1. If the MSB is 0, the slave recognizes that byte as the
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
Table 2. Configuration Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
REG
SCAN1
SCAN0
CS3
CS2
CS1
CS0
SGL/DIF
BIT
NAME
7
REG
6
SCAN1
5
SCAN0
4
CS3
3
CS2
2
CS1
1
CS0
0
SGL/DIF
DESCRIPTION
Register bit 1 = setup byte (see Table 1), 0 = configuration byte.
Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at power-up.
Channel select bits. Four bits select which analog input channels are to be used for conversion
(Tables 3 and 4). Default to 0000 at power-up. For MAX1236/MAX1237, CS3 and CS2 are
internally set to 0.
1 = single-ended, 0 = differential (Tables 3 and 4). Default to 1 at power-up. See the SingleEnded/Differential Input section.
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
CS31
CS21
CS1
CS0
AIN0
0
0
0
0
+
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
AIN1
AIN2
AIN32
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9 AIN10 AIN112 GND
-
+
+
+
+
+
+
+
+
+
+
+
1
0
1
1
1
1
0
0
RESERVED
1
1
0
1
RESERVED
1
1
1
0
RESERVED
1
1
1
1
RESERVED
1. For MAX1236/MAX1237, CS3 and CS2 are internally set to 0.
2. When SEL1 = 1, a single-ended read of AIN3/REF (MAX1236/MAX1237) or AIN11/REF (MAX1238/MAX1239) is ignored; scan
stops at AIN2 or AIN10.
14
______________________________________________________________________________________
-
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
CS31
CS21
CS1
CS0
AIN0
0
0
0
0
+
-
0
0
0
1
-
+
0
0
1
0
+
-
0
0
1
1
-
+
0
1
0
0
+
-
0
1
0
1
-
+
0
1
1
0
+
-
0
1
1
1
-
+
1
0
0
1
0
1
0
1
AIN1
AIN2
AIN32
AIN4
AIN5
AIN6
AIN7
AIN10 AIN112
AIN8
AIN9
0
+
-
0
1
-
+
1
0
+
-
0
1
1
-
+
1
1
0
0
RESERVED
1
1
0
1
RESERVED
1
1
1
0
RESERVED
1
1
1
1
RESERVED
1. For MAX1236/MAX1237, CS3 and CS2 are internally set to 0.
2. When SEL1 = 1, a differential read between AIN2 and AIN3/REF (MAX1236/MAX1237) or AIN10 and AIN11/REF
(MAX1238/MAX1239) returns the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of 1011
returns the negative difference between AIN10 and GND. In differential scanning, the address increments by 2 until limit set by
CS3:CS1 has been reached.
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
a START condition followed by seven address bits and
a read bit (R/W = 1). If the address byte is successfully
received, the MAX1236–MAX1239 (slave) issues an
acknowledge. The master then reads from the slave.
The result is transmitted in two bytes; first four bits of
the first byte are high, then MSB through LSB are consecutively clocked out. After the master has received
the byte(s), it can issue an acknowledge if it wants to
continue reading or a not-acknowledge if it no longer
wishes to read. If the MAX1236–MAX1239 receive a notacknowledge, they release SDA, allowing the master to
generate a STOP or a repeated START condition. See
the Clock Modes and Scan Mode sections for detailed
information on how data is obtained and converted.
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the setup byte’s CLK bit determines the clock mode (Table 1).
At power-up, the MAX1236–MAX1239 are defaulted to
internal clock mode (CLK = 0).
Internal Clock
When configured for internal clock mode (CLK = 0), the
MAX1236–MAX1239 use their internal oscillator as the conversion clock. In internal clock mode, the MAX1236–
MAX1239 begin tracking the analog input after a valid
address on the eighth rising edge of the clock. On the
falling edge of the ninth clock, the analog signal is
acquired and the conversion begins. While converting the
analog input signal, the MAX1236–MAX1239 holds SCL
low (clock stretching). After the conversion completes, the
results are stored in internal memory. If the scan mode is
set for multiple conversions, they all happen in succession
with each additional result stored in memory. The
MAX1236/MAX1237 contain four 12-bit blocks of memory,
and the MAX1238/ MAX1239 contain twelve 12-bit blocks
of memory. Once all conversions are complete, the
MAX1236–MAX1239 release SCL, allowing it to be pulled
high. The master can now clock the results out of the memory in the same order the scan conversion has been done
at a clock rate of up to 1.7MHz. SCL is stretched for a maximum of 0.3µs per channel (see Figure 10).
The device memory contains all of the conversion
results when the MAX1236–MAX1239 release SCL. The
converted results are read back in a first-in-first-out
______________________________________________________________________________________
15
MAX1236–MAX1239
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH INTERNAL CLOCK
1
7
1 1
S
SLAVE ADDRESS
R A
8
CLOCK STRETCH
1
8
A
RESULT 4 MSBs
1
NUMBER OF BITS
A P or Sr
RESULT 8 LSBs
tACQ
tCONV
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
7
1 1
S
SLAVE ADDRESS
R A
8
CLOCK STRETCH
tACQ1
CLOCK STRETCH
tACQ2
tCONV2
tCONV1
1
8
1
1
8
RESULT 1 ( 4MSBs) A RESULT 1 (8 LSBs) A
8
1
1
NUMBER OF BITS
RESULT N (4MSBs) A RESULT N (8LSBs) A P or Sr
tACQN
tCONVN
Figure 10. Internal Clock Mode Read Cycles
(FIFO) sequence. If AIN_/REF is set to be a reference
input or output (SEL1 = 1, Table 6), AIN_/REF is excluded from a multichannel scan. The memory contents can
be read continuously. If reading continues past the
result stored in memory, the pointer wraps around and
point to the first result. Note that only the current conversion results is read from memory. The device must
be addressed with a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal reducing the system noise during conversion. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
External Clock
When configured for external clock mode (CLK = 1),
the MAX1236–MAX1239 use the SCL as the conversion
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
7
1 1
8
1
8
1
1
S
SLAVE ADDRESS
R A
RESULT (4 MSBs)
A
RESULT (8 LSBs)
A
P OR Sr
NUMBER OF BITS
tACQ
tCONV
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
S
7
1 1
SLAVE ADDRESS
R A
8
RESULT 1 (4 MSBs)
8
1
8
1
RESULT 2 (8 LSBs)
A
RESULT N (4 MSBs)
A
tACQ2
tACQN
1
A
tACQ1
tCONV1
8
RESULT N (8 LSBs)
1
1
A P OR Sr
tCONVN
Figure 11. External Clock Mode Read Cycle
16
______________________________________________________________________________________
NUMBER OF BITS
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
SCAN1
SCAN0
SCANNING CONFIGURATION
0
0
Scans up from AIN0 to the input selected by CS3–CS0. When CS3–CS0 exceeds 11, the scanning stops
at AIN11. When AIN_/REF is set to be a REF in/out, scanning stops at AIN10 or AIN3.
0
1
*Converts the input selected by CS3–CS0 eight times (see Tables 3 and 4).
1
0
1
1
Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0–AIN2,
the scanning stops at AIN2 (MAX1236/MAX1237). When AIN/REF is set to be a REF IN/OUT, scanning
stops at AIN3 or AIN10.
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0-AIN6, scanning
stops at AIN6 (MAX1238/MAX1239). When AIN/REF is set to be a REF IN/OUT, scanning stops at AIN or
AIN10.
*Converts channel selected by CS3–CS0.
*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11 and converting occurs
perpetually until not-acknowledge occurs.
clock. In external clock mode, the MAX1236–MAX1239
begin tracking the analog input on the ninth rising clock
edge of a valid slave address byte. Two SCL clock
cycles later, the analog signal is acquired and the conversion begins. Unlike internal clock mode, converted
data is available immediately after the first four empty
high bits. The device continuously converts input channels dictated by the scan mode until given a not
acknowledge. There is no need to readdress the
device with a read command to obtain new conversion
results (see Figure 11).
The conversion must complete in 1ms, or droop on the
track-and-hold capacitor degrades conversion results.
Use internal clock mode if the SCL clock period
exceeds 60µs.
The MAX1236–MAX1239 must operate in external clock
mode for conversion rates from 40ksps to 94.4ksps.
Below 40ksps, internal clock mode is recommended
due to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. If AIN_/REF is set to be a reference
input or output (SEL1 = 1, Table 6), AIN_/REF is excluded from a multichannel scan. The scanned results are
written to memory in the same order as the conversion.
Read the results from memory in the order they were
converted. Each result needs a 2-byte transmission; the
first byte begins with four empty bits, during which SDA
is left high. Each byte has to be acknowledged by the
master or the memory transmission is terminated. It is
not possible to read the memory independently of conversion.
Applications Information
Power-On Reset
The configuration and setup registers (Tables 1 and 2)
default to a single-ended, unipolar, single-channel conversion on AIN0 using the internal clock with VDD as the
reference and AIN_/REF configured as an analog input.
The memory contents are unknown after power-up.
Automatic Shutdown
SEL[2:0] of the setup byte (Table 1 and Table 6) control
the state of the reference and AIN_/REF. If automatic
shutdown is selected (SEL[2:0] = 100), shutdown
occurs between conversions when the MAX1236–
MAX1239 are idle. When operating in external clock
mode, a STOP, not-acknowledge, or repeated START
condition must be issued to place the devices in idle
mode and benefit from automatic shutdown. A STOP
condition is not necessary in internal clock mode to
benefit from automatic shutdown because power-down
occurs once all contents are written to memory (Figure
10). All analog circuitry is inactive in shutdown and
supply current is less than 0.5µA. The digital conversion
results are maintained in memory during shutdown and
are available for access through the serial interface at
any time prior to a STOP or a repeated START condition.
When idle, the MAX1236–MAX1239 continuously wait
for a START condition followed by their slave address
(see the Slave Address section). Upon reading a valid
address byte, the MAX1236–MAX1239 power up. The
internal reference requires 10ms to wake up, so when
using the internal reference it should be powered up
10ms prior to conversion or powered continuously.
Wake-up is invisible when using an external reference
or VDD as the reference.
______________________________________________________________________________________
17
MAX1236–MAX1239
Table 5. Scanning Configuration
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
Table 6. Reference Voltage and AIN_/REF Format
SEL2
AIN_/REF
INTERNAL REFERENCE
STATE
VDD
Analog Input
Always Off
External Reference
Reference Input
Always Off
Internal Reference
Analog Input
Always Off
Internal Reference
Analog Input
Always On
0
Internal Reference
Reference Output
Always Off
1
Internal Reference
Reference Output
Always On
SEL1
SEL0
0
0
X
0
1
X
1
0
0
1
0
1
1
1
1
1
REFERENCE VOLTAGE
Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates and with internal
clock. For example, at a conversion rate of 10ksps, the
average supply current for the MAX1237 is 60µA (typ) and
drops to 6µA (typ) at 1ksps. At 0.1ksps the average supply current is just 1µA, or a minuscule 3µW of power consumption, see Average Supply Current vs. Conversion
Rate in the Typical Operating Characteristics section).
Reference Voltage
SEL[2:0] of the setup byte (Table 1) control the reference
and the AIN_/REF configuration (Table 6). When
AIN_/REF is configured to be a reference input or reference output (SEL1 = 1), differential conversions on
AIN_/REF appear as if AIN_/REF is connected to GND
(see Note 2 and Table 4). Single-ended conversion in
scan mode AIN_/REF is ignored by the internal limiter,
which sets the highest available channel at AIN2 or
AIN10.
Internal Reference
The internal reference is 4.096V for the MAX1236/
MAX1238 and 2.048V for the MAX1237/MAX1239. SEL1 of
the setup byte controls whether AIN_/REF is used for an
analog input or a reference (Table 6). When AIN_/REF is
configured to be an internal reference output (SEL[2:1] =
11), decouple AIN_/REF to GND with a 0.1µF capacitor.
Once powered up, the reference always remains on until
reconfigured. The reference should not be used to supply
current for external circuitry.
of bits (12). Code transitions occur halfway between
successive-integer LSB values. Figures 12 and 13
show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively.
Layout, Grounding, and Bypassing
Only use PC boards. Wire-wrap configurations are not
recommended since the layout should ensure proper
separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not
layout digital signal paths underneath the ADC package. Use separate analog and digital PC board ground
sections with only one star point (Figure 14) connecting
the two ground systems (analog and digital). For lowest
noise operation, ensure the ground return to the star
ground’s power supply is low impedance and as short
as possible. Route digital signals far away from sensitive analog and reference inputs.
OUTPUT CODE
111...111
111...110
FULL-SCALE
TRANSITION
FS = REF + GND
ZS = GND
100...010
100...001
1 LSB =
100...000
VREF
4096
011...111
External Reference
The external reference can range from 1V to VDD. For
maximum conversion accuracy, the reference must be
able to deliver up to 40µA and have an output impedance of 500kΩ or less. If the reference has a higher output impedance or is noisy, bypass it to GND as close to
AIN_/REF as possible with a 0.1µF capacitor.
Transfer Functions
Output data coding for the MAX1236–MAX1239 is binary in unipolar mode and two’s complement in bipolar
mode with 1 LSB = (VREF / 2N) where “N” is the number
18
011...110
011...101
000...001
000...000
0
GND
1
2048
INPUT VOLTAGE (LSB)
Figure 12. Unipolar Transfer Function
______________________________________________________________________________________
1
FS - 2 LSB
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
MAX1236–MAX1239
OUTPUT CODE
011...111
011...110
000...010
000...001
000...000
FS =
VREF
+ AIN2
SUPPLIES
ZS = AIN3V OR 5V
-VREF
+ AIN2
VREF
1 LSB =
4096
VLOGIC = 3V/5V
GND
-FS =
4.7µF
R* = 5Ω
111...111
111...110
0.1µF
111...101
VDD
GND
100...001
100...000
MAX1236–
MAX1239
-FS+1/2 LSB
VREF
AIN- ≥
2
3V/5V
DGND
DIGITAL
CIRCUITRY
AININPUT VOLTAGE (LSB)
+FS - 1 LSB
Figure 13. Bipolar Transfer Function
*OPTIONAL
Figure 14. Power-Supply Grounding Connection
High-frequency noise in the power supply (VDD) could
influence the proper operation of the ADC’s fast comparator. Bypass VDD to the star ground with a network of
two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX1236–MAX1239 power-supply pin. Minimize capacitor lead length for best supply
noise rejection, and add an attenuation resistor (5Ω) in
series with the power supply if it is extremely noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once offset
and gain errors have been nullified. The MAX1236–
MAX1239’s INL is measured using the endpoint.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time between the falling
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N Bits):
SNRMAX[dB] = 6.02dB ✕ N + 1.76dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals.
SignalRMS


SINAD(dB) = 20 × log 

 NoiseRMS + THDRMS 
______________________________________________________________________________________
19
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
Pin Configurations
TOP VIEW
AIN0 1
AIN1 2
ENOB = (SINAD - 1.76) / 6.02
AIN2
3
AIN3/REF 4
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fundamental itself. This is expressed as:
ANALOG
INPUTS
CREF
*RS
0.1µF
SDA
SCL
*RS
GND
5V
RP
5V
RP
µC
5
SCL
15 AIN9
14 AIN10
MAX1238
MAX1239
13 AIN11/REF
12 VDD
AIN5 6
11 GND
AIN6 7
10 SDA
AIN7 8
9
SCL
Ordering Information (continued)
TEMP
RANGE
PINI2C SLAVE INL
PACKAGE ADDRESS (LSB)
-40°C to +85°C 16 QSOP
0110101
±1
MAX1238KEEE* -40°C to +85°C 16 QSOP
0110001
±1
MAX1238LEEE* -40°C to +85°C 16 QSOP
0110011
±1
MAX1238MEEE* -40°C to +85°C 16 QSOP
0110111
±1
MAX1239EEE
-40°C to +85°C 16 QSOP
0110101
±1
MAX1239KEEE
-40°C to +85°C 16 QSOP
0110001
±1
MAX1239LEEE
-40°C to +85°C 16 QSOP
0110011
±1
MAX1239MEEE -40°C to +85°C 16 QSOP
0110111
±1
MAX1238EEE
MAX1236
MAX1237
MAX1238
AIN3**/REF MAX1239
SDA
QSOP
PART
AIN0
AIN1
6
AIN1 2
AIN4 5
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distortion component.
VDD
GND
16 AIN8
AIN3 4
Spurious-Free Dynamic Range
3.3V or 5V
7
AIN0 1
AIN2 3
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
0.1µF
VDD
µMAX
  2

V2 + V32 + V4 2 + V52  

THD = 20 × log 

 
V1
 

Typical Operating Circuit
MAX1236
MAX1237
8
*Future product—contact factory for availability.
SDA
SCL
Chip Information
MAX1236/MAX1237 TRANSISTORS COUNT: 11,362
*OPTIONAL
**AIN11/REF (MAX1238/MAX1239)
20
MAX1238/MAX1239 TRANSISTORS COUNT: 12,956
PROCESS: BiCMOS
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
8
INCHES
DIM
A
A1
A2
b
E
ÿ 0.50±0.1
H
c
D
e
E
H
0.6±0.1
L
1
1
α
0.6±0.1
S
BOTTOM VIEW
D
MIN
0.002
0.030
MAX
0.043
0.006
0.037
0.014
0.010
0.007
0.005
0.120
0.116
0.0256 BSC
0.120
0.116
0.198
0.188
0.026
0.016
6∞
0∞
0.0207 BSC
8LUMAXD.EPS
4X S
8
MILLIMETERS
MAX
MIN
0.05
0.75
1.10
0.15
0.95
0.25
0.36
0.13
0.18
2.95
3.05
0.65 BSC
2.95
3.05
4.78
5.03
0.41
0.66
0∞
6∞
0.5250 BSC
TOP VIEW
A1
A2
A
α
c
e
b
FRONT VIEW
L
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
21-0036
REV.
J
1
1
______________________________________________________________________________________
21
MAX1236–MAX1239
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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