TI1 MAX3077E Sn65hvd3x-ep 3.3-v full-duplex rs-485 drivers and receiver Datasheet

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SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
SN65HVD3x-EP 3.3-V Full-Duplex RS-485 Drivers And Receivers
1 Features
3 Description
•
The SN65HVD3x-EP devices are 3-state differential
line drivers and differential-input line receivers that
operate with 3-V power supply.
1
•
•
•
•
•
•
•
•
1/8 Unit-Load Option Available (up to 256 Nodes
on the Bus)
Bus-Pin ESD Protection Exceeds 15 kV HBM
Optional Driver Output Transition Times for
Signaling Rates (1) of 1 Mbps, 5 Mbps, and
25 Mbps
Low-Current Standby Mode: <1 μA
Glitch-Free Power-Up and Power-Down Protection
for Hot-Plugging Applications
5-V Tolerant Inputs
Bus Idle, Open, and Short-Circuit Fail Safe
Driver Current Limiting and Thermal Shutdown
Meet or Exceed the Requirements of ANSI
TIA/EIA-485-A and RS-422 Compatible
Each driver and receiver has separate input and
output pins for full-duplex bus communication
designs. They are designed for balanced
transmission lines and interoperation with ANSI
TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11, and ISO
8482:1993 standard-compliant devices.
The SN65HVD30, SN65HVD31, and SN65HVD32
are fully enabled with no external enabling pins.
The SN65HVD33, SN65HVD34, and SN65HVD35
have active-high driver enables and active-low
receiver enables. A low (less than 1 μA) standby
current can be achieved by disabling both the driver
and receiver.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
(1)
All devices are characterized for operation from
–55°C to 125°C.
Utility Meters
DTE and DCE Interfaces
Industrial, Process, and Building Automation
Point-of-Sale (POS) Terminals and Networks
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Military (–55°C/125°C) Temperature
Range
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Device Information(1)
PART NUMBER
SN65HVD3x-EP
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm x 3.91 mm
SOIC (14)
8.65 mm x 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
Typical Application Schematic
Y
R
D
Z
A
RT
RT
B
R
R
DE
RE
Master
RE
D
Slave
B
R
A
DE
Z
RT
RT
A
B
Z
Y
D
D
Y
R Slave
D
R RE DE D
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8
1
1
1
2
3
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics: Driver ............................... 7
Electrical Characteristics: Receiver .......................... 8
Switching Characteristics: Driver .............................. 9
Switching Characteristics: Receiver........................ 10
Receiver Equalization Characteristics .................... 10
Dissipation Ratings .............................................. 10
Typical Characteristics .......................................... 11
Parameter Measurement Information ................ 13
9
Detailed Description ............................................ 17
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
17
21
10 Application and Implementation........................ 23
10.1 Application Information.......................................... 23
10.2 Typical Application ............................................... 23
11 Power Supply Recommendations ..................... 27
12 Layout................................................................... 27
12.1 Layout Guidelines ................................................. 27
12.2 Layout Example .................................................... 27
13 Device and Documentation Support ................. 28
13.1
13.2
13.3
13.4
13.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
14 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2012) to Revision E
•
2
Page
Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
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SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
www.ti.com
SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
5 Device Comparison (1)
Table 1. Available Options
BASE
PART NUMBER
SN65HVD30MDREP
(1)
UNIT LOADS
RECEIVER
EQUALIZATION
ENABLES
SOIC MARKING
25 Mbps
1/2
No
No
HVD30EP
(1)
5 Mbps
1/8
No
No
PREVIEW
SN65HVD32MDREP (1)
1 Mbps
1/8
No
No
PREVIEW
SN65HVD33MDREP
25 Mbps
1/2
No
Yes
HVD33EP
SN65HVD34MDREP (1)
5 Mbps
1/8
No
Yes
PREVIEW
SN65HVD35MDREP (1)
1 Mbps
1/8
No
Yes
PREVIEW
SN65HVD31MDREP
(1)
SIGNALING
RATE
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Product Preview
Table 2. Improved Replacement Parts
Part Number
Replace With
xxx3491
xxx3490
SN65HVD33:
SN65HVD30:
Better ESD protection (15 kV vs 2 kV or not specified), higher signaling rate (25 Mbps vs 20 Mbps),
fractional unit load (64 nodes vs 32)
MAX3491E
MAX3490E
SN65HVD33:
SN65HVD30:
Higher signaling rate (25 Mbps vs 12 Mbps), fractional unit load (64 nodes vs 32)
MAX3076E
MAX3077E
SN65HVD33:
SN65HVD30:
Higher signaling rate (25 Mbps vs 16 Mbps), lower standby current (1 μA vs 10 μA)
MAX3073E
MAX3074E
SN65HVD34:
SN65HVD31:
Higher signaling rate (5 Mbps vs 500 kbps), lower standby current (1 μA vs 10 μA)
MAX3070E
MAX3071E
SN65HVD35:
SN65HVD32:
Higher signaling rate (1 Mbps vs 250 kbps), lower standby current (1 μA vs 10 μA)
Copyright © 2006–2015, Texas Instruments Incorporated
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SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
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6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
VCC
R
D
GND
1
8
2
7
3
6
4
5
D Package
14-Pin SOIC
Top View
NC
R
RE
DE
D
GND
GND
A
B
Z
Y
8
A
2
R
7
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
VCC
A
B
Z
Y
NC
B
NC - No internal connection
Pins 6 and 7 are connected together internally
Pins 13 and 14 are connected together internally
5
Y
3
D
6
Z
Pin Functions
PIN
D
(8-PIN)
D
(14-PIN)
TYPE
A
8
12
Bus input
Receiver input (complementary to B)
B
7
11
Bus input
Receiver input (complementary to A)
D
3
5
Digital input
Driver data input
DE
—
4
Digital input
Driver enable, active high
Reference
potential
Local device ground
No connect; must be left floating
NAME
DESCRIPTION
GND
4
6, 7
NC
—
1, 8
No connect
R
2
2
Digital output
Receive data output
RE
—
3
Digital output
Receiver enable, active low
VCC
1
13, 14
Supply
Y
5
9
Bus output
Driver output (complementary to Z)
Z
6
10
Bus output
Driver output (complementary to Y)
4
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3-V to 3.6-V supply
Copyright © 2006–2015, Texas Instruments Incorporated
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SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
UNIT
–0.3
6
V
Voltage range at any bus terminal (A, B, Y, Z)
–9
14
V
V(TRANS)
Voltage input, transient pulse through 100 Ω (see Figure 21) (A, B, Y, Z) (3)
–50
50
V
VI
Input voltage range (D, DE, RE)
–0.5
7
V
PD(cont)
Continuous total power dissipation
IO
Output current (receiver output only, R)
TJ
Junction temperature
Tstg
Storage temperature range
VCC
Supply voltage range
V(A), V(B),
V(Y), V(Z)
(1)
(2)
(3)
(4)
Internally limited (4)
–65
11
mA
165
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
This tests survivability only and the output state of the receiver is not specified.
The thermal shutdown protection circuit internally limits the continuous total power dissipation. Thermal shutdown typically occurs when
the junction temperature reaches 165°C.
7.2 ESD Ratings
MIN
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS- Bus pins and GND
001, all pins (1)
All pins
±16000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±1000
±4000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Supply voltage
VI or VIC
Voltage at any bus terminal (separately or common mode)
NOM
MAX
3
3.6
V
–7 (1)
12
V
'HVD30, 'HVD33
25
'HVD31, 'HVD34
5
1/tUI
Signaling rate
RL
Differential load resistance
VIH
High-level input voltage
D, DE, RE
VIL
Low-level input voltage
D, DE, RE
VID
Differential input voltage
'HVD32, 'HVD35
IOH
High-level output current
IOL
Low-level output current
TA
Ambient still-air temperature
(1)
(2)
UNIT
Mbps
1
54
Driver
Ω
60
2
VCC
V
0
0.8
V
–12
12
V
–60
Receiver
mA
–8
Driver
60
Receiver
8
125 (2)
–55
mA
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
7.4 Thermal Information
THERMAL METRIC (1)
D (SOIC)
D (SOIC)
8 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
135
92
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43
59
°C/W
RθJB
Junction-to-board thermal resistance
44
61
°C/W
ψJT
Junction-to-top characterization parameter
12.1
5.7
°C/W
ψJB
Junction-to-board characterization parameter
49.7
30.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
7.5 Electrical Characteristics: Driver
over recommended operating conditions (unless otherwise noted)
PARAMETER
VI(K)
Input clamp voltage
TEST CONDITIONS
II = –18 mA
MAX
–1.5
IO = 0
|VOD(SS)|
MIN TYP (1)
V
VCC +
0.1
2.3
Steady-state differential output voltage RL = 54 Ω, See Figure 10 (RS-485)
RL = 100 Ω, See Figure 10 (RS-422)
Vtest = –7 V to 12 V, See Figure 11
UNIT
1.5
2
2
2.3
V
1.5
Δ|VOD(SS)|
Change in magnitude of steady-state
differential output voltage between
states
RL = 54 Ω, See Figure 10 and Figure 11
VOD(RING)
Differential output voltage overshoot
and undershoot
RL = 54 Ω, CL = 50 pF, See Figure 14 and
Figure 12
VOC(PP)
Peak-to-peak
common-mode
output voltage
VOC(SS)
Steady-state common-mode output
voltage
See Figure 13
1.6
2.3
V
ΔVOC(SS)
Change in steady-state common-mode
See Figure 13
output voltage
–0.05
0.05
V
'HVD30, 'HVD33
'HVD31, 'HVD32,
'HVD34, 'HVD35
'HVD30, 'HVD31,
'HVD32
IZ(Z) or
IY(Z)
High-impedance
state output
current
'HVD33, 'HVD34,
'HVD35
IZ(S) or
IY(S)
Short-circuit output current
II
Input current
C(OD)
Differential output capacitance
(1)
(2)
–0.2
0.2
V
10% (2)
V
0.5
See Figure 13
V
0.25
VCC = 0 V, VZ or VY = 12 V,
Other input at 0 V
90
VCC = 0 V, VZ or VY = –7 V,
Other input at 0 V
VCC = 3 V or 0 V, DE = 0 V,
VZ or VY = 12 V
VCC = 3 V or 0 V, DE = 0 V,
VZ or VY = –7 V
VZ or VY = –7 V
VZ or VY = 12 V
–10
μA
Other input
at 0 V
90
–10
Other input
at 0 V
D, DE
±250
0
VOD = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
mA
100
16
μA
pF
All typical values at 25°C with 3.3-V supply
10% of the peak-to-peak differential output voltage swing, per TIA/EIA-485
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7.6 Electrical Characteristics: Receiver
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going differential input threshold
voltage
IO = –8 mA
VIT–
Negative-going
differential input
threshold voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ – VIT–)
VIK
Enable-input clamp voltage
MIN
'HVD30
'HVD33
IO(Z)
High-impedance-state output current
50
V
0.4
VO = 0 or VCC, RE at VCC
–1
Other
input
at 0 V
VA or VB = 12 V, VCC = 0 V
VA or VB = –7 V
Other
input
at 0 V
VA or VB = 12 V, VCC = 0 V
VA or VB = –7 V
VA or VB = –7 V, VCC = 0 V
IIH
Input current, RE
VIH = 0.8 V or 2 V
CID
Differential input capacitance
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
1
0.05
0.1
0.06
0.1
–0.10
–0.04
–0.10
–0.03
VA or VB = 12 V
'HVD30, 'HVD33
mV
2.4
VA or VB = –7 V, VCC = 0 V
Bus input current
V
–1.5
VA or VB = 12 V
IA or
IB
–0.02
V
VID = –200 mV, IO = 8 mA, See Figure 17
'HVD31, 'HVD32,
'HVD34, 'HVD35
UNIT
-0.2
VID = 200 mV, IO = –8 mA, See Figure 17
Output voltage
MAX
–0.15
II = –18 mA
VO
TYP (1)
0.20
0.35
0.24
0.4
–0.35
–0.18
–0.25
–0.13
V
μA
mA
μA
–60
15
pF
SUPPLY CURRENT
'HVD30
'HVD31, 'HVD32
'HVD33
ICC
Supply current
1.8
'HVD34, 'HVD35
'HVD33, 'HVD34,
'HVD35
RE at VCC, D at VCC, DE at 0 V,
No load (receiver disabled and driver disabled)
'HVD33
RE at 0 V, D at 0 V or VCC, DE at VCC,
No load (receiver enabled and driver enabled)
2.1
RE at VCC, D at 0 V or VCC, DE at VCC
No load (receiver disabled and driver enabled)
1.8
'HVD33
'HVD34, 'HVD35
8
6.4
RE at 0 V, D at 0 V or VCC, DE at 0 V,
No load (receiver enabled and driver disabled)
'HVD34, 'HVD35
(1)
2.1
D at 0 V or VCC and no load
mA
2.2
0.022
1.5
6.5
μA
mA
6.2
All typical values at 25°C with 3.3-V supply
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SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
7.7 Switching Characteristics: Driver
over recommended operating conditions (unless otherwise noted)
PARAMETER
Propagation delay time,
low- to high-level output
tPLH
Propagation delay time,
high- to low-level output
tPHL
TEST CONDITIONS
'HVD30, 'HVD33
4
10
'HVD31, 'HVD34
25
38
65
'HVD32, 'HVD35
120
175
305
'HVD30, 'HVD33
4
9
23
25
38
65
'HVD32, 'HVD35
120
175
305
2.5
5
18
tr
Differential output signal
fall time
tf
tsk(p)
tPZH1
Pulse skew (|tPHL – tPLH|)
Propagation delay time, highimpedance to high-level output
'HVD31, 'HVD34
20
37
60
'HVD32, 'HVD35
120
185
300
'HVD30, 'HVD33
2.5
5
18
'HVD31, 'HVD34
20
35
60
'HVD32, 'HVD35
120
180
300
'HVD30, 'HVD33
0.6
'HVD31, 'HVD34
2.0
'HVD32, 'HVD35
5.1
45
'HVD34
235
'HVD33
Propagation delay time, highlevel to high-impedance output
'HVD34
RL = 110 Ω, RE at 0 V,
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z,
See Figure 15
Propagation delay time, highimpedance to low-level output
65
35
190
'HVD34
RL = 110 Ω, RE at 0 V,
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y,
See Figure 16
tPZL2
(1)
ns
ns
ns
490
30
120
'HVD35
tPZH2
ns
165
'HVD34
'HVD33
Propagation delay time, lowlevel to high-impedance output
tPLZ
ns
25
'HVD33
'HVD35
ns
490
'HVD35
tPZL1
ns
ns
'HVD33
'HVD35
tPHZ
RL = 54 Ω, CL = 50 pF,
See Figure 14
UNIT
23
'HVD31, 'HVD34
'HVD30, 'HVD33
Differential output signal
rise time
MIN TYP (1) MAX
ns
290
'HVD30
Propagation delay time, standby
to high-level output
'HVD33
RL = 110 Ω, RE at 3 V,
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z,
See Figure 15
4000
'HVD30
Propagation delay time, standby
to low-level output
'HVD33
RL = 110 Ω, RE at 3 V,
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y,
See Figure 16
4000
5000
5000
ns
ns
All typical values at 25°C with 3.3-V supply
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7.8 Switching Characteristics: Receiver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tPLH
Propagation delay time,
low- to high-level output
tPLH
Propagation delay time,
high- to low-level output
TEST CONDITIONS
TYP
MAX
'HVD30, 'HVD33
26
60
'HVD31, 'HVD32, 'HVD34,
'HVD35
47
70
'HVD30, 'HVD33
29
60
'HVD31, 'HVD32, 'HVD34,
'HVD35
49
70
VID = –1.5 V to 1.5 V,
CL = 15 pF, See Figure 18
'HVD30, 'HVD33
tsk(p)
Pulse skew (|tPHL – tPLH|) 'HVD31, 'HVD34, 'HVD32,
'HVD35
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Output disable time from high level
tPZH1
Output enable time to high level
tPZH2
Propagation delay time,
standby to high-level
output
tPLZ
Output disable time from low level
tPZL1
Output enable time to low level
tPZL2
Propagation delay time,
standby to low-level
output
MIN
'HVD30
10
'HVD33
18
DE at 3 V
CL = 15 pF,
See Figure 19
CL = 15 pF,
See Figure 20
DE at 0 V
ns
ns
12.5
ns
20
ns
20
ns
5000
DE at 3 V
'HVD30
ns
4000
DE at 0 V
'HVD33
ns
12
10
'HVD30
UNIT
'HVD33
ns
20
ns
20
ns
4000
ns
5000
ns
MAX
UNIT
7.9 Receiver Equalization Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
25 Mbps
tj(pp)
Peak-to-peak
eye-pattern jitter
Pseudo-random NRZ code
with a bit pattern length of
216 – 1, Belden 3105A cable
10 Mbps
5 Mbps
3 Mbps
1 Mbps
(1)
(2)
TYP (1)
MIN
100 m
'HVD33
(2)
PREVIEW
150 m
'HVD33 (2)
PREVIEW
200 m
'HVD33 (2)
PREVIEW
200 m
'HVD33
(2)
PREVIEW
250 m
'HVD33 (2)
PREVIEW
300 m
'HVD33 (2)
PREVIEW
500 m
'HVD34 (2)
PREVIEW
'HVD33 (2)
PREVIEW
'HVD34 (2)
PREVIEW
(2)
PREVIEW
500 m
1000 m
'HVD34
ns
All typical values are at VCC = 5 V and temperature = 25°C.
The SN65HVD33-EP and the SN65HVD34-EP do not have receiver equalization, but are specified for comparison.
7.10 Dissipation Ratings
PARAM
ETER
DEVICE
TEST CONDITIONS
MIN MAX UNIT
'HVD30 (25 Mbps)
'HVD31 (5 Mbps)
PD
197
RL = 60 Ω, CL = 50 pF,
Input to D a 50% duty cycle square wave at indicated signaling rate, TA = 85°C
'HVD32 (1 Mbps)
197
RL = 60 Ω, CL = 50 pF, DE at VCC, RE at 0 V,
Input to D a 50% duty cycle square wave at indicated signaling rate, TA = 85°C
'HVD35 (1 Mbps)
10
mW
193
'HVD33 (25 Mbps)
'HVD34 (5 Mbps)
213
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mW
248
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7.11 Typical Characteristics
60
55
TA = 25°C RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
55
ICC - RMS Supply Current - mA
50
ICC - RMS Supply Current - mA
TA = 25°C RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
45
VCC = 3.3 V
40
35
50
VCC = 3.3 V
45
40
35
30
30
0
5
10
15
20
0
25
1
2
Figure 1. 'HVD30, 'HVD33 RMS Supply Current Signaling
Rate
4
5
Figure 2. 'HVD31, 'HVD34 RMS Supply Current Signaling
Rate
250
60
TA = 25°C RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
55
TA = 25°C
RE = 0 V
DE = 0 V
200
150
II - Bus Input Current - mA
ICC - RMS Supply Current - mA
3
Signaling Rate - Mbps
Signaling Rate - Mbps
50
VCC = 3.3 V
45
40
100
50
VCC = 3.3 V
0
–50
–100
35
–150
–200
–7
30
0
0.2
0.4
0.6
0.8
1
–4
–1
Signaling Rate - Mbps
Figure 3. 'HVD32, 'HVD35 RMS Supply Current Signaling
Rate
5
8
11
14
Figure 4. Bus Input Current vs Input Voltage
0.14
60
IOL - Driver Low-Level Output Current - A
TA = 25°C
RE = 0 V
DE = 0 V
40
II - Bus Input Current - uA
2
VI - Bus Input Voltage - V
20
0
VCC = 3.3 V
-20
-40
VCC = 3.3 V
DE = VCC
D=0V
0.12
0.1
0.08
0.06
0.04
0.02
0
–0.02
-60
-7
-4
-1
2
5
8
11
14
VI - Bus Input Voltage - V
Figure 5. 'HVD31, 'HVD32, 'HVD34, 'HVD35 Bus Input
Current vs Input Voltage
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0
0.5
1
1.5
2
2.5
3
3.5
VOL - Low-Level Output Voltage - V
Figure 6. Driver Low-Level Output Current vs Low-Level
Output Voltage
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Typical Characteristics (continued)
2.2
VCC = 3.3 V
DE = VCC
D=0V
–0.01
VOD - Driver Differential Output Voltage - V
IOH - Driver High-Level Output Current - A
0.01
–0.03
–0.05
–0.07
–0.09
–0.11
–0.13
VCC = 3.3 V
DE = VCC
D = VCC
2.1
2.0
1.9
1.8
0
0.5
1
1.5
2
2.5
3
–40
3.5
–15
10
35
60
85
VOH - High-Level Output Voltage - V
TA - Free-Air Temperature - °C
Figure 7. Driver High-Level Output Current vs High-Level
Output Voltage
Figure 8. Driver Differential Output Voltage vs Free-Air
Temperature
40
TA = 25°C
RL = 54 W
D = VCC
DE = VCC
IO - Driver Output Current - mA
35
30
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
VCC Supply Voltage - V
Figure 9. Driver Output Current vs Supply Voltage
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8 Parameter Measurement Information
VCC
DE
II
Y
IY
VOD
0 or 3 V
Z
RL
IZ
VI
VZ
VY
Figure 10. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
VCC
DE
D
Y
VOD
0 or 3 V
60 Ω ±1%
+
_ −7 V < V(test) < 12 V
Z
375 Ω ±1%
Figure 11. Driver VOD With Common-Mode Loading Test Circuit
VOD(SS)
VOD(RING)
0 V Differential
VOD(RING)
–VOD(SS)
Figure 12. VOD(RING) Waveform and Definitions
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from
the VOD(H) and VOD(L) steady state values.
VCC
DE
Input
D
27 Ω ± 1%
Y
Y
VY
Z
VZ
VOC(PP)
Z
27 Ω ± 1%
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
Input: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 13. Test Circuit and Definitions for Driver Common-Mode Output Voltage
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Parameter Measurement Information (continued)
Y
»
W
Z
W
»
A.
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 14. Driver Switching Test Circuit and Voltage Waveforms
D
3V
0V
3V
S1
Y
Z
Y
S1
D
VO
1.5 V
1.5 V
VI
0.5 V
t PZH(1 & 2)
Z
0V
V OH
DE
Input
Generator
VI
RL = 110 W
±1%
CL = 50 pF
±20%
50 W
VO
2.3 V
~0V
tPHZ
A.
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
B.
CL Includes Fixture and Instrumentation Capacitance
Figure 15. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
D
3V
0V
VCC
S1
Z
Y
RL = 110 Ω
± 1%
Y
A.
1.5 V
VO
DE
VI
1.5 V
VI
S1
D
Input
Generator
3V
0V
Z
t PZL(1&2)
t PLZ
VCC
CL = 50 pF ±20%
50 Ω
0.5 V
CL Includes Fixture
and Instrumentation
Capacitance
VO
2.3 V
VOL
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 16. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
IA
VA
VA + VB
2
VIC
A
R
VID
IO
B
VB
IB
RE
II
VO
VI
Figure 17. Receiver Voltage and Current Definitions
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Parameter Measurement Information (continued)
3V
A
R
Input
Generator
VI
50 Ω
1.5 V
0V
B
1.5 V
0V
CL = 15 pF
±20%
RE
1.5 V
VI
VO
t PLH
VO
t PHL
90% 90%
1.5 V
10%
tr
A.
CL Includes Fixture and Instrumentation Capacitance
B.
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
VOH
1.5 V
10% V
OL
tf
Figure 18. Receiver Switching Test Circuit and Voltage Waveforms
1.5 V
V CC
A
R
0V
B
VI
S1
C L = 15 pF
±20%
RE
Input
Generator
1 k W ±1%
VO
3V
A
VI
1.5V
1.5V
0V
B
t PHZ
t PZH(1 & 2)
V OH
50 W
1.5 V
VO
0.5V
~0 V
A.
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 19. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
0V
V CC
A
R
1.5 V
V O 1 k W ±1%
B
RE
Input
V
Generator I
50 W
C L = 15 pF
±20%
S1
3V
A
VI
1.5V
1.5V
B
0V
t PZL(1 & 2)
VO
t PLZ
1.5 V
V CC
0.5 V
V OL
A.
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 20. Receiver Enable Time From Standby (Driver Disabled)
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Parameter Measurement Information (continued)
0 V or 3 V
DE
A
Y
D
R
Z
100 W
±1%
+
-
Pulse Generator
15 ms duration
1% Duty Cycle
tr, tf £ 100 ns
100 W
±1%
B
RE
0 V or 3 V
+
-
Figure 21. Test Circuit, Transient Over Voltage Test
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9 Detailed Description
9.1 Overview
The SN65HVD3x-EP devices are low-power, full-duplex RS-485 transceivers available in three speed grades
suitable for data transmission of 1 Mbps, 5 Mbps, and 50 Mbps.
The SN65HVD30, SN65HVD31, and SN65HVD32 devices are fully enabled with no external enabling pins. The
SN65HVD33, SN65HVD34, and SN65HVD35 devices have active-high driver enables and active-low receiver
enables. A standby current of less than 1 µA can be achieved by disabling both driver and receiver.
9.2 Functional Block Diagram
VCC
VCC
A
R
A
R
R
R
B
B
RE
VCC
DE
Z
D
Z
D
D
D
Y
Y
GND
GND
a) SN65HVD33, SN65HVD34,
SN65HVD35
b) SN65HVD30, SN65HVD31,
SN65HVD32
9.3 Feature Description
9.3.1 Low-Power Standby Mode
When both the driver and receiver are disabled (DE is low and RE is high), the device is in standby mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against
inadvertently entering standby mode during driver or receiver enabling. The device in standby mode only when
the enable inputs are held in this state for 300 ns or more. In this low-power standby mode, most internal circuitry
is powered down, and the supply current is typically less than 1 nA. When either the driver or the receiver is reenabled, the internal circuitry becomes active.
12
R
RE
2
11
A
B
3
Low-Power
Standby
DE
4
9
D
5
10
Y
Z
Figure 22. Low-Power Standby Logic Diagram
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after
the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the
driver is enabled, the driver output defaults to Y high and Z low, in accordance with the driver-failsafe feature.
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Feature Description (continued)
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the
bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If
there is no valid state on the bus the receiver responds as described in the failsafe operation section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the
active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver
outputs are valid.
9.3.2 Driver Output Current Limiting
The RS-485 standard (ANSI/TIA/EIA-485-A or equivalently ISO 8482) specifies a 250-mA driver output current
limit to prevent damage caused by data contention on the bus. That applies in the event that two or more
transceivers drive the bus to opposing states at the same time. The SN65HVD3x-EP family of devices includes
current-limiting circuitry that prevents damage under these conditions.
NOTE
This current limit prevents damage during the bus contention, but the logic state of the bus
can be indeterminate as specified by the standard, so communication errors can occur.
In a specific combination of circumstances, a condition can occur in which current through the bus pin exceeds
the 250-mA limit. This combination of conditions is not normally included in RS-485 applications:
• Loading capacitance on the pin is less than 500 pF
• The bus pin is directly connected to a voltage more negative than –1 V
• The device is supplied with VCC equal to or greater than 3.3 V
• The driver is enabled
• The bus pin is driving to the logic high state
In these specific conditions, the normal current-limit circuitry and thermal-shutdown circuitry does not limit or
shutdown the current flow. If the current is allowed to continue, the device heats up in a localized area near the
driver outputs, and the device can be damaged.
Typical RS-485 twisted-pair cable has a capacitance of approximately 50 pF/meter. Therefore, it is expected that
10 meters of cable can provide sufficient capacitance to prevent this latch-up condition.
The –7 to +12-V common mode range specified by RS-485 is intended to allow communication between
transceivers separated by significant distances when ground offsets may occur due to temporary current surges,
electrical noise, and so on. Under those circumstances, the inherent cable needed to connect separated
transceivers ensures that the conditions previously listed do not occur. For a transceiver separated by only a
short cable length or backplane applications, it is unusual for there to be a steady-state negative common-mode
voltage. It is possible for a negative power supply to be shorted to the bus lines due to miswiring or cable
damage; however, this is a different root cause fault, and robust devices such as the SN65HVD178x family
should be used for surviving power supply or miswiring faults.
The 250-mA current limit in the RS-485 standard is intended to prevent damage caused by data contention on
the bus; that is, in the event that two or more transceivers drive the bus to different states at the same time.
These devices are not damaged under these conditions because all RS-485 drivers have output impedance
sufficient to prevent the direct connection condition stated previously. Typical RS-485 driver output impedance is
on the order of 10 Ω to 30 Ω.
9.3.3 Hot-Plugging
These devices are designed to operate in hot swap or hot pluggable applications. Key features for hot-pluggable
applications are:
• Power-up
• Power-down glitch-free operation
• Default disabled input/output pins
• Receiver failsafe
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Feature Description (continued)
As shown in Figure 9, an internal power-on reset circuit keeps the driver outputs in a high-impedance state until
the supply voltage has reached a level at which the device reliably operates. This ensures that no spurious bits
are transmitted on the bus pin outputs as the power supply turns on or turns off.
As shown in the Device Functional Modes, the enable inputs have the feature of default disable on both the
driver enable and receiver enable. This ensures that the device neither drives the bus nor reports data on the R
pin until the associated controller actively drives the enable pins.
9.3.4 Receiver Failsafe
The differential receivers of the SN65HVD3x-EP family are failsafe to invalid bus states caused by:
• Open bus conditions such as a disconnected connector
• Shorted bus conditions such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a failsafe logic high state so that the output of the receiver
is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a high when the differential input VID is more positive than 200 mV, and must output a low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VIT+, VIT–, and VHYS (the separation between VIT+ and VIT–. As shown in the Electrical Characteristics: Receiver
table, differential signals more negative than –200 mV always cause a low receiver output, and differential
signals more positive than 200 mV always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VIT+ threshold, and the receiver output is
high. Only when the differential input is more than VHYS below VIT+ does the receiver output transition to a low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value (VHYS) as well as the value of VIT+.
R
VHYS
50mV
-70
-20
0
70
VID - mV
Vnoise-max = 140mVpp
Figure 23. SN65HVD30-35 Noise Immunity Under Bus Fault Conditions
9.3.5 Safe Operation With Bus Contention
These devices incorporate a driver current limit of 250 mA across the RS-485 common-mode range of –7 V to
+12 V. As stated in the Application Guidelines for TIA/EIA-485-A (1), this sets a practical limitation to prevent
damage during bus contention events. Contention can occur during system initialization, during system faults, or
whenever two or more drivers are active at the same time.
(1)
TIA/EIA Telecommunications System Bulletin TSB89, Application Guidelines for TIA/EIA-485-A
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Feature Description (continued)
Figure 24 shows a 2-node system to demonstrate bus contention by forcing both drivers to be active in opposing
states.
Vcc2
Vcc1
ALWAYS
HIGH
D
ALWAYS
ENABLED
DE
±7V
OFFSET
GND
1
GND
2
Node 1 D-pin
Node 2 DE -pin
Bus Vdiff
CONTENTION
Figure 24. Bus Contention Example
Figure 25 shows typical operation in a bus contention event. The bottom trace illustrates how the SN65HVD33
device at Node 1 continues normal operation after a contention event between the two drivers with a –7-V
ground offset on Node 2. This illustrates how the SN65HVD3x-EP family of devices operates robustly in spite of
bus contention faults, even with large common-mode offsets.
Node 1 D-pin
-7V offset
Node 2 DE-pin
Bus with intermittent contention
Figure 25. SN65HVD3x-EP Drivers Operate Correctly After Bus Contention Faults
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9.4 Device Functional Modes
Table 3-Table 6 list the functional modes of the S65HVDxx Devices.
Table 3. SN65HVD33, SN65HVD34, SN65HVD35 Driver
INPUTS
OUTPUTS
D
DE
Y
Z
H
H
H
L
H
L
H
L
X
L or open
Z
Z
Open
H
L
H
Table 4. SN65HVD33, SN65HVD34, SN65HVD35
Receiver
DIFFERENTIAL INPUTS
VID = V(A) – V(B)
ENABLE
RE
OUTPUT
R
VID ≤ –0.2 V
L
L
–0.2 V < VID < –0.02 V
L
—
–0.02 V ≤ VID
L
H
X
H or open
Z
Open Circuit
L
H
Idle circuit
L
H
Short Circuit, V(A) = V(B)
L
H
Table 5. SN65HVD30, SN65HVD31, SN65HVD32 Driver
OUTPUTS
INPUT
D
Y
Z
H
H
L
L
L
H
Open
L
H
Table 6. SN65HVD30, SN65HVD31, SN65HVD32
Receiver
DIFFERENTIAL INPUTS
VID = V(A) – V(B)
OUTPUT
R
VID ≤ –0.2 V
L
–0.02 V ≤ VID
H
Open Circuit
H
Idle circuit
H
Short Circuit, V(A) = V(B)
H
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D and DE Input
RE Input
VCC
VCC
130 kW
Input
470 W
Input
470 W
9V
9V
125 kW
A Input
B Input
VCC
VCC
R1
22 V
R1
22 V
R3
R3
Input
Input
22 V
R2
22 V
R2
R Output
Y and Z Outputs
VCC
VCC
16 V
5W
Output
Output
16 V
9V
Figure 26. Equivalent Input and Output Schematic Diagrams
Table 7. Input Attenuator Resistance Values
PART NUMBER
22
R1, R2
R3
SN65HVD30, SN65HVD33
9 kΩ
45 kΩ
SN65HVD31, SN65HVD32, SN65HVD34, SN65HVD35
36 kΩ
180 kΩ
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SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN65HVD3x-EP family consists of full-duplex RS-485 transceivers commonly used for asynchronous data
transmissions. Full-duplex implementation requires two signal pairs (four wires), and allows each node to
transmit data on one pair while simultaneously receiving data on the other pair.
To eliminate line reflections, each cable end is terminated with a termination resistor (RT) whose value matches
the characteristic impedance (Z0) of the cable. This method, known as parallel termination, allows for higher data
rates over longer cable length.
Y
R
D
Z
A
RT
RT
B
R
R
DE
RE
Master
RE
D
Slave
B
R
A
DE
Z
RT
RT
A
B
Z
Y
D
D
Y
R Slave
D
R RE DE D
Figure 27. Typical RS-485 Network With Full-Duplex Transceivers
10.2 Typical Application
A full-duplex RS-485 network consists of multiple transceivers connecting in parallel to two bus cables. On one
signal pair, a master driver transmits data to multiple slave receivers. The master driver and slave receivers can
remain fully enabled at all times. On the other signal pair, multiple slave drivers transmit data to the master
receiver. To avoid bus contention, the slave drivers must be intermittently enabled and disabled such that only
one driver is enabled at any time, as in half-duplex communication. The master receiver can remain fully enabled
at all times.
Because the driver cannot be disabled, only connect one driver to the bus when using the SN65HVD30,
SN65HVD31, or SN65HVD32 devices.
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Typical Application (continued)
VCC
VCC
A
R
A
R
R
R
B
RE
B
RE
DE
DE
VCC
D
D
Z
D
Z
D
Y
Y
GND
GND
a) Master enable
control
b) Slave enable
control
Figure 28. Full-Duplex Transceiver Configurations
10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable can be without introducing data
errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require
data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for
small signal jitter of up to 5 or 10%.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
Data Rate (bps)
Figure 29. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (such as 26 Mbps for the SN65HVD30 and SN65HVD33 devices) in cases
where the interconnect is short enough (or has suitably low attenuation at signal frequencies) to not degrade the
data.
24
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SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
Typical Application (continued)
10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, must be as short as possible. Stubs present a nonterminated piece of bus line that can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub must be less than one-tenth of the rise time of the driver; thus giving a maximum physical stub length as
shown in Equation 1.
Lstub ≤ 0.1 × tr × v × c
where:
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
Per Equation 1, Table 8 shows the maximum cable-stub lengths for the minimum driver output rise times of the
SN65HVD3x-EP full-duplex family of transceivers for a signal velocity of 78%.
Table 8. Maximum Stub Length
MAXIMUM STUB LENGTH
DEVICE
MINIMUM DRIVER OUTPUT RISE TIME
(ns)
(m)
(ft)
SN65HVD30
4
0.1
0.3
SN65HVD31
25
0.6
1.9
SN65HVD32
120
2.8
9.2
SN65HVD33
4
0.1
0.3
SN65HVD34
25
0.6
1.9
SN65HVD35
120
2.8
9.2
10.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the SN65HVD30 and SN65HVD33 devices
are 1/2 UL transceivers, it is possible to connect up to 64 receivers to the bus. Likewise, the SN65HVD31,
SN65HVD32, SN65HVD34, and SN65HVD35 devices are 1/8 UL transceivers that can support up to 256
receivers.
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SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
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10.2.2 Detailed Design Procedure
To protect bus nodes against high-energy transients, the implementation of external transient protection devices
is necessary (see Figure 30).
3.3 V
100 nF
R1
10 kΩ
VCC
TVS
A
R
RxD
B
RE
DIR
MCU/
UART
R2
R1
SN65HVD33
DE
DIR
TVS
Z
D
TxD
Y
10 kΩ
GND
R2
Figure 30. Transient Protection Against ESD, EFT, and Surge Transients
Table 9. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
3.3-V Full-Duplex RS-485 Transceiver
SN65HVD33
R1, R2
10-Ω, Pulse-Proof Thick-Film Resistor
CRCW060310RJNEAHP
Vishay
TI
TVS
Bidirectional 400-W Transient Suppressor
CDSOT23-SM712
Bourns
10.2.3 Application Curve
Signals from top to bottom: D, Y, Z, VOD
Figure 31. SN65HVD33-EP Transient Waveform
26
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SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply must be decoupled with a
100-nF ceramic capacitor located as close as possible to the supply pins. This helps to reduce supply voltage
ripple present on the outputs of switched-mode power supplies and also helps compensate for the resistance
and inductance of the PCB power planes.
12 Layout
12.1 Layout Guidelines
Robust and reliable bus-node design often requires the use of external transient protection devices to protect
against EFT and surge transients that can occur in industrial environments. Because these transients have a
wide frequency bandwidth (from approximately 3 MHz to 3 GHz), high-frequency layout techniques must be
applied during PCB design.
• Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
• Use VCC and ground planes to provide low-inductance. High-frequency currents follow the path of least
inductance and not the path of least impedance.
• Design the protection components into the direction of the signal path. Do not force the transients currents to
divert from the signal path to reach the protection device.
• Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, and
controller ICs on the board.
• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via inductance.
• Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
• Insert series pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the
specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into
the transceiver and prevent it from latching up.
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs), which reduces the transients to a few hundred volts of clamping voltage and transient
blocking units (TBUs) that limit transient current to 200 mA.
12.2 Layout Example
5
Via to ground
4
Via to VCC
R
6 R
1
R
MCU
R
7
5
R
TVS
6 R
R
7
5
1
R
5
R
5
JMP
C
TVS
SN65HVD33
Figure 32. SN65HVD33-EP Layout Example
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SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367E – SEPTEMBER 2006 – REVISED SEPTEMBER 2015
www.ti.com
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 10. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN65HVD30-EP
Click here
Click here
Click here
Click here
Click here
SN65HVD31-EP
Click here
Click here
Click here
Click here
Click here
SN65HVD32-EP
Click here
Click here
Click here
Click here
Click here
SN65HVD33-EP
Click here
Click here
Click here
Click here
Click here
SN65HVD34-EP
Click here
Click here
Click here
Click here
Click here
SN65HVD35-EP
Click here
Click here
Click here
Click here
Click here
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Oct-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65HVD30MDREP
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HVD30EP
SN65HVD30MDREPG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HVD30EP
SN65HVD33MDREP
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HVD33EP
SN65HVD33MDREPG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HVD33EP
V62/06634-01XE
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HVD30EP
V62/06634-04YE
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HVD33EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Oct-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD30-EP, SN65HVD33-EP :
• Catalog: SN65HVD30, SN65HVD33
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD30MDREP
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD33MDREP
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD30MDREP
SOIC
SN65HVD33MDREP
SOIC
D
8
2500
367.0
367.0
35.0
D
14
2500
333.2
345.9
28.6
Pack Materials-Page 2
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