MAXIM MAX3629

19-4467; Rev 0; 2/09
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
The MAX3629 is a low-jitter precision clock generator
optimized for network applications. The device integrates a crystal oscillator and a phase-locked loop
(PLL) to generate high-frequency clock outputs for
Ethernet applications.
Maxim’s proprietary PLL design features ultra-low jitter
(0.4psRMS) and excellent power-supply noise rejection
(PSNR), minimizing design risk for network equipment.
The MAX3629 contains five LVDS outputs and three
LVCMOS outputs. The output frequencies are selectable among 125MHz, 156.25MHz, and 312.5MHz by
pin control.
Applications
Ethernet Networking Equipment
Features
♦ Crystal Oscillator Interface: 25MHz
♦ OSC_IN Interface:
PLL Enabled: 25MHz
PLL Disabled: 20MHz to 320MHz
♦ Outputs:
One LVDS Output at 125MHz/156.25MHz/
312.5MHz (Selectable with FSELA)
Four LVDS Outputs at 125MHz/156.25MHz/
312.5MHz (Selectable with FSELB)
Three LVCMOS Outputs at 125MHz/156.25MHz
(Selectable with FSELB)
♦ Low Phase Jitter: 0.4psRMS (12kHz to 20MHz)
♦ Excellent PSNR
♦ Operating Temperature Range: 0°C to +70°C
Typical Operating Circuit
Ordering Information
+3.3V ±5%
0.1μF
10.5Ω
ASIC
X_OUT
Q2
VDD
PLL_BP
Q3
Q4
GND, OPEN, OR VDD
FSELA
GND, OPEN, OR VDD
FSELB
Q4
Z0 = 50Ω
125MHz/156.25MHz/
312.5MHz
ASIC
33Ω
Q5
21
20
19
18
17
16
FSELB
PLL_BP 26
15
RESERVED
VDD 27
14
Q4
13
Q4
MAX3629
OSC_IN 29
100Ω
125MHz/156.25MHz
Z0 = 50Ω
Q6
125MHz/156.25MHz
Z0 = 50Ω
Q7
125MHz/156.25MHz
Z0 = 50Ω
33Ω
22
FSELA 28
ASIC
Z0 = 50Ω
33Ω
GND
100Ω
Z0 = 50Ω
Z0 = 50Ω
125MHz/156.25MHz/
312.5MHz
23
VDDA 25
Z0 = 50Ω
27pF
Q3
24
X_IN 30
X_OUT 31
*EP
+
GND 32
12
VDDO_DIFF
11
Q3
10
Q3
9
GND
ASIC
1
2
3
4
5
6
7
8
Q2
X_IN
Z0 = 50Ω
125MHz/156.25MHz/
312.5MHz
Q2
Q2
25MHz
(CL = 18pF)
GND
100Ω
TOP VIEW
Q5
ASIC
VDDO_SE
100Ω
Z0 = 50Ω
Q6
33pF
Pin Configuration
Q1
Q1
Z0 = 50Ω
125MHz/156.25MHz/
312.5MHz
VDDO_DIFF
MAX3629
ASIC
Q7
Q1
100Ω
Z0 = 50Ω
GND
OSC_IN
32 TQFN-EP*
Q1
Q0
Z0 = 50Ω
125MHz/156.25MHz/
312.5MHz
0°C to +70°C
VDDO_SE
Q0
MAX3629CTJ+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
VDDO_SE
0.01μF
PIN-PACKAGE
Q0
VDDO_DIFF
VDDA
TEMP RANGE
GND
VDD
10μF
PART
RESERVED
0.1μF
Q0
0.1μF
ASIC
THIN QFN-EP
(5mm × 5mm)
ASIC
*EXPOSED PAD CONNECTED TO GROUND.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX3629
General Description
MAX3629
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range at VDD, VDDA,
VDDO_SE, VDDO_DIFF ................................................-0.3V to +4.0V
Voltage Range at Q0, Q0, Q1, Q1, Q2, Q2,
Q3, Q3, Q4, Q4, Q5, Q6, Q7, PLL_BP,
FSELA, FSELB, OSC_IN .........................-0.3V to (VDD + 0.3V)
Voltage Range at X_IN Pin ....................................-0.3V to +1.2V
Voltage Range at X_OUT Pin ..........................-0.3V to (VDD - 0.6V)
Continuous Power Dissipation (TA = +70°C)
32-Pin TQFN-EP (derate 34.5mW/°C above +70°C)..2759mW
Operating Junction Temperature ......................-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is
bypassed, PLL_BP = low.) (Note 1)
PARAMETER
Power-Supply Current (Note 2)
SYMBOL
IDD
CONDITIONS
MIN
TYP
MAX
PLL enabled
176
224
PLL bypassed
160
UNITS
mA
LVDS OUTPUTS (Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4 Pins)
Output High Voltage
VOH
Output Low Voltage
VOL
Differential Output Voltage
Amplitude
Change in Magnitude of
Differential Output for
Complementary States
Output Offset Voltage
Change in Magnitude of Output
Offset Voltage for
Complementary States
|V OD |
1.475
0.925
Figure 1
1.125
|V OS |
Differential Output Impedance
80
Output Current
Clock Output Rise/Fall Time
250
|V OD |
VOS
tr, t f
Output Duty-Cycle Distortion
V
V
105
Shorted together
5
Short to ground (Note 3)
8
400
mV
25
mV
1.275
V
25
mV
140
mA
20% to 80%, RL = 100
PLL enabled
100
180
330
48
50
52
PLL bypassed (Note 4)
46
50
54
2.6
ps
%
LVCMOS/LVTTL OUTPUTS (Q5, Q6, Q7 Pins)
Output High Voltage
VOH
I OH = -12mA
Output Low Voltage
VOL
I OL = 12mA
Output Rise/Fall Time
tr, t f
Output Duty-Cycle Distortion
Output Impedance
2
20% to 80% at 125MHz (Note 5)
PLL enabled, PLL bypassed (Note 4)
R OUT
VDD
V
0.4
V
0.15
0.5
0.8
ns
45
50
55
%
15
_______________________________________________________________________________________
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
(VDD = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is
bypassed, PLL_BP = low.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SPECIFICATIONS (FSELA, FSELB, PLL_BP Pins)
Input-Voltage High
VIH
2.0
VDD
V
Input-Voltage Low
VIL
0
0.8
V
Input High Current
I IH
VIN = VDD
80
μA
Input Low Current
I IL
VIN = 0V
-80
μA
LVCMOS/LVTTL INPUT SPECIFICATIONS (OSC_IN) (Note 6)
PLL enabled
Input Clock Frequency
Input Amplitude Range
MHz
20
320
(Note 7)
1.2
3.6
V
80
μA
Input High Current
I IH
VIN = VDD
Input Low Current
I IL
VIN = 0V
Reference Clock Duty Cycle
Input Capacitance
25
PLL bypassed
-80
40
CIN
μA
50
60
%
1.5
pF
625
MHz
CLOCK OUTPUT AC SPECIFICATIONS
VCO Center Frequency
Output Frequency with PLL
Enabled (Q0)
FSELA = GND
125
FSELA = VDD
156.25
FSELA = high-Z
Output Frequency with PLL
Enabled (Q1 to Q7)
FSELB = GND
125
FSELB = VDD
156.25
FSELB = high-Z (Note 8)
Output Frequency with PLL
Disabled
LVDS outputs
20
320
LVCMOS outputs
20
160
0.4
12kHz to 20MHz, PLL_BP = high-Z
(Note 10)
0.4
Power-Supply Noise Rejection
(Note 11)
LVDS output
-55
LVCMOS output
-47
Deterministic Jitter Due to
Supply Noise (Note 12)
LVDS output
9
LVCMOS output
23
(Note 13)
-73
f = 100Hz
-116
f = 1kHz
-124
f = 10kHz
-127
f = 100kHz
-131
f = 1MHz
-144
f > 10MHz
-149
Nonharmonic and Subharmonic
Spurs
LVDS Clock Output SSB Phase
Noise at 125MHz (Note 14)
RJRMS
MHz
312.5
12kHz to 20MHz, PLL_BP = high (Note 9)
Integrated Phase Jitter at
125MHz/156.25MHz
MHz
312.5
MHz
psRMS
dBc
psP-P
dBc
dBc/Hz
_______________________________________________________________________________________
3
MAX3629
ELECTRICAL CHARACTERISTICS (continued)
MAX3629
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is
bypassed, PLL_BP = low.) (Note 1)
PARAMETER
LVCMOS Clock Output SSB
Phase Noise at 125MHz
(Note 14)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
4
SYMBOL
CONDITIONS
MIN
TYP
f = 100Hz
-115
f = 1kHz
-124
f = 10kHz
-126
f = 100kHz
-130
f = 1MHz
-144
f > 10MHz
-151
MAX
UNITS
dBc/Hz
A series resistor of up to 10.5Ω is allowed between VDD and VDDA for filtering supply noise when system power-supply tolerance is VDD = 3.3V ±5%. See Figure 4.
All outputs unloaded.
The current when an LVDS output is shorted to ground is the steady-state current after the detection circuitry has settled. It
is expected that the LVDS output short to ground condition is short-term only.
Measured with OSC_IN input with 50% duty cycle.
Measured with a series resistor of 33Ω to a load capacitance of 3.0pF. See Figure 2.
The OSC_IN input can be DC- or AC-coupled.
Must be within the absolute maximum rating of VDD + 0.3V.
AC characteristics of LVCMOS outputs (Q5, Q6, and Q7) are only guaranteed up to 160MHz.
Measured with 25MHz crystal (with OSC_IN left open).
Measured with 25MHz reference clock applied to OSC_IN.
Measured at 125MHz output with 40mVP-P sinusoidal signal on the supply at 100kHz. Measured with a 10.5Ω resistor
between VDD and VDDA.
Parameter calculated based on PSNR.
Measurement includes XTAL oscillator feedthrough, crosstalk, intermodulation spurs, etc.
Measured with 25MHz XTAL oscillator.
_______________________________________________________________________________________
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
MAX3629
Qx
RL = 100Ω
VOD
V
Qx
Qx
VOH
IVODI
SINGLE-ENDED OUTPUT
VOS
Qx
VOL
Qx - Qx
DIFFERENTIAL OUTPUT
0
VODP-P = 2IVODI
Figure 1. Driver Output Levels
VCC
800Ω
MAX3629
33Ω
Q5 TO Q7
Z0 = 50Ω
3pF
800Ω
OSCILLOSCOPE
0.1μF
Z0 = 50Ω
50Ω
50Ω
Figure 2. LVCMOS Output Measurement Setup
_______________________________________________________________________________________
5
Typical Operating Characteristics
(Typical values are at VDD = +3.3V, TA = +25°C, crystal frequency = 25MHz.)
PHASE NOISE AT 125MHz
CLOCK FREQUENCY (Q0)
SUPPLY CURRENT
vs. TEMPERATURE
150
125
PLL_BP = LOW
100
75
50
-110
-120
-130
-140
-160
0
10
20
30
40
50
60
0.1
70
1
10
100
1000 10,000 100,000
AMBIENT TEMPERATURE (°C)
OFFSET FREQUENCY (kHz)
PHASE NOISE AT 125MHz
CLOCK FREQUENCY (Q7)
PHASE NOISE AT 156.25MHz
CLOCK FREQUENCY (Q0)
-90
-100
-110
-120
-130
-140
-80
MAX3629 toc04
MAX3629 toc03
-80
NOISE POWER DENSITY (dBc/Hz)
0
NOISE POWER DENSITY (dBc/Hz)
-100
-150
25
-90
-100
-110
-120
-130
-140
-150
-150
-160
-160
1
10
100
0.1
1000 10,000 100,000
10
100
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
PHASE NOISE AT 156.25MHz
CLOCK FREQUENCY (Q7)
PHASE NOISE AT 312.5MHz
CLOCK FREQUENCY (Q0)
MAX3629 toc05
-80
-90
-100
-110
-120
-130
-140
-80
-90
-100
-110
-120
-130
-140
-150
-150
-160
-160
0.1
1
OFFSET FREQUENCY (kHz)
NOISE POWER DENSITY (dBc/Hz)
0.1
1
10
100
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
6
-90
MAX3629 toc06
SUPPLY CURRENT (mA)
175
MAX3629 toc02
PLL_BP = HIGH
200
-80
NOISE POWER DENSITY (dBc/Hz)
225
MAX3629 toc01
250
NOISE POWER DENSITY (dBc/Hz)
MAX3629
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
0.1
1
10
100
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
_______________________________________________________________________________________
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
DIFFERENTIAL OUTPUT WAVEFORM
AT 156.25MHz (LVDS OUTPUT)
DIFFERENTIAL OUTPUT WAVEFORM
AT 125MHz (LVDS OUTPUT)
MAX3629 toc08
MAX3629 toc07
100mV/div
100mV/div
1ns/div
1ns/div
DIFFERENTIAL OUTPUT WAVEFORM
AT 312.5MHz (LVDS OUTPUT)
OUTPUT WAVEFORM
AT 125MHz (CMOS OUTPUT)
MAX3629 toc10
MAX3629 toc09
15mV/div
100mV/div
MEASURED USING SETUP IN FIGURE 2
1ns/div
SPURS INDUCED BY POWER-SUPPLY NOISE
vs. NOISE FREQUENCY
SPURS INDUCED BY POWER-SUPPLY NOISE
vs. NOISE FREQUENCY
SPUR AMPLITUDE (dBc)
-20
VNOISE = 200mVP-P
-40
VNOISE = 40mVP-P
-50
-60
VNOISE = 100mVP-P
-70
fC = 125MHz, OUTPUT = Q7
-10
SPUR AMPLITUDE (dBc)
fC = 156.25MHz, OUTPUT = Q0
-30
0
MAAX3629 toc11
0
-10
-20
VNOISE = 200mVP-P
-30
-40
-50
VNOISE = 100mVP-P
-60
-70
-80
MAAX3629 toc12
500ps/div
VNOISE = 40mVP-P
-80
-90
-90
10
100
1000
NOISE FREQUENCY (kHz)
10,000
10
100
1000
10,000
NOISE FREQUENCY (kHz)
_______________________________________________________________________________________
7
MAX3629
Typical Operating Characteristics (continued)
(Typical values are at VDD = +3.3V, TA = +25°C, crystal frequency = 25MHz.)
MAX3629
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
Pin Description
PIN
NAME
1
Q0
LVDS, Noninverting Clock Output
2
Q0
LVDS, Inverting Clock Output
3, 9, 17, 21,
32
GND
4
Q1
LVDS, Noninverting Clock Output
LVDS, Inverting Clock Output
Supply Ground
5
Q1
6, 12
VDDO_DIFF
7
Q2
LVDS, Noninverting Clock Output
LVDS, Inverting Clock Output
Power Supply for Q0, Q1, Q2, Q3, and Q4 Clock Outputs. Connect to +3.3V.
8
Q2
10
Q3
LVDS, Noninverting Clock Output
11
Q3
LVDS, Inverting Clock Output
13
Q4
LVDS, Noninverting Clock Output
14
Q4
LVDS, Inverting Clock Output
15
RESERVED
Reserved. Connect to GND.
16
FSELB
18, 20, 22
Q5, Q6, Q7
19, 23
VDDO_SE
24
RESERVED
25
VDDA
26
PLL_BP
27
VDD
28
FSELA
29
8
FUNCTION
OSC_IN
30
X_IN
31
X_OUT
—
EP
Three-State LVCMOS/LVTTL Input. Controls the Q1 to Q7 output divider. When connected to logiclow, the output frequency is 125MHz. When connected to logic-high, the output frequency is
156.25MHz. When left open (high-Z), the output frequency is 312.5MHz. For Q5 to Q7 LVCMOS
outputs, the output specification is only valid up to 160MHz.
LVCMOS Clock Output
Power Supply for Q5, Q6, and Q7 Clock Outputs. Connect to +3.3V.
Reserved. Leave open.
Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this
pin can connect to VDD through a 10.5 resistor as shown in Figure 4.
Three-State LVCMOS/LVTTL Input (Active Low). When connected to logic-high, the PLL locks to the
crystal interface (25MHz typical at X_IN and X_OUT). When left open (high-Z), the PLL locks to the
OSC_IN input (25MHz typical). When connected to logic-low, the PLL is bypassed and the OSC_IN
input is selected. When bypass mode is selected, the VCO/PLL is disabled to save power and
eliminate intermodulation spurs.
Power Supply for Digital Part of the Chip. Connect to +3.3V.
Three-State LVCMOS/LVTTL Input. Controls the Q0 output divider. When connected to logic-low, the
output frequency is 125MHz. When connected to logic-high, the output frequency is 156.25MHz.
When left open (high-Z), the output frequency is 312.5MHz.
LVCMOS Input. Self-biased to allow AC- or DC-coupling. When PLL_BP is open, the OSC_IN input
frequency should be 25MHz. When the PLL is in bypass mode (PLL_BP = low), the OSC_IN input
frequency can be between 20MHz and 320MHz. When PLL_BP is high, the OSC_IN should be
disconnected.
Crystal Oscillator Input
Crystal Oscillator Output
Exposed Pad. Connect to GND for proper electrical and thermal performance.
_______________________________________________________________________________________
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
VDDA
FSELA
PLL_BP
MAX3629
VDD
VDDO_DIFF
PLL_BP
LOGIC
125/156.25/
312.5MHz
0
OSC_IN
CMOS
0/OPEN
PFD
FILTER
VCO
DIVIDER
5, 4, OR 2
LVDS
BUFFER
LVDS
BUFFER
CRYSTAL
OSCILLATOR
X_OUT
DIVIDE
25
DIVIDER
5, 4, OR 2
0
1/OPEN
LVDS
BUFFER
LVDS
BUFFER
LVDS
BUFFER
MAX3629
Q0
1/OPEN
1
X_IN
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
LVCMOS
BUFFER
Q5
LVCMOS
BUFFER
Q6
LVCMOS
BUFFER
Q7
125/156.25MHz
FSELB
VDDO_SE
Figure 3. Functional Diagram
_______________________________________________________________________________________
9
MAX3629
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
Detailed Description
The MAX3629 is a frequency generator designed to
operate at Ethernet frequencies. It consists of an onchip crystal oscillator, PLL, LVCMOS output buffers,
and LVDS output buffers. Using a low-frequency clock
(crystal or CMOS input) as a reference, the internal PLL
generates a high-frequency output clock with excellent
jitter performance. The outputs can be switched among
125MHz, 156.25MHz, and 312.5MHz.
Crystal Oscillator
An integrated oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an
external crystal connected between X_IN and X_OUT.
The crystal frequency is 25MHz.
Applications Information
Power-Supply Filtering
The MAX3629 is a mixed analog/digital IC. The PLL
contains analog circuitry susceptible to random noise.
To take full advantage of on-board filtering and noise
attenuation, in addition to excellent on-chip power-supply rejection, this part provides a separate power-supply pin, VDDA, for the VCO circuitry. The purpose of this
design technique is to ensure clean input power supply
to the VCO circuitry and to improve the overall immunity
to power-supply noise. Figure 4 illustrates the recommended power-supply filter network for VDDA. This network requires that the power supply is +3.3V ±5%.
Decoupling capacitors should be used on all other supply pins for best performance.
OSC_IN Buffer
The LVCMOS OSC_IN buffer is internally biased to
allow AC- or DC-coupling. This input is internally ACcoupled, and is designed to operate at 25MHz when
the PLL is enabled (PLL_BP is left open). When the PLL
is bypassed (PLL_BP is set low), the OSC_IN buffer can
be operated from 20MHz to 320MHz.
PLL
The PLL takes the signal from the crystal oscillator or
reference clock input and synthesizes a low-jitter, highfrequency clock. The PLL contains a phase-frequency
detector (PFD), a lowpass filter, and a voltage-controlled oscillator (VCO) that operates at 625MHz. The
VCO output is connected to the PFD input through a
feedback divider that divides the VCO frequency by 25
to lock onto the 25MHz reference clock or oscillator. For
output Q0, the FSELA pin is used to select among
125MHz, 156.25MHz, and 312.5MHz. For outputs Q1 to
Q4, the FSELB pin is used to select among 125MHz,
156.25MHz, and 312.5MHz. For outputs Q5, Q6, and
Q7, the FSELB pin is used to select between 125MHz
and 156.25MHz. To minimize noise-induced jitter, the
VCO supply (VDDA) is isolated from the core logic and
output buffer supplies.
LVDS Drivers
The high-frequency outputs—Q0, Q1, Q2, Q3, and Q4—
are differential LVDS buffers designed to drive 100Ω.
LVCMOS Driver
LVCMOS outputs Q5, Q6, and Q7 are provided on the
MAX3629. They are designed to drive single-ended
high-impedance loads. The output specifications are
only valid up to 160MHz.
10
+3.3V ±5%
VDD
0.1μF
10.5Ω
VDDA
0.01μF
10μF
Figure 4. Analog Supply Filtering
Crystal Input Layout
and Frequency Stability
The MAX3629 features integrated on-chip crystal oscillators to minimize system implementation cost. The integrated crystal oscillator is a Pierce-type that uses the
crystal in its parallel resonance mode. It is recommended to use a 25MHz crystal with a load specification of
CL = 18pF. The crystal frequency should be chosen so
that the VCO operates at 625MHz. See Table 1 for the
recommended crystal specifications.
The crystal, trace, and two external capacitors should
be placed on the board as close as possible to the
X_IN and X_OUT pins to reduce crosstalk and active
signals into the oscillator.
The layout shown in Figure 5 gives approximately 2pF
of trace plus footprint capacitors per side of the crystal
(Y1). The dielectric material is FR-4 and dielectric thickness of the reference board is 15 mils. Using a 25MHz
crystal and the capacitor values of C45 = 27pF and
______________________________________________________________________________________
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
MAX3629
Table 1. Crystal Selection Parameters
PARAMETER
Crystal Oscillation Frequency
SYMBOL
f OSC
Shunt Capacitance
CO
Load Capacitance
CL
Equivalent Series Resistance (ESR)
RS
MIN
TYP
MAX
25
UNITS
MHz
7.0
18
pF
pF
Maximum Crystal Drive Level
50
300
μW
C46 = 33pF, the measured output frequency accuracy
is -1ppm at +25°C ambient temperature.
Crystal Selection
The crystal oscillator is designed to drive a fundamental
mode, AT-cut crystal resonator. See Table 1 for recommended crystal specifications. See Figure 6 for external
capacitance connection.
27pF
X_IN
CRYSTAL
(CL = 18pF)
X_OUT
33pF
Figure 6. Crystal, Capacitors Connection
Figure 5. Crystal Layout
______________________________________________________________________________________
11
MAX3629
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
Interface Models
Figures 7 and 8 show examples of interface models.
VDD
1.4V
180kΩ
OSC_IN
ESD
STRUCTURES
Figure 7. Simplified OSC_IN Pin Circuit Schematic
VDDO_SE
10Ω
Q5 TO Q7
Layout Considerations
The inputs and outputs are the most critical paths for
the MAX3629 and great care should be taken to minimize discontinuities on these transmission lines
between the connector and the IC. Here are some suggestions for maximizing the performance of the
MAX3629:
• An uninterrupted ground plane should be positioned beneath the clock outputs. The ground
plane under the crystal should be removed to minimize capacitance.
• Ground pin vias should be placed close to the IC
and the input/output interfaces to allow a return
current path to the MAX3629 and the receive
devices.
• Supply decoupling capacitors should be placed
close to the supply pins, preferably on the same
layer as the MAX3629.
• Take care to isolate crystal input traces from the
MAX3629 outputs.
• The crystal, trace, and two external capacitors
should be placed on the board as close as possible to the X_IN and X_OUT pins to reduce
crosstalk and active signals into the oscillator.
• Maintain 100Ω differential (or 50Ω single-ended)
transmission line impedance into and out of the
part.
• Use good high-frequency layout techniques and
multilayer boards with an uninterrupted ground
plane to minimize EMI and crosstalk.
10Ω
Refer to the MAX3629 evaluation kit for more information.
ESD
STRUCTURES
Figure 8. Simplified LVCMOS Output Circuit Schematic
Exposed-Pad Package
The exposed pad on the 32-pin TQFN package provides a very low inductance path for return current traveling to the PCB ground plane. The pad is also
electrical ground on the MAX3629 and must be soldered to the circuit board ground for proper electrical
performance.
Package Information
Chip Information
PROCESS: BiCMOS
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
32 TQFN-EP
T3255+5
21-0140
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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