19-1446; Rev 0; 3/99
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
The MAX5122/MAX5123 low-power, 12-bit, voltage-output, digital-to-analog converters (DACs) feature an internal precision bandgap reference and output amplifier.
The MAX5122 operates on a single +5V supply with an
internal +2.5V reference, and offers a configurable output
amplifier. If necessary, the user can override the on-chip,
<10ppm/°C voltage reference with an external reference.
The MAX5123 has the same features as the MAX5122 but
operates from a single +3V supply and has an internal
+1.25V precision reference. The user-accessible inverting
input and output of the amplifier allows specific gain configurations, remote sensing, and high output drive capability for a wide range of force/sense applications. Both
devices draw only 500µA of supply current, which
reduces to 3µA in power-down mode. In addition, their
power-up reset feature allows for a user-selectable initial
output state of either 0V or midscale and reduces output
glitches during power-up.
The serial interface is compatible with SPI™, QSPI™, and
MICROWIRE™, which makes the MAX5122/MAX5123
suitable for cascading multiple devices. Each DAC has
a double-buffered input organized as an input register
followed by a DAC register. A 16-bit shift register loads
data into the input register. The DAC register may be
updated independently or simultaneously with the input
register.
Both devices are available in a 16-pin QSOP package
and are specified for the extended-industrial (-40°C to
+85°C) operating temperature range. For pin-compatible
14-bit upgrades, see the MAX5171/MAX5173 data sheet;
for the pin-compatible 13-bit version, see the MAX5132/
MAX5133 data sheet.
Features
♦ Single-Supply Operation
+5V (MAX5122)
+3V (MAX5123)
♦ Built-In 10ppm/°C max Precision Bandgap Reference
+2.5V (MAX5122)
+1.25V (MAX5123)
♦ SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial
Interface
♦ Pin-Programmable Shutdown Mode and PowerUp Reset (0 or Midscale Output Voltage)
♦ Buffered Output Capable of Driving 5kΩ 100pF
or 4–20mA Loads
♦ Space-Saving 16-Pin QSOP Package
♦ Pin-Compatible 13-Bit Upgrades Available
(MAX5132/MAX5133)
♦ Pin-Compatible 14-Bit Upgrades Available
(MAX5171/MAX5173)
Ordering Information
PART
TEMP. RANGE
PINPACKAGE
INL
(LSB)
MAX5122AEEE
-40°C to +85°C
16 QSOP
±0.5
MAX5122BEEE
-40°C to +85°C
16 QSOP
±1
MAX5123AEEE
-40°C to +85°C
16 QSOP
±1
MAX5123BEEE
-40°C to +85°C
16 QSOP
±2
Applications
Pin Configuration
Industrial Process Control
Automatic Test Equipment
Digital Offset and Gain Adjustment
TOP VIEW
FB 1
16 VDD
OUT 2
Motion Control
15 REFADJ
14 REF
RSTVAL 3
Microprocessor-Controlled Systems
PDL 4
CLR 5
MAX5122
MAX5123
12 PD
CS 6
11 UPO
DIN 7
10 DOUT
9
SCLK 8
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
13 AGND
DGND
QSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX5122/MAX5123
General Description
MAX5122/MAX5123
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND ...............................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs (DOUT, UPO) to DGND .....-0.3V to (VDD + 0.3V)
FB, OUT to AGND ......................................-0.3V to (VDD + 0.3V)
REF, REFADJ to AGND ..............................-0.3V to (VDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
QSOP (derate 8.00mW/°C above +70°C) .....................667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5122 (+5V)
(VDD = +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, output amplifier configured
in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
12
Bits
MAX5122A
-0.5
0.5
MAX5123B
-1
1
1
LSB
Integral Nonlinearity (Note 1)
INL
Differential Nonlinearity
DNL
-1
Offset Error (Note 2)
VOS
-10
Gain Error
GE
-3
LSB
10
mV
-0.2
3
mV
MAX5122A
3
10
MAX5123B
10
30
20
250
µV/V
2.5
2.525
V
Full-Scale Temperature
Coefficient (Note 3)
TCVFS
Power-Supply Rejection Ratio
PSRR
4.5V ≤ VDD ≤ 5.5V
VREF
TA = +25°C
ppm/°C
REFERENCE
Output Voltage
Output Voltage Temperature
Coefficient
Reference External Load Regulation
TCVREF
VOUT/IOUT
2.475
MAX5122A
3
MAX5122B
10
0 ≤ IOUT ≤ 100µA (sourcing)
0.1
Reference Short-Circuit Current
ppm/°C
1
4
REFADJ Current
REFADJ = VDD
3.3
µV/µA
mA
7
µA
DIGITAL INPUT
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
3
VHYS
Input Leakage Current
IIN
Input Capacitance
CIN
V
0.8
200
VIN = 0 or VDD
-1
0.001
V
mV
1
8
µA
pF
DIGITAL OUTPUTS
Output High Voltage
VOH
ISOURCE = 2mA
Output Low Voltage
VOL
ISINK = 2mA
2
VDD - 0.5
V
0.13
_______________________________________________________________________________________
0.4
V
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
(VDD = +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, output amplifier configured
in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
Output Settling Time
To ±0.5LSB, VSTEP = 2.5V
Output Voltage Swing (Note 4)
0.6
V/µs
20
µs
0 to VDD
Current into FB
-0.1
Time Required to Exit Shutdown
CS = VDD, fSCLK = 100kHz,
VSCLK = 5Vp-p
Digital Feedthrough
0
V
0.1
µA
2
ms
5
nV-sec
POWER REQUIREMENTS
Power-Supply Voltage (Note 5)
Power-Supply Current (Note 5)
Power-Supply Current in Shutdown
VDD
4.5
5.5
V
IDD
500
600
µA
ISHDN
3
20
µA
ELECTRICAL CHARACTERISTICS—MAX5123 (+3V)
(VDD = +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, output amplifier connected
in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
12
Bits
MAX5123A
-1
1
MAX5123B
-2
2
DNL
-1
1
LSB
Offset Error (Note 2)
VOS
-10
Gain Error
GE
-5
Integral Nonlinearity (Note 1)
INL
Differential Nonlinearity
LSB
10
mV
-0.2
5
mV
MAX5123A
3
10
MAX5123B
10
30
20
250
µV/V
1.25
1.263
V
Full-Scale Temperature
Coefficient (Note 3)
TCVFS
Power-Supply Rejection Ratio
PSRR
2.7V ≤ VDD ≤ 3.3V
VREF
TA = +25°C
ppm/°C
REFERENCE
Output Voltage
Output Voltage Temperature
Coefficient
Reference External Load Regulation
TCVREF
VOUT/IOUT
1.237
MAX5123A
3
MAX5123B
10
0 ≤ IOUT ≤ 100µA (sourcing)
0.1
REFADJ = VDD
3.3
Reference Short-Circuit Current
ppm/°C
1
4
REFADJ Current
µV/µA
mA
7
µA
DIGITAL INPUT
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
VHYS
2.2
V
0.8
200
V
mV
_______________________________________________________________________________________
3
MAX5122/MAX5123
ELECTRICAL CHARACTERISTICS—MAX5122 (+5V) (continued)
MAX5122/MAX5123
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
ELECTRICAL CHARACTERISTICS—MAX5123 (+3V) (continued)
(VDD = +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, output amplifier connected
in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Input Leakage Current
IIN
Input Capacitance
CIN
CONDITIONS
VIN = 0 or VDD
MIN
TYP
MAX
UNITS
-1
0.001
1
µA
8
pF
DIGITAL OUTPUTS
Output High Voltage
VOH
ISOURCE = 2mA
Output Low Voltage
VOL
ISINK = 2mA
VDD - 0.5
V
0.13
0.4
V
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
Output Settling Time
To ±0.5LSB, VSTEP = 1.25V
Output Voltage Swing (Note 4)
Current into FB
-0.1
Time Required to Exit Shutdown
CS = VDD, fSCLK = 100kHz,
VSCLK = 3Vp-p
Digital Feedthrough
0.6
V/µs
20
µs
0 to VDD
V
0
0.1
µA
2
ms
5
nV-sec
POWER REQUIREMENTS
Power-Supply Voltage (Note 5)
VDD
3.6
V
Power-Supply Current (Note 5)
IDD
500
600
µA
ISHDN
3
20
µA
Power-Supply Current in Shutdown
2.7
TIMING CHARACTERISTICS—MAX5122 (+5V)
(VDD = +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, output amplifier connected
in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
100
ns
SCLK Pulse Width High
tCH
40
ns
SCLK Pulse Width Low
tCL
40
ns
CS Fall to SCLK Rise Setup Time
tCSS
40
ns
SCLK Rise to CS Rise Hold Time
tCSH
0
ns
SDI Setup Time
tDS
40
ns
SDI Hold Time
tDH
0
ns
SCLK Rise to DOUT Valid
Propagation Delay Time
tDO1
CLOAD = 200pF
80
ns
SCLK Fall to DOUT Valid
Propagation Delay Time
tDO2
CLOAD = 200pF
80
ns
SCLK Rise to CS Fall Delay Time
tCS0
10
ns
CS Rise to SCLK Rise Hold Time
tCS1
40
ns
CS Pulse Width High
tCSW
100
ns
4
_______________________________________________________________________________________
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
(VDD = +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, output amplifier connected
in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
150
ns
SCLK Pulse Width High
tCH
75
ns
SCLK Pulse Width Low
tCL
75
ns
CS Fall to SCLK Rise Setup Time
tCSS
60
ns
SCLK Rise to CS Rise Hold Time
tCSH
0
ns
SDI Setup Time
tDS
60
ns
SDI Hold Time
tDH
0
ns
SCLK Rise to DOUT Valid
Propagation Delay Time
tDO1
CLOAD = 200pF
200
ns
SCLK Fall to DOUT Valid
Propagation Delay Time
tDO2
CLOAD = 200pF
200
ns
SCLK Rise to CS Fall Delay Time
tCS0
10
ns
CS Rise to SCLK Rise Hold Time
tCS1
75
ns
CS Pulse Width High
tCSW
150
ns
Note 1: Accuracy is guaranteed by the following table:
Accuracy Guaranteed
VDD
(V)
From Code:
To Code:
5
16
4095
3
33
4095
Note 2: Offset is measured at the code closest to 10mV.
Note 2: The temperature coefficient is determined by the “box” method, in which the maximum ∆VOUT over the temperature range
is divided by ∆T and the typical reference voltage.
Note 4: Accuracy is better than 1.0LSB for VOUT = 10mV to (VDD - 180mV). Guaranteed by PSR test on end points.
Note 5: RLOAD = ∞and digital inputs are at either VDD or DGND.
_______________________________________________________________________________________
5
MAX5122/MAX5123
TIMING CHARACTERISTICS—MAX5123 (+3V)
Typical Operating Characteristics
(VDD = +5V, RL = 5kΩ, CL = 100pF, output amplifier in unity-gain configuration, TA = +25°C, unless otherwise noted.)
MAX5122
DIFFERENTIAL NONLINEARITY vs.
DIGITAL INPUT CODE
0.10
DNL (LSB)
0.05
0.15
0
0
-0.05
-0.05
-0.10
-0.10
-0.15
-0.15
-0.20
1,000
2,000
3,000
4,000
2.500
2.495
0
1,000
2,000
3,000
4,000
-60 -40
5,000
-20
0
20
40
60
80
100
DIGITAL INPUT CODE
DIGITAL INPUT CODE
TEMPERATURE (°C)
MAX5122
SUPPLY CURRENT vs. TEMPERATURE
MAX5122
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5122
SHUTDOWN CURRENT vs. TEMPERATURE
350
(CODE = 000 HEX)
300
400
(CODE = AAA HEX)
350
(CODE = 000 HEX)
300
250
MAX5122/23 toc06
450
2.00
1.75
SHUTDOWN CURRENT (µA)
(CODE = AAA HEX)
400
MAX5122/23 toc05
450
500
SUPPLY CURRENT (µA)
MAX5122/23 toc04
500
1.50
1.25
1.00
0.75
0.50
0.25
250
200
-60
-40
-20
0
20
40
60
80
100
0
4.0
4.5
5.0
5.5
6.0
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
MAX5122
FULL-SCALE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX5122
FULL-SCALE OUTPUT ERROR vs. RESISTIVE LOAD
-60
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
MAX5122
DYNAMIC RESPONSE RISE TIME
2.505
2.500
2.495
0.25
FULL-SCALE OUTPUT ERROR (LSB)
RL = 5kΩ
CL = 100pF
MAX5122/23 toc07
MAX5122/23-09
2.510
MAX5122/23 toc08
SUPPLY CURRENT (µA)
5,000
2.505
2.490
-0.20
0
CS
5V/div
-0.50
OUT
1V/div
-1.25
-2.00
2.490
-60
-40
-20
0
20
40
TEMPERATURE (°C)
6
0.05
2.510
REFERENCE VOLTAGE (V)
0.10
MAX5122/23 toc02
0.15
INL (LSB)
0.20
MAX5122/23 toc01
0.20
MAX5122
REFERENCE VOLTAGE vs. TEMPERATURE
MAX5122/23 toc03
MAX5122
INTEGRAL NONLINEARITY vs.
DIGITAL INPUT CODE
FULL-SCALE OUTPUT (V)
MAX5122/MAX5123
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
60
80
100
0.1
1
10
100
2µs/div
RL (kΩ)
_______________________________________________________________________________________
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
MAX5122
MAJOR CARRY TRANSITION
MAX5122
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5122
DYNAMIC RESPONSE FALL TIME
MAX5122/23-11
MAX5122/23-10
SCLK
2V/div
CS
5V/div
OUT
1V/div
5µs/div
MAX5123
DIFFERENTIAL NONLINEARITY vs.
DIGITAL INPUT CODE
0.05
DNL (LSB)
0.10
0.05
0
0
-0.05
-0.10
-0.05
-0.10
-0.15
-0.15
-0.20
-0.25
-0.20
1,000
2,000
3,000
4,000
1.255
1.250
1.245
1.240
0
5,000
1.260
MAX5122/23 toc15
0.10
REFERENCE VOLTAGE (V)
0.15
MAX5122/23 toc14
0.20
MAX5123
REFERENCE VOLTAGE vs. TEMPERATURE
0.15
MAX5122/23 toc13
0.25
0
OUT
100mV/div
AC COUPLED
2µs/div
MAX5123
INTEGRAL NONLINEARITY vs.
DIGITAL INPUT CODE
1,000
2,000
3,000
4,000
5,000
-60 -40
-20
0
20
40
60
80
100
DIGITAL INPUT CODE
DIGITAL INPUT CODE
TEMPERATURE (°C)
MAX5123
SUPPLY CURRENT vs. TEMPERATURE
MAX5123
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5123
SHUTDOWN CURRENT vs. TEMPERATURE
SUPPLY CURRENT (µA)
(CODE = AAA HEX)
300
(CODE = 000 HEX)
250
350
300
(CODE = 000 HEX)
250
200
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
100
0.4
0.3
0.2
0.1
200
-60
MAX5122/23 toc18
(CODE = AAA HEX)
350
0.5
SHUTDOWN CURRENT (µA)
400
MAX5122/23 toc16
400
MAX5122/23 toc17
INL (LSB)
CS
2V/div
OUT
1mV/div
AC COUPLED
2µV/div
SUPPLY CURRENT (µA)
MAX5122/23-12
2.50
2.75
3.00
3.25
SUPPLY VOLTAGE (V)
3.50
-60
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX5122/MAX5123
Typical Operating Characteristics (continued)
(VDD = +5V, RL = 5kΩ, CL = 100pF, output amplifier in unity-gain configuration, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = +5V, RL = 5kΩ, CL = 100pF, output amplifier in unity-gain configuration, TA = +25°C, unless otherwise noted.)
MAX5123
FULL-SCALE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX5123
FULL-SCALE OUTPUT ERROR
vs. RESISTIVE LOAD
1.250
1.245
1.240
MAX5122/23-21
MAX5122/23 toc20
1.255
-1
CS
2V/div
-2
OUT
400mV/div
-3
-4
-60
-40
-20
0
20
40
60
80
100
0.01
0.1
TEMPERATURE (°C)
10
100
MAX5123
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5122/23-22
1µs/div
MAX5123
MAJOR CARRY TRANSITION
MAX5122/23-23
MAX5122/23-24
SCLK
2V/div
CS
2V/div
CS
2V/div
OUT
500µV/div
AC COUPLED
OUT
400mV/div
1µs/div
1
RL (kΩ)
MAX5123
DYNAMIC-RESPONSE FALL TIME
8
MAX5123
DYNAMIC-RESPONSE RISE TIME
0
FULL-SCALE OUTPUT ERROR (LSB)
MAX5122/23 toc19
1.260
FULL-SCALE OUTPUT (V)
MAX5122/MAX5123
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
2µs/div
OUT
100mV/div
AC COUPLED
5µV/div
_______________________________________________________________________________________
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
PIN
NAME
FUNCTION
1
FB
2
OUT
Analog Output Voltage. High impedance if part is in shutdown.
3
RSTVAL
Reset Value Input (Digital Input).
1: Connect to VDD to select midscale as the output reset value.
0: Connect to DGND to select 0V as the output reset value.
4
PDL
Power-Down Lockout (Digital Input).
1: Normal operation.
0: Disallows shutdown (device cannot be powered down).
5
CLR
Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTVAL) output state. Clearing the
DAC will cause it to exit a software shutdown state.
6
CS
Active-Low Chip-Select Input (Digital Input)
7
DIN
Serial Data Input. Data is clocked in on the rising edge of SCLK.
8
SCLK
Serial Clock Input
9
DGND
Digital Ground
10
DOUT
Serial Data Output
11
UPO
12
PD
13
AGND
14
REF
15
REFADJ
16
VDD
Amplifier Inverting Sense Input (Analog Input)
User-Programmable Output (Digital Output)
Power-Down Input (Digital Input). Pulling PD high when PDL = VDD places the IC into shutdown with a maximum shutdown current of 20µA.
Analog Ground
Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5V
(MAX5122) or +1.25V (MAX5123) nominal output, externally adjustable at REFADJ. In external reference
mode, disable the internal reference by pulling REFADJ to VDD and applying the external reference to REF.
Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to VDD when using an
external reference.
Positive Power Supply. Bypass with a 0.1µF capacitor in parallel with a 4.7µF capacitor to AGND.
_______________________________________________________________________________________
9
MAX5122/MAX5123
Pin Description
MAX5122/MAX5123
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
CS
PDL
PD
VDD AGND DGND
DIN SCLK
SR
CONTROL
DOUT
16-BIT
SHIFT REGISTER
RSTVAL
LOGIC
OUTPUT
UPO
DECODE
CONTROL
CLR
FB
12
MAX5122
MAX5123
BANDGAP 1.25V
REFERENCE
INPUT
REGISTER
2X
(X1)
4k
DAC
REGISTER
OUT
DAC
2.5V (1.25V)
REFERENCE
BUFFER
REFADJ
REF
( ) ARE FOR MAX5123 ONLY.
Figure 1. Simplified Functional Diagram
_______________Detailed Description
The MAX5122/MAX5123 12-bit, force/sense DACs are
easily configured with a 3-wire serial interface. They
include a 16-bit data-in/data-out shift register and have
a double-buffered digital input consisting of an input
register and a DAC register. In addition, these devices
employ precision bandgap references, as well as an
output amplifier with accessible feedback and output
pins that can be used to set the gain externally (Figure
1) or for forcing and sensing applications. These DACs
are designed with an inverted R-2R ladder network
(Figure 2) that produces a weighted voltage proportional to the digital input code.
Internal Reference
Both devices use an on-board precision bandgap reference with a low temperature coefficient of only
10ppm/°C (max) to generate an output voltage of +2.5V
(MAX5122) or +1.25V (MAX5123). The REF pin can
source up to 100µA and may become unstable with
capacitive loads exceeding 100pF. REFADJ can be
used for minor adjustments to the reference voltage.
FB
R
2R
2R
D0
R
2R
D9
OUT
R
2R
D10
2R
D11
REF*
AGND
NOTE: SHOWN FOR ALL 1s ON DAC.
*INTERNAL REFERENCE: +2.5V (MAX5122),
+1.25V (MAX5123); OR EXTERNAL REFERENCE
Figure 2. Simplified Inverted R-2R DAC Structure
10
______________________________________________________________________________________
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
External Reference
An external reference may be applied to the REF pin.
Disable the internal reference by pulling REFADJ to
VDD. This allows an external reference signal (AC- or
DC-based) to be fed into the REF pin. For proper operation, do not exceed the input voltage range limits of 0
to (VDD - 1.4V) for VREF.
Determine the output voltage using the following equation (REFADJ = VDD):
VOUT = VREF [(NB / 4096) G]
where NB is the numeric value of the MAX5122/
MAX5123 input code (0 to 4095), VREF is the external
reference voltage, and G is the gain of the output
amplifier, set by an external resistor-divider. The REF
pin has a minimum input resistance of 40kΩ and is
code-dependent.
Output Amplifier
The MAX5122/MAX5123’s DAC output is internally
buffered by a precision amplifier with a typical slew rate
of 0.6V/µs. Access to the output amplifier’s inverting
input (FB) provides the user greater flexibility with
amplifier gain setting and signal conditioning (see
Applications Information).
The output amplifier typically settles to ±0.5LSB from a
full-scale transition within 20µs when it is connected in
unity gain and loaded with 5kΩ 100pF. Loads less
than 1kΩ may result in degraded performance.
Power-Down Mode
These devices feature software- and hardware-programmable (PD pin) shutdown modes that reduce the
typical supply current to 3µA. To enter software shutdown mode, program the control sequence for the DAC
as shown in Table 1.
In shutdown mode, the amplifier output becomes highimpedance and the serial interface remains active.
Data in the input registers is saved, allowing the
MAX5122/MAX5123 to recall the output state prior to
entering shutdown when returning to normal operation.
To exit shutdown mode, load both input and DAC registers simultaneously or update the DAC register from the
input register. When returning from shutdown to normal
operation, wait 2ms for the reference to settle. When
using an external reference, the DAC requires only
20µs for the output to stabilize.
+3V
+5V
MAX5122
90k
400k
400k
100k
MAX5123
15k
REFADJ
33nF
Figure 3a. MAX5122 Reference Adjust Circuit
100k
REFADJ
33nF
Figure 3b. MAX5123 Reference Adjust Circuit
______________________________________________________________________________________
11
MAX5122/MAX5123
The circuit in Figure 3 achieves a nominal reference
adjustment range of ±1%. Connect a 33nF capacitor
from REFADJ to AGND to establish low-noise DAC
operation. Larger capacitor values may be used, but
will result in increased start-up delay. The time constant
(τ) for the start-up delay is determined by the REFADJ
input impedance of 4kΩ and CREFADJ:
τ= 4kΩ · CREFADJ
MAX5122/MAX5123
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
S0*
FUNCTION
C2
C1
C0
D11 ............... D0
S0*
0
0
0
XXXXXXXXXXXX
0
No operation.
0
0
1
12-Bit DAC Data
0
Load input register; DAC register unchanged.
0
1
0
12-Bit DAC Data
0
Simultaneously load input and DAC registers; exit shutdown.
0
1
1
XXXXXXXXXXXX
0
Update DAC register from input register; exit shutdown.
1
0
1
XXXXXXXXXXXX
0
Shutdown DAC (provided PDL = 1).
1
0
0
XXXXXXXXXXXX
0
UPO goes low (default).
1
1
0
XXXXXXXXXXXX
0
UPO goes high.
1
1
1
1XXXXXXXXXXX
0
Mode 1; DOUT clocked out on SCLK’s rising edge.
1
1
1
00XXXXXXXXXX
0
Mode 0; DOUT clocked out on SCLK’s falling edge (default).
X = Don’t care
* S0 is a sub-bit and always zero.
Power-Down Lockout Input (PDL)
The power-down lockout pin (PDL) disables shutdown
when low. When in shutdown mode, a high-to-low transition on PDL will wake up the DAC with its output still
set to the state prior to power-down. PDL can also be
used to wake up the device asynchronously.
Power-Down Input (PD)
Pulling PD high places the MAX5122/MAX5123 in shutdown. Pulling PD low will not return the MAX5122/
MAX5123 to normal operation. A high-to-low transition
on PDL or appropriate commands (Table 1) via the serial interface are required to exit power-down mode.
Serial-Interface Configuration
(SPI/QSPI/MICROWIRE/PIC16/PIC17)
The MAX5122/MAX5123 3-wire serial interface is compatible with SPI, QSPI, PIC16/PIC17 (Figure 4) and
MICROWIRE (Figure 5) interface standards. The 2byte-long serial input word contains three control bits,
12 data bits in MSB-first format, and one sub-bit, which
is always zero (Table 2).
The MAX5122/MAX5123’s digital inputs are double
buffered, which allows the user to:
• Load the input register without updating the DAC
register,
• Update the DAC register with data from the input
register,
• Update the input and DAC registers concurrently.
VDD
SS
DIN
MAX5122
MAX5123 SCLK
CS
( ) ARE FOR PIC16/PIC17 ONLY.
MOSI
SCK
SPI/QSPI
PORT
(PIC16/PIC17)
I/O
CPOL = 0, CPHA = 0
(CKE = 1, CKP = 0, SMP= 0
SSPM3 - SSPM0 = 0001)
Figure 4. SPI/QSPI Interface Connections (PIC16/PIC17)
SCLK
MAX5122
MAX5123
SK
MICROWIRE
PORT
DIN
SO
CS
I/O
Figure 5. MICROWIRE Interface Connections
12
______________________________________________________________________________________
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
MAX5122 and 6.6MHz for the MAX5123. Figure 7
depicts a more detailed timing diagram of the serial
interface.
PIC16 with SSP Module
and PIC17 Interface
The MAX5122/MAX5123 are compatible with a
PIC16/PIC17 microcontroller (µC), using the synchronous serial port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 4
and configure the PIC16/PIC17 as system master by initializing its synchronous serial port control register (SSPCON) and synchronous serial port status register
(SSPSTAT) to the bit patterns shown in Tables 3 and 4.
In SPI mode, the PIC16/PIC17 µCs allow eight bits of
data to be synchronously transmitted and received
simultaneously. Two consecutive 8-bit writings (Figure
6) are necessary to feed the DAC with three control bits,
12 data bits, and one sub-bit. DIN data transitions on
the serial clock’s falling edge and is clocked into the
DAC on SCLK’s rising edge. The first eight bits of DIN
contain the three control bits (C2, C1, C0) and the first
five data bits (D11–D7). The second 8-bit data stream
contains the remaining bits (D6–D0), and the sub-bit S0.
• The configuration of the device after shutdown.
The general timing diagram in Figure 6 illustrates how
data is acquired. CS must be low for the part to receive
data. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. When CS transitions
high, data is latched into the input and/or DAC registers, depending on the setting of the three control bits
C2, C1, and C0. The maximum serial clock frequency
guaranteed for proper operation is 10MHz for the
Table 2. Serial Data Format
MSB ............................................................................... LSB
⇐
⇒
16 BITS OF SERIAL DATA
Control Bits
MSB ..... Data Bits ..... LSB
Sub-Bit
C2, C1, C0
D11................................D0
S0
CS
COMMAND
EXECUTED
SCLK
1
DIN
C2
8
C1
C0 D11 D10
D9
D8
D7
9
D6
16
D5
D4
D3
D2
D1
D0
S0
Figure 6. Serial-Interface Timing
tCSW
CS
tCS0
tCSH
tCSS
tCS1
SCLK
tCH
tCL
tCP
DIN
tDS
tDO1
tDO2
tDH
DOUT
Figure 7. Detailed Serial-Interface Timing
______________________________________________________________________________________
13
MAX5122/MAX5123
The 16-bit input word may be sent in two 1-byte packets (SPI-, MICROWIRE-, and PIC16/PIC17-compatible),
with CS low during this period. The control bits C2, C1,
and C0 (table 1) determine:
• The clock edge on which DOUT transitions,
• The state of the user-programmable logic output,
MAX5122/MAX5123
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
Table 3. Detailed SSPCON Register Contents
CONTROL BIT
MAX5122/MAX5123
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPCON)
WCOL
BIT7
X
Write Collision Detection Bit
SSPOV
BIT6
X
Receive Overflow Detect Bit
SSPEN
BIT5
1
Synchronous Serial Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI as serialport pins.
Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
CKP
BIT4
0
SSPM3
BIT3
0
SSPM2
BIT2
0
SSPM1
BIT1
0
SSPM0
BIT0
1
Synchronous Serial Port Mode Select Bit. Sets SPI master mode
and selects fCLK = fOSC / 16
X = Don’t care
Table 4. Detailed SSPSTAT Register Contents
CONTROL BIT
MAX5130/MAX5131
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPSTAT)
SMP
BIT7
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
CKE
BIT6
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.
D/A
BIT5
X
Data Address Bit
P
BIT4
X
Stop Bit
S
BIT3
X
Start Bit
R/W
BIT2
X
Read/Write Bit Information
UA
BIT1
X
Update Address
BF
BIT0
X
Buffer Full Status Bit
X = Don’t care
Serial Data Output
User-Programmable Output (UPO)
The contents of the internal shift-register are output
serially on DOUT which allows for daisy-chaining of
multiple devices (see Applications Information) as well
as data readback. The MAX5122/MAX5123 may be
programmed to shift data out of DOUT on the serial
clock’s rising edge (Mode 1) or on the falling edge
(Mode 0). The latter is the default during power-up and
provides a lag of 16 clock cycles, maintaining SPI,
QSPI, MICROWIRE, and PIC16/PIC17 compatibility. In
Mode 1, the output data lags DIN by 15.5 clock cycles.
During power-down, DOUT retains its last digital state
prior to shutdown.
The UPO feature allows an external device to be controlled through the serial-interface setup (Table 1) thereby reducing the number of microcontroller I/O ports
required. During power-down, this output will retain the
last digital state before shutdown. With CLR pulled low,
UPO will reset to the default state after wake-up.
14
______________________________________________________________________________________
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (Figure 8a) is the deviation of the
values on an actual transfer function from a straight
line. This straight line can be either a best-straight-line
fit (closest approximation to the actual transfer curve)
or a line drawn between the endpoints of the transfer
function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every
single step.
Differential Nonlinearity (DNL)
Differential nonlinearity (Figure 8b) is the difference
between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than or equal
to 1LSB, the DAC guarantees no missing codes and is
monotonic.
Offset Error
The offset error (Figure 8c) is the difference between
the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.
Gain Error
Gain error (Figure 8d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corresponds to the same percentage error in each step.
7
ACTUAL
DIAGRAM
ANALOG OUTPUT VALUE (LSB)
ANALOG OUTPUT VALUE (LSB)
3
6
5
4
AT STEP
O11 (1/2 LSB )
3
2
AT STEP
001 (1/4 LSB )
1
ACTUAL
OFFSET POINT
0
000
001
010
011
100
101
110
2
IDEAL DIAGRAM
OFFSET ERROR
(+1 1/4 LSB)
1
IDEAL OFFSET
POINT
0
111
000
001
DIGITAL INPUT CODE
Figure 8a. Integral Nonlinearity
IDEAL FULL-SCALE OUTPUT
7
1 LSB
5
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
4
3
1 LSB
2
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
0
ANALOG OUTPUT VALUE (LSB)
ANALOG OUTPUT VALUE (LSB)
011
Figure 8c. Offset Error
6
1
010
DIGITAL INPUT CODE
GAIN ERROR
(-1 1/4 LSB)
6
IDEAL DIAGRAM
ACTUAL
FULL-SCALE
OUTPUT
5
4
0
000
001
010
011
100
101
000 100
DIGITAL INPUT CODE
Figure 8b. Differential Nonlinearity
101
110
111
DIGITAL INPUT CODE
Figure 8d. Gain Error
______________________________________________________________________________________
15
MAX5122/MAX5123
__________Applications Information
MAX5122/MAX5123
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its
new output value within the converter’s specified accuracy.
+5V/+3V
REF
VDD
50k
MAX5122
MAX5123
Digital Feedthrough
Digital feedthrough is noise generated on the DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
FB
50k
DAC
OUT
AGND
DGND
Unipolar Output
Figure 9 shows the MAX5122/MAX5123 setup for unipolar, Rail-to-Rail® operation with a closed- loop gain of
2V/V. With its internal reference of +2.5V, the MAX5122
provides a convenient unipolar output range of 0 to
+4.99878V, while the MAX5123 offers an output range of
0 to +2.49939V with its on-board +1.25V reference.
Table 5 lists example codes for unipolar output voltages.
NOTE: GAIN = +2V/V
Figure 9. Unipolar Output Circuit Using Internal
(+1.25V/+2.5V) or External Reference. With external reference,
pull REFADJ to VDD.
Bipolar Output
The MAX5122/MAX5123 can be configured for unitygain bipolar operation (FB = OUT) using the circuit
shown in Figure 10. The output voltage VOUT is then
given by the following equation:
VOUT = VREF [{G (NB / 4096)} - 1]
where NB is the numeric value of the DAC’s binary
input code, VREF is the voltage of the internal (or external) precision reference, and G is the overall gain. The
application circuit in Figure 10 uses a low-cost op amp
(MAX4162) external to the MAX5122/MAX5123.
Together with the MAX5122/MAX5123 this circuit offers
an overall gain of +2V/V. Table 6 lists example codes
for bipolar output voltages.
Reset (RSTVAL) and
Clear (CLR) Functions
The MAX5122/MAX5123 DACs feature a clear pin (CLR),
which resets the output to a certain value, depending
upon how RSTVAL is set. RSTVAL = DGND selects an
output of 0, and RSTVAL = VDD selects a midscale output when CLR is pulled low.
The CLR pin has a minimum input resistance of 40kΩ in
series with a diode to the supply voltage (VDD). If the
digital voltage is higher than the supply voltage for the
part, a small input current may flow, but this current will
be limited to (V CLR - VDD - 0.5V) / 40kΩ.
Note: Clearing the DAC will also cause the part to exit
a software shutdown (PD = 0).
+5V/+3V
50k
REF
VDD
FB
MAX5122
MAX5123
V+
VOUT
DAC
OUT
DGND
AGND
V-
MAX4162
Figure 10. Unity-Gain Bipolar Output Circuit Using Internal
(+1.25V/+2.5V) or External Reference. With external reference,
pull REFADJ to VDD.
Daisy-Chaining Devices
Any number of MAX5122/MAX5123s may be daisychained by simply connecting the serial data output pin
(DOUT) of one device to the serial data input pin (DIN)
of the following device in the chain (Figure 11).
Another configuration (Figure 12) allows several
MAX5122/MAX5123 DACs to share one common DIN
signal line. In this configuration, the data bus is common
to all devices; data is not shifted through a daisy-chain.
However, more I/O lines are required in this configuration, because each IC needs a dedicated CS line.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
16
50k
______________________________________________________________________________________
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
MAX5122/MAX5123
Table 5. Unipolar Code Table (Gain = +1.6384V/V)
DAC CONTENTS
ANALOG OUTPUT
INTERNAL REFERENCE
SUB-BIT
S0
MAX5122
MAX5123
EXTERNAL REFERENCE
MAX5122/MAX5123
1111 1111 1111
0
+4.99878V
+2.49939V
VREF (4095 / 4096) 2
1000 0000 0001
0
+2.50122V
+1.25061V
VREF (2049 / 4096) 2
1000 0000 0000
0
+2.5V
+1.25V
VREF (2048 / 4096) 2
0111 1111 1111
0
+2.49878V
+1.24939V
VREF (2047 / 4096) 2
0000 0000 0001
0
+1.2207mV
+610.35µV
VREF (1 / 4096) 2
0000 0000 0000
0
0V
0V
0
MSB
LSB
Table 6. Bipolar Code Table (Figure 10)
DAC CONTENTS
ANALOG OUTPUT
INTERNAL REFERENCE
SUB-BIT
S0
MAX5122
MAX5123
EXTERNAL REFERENCE
MAX5122/MAX5123
1111 1111 1111
0
+2.49878V
+1.24939V
VREF [ {2 (4095 / 4096)} - 1]
1000 0000 0001
0
+1.2207mV
+610.35µV
VREF [ {2 (2049 / 4096)} - 1]
1000 0000 0000
0
0V
0V
VREF [ {2 (2048 / 4096)} - 1]
0111 1111 1111
0
-1.2207mV
-610.35µV
VREF [ {2 (2047 / 4096)} - 1]
0000 0000 0001
0
-2.49878V
-1.24939V
VREF [ {2 (1 / 4096)} - 1]
0000 0000 0000
0
-2.5V
-1.25V
-VREF
MSB
LSB
SCLK
DIN
CS
SCLK
SCLK
I
II
III
MAX5122
MAX5123
MAX5122
MAX5123
MAX5122
MAX5123
DOUT
DIN
DOUT
CS
DIN
CS
DOUT
TO OTHER
SERIAL DEVICES
Figure 11. Daisy-Chaining Multiple Devices with the Digital I/Os DIN/DOUT
______________________________________________________________________________________
17
MAX5122/MAX5123
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
Using an External Reference
with AC Components
V DD ). Bypass the power supply (VDD) with a 4.7µF
capacitor in parallel with a 0.1µF capacitor to AGND.
Minimize lead lengths to reduce lead inductance.
The MAX5122/MAX5123 have multiplying capabilities
within the reference input voltage range specifications.
Figure 13 shows a technique for applying a sinusoidal
input to REF, where the AC signal is offset before being
applied to the reference input.
Layout Considerations
Digital and AC signals coupling to AGND can create
noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques,
such as a multilayer board with a low-inductance
ground plane. Wire-wrapped boards and sockets are
not recommended. If noise becomes an issue, shielding may be required.
Power-Supply and Bypassing
Considerations
On power-up, the input and DAC registers are cleared to
either zero (RSTVAL = DGND) or midscale (RSTVAL =
DIN
SCLK
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
I
CS
II
CS
MAX5122
MAX5123
III
CS
MAX5122
MAX5123
MAX5122
MAX5123
SCLK
SCLK
SCLK
DIN
DIN
DIN
Figure 12. Multiple Devices Share One Common Digital Input (DIN)
___________________Chip Information
+5V/
+3V
TRANSISTOR COUNT: 3308
SUBSTRATE CONNECTED TO AGND
+5V/+3V
26k
AC
REFERENCE
INPUT
500mVp-p
MAX495
10k
REF
VDD
FB
DAC
OUT
MAX5122
MAX5123
AGND
DGND
Figure 13. External Reference with AC Components
18
______________________________________________________________________________________
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
QSOP.EPS
______________________________________________________________________________________
19
MAX5122/MAX5123
Package Information
MAX5122/MAX5123
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.