Maxim MAX548ACPA 2.5v to 5.5v, low-power, single/dual, 8-bit voltage-output dacs in î¼max package Datasheet

19-1206; Rev 0; 3/97
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
____________________________Features
♦ +2.5V to +5.5V Single-Supply Operation
♦ ±1LSB (max) TUE
♦ Power-On Reset Clears All Registers to Zero
♦ Low Operating Current:
150µA (MAX548A/MAX549A, VREF = +2.5V)
75µA (MAX550A, VREF = +2.5V)
♦ 1µA Shutdown Mode
♦ 10MHz, 3-Wire Serial Interface Compatible with
SPI/QSPI and Microwire
♦ µMAX Package—50% Smaller than 8-Pin SO
♦ Independent Shutdown of DACs
(MAX548A/MAX549A)
The MAX548A/MAX549A/MAX550A’s low power consumption and small µMAX and DIP packages make
these devices ideal for portable and battery-powered
applications.
______________Ordering Information
MAX548ACPA
0°C to +70°C
8 Plastic DIP
________________________Applications
MAX548ACUA
MAX548AC/D
MAX548AEPA
MAX548AEUA
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
8 µMAX
Dice*
8 Plastic DIP
8 µMAX
Battery-Powered Systems
VCXO Control
Comparator-Level Settings
GaAs Amp Bias Control
PART
PIN-PACKAGE†
TEMP. RANGE
Ordering Information continued at end of data sheet.
*Dice are specified at TA = +25°C, DC parameters only.
†Contact factory for availability of 8-pin SO package.
Digital Gain and Offset Control
_____________________Selector Guide
FEATURE
MAX548A
MAX549A
MAX550A
Number of DACs
2
2
1
DAC Reference
VDD
External
External
Asynchronous
Load DAC Input
√
—
√
µMAX Package
√
√
√
_________________Pin Configurations
TOP VIEW
GND 1
8
VDD
7
OUTB
CS 3
6
LDAC
DIN 4
5
SCLK
OUTA 2
MAX548A
DIP/µMAX
SPI and QSPI are trademarks of Motorola Inc.
Microwire is a trademark of National Semiconductor Corp.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX548A/MAX549A/MAX550A
_______________General Description
The MAX548A/MAX549A/MAX550A serial, 8-bit voltageoutput digital-to-analog converters (DACs) operate from
a single +2.5V to +5.5V supply. Their ±1LSB TUE specification is guaranteed over temperature. Operating current (supply current plus reference current) is typically
75µA per DAC with VDD = 2.5V. In shutdown, the DAC
is disconnected from the reference, reducing current
drain to less than 1µA. The MAX548A/MAX549A allow
each DAC to be shut down independently.
The 10MHz, 3-wire serial interface is compatible with
SPI™/QSPI™ and Microwire™ interface standards.
Double-buffered inputs provide flexibility when updating the DACs; the input and DAC registers can be
updated individually or simultaneously.
The MAX548A is a dual DAC with an asynchronous
load input; it uses VDD as the reference input. The
MAX549A is a dual DAC with an external reference
input. The MAX550A is a single DAC with an external
reference input and an asynchronous load input.
MAX548A/MAX549A/MAX550A
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
ABSOLUTE MAXIMUM RATINGS
VDD, SCLK, DIN, CS, LDAC, OUT_ to GND ...............-0.3V to 6V
REF to GND ................................................-0.3V to (VDD + 0.3V)
Maximum Current (any pin) .............................................±50mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 9.09mW/°C above +70°C) .............727mW
µMAX (derate 4.10mW/°C above +70°C) .....................330mW
Operating Temperature Ranges
MAX5_ _AC_ A.....................................................0°C to +70°C
MAX5_ _AE_ A ..................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
8
Guaranteed
monotonic
Bits
MAX5_ _AEUA (Note 1)
±0.9
All others
±0.9
Differential Nonlinearity
DNL
Total Unadjusted Error
TUE
Zero-Code Error
ZCE
±1
LSB
Full-Scale Error
FSE
±1
LSB
VDD
V
MAX5_ _AEUA (Note 1)
±1
All others
±1
LSB
LSB
REFERENCE INPUT
Reference Input
Voltage Range
VREF
Reference Input Resistance
DAC Code = 55 Hex (Note 2)
RREF
Reference Input Current
DAC Code = 55 Hex (Note 3)
MAX549A/MAX550A for specified
performance
2.5
MAX549A
16.7
MAX550A
33.3
MAX549A
IREF
MAX550A
kΩ
VDD = VREF = 5.5V
330
550
VDD = VREF = 2.5V
150
250
VDD = VREF = 5.5V
165
275
VDD = VREF = 2.5V
75
125
µA
DAC OUTPUT
DAC Output Voltage Swing
DAC Output Resistance
ROUT
DAC Output Resistance
Matching
∆ROUT/
ROUT
MAX548A
0
VDD
MAX549A/MAX550A
0
VREF
MAX548A/MAX549A
V
33.3
kΩ
±0.2
%
DIGITAL INPUTS
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
IIN
Input Capacitance (Note 4)
CIN
2
0.7VDD
VIN = 0V or VDD
_______________________________________________________________________________________
V
0.3VDD
V
±1
µA
10
pF
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Digital Feedthrough and
Crosstalk
CS = high, all digital inputs from 0V to VDD
50
nV-sec
Voltage-Output Settling Time
To ±1/2LSB, CL = 20pF
4
µs
Voltage-Output Slew Rate
CL = 20pF
Wake-Up Time at Power-Up
CL = 20pF
VDD = 2.5V
1.4
VDD = 5.5V
3.1
V/µs
4
µs
POWER SUPPLIES
Supply Voltage Range
Supply Current (MAX548A)
Supply Current
(MAX549A/MAX550A)
VDD
Outputs unloaded, all inputs = GND or VDD
IDD
Outputs unloaded,
all inputs = GND or
VDD (Note 5)
IDD
Shutdown Current
2.5
5.5
VDD = 5.5V
330
550
VDD = 2.5V
150
250
Outputs unloaded, all inputs = GND or VDD;
VDD = 5.5V
0.3
10
Shutdown mode
0.3
V
µA
µA
µA
TIMING CHARACTERISTICS
(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Digital inputs switching from 0V to VDD.) (Figure 3) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Pulse Width High
tCH
40
ns
SCLK Pulse Width Low
tCL
40
ns
DIN to SCLK High Setup
tDS
30
ns
DIN to SCLK High Hold
tDH
VDD = 2.5V
0
VDD = 5.5V
10
ns
CS Low to SCLK High Setup
tCSS0
30
ns
CS High to SCLK High Setup
tCSS1
30
ns
SCLK High to CS Low Hold
tCSH0
10
ns
VDD = 2.5V
10
VDD = 5.5V
20
Delay, SCLK High to CS High
tCSH1
CS Pulse Width High
tCSW
40
ns
tCP
80
ns
SCLK Period
ns
LDAC Pulse Width Low
t LDAC
MAX548A/MAX550A only
50
ns
CS High to LDAC Low
tCSLD
MAX548A/MAX550A only
50
ns
5
µs
VDD High to CS Low
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Cold temperature specifications (to -40°C) guaranteed by design using six sigma design limits.
Worst-case input resistance at REF occurs at DAC code 55 hex.
Worst-case reference input current occurs at DAC code 55 hex.
Guaranteed by design. Not production tested.
IDD measured with DACs loaded with worst-case DAC code 55 hex.
_______________________________________________________________________________________
3
MAX548A/MAX549A/MAX550A
ELECTRICAL CHARACTERISTICS (continued)
__________________________________________Typical Operating Characteristics
(VDD = VREF = 2.5V, RL = 1MΩ, CL = 15pF, TA = +25°C, unless otherwise noted.)
OPERATING CURRENT PER DAC
vs. TEMPERATURE
SHUTDOWN CURRENT
vs. TEMPERATURE
MAX548A-550A TOC-02
200
SHUTDOWN CURRENT (nA)
VDD = VREF = 5.0V
149.8
240
MAX548A-550A TOC-01
149.4
75.4
75.0
160
VDD = VREF = 5.0V
120
40
36
32
VDD = VREF = 2.5V
74.6
VDD = VREF = 2.5V
28
-20
20
60
100
-60
20
60
TEMPERATURE (°C)
MAX549A/MAX550A
REFERENCE SMALL-SIGNAL
FREQUENCY RESPONSE
MAX549A/MAX550A
REFERENCE AC FEEDTHROUGH
vs. FREQUENCY
VDD = 2.5V
VREF = 100mVp-p SINE WAVE
0
0
-20
RELATIVE OUTPUT (dB)
10
-10
VDD = 5V
VREF = 2Vp-p SINE WAVE
-20
-20
TEMPERATURE (°C)
MAX548A-550A TOC-03
-60
-30
100
MAX548A-550A TOC-04
-40
-60
-80
-40
VREF = 1Vp-p SINE WAVE
DAC CODE = 00 hex
DAC CODE = FF hex
-50
10k
100k
-100
1M
10M
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
DIGITAL FEEDTHROUGH
SETTLING TIME (FALLING)
MAX548A-550A TOC-05
1k
DAC CODE FF hex to 00 hex
SCLK, 5V/div
1M
MAX548A-550A TOC-06
OPERATING CURRENT PER DAC (µA)
150.2
RELATIVE OUTPUT (dB)
MAX548A/MAX549A/MAX550A
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
OUT, 1V/div
OUT, 50mV/div
CS, 5V/div
200ns/div
4
2µs/div
_______________________________________________________________________________________
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
(VDD = VREF = 2.5V, RL = 1MΩ, CL = 15pF, TA = +25°C, unless otherwise noted.)
MAX548A-550A TOC-07
CODE = 00 hex
DAC CODE 00 hex to FF hex
MAX548A-550A TOC-08
SETTLING TIME (RISING)
OUTPUT GLITCH FILTERING
OUT, 1V/div
OUT, 50mV/div, CL = 0pF
OUT, 50mV/div, CL = 100pF
OUT, 50mV/div, CL = 220pF
OUT, 50mV/div, CL = 1000pF
CS, 5V/div
CS, 5V/div
2µs/div
5µs/div
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
MAX548A
MAX549A
MAX550A
1
1
1
GND
Ground
2
2
—
OUTA
DAC A Output Voltage
—
—
2
OUT
3
3
3
CS
Chip-Select Input. A logic low on CS enables serial data to be
clocked into the input shift register. Programming commands are
executed at CS’s rising edge.
4
4
4
DIN
Serial-Data Input. Data is clocked into the 16-bit input shift register on
SCLK’s rising edge.
5
5
5
SCLK
Serial-Clock Input. Data is clocked in on SCLK’s rising edge.
6
—
6
LDAC
Load DAC Input. After CS goes high and if programmed by the
control word, a falling edge on LDAC updates the DAC latch(es).
Connect LDAC to VDD if unused.
7
6
—
OUTB
DAC B Output Voltage
—
7
7
REF
External Reference Voltage Input for DAC(s)
8
8
8
VDD
Positive Power Supply (+2.5V to +5.5V)
DAC Output Voltage
_______________________________________________________________________________________
5
MAX548A/MAX549A/MAX550A
_____________________________Typical Operating Characteristics (continued)
MAX548A/MAX549A/MAX550A
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
_______________Detailed Description
The magnitude of the expected error is the ratio of the
DAC output resistance to the DC load resistance at the
output.
Typically, an energy pulse is coupled into the DAC output on CS’s rising edge. Since each DAC output is
unbuffered, connecting a small capacitor (200pF to
1000pF) from the output to ground creates a lowpass
filter that effectively suppresses the pulse for sensitive
applications (see Typical Operating Characteristics).
Analog Section
The MAX548A/MAX549A/MAX550A are 8-bit, voltageoutput digital-to-analog converters (DACs). The
MAX548A/MAX549A are dual DACs, and the MAX550A
is a single DAC. Each DAC consists of an R-2R ladder
network that converts 8-bit digital inputs into equivalent
analog output voltages in proportion to the applied reference voltage (Figure 1).
The DACs feature double-buffered inputs and
unbuffered outputs. The MAX549A/MAX550A require
an external reference. The MAX548A’s reference inputs
are internally connected to VDD . The power-supply
range is from +2.5V to +5.5V.
Shutdown Mode
When the MAX548A/MAX549A/MAX550A are in shutdown mode, the R-2R ladder disconnects from the reference source. The MAX549A/MAX550A supply current
does not change, but the REF input current decreases to
less than 1µA. This allows the externally applied system
reference to remain active with minimal power
consumption. The MAX548A supply current also
decreases to less than 1µA in shutdown mode. When the
MAX548A/MAX549A/MAX550A exit shutdown mode,
recovery time is equivalent to the DAC’s settling time.
Reference Input
The voltage applied at REF (VDD for the MAX548A) sets
the full-scale output for all the DACs and may range
from +2.5V to VDD. The REF input resistance is code
dependent, with the lowest value occurring with code
01010101 (55 hex). To minimize INL errors, the reference voltage source should have less than 3Ω output
impedance.
Serial Interface
The serial interface is SPI/QSPI and Microwire compatible. An active-low chip select (CS) enables the input
shift register to receive data from the serial input (DIN).
Data is clocked into the shift register on the rising edge
of the serial-clock signal (SCLK). The clock frequency
can be as high as 10MHz.
Transmit data MSB first in one 16-bit word or two 8-bit
bytes. The write cycle can be segmented to allow two
8-bit-wide transfers when CS remains low. After all 16
bits are clocked into the input shift register, a rising
DAC Output
The MAX548A/MAX549A/MAX550A contain DACs with
unbuffered outputs; each output connects directly to an
R-2R ladder. Typical output impedance is 33.3kΩ. This
configuration minimizes power consumption and
reduces offset errors. For highest accuracy, apply high
resistive loads (1MΩ and up). Lower resistive loads can
be driven, but output loading increases full-scale error.
R
2R
2R
2R
2R
R
R
R
R
2R
2R
R
R
2R
2R
2R
REF
OUT_
GND
GND
LSB
MSB
DAC_ REGISTER
NOTE: SWITCH POSITIONS SHOWN FOR DAC CODE FF HEX.
Figure 1. DAC Simplified Circuit Diagram
6
_______________________________________________________________________________________
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
Initialization
The MAX548A/MAX549A/MAX550A have an internal
power-on reset. At power-up, all internal registers are
reset to zero; therefore, an initialization write sequence
is not necessary.
Serial-Input Data Format and Control Codes
The control byte determines which input registers/DAC
registers are updated (Table 1). The DAC input registers are updated on the rising edge of CS. The DAC
registers can be updated on CS’s rising edge or on
LDAC’s falling edge after CS goes high. Bit C0 of the
control byte determines how the DAC registers are
updated for the MAX548A/MAX550A. The MAX549A
has no LDAC pin; the DAC registers are always updated on CS’s rising edge (C0 in the control byte has
no effect).
Tables 2, 3, and 4 list the serial-input command format
for the MAX548A, MAX549A, and MAX550A, respectively. The 16-bit input word consists of an 8-bit control
byte and an 8-bit data byte. The control byte is not
decoded internally. Every control bit performs one
Table 1. Control-Byte/Input-Word Bit Definitions
CONTROL BYTE
DATA
BYTE
X = Don’t care
BIT NAME
STATE
UB1*
X
Unassigned Bit 1
UB2
X
Unassigned Bit 2
UB3
X
Unassigned Bit 3
C2
0
Power-Up Mode
C2
1
Power-Down Mode
C1
0
DAC Register Load Operation Disabled
C1
1
DAC Register Load Operation Enabled
C0
0
DAC Register Updated on CS’s Rising Edge
C0
1
DAC Register Updated on LDAC’s Falling Edge (MAX549A = Don’t Care)
A1
0
Do Not Address DAC B (MAX550A = Don’t Care)
A1
1
Address DAC B (MAX550A = Don’t Care)
A0
0
Do Not Address DAC A
A0
1
Address DAC A
D7
—
DAC Data Bit 7 (MSB)
D6
—
DAC Data Bit 6
D5
—
DAC Data Bit 5
D4
—
DAC Data Bit 4
D3
—
DAC Data Bit 3
D2
—
DAC Data Bit 2
D1
—
DAC Data Bit 1
D0**
—
DAC Data Bit 0 (LSB)
*Clocked in first
OPERATION
**Clocked in last
_______________________________________________________________________________________
7
MAX548A/MAX549A/MAX550A
edge on CS programs the DAC. The input registers can
be loaded independently or simultaneously without
updating the DAC registers. This allows both DAC registers to be updated simultaneously with different digital
values. The DAC outputs reflect the data stored in the
DAC registers. LDAC can be used to asynchronously
update the DAC registers independently of CS
(MAX548A/MAX550A). With C1 set high, setting C0 in
the control word forces the DAC register(s) to be
updated on LDAC’s falling edge, rather than CS’s rising
edge (Table 1).
MAX548A/MAX549A/MAX550A
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
function. Data is clocked in starting with unassigned bit
1 (UB1), followed by the remaining control bits and the
DAC data byte. The data byte’s LSB (D0) is the last bit
clocked into the input register (Figure 2).
Table 5 is an example of a 16-bit input word that performs the following functions:
• Loads 80 hex (128 decimal) into the DAC input register (DAC A for the MAX548A/MAX549A)
• Updates the DAC register(s) on CS’s rising edge.
Table 6 shows how to calculate the output voltage
based on the input code. Figure 3 gives detailed timing
information.
INSTRUCTION
EXECUTED
CS
LDAC
MAX548A/
MAX550A
ONLY
1
8
OPTIONAL
PAUSE
9
16
SCLK
DIN
UB1 UB2 UB3 C2
C1
C0
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 2. Serial-Interface Timing Diagram
tLDAC
LDAC
tCSLD
CS
tCSW
tCSH0
tCSS0
tCSH1
tCH
SCLK
tCL
tDS
tCSS1
tDH
DIN
Figure 3. Detailed Serial-Interface Timing Diagram
8
_______________________________________________________________________________________
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
UB1
UB2
CONTROL BYTE
DATA BYTE
Loaded First
Loaded Last
UB3
C2
C1
LDAC
C0
A1
A0
D7........D0
Pin 6
MAX548A/MAX549A/MAX550A
Table 2. MAX548A Serial-Interface Programming Commands
COMMAND
(Commands executed on CS’s rising edge)
UNASSIGNED COMMANDS
X
X
X
0
0
X
0
0
XXXXXXXX
X
Unassigned command
X
X
X
1
X
X
0
0
XXXXXXXX
X
Unassigned operation
COMMANDS LOADING INPUT REGISTER(S) ONLY
X
X
X
0
0
X
0
1
8-Bit DAC Data
X
Load DAC A input register. DAC B input register
and both DAC registers unchanged.
X
X
X
0
0
X
1
0
8-Bit DAC Data
X
Load DAC B input register. DAC A input register
and both DAC registers unchanged.
X
X
X
0
0
X
1
1
8-Bit DAC Data
X
Load both DAC input registers. Both DAC registers unchanged.
COMMANDS UPDATING DAC REGISTER(S)
X
X
X
0
1
0
0
0
XXXXXXXX
X
Update both DAC registers with current contents
of their input registers. Both input registers
unchanged.
X
X
X
0
1
0
0
1
8-Bit DAC Data
X
Load DAC A input register and update both DAC
registers. DAC B input register unchanged.
X
X
X
0
1
0
1
0
8-Bit DAC Data
X
Load DAC B input register and update both DAC
registers. DAC A input register unchanged.
X
X
X
0
1
0
1
1
8-Bit DAC Data
X
Load both DAC input registers and update both
DAC registers.
X
X
X
0
1
1
0
0
XXXXXXXX
0
Update both DAC registers with current contents
of their input registers. Both input registers
unchanged.
X
X
X
0
1
1
0
1
8-Bit DAC Data
0
Load DAC A input register and update both DAC
registers. DAC B input register unchanged.
X
X
X
0
1
1
1
0
8-Bit DAC Data
0
Load DAC B input register and update both DAC
registers. DAC A input register unchanged.
X
X
X
0
1
1
1
1
8-Bit DAC Data
0
Load both DAC input registers and update both
DAC registers.
COMMANDS UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
X
X
X
0
1
1
0
0
XXXXXXXX
1
After CS’s rising edge and on LDAC’s falling
edge, update both DAC registers with current
contents of their input registers. Both input registers unchanged.
X
X
X
0
1
1
0
1
8-Bit DAC Data
1
Load DAC A input register. After CS’s rising edge
and on LDAC’s falling edge, update both DAC
registers.
X
X
X
0
1
1
1
0
8-Bit DAC Data
1
Load DAC B input register. After CS’s rising edge
and on LDAC’s falling edge, update both DAC
registers.
X
X
X
0
1
1
1
1
8-Bit DAC Data
1
Load both DAC input registers. After CS’s rising
edge and on LDAC’s falling edge, update both
DAC registers.
_______________________________________________________________________________________
9
MAX548A/MAX549A/MAX550A
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
Table 2. MAX548A Serial-Interface Programming Commands (continued)
COMMANDS FOR POWERING DOWN
UB1
UB2
CONTROL BYTE
DATA BYTE
Loaded First
Loaded Last
UB3
C2
C1
C0
A1
A0
D7........D0
LDAC
Pin 6
COMMAND
(Commands executed on CS’s rising edge)
COMMANDS POWERING DOWN AND LOADING INPUT REGISTER(S) ONLY
X
X
X
1
0
X
0
1
8-Bit DAC Data
X
Load DAC A input register and power down DAC
A. DAC B registers unchanged.
X
X
X
1
0
X
1
0
8-Bit DAC Data
X
Load DAC B input register and power down DAC
B. DAC A registers unchanged.
X
X
X
1
0
X
1
1
8-Bit DAC Data
X
Load both DAC input registers and power down
both DACs. Both DAC registers unchanged
COMMANDS POWERING DOWN AND UPDATING DAC REGISTER(S)
X
X
X
1
1
0
0
1
8-Bit DAC Data
X
Load DAC A input register, power down DAC A,
and update both DAC registers. DAC B input
register unchanged.
X
X
X
1
1
0
1
0
8-Bit DAC Data
X
Load DAC B input register, power down DAC B,
and update both DAC registers. DAC A input
register unchanged.
X
X
X
1
1
0
1
1
8-Bit DAC Data
X
Load both DAC input registers, power down both
DACs, and update both DAC registers.
X
X
X
1
1
1
0
1
8-Bit DAC Data
0
Load DAC A input register, power down
DAC A, and update both DAC registers. DAC B
input register unchanged.
X
X
X
1
1
1
1
0
8-Bit DAC Data
0
Load DAC B input register, power down
DAC B, and update both DAC registers. DAC A
input register unchanged.
X
X
X
1
1
1
1
1
8-Bit DAC Data
0
Load both DAC input registers and power down
both DACs. Update both DAC registers.
COMMANDS POWERING DOWN AND UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
X
X
X
1
1
1
0
1
8-Bit DAC Data
1
Load DAC A input register and power down DAC
A. While powered down, on LDAC’s falling edge,
update both DAC registers. DAC B input register
unchanged.
X
X
X
1
1
1
1
0
8-Bit DAC Data
1
Load DAC B input register and power down DAC
B. While powered down, on LDAC’s falling edge,
update both DAC registers. DAC A input register
unchanged.
X
X
X
1
1
1
1
1
8-Bit DAC Data
1
Load both DAC input registers and power down
both DACs. While powered down, on LDAC’s
falling edge, update both DAC registers.
X = Don’t care
10
______________________________________________________________________________________
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
UB1
UB2
CONTROL BYTE
DATA BYTE
Loaded First
Loaded Last
UB3
C2
C1
C0
A1
A0
D7........D0
0
X
0
0
XXXXXXXX
COMMAND
(Commands executed on CS’s rising edge)
UNASSIGNED COMMAND
X
X
X
X
Unassigned command
COMMANDS LOADING INPUT REGISTER(S) ONLY
X
X
X
0
0
X
0
1
8-Bit DAC Data
Load DAC A input register. DAC registers unchanged.
X
X
X
0
0
X
1
0
8-Bit DAC Data
Load DAC B input register. DAC registers unchanged.
X
X
X
0
0
X
1
1
8-Bit DAC Data
Load both DAC input registers. DAC registers
unchanged.
COMMANDS UPDATING DAC REGISTER(S)
Update both DAC registers with current contents of their
input registers. Both input registers unchanged.
X
X
X
X
1
X
0
0
XXXXXXXX
X
X
X
0
1
X
0
1
8-Bit DAC Data
Load DAC A input register and update both DAC
registers. DAC B input register unchanged.
X
X
X
0
1
X
1
0
8-Bit DAC Data
Load DAC B input register and update both DAC
registers. DAC A input register unchanged.
X
X
X
0
1
X
1
1
8-Bit DAC Data
Load both DAC input registers and update both DAC
registers.
COMMANDS POWERING DOWN AND LOADING INPUT REGISTER(S) ONLY
X
X
X
1
0
X
0
1
8-Bit DAC Data
Load DAC A input register and power down DAC A.
DAC B input register and both DAC registers unchanged.
X
X
X
1
0
X
1
0
8-Bit DAC Data
Load DAC B input register and power down DAC B.
DAC A input register and both DAC registers unchanged.
X
X
X
1
0
X
1
1
8-Bit DAC Data
Load both DAC input registers and power down both
DACs. Both DAC registers unchanged.
COMMANDS POWERING DOWN AND UPDATING DAC REGISTER(S)
X
X
X
1
1
X
0
1
8-Bit DAC Data
Load DAC A input register, power down DAC A, and
update both DAC registers. DAC B input register
unchanged.
X
X
X
1
1
X
1
0
8-Bit DAC Data
Load DAC B input register, power down DAC B, and
update both DAC registers. DAC A input register
unchanged.
X
X
X
1
1
X
1
1
8-Bit DAC Data
Load both DAC input registers, power down both DACs,
and update both DAC registers.
X = Don’t care
______________________________________________________________________________________
11
MAX548A/MAX549A/MAX550A
Table 3. MAX549A Serial-Interface Programming Commands
MAX548A/MAX549A/MAX550A
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
Table 4. MAX550A Serial-Interface Programming Commands
UB1
UB2
CONTROL BYTE
DATA BYTE
Loaded First
Loaded Last
UB3
C2
C1
LDAC
C0
A1
A0
D7........D0
Pin 6
COMMAND
(Commands executed on CS’s rising edge)
UNASSIGNED COMMANDS
X
X
X
0
0
X
X
0
XXXXXXXX
X
Unassigned command
X
X
X
1
X
X
X
0
XXXXXXXX
X
Unassigned operation
1
8-Bit DAC Data
X
Load DAC input register. DAC register unchanged.
COMMANDS LOADING INPUT REGISTER ONLY
X
X
X
0
0
X
X
COMMANDS LOADING DAC REGISTER
X
X
X
0
1
0
X
0
XXXXXXXX
X
Update DAC register with current contents of
input register. Input register unchanged.
X
X
X
0
1
0
X
1
8-Bit DAC Data
X
Load DAC input register and update DAC register.
X
X
X
0
1
1
X
0
XXXXXXXX
0
Update DAC register with current contents of
input register. Input register unchanged.
X
X
X
0
1
1
X
1
8-Bit DAC Data
0
Load DAC input register and update DAC register.
COMMANDS UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
X
X
X
0
1
1
X
0
XXXXXXXX
1
After CS’s rising edge and on LDAC’s falling
edge, update DAC register with current contents
of input register. Input register unchanged.
X
X
X
0
1
1
X
1
8-Bit DAC Data
1
Load DAC input register. After CS’s rising edge
and on LDAC’s falling edge, update DAC register.
COMMAND POWERING DOWN AND LOADING INPUT REGISTER ONLY
X
X
X
1
0
X
X
1
8-Bit DAC Data
X
Load DAC input register and power down DAC.
COMMANDS POWERING DOWN AND UPDATING DAC REGISTER
X
X
X
1
1
0
X
1
8-Bit DAC Data
X
Load DAC input register, power down DAC, and
update DAC register.
X
X
X
1
1
1
X
1
8-Bit DAC Data
0
Load DAC input register, power down DAC, and
update DAC register.
COMMAND POWERING DOWN AND UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
X
X
X
1
1
1
X
1
8-Bit DAC Data
Load DAC input register and power down DAC.
While powered down, on LDAC’s falling edge,
update DAC register.
1
X = Don’t care
Table 5. Example Input Word
CONTROL BYTE
DATA BYTE
Loaded First
Loaded Last
UB1
UB2
UB3
C2
C1
C0
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
0
1
0
0
1
1
0
0
0
0
0
0
0
X = Don’t care
12
______________________________________________________________________________________
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
Careful PC board layout minimizes crosstalk in DAC registers, the reference, and the digital inputs. Separate analog
traces by running ground traces between them. Make sure
that high-frequency digital lines are not routed parallel to
analog lines.
AC Considerations
Digital Feedthrough
High-speed data at any of the digital input pins can
couple through a DAC’s internal stray package capacitance and cause noise (digital feedthrough) at the DAC
output, even though LDAC and/or CS are held high
(see Typical Operating Characteristics). Test digital
feedthrough by holding LDAC and/or CS high and toggling the digital inputs from all 1s to all 0s.
__________Applications Information
Power-Supply
and Ground Considerations
Connect GND to the highest quality ground available.
Bypass VDD with a 0.1µF to 0.22µF capacitor to GND.
The reference input can be used without bypassing.
However, for optimum line/load-transient response and
noise performance, bypass the reference input with a
0.1µF to 4.7µF capacitor to GND.
Analog Feedthrough
Due to internal stray capacitance, higher frequency analog
input signals at REF can couple to the output, even when
the input digital code is all 0s. This condition is shown in
the MAX549A/MAX550A Reference AC Feedthrough vs.
Frequency graph in the Typical Operating Characteristics.
Test analog feedthrough by setting all DAC outputs to 0V
and sweeping REF.
Table 6. Analog Output vs. Code
DAC CONTENTS
ANALOG OUTPUT (V)
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
+VREF(129 / 256)
1
0
0
0
0
0
0
0
+VREF(128 / 256) = +VREF / 2
0
1
1
1
1
1
1
1
+VREF(127 / 256)
0
0
0
0
0
0
0
1
+VREF(1 / 256)
0
0
0
0
0
0
0
0
0
+VREF(255 / 256)
Note: 1LSB = VREF x 2-8 = VREF(1 / 256); ANALOG OUTPUT = +VREF(I / 256), where I = Integer Value of Digital Input.
_____________________________________________Pin Configurations (continued)
TOP VIEW
GND 1
OUTA 2
8
VDD
GND 1
7
REF
OUT 2
MAX549A
8
VDD
7
REF
MAX550A
CS 3
6
OUTB
CS 3
6
LDAC
DIN 4
5
SCLK
DIN 4
5
SCLK
DIP/µMAX
DIP/µMAX
______________________________________________________________________________________
13
MAX548A/MAX549A/MAX550A
Microprocessor Interfacing
The MAX548A/MAX549A/MAX550A serial interface is
SPI/QSPI and Microwire compatible. For SPI/QSPI, clear
the CPOL and CPHA bits (CPOL = 0 and CPHA = 0).
CPOL = 0 sets the clock idle state to zero, and CPHA =
0 changes data at SCLK’s falling edge. This is the
Microwire default condition. If a serial port is not available on your microprocessor, three bits of a parallel port
can be used to emulate a serial port by bit manipulation.
Operate the serial clock only when necessary, to minimize digital feedthrough at the DAC registers.
MAX548A/MAX549A/MAX550A
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
_________________________________________________________Functional Diagram
VDD
8
DAC A
INPUT
REGISTER
8
8
DAC A
REGISTER
DAC A
R-2R LADDER
OUTA
DIN
SCLK
INPUT
CS
SHIFT
REGISTER
LDAC
AND
CONTROL
MAX548A/
MAX550A
ONLY
REF
MAX549A/
MAX550A
ONLY
VDD
MAX548A
ONLY
8
DAC B
INPUT
REGISTER
8
8
DAC B
REGISTER
DAC B
R-2R LADDER
OUTB
MAX548A/
MAX549A
ONLY
MAX548A
MAX549A
MAX550A
GND
_Ordering Information (continued)
PART
TEMP. RANGE
MAX549ACPA
0°C to +70°C
8 Plastic DIP
PIN-PACKAGE
MAX549ACUA
MAX549AC/D
MAX549AEPA
MAX549AEUA
MAX550ACPA
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
8 µMAX
Dice*
8 Plastic DIP
8 µMAX
8 Plastic DIP
MAX550ACUA
MAX550AC/D
MAX550AEPA
MAX550AEUA
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
8 µMAX
Dice*
8 Plastic DIP
8 µMAX
___________________Chip Information
TRANSISTOR COUNT: 1562
*Dice are specified at TA = +25°C, DC parameters only.
14
______________________________________________________________________________________
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
PDIPN.EPS
______________________________________________________________________________________
15
MAX548A/MAX549A/MAX550A
________________________________________________________Package Information
___________________________________________Package Information (continued)
8LUMAXD.EPS
MAX548A/MAX549A/MAX550A
+2.5V to +5.5V, Low-Power, Single/Dual,
8-Bit Voltage-Output DACs in µMAX Package
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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