19-4924; Rev 1; 2/10 TION KIT EVALUA BLE A IL A V A IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET Features The MAX5972A provides a complete interface for a powered device (PD) to comply with the IEEE® 802.3af/ at standard in a power-over-Ethernet (PoE) system. The MAX5972A provides the PD with a detection signature, classification signature, and an integrated isolation power switch with inrush current control. During the inrush period, the MAX5972A limits the current to less than 180mA before switching to the higher current limit (720mA to 880mA) when the isolation power MOSFET is fully enhanced. The device features an input UVLO with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition during power-on/-off conditions. The MAX5972A can withstand up to 100V at the input. S IEEE 802.3af/at Compliant The MAX5972A supports a 2-event classification method as specified in the IEEE 802.3at standard and provides a signal to indicate when probed by Type 2 power-sourcing equipment (PSE). The device detects the presence of a wall adapter power-source connection and allows a smooth switch over from the PoE power source to the wall power adapter. S Thermally Enhanced, 5mm x 5mm, 16-Pin TQFN The MAX5972A also provides a power-good (PG) signal, two-step current limit and foldback, overtemperature protection, and di/dt limit. MAX5972AETE+ S PoE Classification 0 to 5 S 100V Input Absolute Maximum Rating S Inrush Current Limit of 180mA Maximum S Current Limit During Normal Operation Between 720mA and 880mA S Current Limit and Foldback S Legacy UVLO at 36V S Overtemperature Protection Ordering Information PART PINPACKAGE -40NC to +85NC 16 TQFN-EP* –– 1 VDD 2 DET 3 I.C. 4 N.C. N.C. 15 14 13 + MAX5972A EP* VSS 6 7 8 RTN N.C. 16 RTN TOP VIEW N.C. Pin Configuration 5 WiMAX is a trademark of WiMAX Forum. IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc. SLEEP MODE +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. IP Phones, Wireless Access Nodes, IP Security Cameras WiMAXK Base Station TEMP RANGE VSS Applications IEEE 802.3af/at-Powered Devices S Simplified Wall Adapter Interface N.C. The MAX5972A is available in a 16-pin, 5mm x 5mm, TQFN power package. This device is rated over the -40NC to +85NC extended temperature range. S 2-Event Classification or an External Wall Adapter Indicator Output 12 CLS 11 2EC 10 PG 9 WAD TQFN (5mm × 5mm) *EP = EXPOSED PAD. CONNECT TO VSS. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX5972A General Description MAX5972A IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET ABSOLUTE MAXIMUM RATINGS VDD to VSS...........................................................-0.3V to +100V DET, RTN, WAD, PG, 2EC to VSS........................ -0.3V to +100V CLS to VSS...............................................................-0.3V to +6V Maximum Current on CLS (100ms maximum)..................100mA Continuous Power Dissipation (TA = +70NC) (Note 1) 16-Pin TQFN (derate 28.6mW/NC above +70NC) Multilayer Board......................................................2285.7mW Package Thermal Resistance (Note 2) BJA. ..............................................................................35NC/W BJC..............................................................................2.7NC/W Operating Temperature Range........................... -40NC to +85NC Maximum Junction Temperature......................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s)............................... +300NC Note 1: Maximum power dissipation is obtained using JEDEC JESD51-5 and JESD51-7 specifications. Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = (VDD - VSS) = 48V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 FA kI DETECTION MODE Input Offset Current Effective Differential Input Resistance IOFFSET dR VIN = 1.4V to 10.1V (Note 4) VIN = 1.4V up to 10.1V with 1V step, VDD = RTN = WAD = PG = 2EC (Note 5) 23.95 25.00 25.50 22.0 22.8 23.6 CLASSIFICATION MODE Classification Disable Threshold VTH,CLS VIN rising (Note 6) Classification Stability Time Classification Current 0.2 ICLASS VIN = 12.5V to 20.5V, VDD = RTN = WAD = PG = 2EC V ms Class 0, RCLS = 615I 0 3.96 Class 1, RCLS = 117I 9.12 11.88 Class 2, RCLS = 66.5I 17.2 19.8 Class 3, RCLS = 43.7I 26.3 29.7 Class 4, RCLS = 30.9I 36.4 43.6 Class 5, RCLS = 21.3I 52.7 63.3 mA TYPE 2 (802.3at) CLASSIFICATION MODE Mark Event Threshold VTHM VIN falling 10.1 Hysteresis on Mark Event Threshold 10.7 11.6 0.84 Mark Event Current IMARK VIN falling to enter mark event, 5.2V P VIN P 10.1V 0.25 Reset Event Threshold VTHR VIN falling 2.8 V V 0.85 mA 4 5.2 V 60 V 0.27 0.55 mA POWER MODE VIN Supply Voltage Range VIN Supply Current IQ 2 _______________________________________________________________________________________ IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET (VIN = (VDD - VSS) = 48V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) MIN TYP MAX UNITS VIN Turn-On Voltage PARAMETER VON VIN rising 34.3 35.4 36.6 V VIN Turn-Off Voltage VOFF VIN falling 30 V (Note 7) 4.2 V VIN falling from 40V to 20V (Note 8) 30 tDELAY = minimum PG current pulse width after entering into power mode 80 VIN Turn-On/-Off Hysteresis VIN Deglitch Time SYMBOL VHYST_UVLO tOFF_DLY Inrush to Operating Mode Delay tDELAY Isolation Power MOSFET On-Resistance RON_ISO RTN Leakage Current IRTN_LKG CONDITIONS IRTN = 600mA 120 Fs 96 112 TJ = +25NC 0.7 1.1 TJ = +85NC 0.9 1.5 I TJ = +125NC 1.15 10 FA VRTN = 12.5V to 30V ms CURRENT LIMIT Inrush Current Limit Current Limit During Normal Operation IINRUSH ILIM Foldback Threshold During initial turn-on period, VRTN = 1.5V 90 135 180 mA After inrush completed, VRTN = 1V 720 800 880 mA VRTN (Note 9) 13 16.5 V VWAD rising, VIN = 14V to 48V (referenced to RTN) 8 LOGIC WAD Detection Threshold VWAD-REF WAD Detection Threshold Hysteresis WAD Input Current 0.725 VWAD = 10V (referenced to RTN) 2EC Sink Current V2EC = 3.5V (referenced to RTN), VSS unconnected 2EC Off-Leakage Current V2EC = 48V PG Sink Current VRTN = 1.5V, VPG = 0.8V, during inrush period PG Off-Leakage Current VPG = 60V 10 V VWAD falling, VRTN = 0V, VSS unconnected IWAD-LKG 9 1 125 1.5 230 3.5 FA 2.25 mA 1 FA 375 FA 1 FA THERMAL SHUTDOWN Thermal-Shutdown Threshold Thermal-Shutdown Hysteresis TSD TJ rising +140 NC TJ falling +28 NC This device is 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design. The input offset current is illustrated in Figure 1. Effective differential input resistance is defined as the differential resistance between VDD and VSS. See Figure 1. Classification current is turned off whenever the device is in power mode. UVLO hysteresis is guaranteed by design, not production tested. A 20V glitch on input voltage that takes VDD below VON shorter than or equal to tOFF_DLY does not cause the MAX5972A to exit power-on mode. Note 9: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload condition across VDD and RTN. Note Note Note Note Note Note 3: 4: 5: 6: 7: 8: _______________________________________________________________________________________ 3 MAX5972A ELECTRICAL CHARACTERISTICS (continued) MAX5972A IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET IIN dRi = 1V (VINi + 1 - VINi) = (IINi + 1 - IINi) (IINi + 1 - IINi) IOFFSET = IINi - VINi dRi IINi + 1 dRi IINi IOFFSET VINi 1V VIN VINi + 1 Figure 1. Effective Differential Input Resistance/Offset Current Typical Operating Characteristics (VIN = (VDD - VSS) = 54V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to VSS.) SIGNATURE RESISTANCE vs. INPUT VOLTAGE 0.2 TA = -40NC 25.0 TA = +25NC 24.5 0.1 TA = +85NC 24.0 0 0 2 4 6 2 TA = -40NC TA = +85NC 0 TA = +25NC -2 -4 2 0 10 8 4 4 6 8 10 0 2 VIN (V) VIN (V) CLASSIFICATION CURRENT vs. INPUT VOLTAGE CLASS 5 60 4 6 VIN (V) CLASSIFICATION SETTLING TIME MAX5972A toc05 MAX5972A toc04 70 MAX5972A toc03 25.5 RSIGNATURE (kI) IIN (mA) 0.3 IIN = IVDD + IDET RDET = 24.9kI RTN = 2EC = PG = WAD = VDD INPUT OFFSET CURRENT (FA) IIN = IVDD + IDET RDET = 24.9kI RTN = 2EC = PG = WAD = VDD -40°C P TA P +85NC 0.4 26.0 MAX5972A toc01 0.5 INPUT OFFSET CURRENT vs. INPUT VOLTAGE MAX5972A toc02 DETECTION CURRENT vs. INPUT VOLTAGE VIN 10V/div 0V IIN (mA) 50 CLASS 4 40 30 CLASS 3 20 CLASS 2 IIN 0A 200mA/div VCLS 1V/div CLASS 1 10 0V CLASS 0 RCLS = 30.9I 0 0 5 10 15 20 25 30 100Fs/div VIN (V) 4 _______________________________________________________________________________________ 8 10 IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET 2EC SINK CURRENT vs. 2EC VOLTAGE PG SINK CURRENT vs. PG VOLTAGE TA = +25NC TA = -40NC TA = +85NC 1.2 0.8 TA = +85NC 200 150 VSS UNCONNECTED V2EC REFERENCED TO RTN VWAD = 14V 0.4 100 0 10 20 30 40 50 50 60 0 10 20 30 40 50 60 V2EC (V) VPG (V) INRUSH CURRENT LIMIT vs. RTN VOLTAGE NORMAL OPERATION CURRENT LIMIT vs. RTN VOLTAGE 900 MAX5972A toc08 150 800 CURRENT LIMIT (mA) 130 MAX5972A toc09 0 INRUSH CURRENT LIMIT (mA) TA = +25NC 250 IPG (FA) I2EC (mA) 1.6 MAX5972A toc07 TA = -40NC 300 MAX5972A toc06 2.0 110 90 700 600 500 400 300 70 200 50 0 10 20 30 40 50 100 60 0 10 20 30 40 50 VRTN (V) VRTN (V) INRUSH CONTROL WAVEFORM WITH TYPE 2 CLASSIFICATION ENTERING POWER MODE WITH TYPE 2 CLASSIFICATION MAX5972A toc11 MAX5972A toc10 USING TYPICAL APPLICATION CIRCUIT 2EC PULLED UP TO VDD WITH 10kI 0V V2EC 50V/div USING TYPICAL APPLICATION CIRCUIT 2EC PULLED UP TO VDD WITH 10kI VRTN 50V/div 0V IRTN 100mA/div 0V VPG 0V 10V/div V2EC 0V 40V/div VRTN 0V 50V/div IRTN 0A 200mA/div 0A 200µs/div 60 VDD 50V/div VDD 0V 50V/div 20ms/div _______________________________________________________________________________________ 5 MAX5972A Typical Operating Characteristics (continued) (VIN = (VDD - VSS) = 54V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to VSS.) MAX5972A IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET Pin Description PIN NAME 1, 13–16 N.C. No Connection. Not internally connected. 2 VDD 3 DET Positive Supply Input. Connect a 68nF (min) bypass capacitor between VDD and VSS. Detection Resistor Input. Connect a signature resistor (RDET = 24.9kI) from DET to VDD. 4 I.C. Internally Connected. Leave unconnected. 5, 6 VSS Negative Supply Input. VSS connects to the source of the integrated isolation n-channel power MOSFET. 7, 8 RTN Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power MOSFET. Connect RTN to the downstream DC-DC converter ground as shown in the Typical Application Circuit. WAD Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment VDD - VSS crosses the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation n-channel power MOSFET turns off, 2EC current sink turns on. Connect WAD directly to RTN when the wall power adapter or other auxiliary power source is not used. 9 FUNCTION PG Open-Drain Power-Good Indicator Output. PG sinks 230FA to disable the downstream DC-DC converter while turning on the hot-swap MOSFET switch. PG current sink is disabled during detection, classification, and in the steady-state power mode. The PG current sink is turned on to disable the downstream DC-DC converter when the device is in sleep mode. 11 2EC Active-Low 2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is enabled at 2EC when a Type 2 PSE or a wall adapter is detected. When powered by a Type 2 PSE, the 2EC current sink is enabled after the isolation MOSFET is fully on until VIN drops below the UVLO threshold. 2EC is latched when powered by a Type 2 PSE until VIN drops below the reset threshold. 2EC also asserts when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. 2EC is not latched if asserted by WAD. 12 CLS Classification Resistor Input. Connect a resistor (RCLS) from CLS to VSS to set the desired classification current. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification. –– EP Exposed Pad. Do not use EP as an electrical connection to VSS. EP is internally connected to VSS through a resistive path and must be connected to VSS externally. To optimize power dissipation, solder the exposed pad to a large copper power plane. 10 6 _______________________________________________________________________________________ IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET VDD VDD EN CLS CLASSIFICATION VDD 2EC D SET Q CLR Q D SET Q CLR Q 5V REGULATOR 1.5mA VDD 5V PG 46µA DET VON/VOFF VDD 230µA VDD THERMAL SHUTDOWN tDELAY R S WAD Q 9V VSS ISWITCH RTN ISOLATION SWITCH K x ISWITCH MAX5972A S I0 1/K I1 MUX _______________________________________________________________________________________ 7 MAX5972A Simplified Block Diagram IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET MAX5972A Typical Operating Circuit 2-EVENT CLASSIFICATION DETECTION GND VDD RJ-45 AND BRIDGE RECTIFIER 2EC/WAD DET MAX5972A 1.5mA WAD GND ENABLE DC-DC CONVERTER CLS SMAJ58A 24V/48V BATTERY RCLS -54V IN+ PG RDET 24.9kI 68nF 2EC VSS Detailed Description Operating Modes Depending on the input voltage (VIN = VDD - VSS), the MAX5972A operates in four different modes: PD detection, PD classification, mark event, and PD power. The device enters PD detection mode when the input voltage is between 1.4V and 10.1V. The device enters PD classification mode when the input voltage is between 12.6V and 20V. The device enters PD power mode once the input voltage exceeds VON. Detection Mode (1.4V ≤ VIN ≤ 10.1V) In detection mode, the power source equipment (PSE) applies two voltages on VIN in the range of 1.4V to 10.1V (1V step minimum) and then records the current measurements at the two points. The PSE then computes DV/DI to ensure the presence of the 24.9kω signature resistor. Connect the signature resistor (RDET) from VDD to DET for proper signature detection. The MAX5972A pulls DET low IN- RTN in detection mode. DET goes high impedance when the input voltage exceeds 12.5V. In detection mode, most of the MAX5972A internal circuitry is off and the offset current is less than 10µA. If the voltage applied to the PD is reversed, install protection diodes at the input terminal to prevent internal damage to the MAX5972A (see the Typical Application Circuit). Since the PSE uses a slope technique (DV/DI) to calculate the signature resistance, the DC offset due to the protection diodes is subtracted and does not affect the detection process. Classification Mode (12.6V ≤ VIN ≤ 20V) In the classification mode, the PSE classifies the PD based on the power consumption required by the PD. This allows the PSE to efficiently manage power distribution. Class 0 to 5 is defined as shown in Table 1. (The IEEE 802.3af/at standard defines only Class 0 to 4 and Class 5 for any special requirement.) An external resistor (RCLS) connected from CLS to VSS sets the classification current. 8 _______________________________________________________________________________________ IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET IEEE 802.3at PD CLASSIFICATION CURRENT SPECIFICATION (mA) CLASS MAXIMUM POWER USED BY PD (W) RCLS (I) VIN* (V) MIN MAX MIN 0 0.44 to 12.95 615 12.6 to 20 0 4 0 5 1 0.44 to 3.94 117 12.6 to 20 9 12 8 13 21 CLASS CURRENT SEEN AT VIN (mA) MAX 2 3.84 to 6.49 66.5 12.6 to 20 17 20 16 3 6.49 to 12.95 43.7 12.6 to 20 26 30 25 31 4 12.95 to 25.5 30.9 12.6 to 20 36 44 35 45 5 > 25.5 21.3 12.6 to 20 52 64 51 68 *VIN is measured across the MAX5972A input VDD to VSS. The PSE determines the class of a PD by applying a voltage at the PD input and measuring the current sourced out of the PSE. When the PSE applies a voltage between 12.6V and 20V, the MAX5972A exhibits a current characteristic with a value shown in Table 1. The PSE uses the classification current information to classify the power requirement of the PD. The classification current includes the current drawn by RCLS and the supply current of the MAX5972A so the total current drawn by the PD is within the IEEE 802.3af/at standard figures. The classification current is turned off whenever the device is in power mode. 2-Event Classification and Detection During 2-event classification, a Type 2 PSE probes PD for classification twice. In the first classification event, the PSE presents an input voltage between 12.6V and 20.5V and the MAX5972A presents the programmed load ICLASS. The PSE then drops the probing voltage below the mark event threshold of 10.1V and the MAX5972A presents the mark current (IMARK). This sequence is repeated one more time. When the MAX5972A is powered by a Type 2 PSE, the 2-event identification output 2EC asserts low after the internal isolation n-channel MOSFET is fully turned on. 2EC current sink is turned off when VDD goes below the UVLO threshold (VOFF) and turns on when VDD goes above the UVLO threshold (VON), unless VDD goes below VTHR to reset the latched output of the Type 2 PSE detection flag. Alternatively, the 2EC output also serves as a wall adapter detection output when the MAX5972A is powered by an external wall power adapter. See the Wall Power Adapter Detection and Operation section for more information. Power Mode (Wake Mode) The MAX5972A enters power mode when VIN rises above the undervoltage lockout threshold (VON). When VIN rises above VON, the MAX5972A turns on the internal n-channel isolation MOSFET to connect VSS to RTN with inrush current limit internally set to 135mA (typ). The isolation MOSFET is fully turned on when the voltage at RTN is near VSS and the inrush current is reduced below the inrush limit. Once the isolation MOSFET is fully turned on, the MAX5972A changes the current limit to 800mA. The open-drain power-good output (PG) remains low for a minimum of tDELAY until the power MOSFET fully turns on to keep the downstream DC-DC converter disabled during inrush. Undervoltage Lockout The MAX5972A operates up to a 60V supply voltage with a turn-on UVLO threshold (VON) at 35.4V and a turn-off UVLO threshold (VOFF) at 31V. When the input voltage is above VON, the MAX5972A enters power mode and the internal MOSFET is turned on. When the input voltage goes below VOFF for more than tOFF_DLY, the MOSFET turns off. Power-Good Output An open-drain output (PG) is used to allow disabling downstream DC-DC converter until the n-channel isolation MOSFET is fully turned on. PG is pulled low to VSS for a period of tDELAY and until the internal isolation MOSFET is fully turned on. The PG is also pulled low during sleep mode and coming out of thermal shutdown. Thermal-Shutdown Protection The MAX5972A includes thermal protection from excessive heating. If the junction temperature exceeds the thermal-shutdown threshold of +140NC, the MAX5972A _______________________________________________________________________________________ 9 MAX5972A Table 1. Setting Classification Current MAX5972A IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET Applications Information turns off the internal power MOSFET and 2EC current sink. When the junction temperature falls below +112NC, the devices enter inrush mode and then return to power mode. Inrush mode ensures the downstream DC-DC converter is turned off as the internal power MOSFET is turned on. Operation with 12V Adapter Layout Procedure Careful PCB layout is critical to achieve high efficiency and low EMI. Follow these layout guidelines for optimum performance: Wall Power Adapter Detection and Operation 1) Place the input capacitor, classification resistor, and transient voltage suppressor as close as possible to the MAX5972A. For applications where an auxiliary power source such as a wall power adapter is used to power the PD, the MAX5972A features wall power adapter detection. The MAX5972A gives highest priority to the WAD and smoothly switches the power supply to WAD when it is detected. Once the input voltage (VDD - VSS) exceeds the mark event threshold, the MAX5972A enables wall adapter detection. The wall power adapter is connected from WAD to RTN. The MAX5972A detects the wall power adapter when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is detected, the internal n-channel isolation MOSFET turns off, 2EC current sink turns on, and classification current is disabled if VIN is in the classification range. 2) Use large SMT component pads for power dissipating devices such as the MAX5972A and the external diodes. 3) Use short and wide traces for high-power paths. 4) Use the MAX5972A evaluation kit layout as a reference. 5) Place enough vias in the pad for the EP of the MAX5972A so that heat generated inside can be effectively dissipated by the PCB copper. The recommended spacing for the vias is 1mm to 1.2mm pitch. The thermal vias should be plated (1oz copper) and have a small barrel diameter (0.3mm to 0.33mm). 2-EVENT CLASSIFICATION (ASSERTED ON) GND VDD RJ-45 AND BRIDGE RECTIFIER GND ENABLE 2EC/WAD DET MAX5972A 1.5mA DC-DC CONVERTER WAD CLS SMAJ58A 12V BATTERY RCLS -54V IN+ PG RDET 24.9kI 68nF 2EC VSS IN- RTN THIS CIRCUIT ACHIEVES PROPER 2EC LOGIC WHEN BATTERY IS < 12.5V Figure 2. Typical Configuration When Using a 12V Wall Power Adapter 10 ������������������������������������������������������������������������������������� IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET ISOLATED 2-EVENT CLASSIFICATION OUTPUT GND GND 2EC VDD PG PG VAC 24.9kI 68nF MAX5972A WAD 1.5mA CLS SMAJ58A VAC DET 2EC/WAD 24/48V BATTERY 43.7I VSS -54V GND 33kI 1.37MI 249I 4.7µF 0.1µF 51.5kI ULVO/EN IN UFLG FB 10kI CS COMP 0.1µF MAX15000 0.1µF 22µF VCC VCC ISOLATED RTN 22.1I NDRV GND CS CS ISOLATED +5.3V/2A GND RTN PG RTN RTN RT 649I 619I 1kI 18.1kI 8.2nF 0.75I 8.06kI 330pF 0.1µF 4.99kI VCC 4.99kI 1kI RTN 100pF 33nF 8.06I 1kI 2.49kI 2.2nF RTN ISOLATED RTN ______________________________________________________________________________________ 11 MAX5972A Typical Application Circuit MAX5972A IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 16 TQFN-EP T1655+4 21-0140 12 ������������������������������������������������������������������������������������� IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET REVISION NUMBER REVISION DATE 0 8/09 Initial release 1 2/10 Removed the MAX5972B from the data sheet. DESCRIPTION PAGES CHANGED — 1–16 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products 13 Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX5972A Revision History