Jun. 2001
Edition 0.2
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F76UL
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DESCRIPTION
The Fujitsu MB15F76UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 6000MHz and a
1500MHz prescalers. Both IF and RF PLL section have a 1/4 divider. And a 16/17 or a 32/33 for the 6000MHz
prescaler, and a 4/5 or a 8/9 for the 1500MHz prescaler can be selected for the prescaler that enables pulse swallow
operation.
The latest BiCMOS process is used, as a result, a supply current is typically 9.0mA typ. at 3.0V. The supply voltage
range is from 2.7V to 3.6V. A refined charge pump supplies well-balanced output current with 1.5mA and 6mA
selectable by serial data. Fast locking is acheived for adopting the new circuit.
The new package(BCC20) decreases a mount area of MB15F76UL more than 30% comparing with the former
BCC16(for dual PLL).
MB15F76UL is ideally suited for wireless communications, such as W-LAN.
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FEATURES
• High frequency operation: RF synthesizer : 6000MHz max
IF synthesizer : : 1500MHz max
• Low power supply voltage: V C C = 2.7 to 3.6 V
• Ultra Low power supply current : I C C = 9.0 mA typ. (VCC = V p =3.0V, Ta=25°C, SW=0 in RF, IF locking state)
• Direct power saving function : Power supply current in power saving mode
Typ. 0.1 µA(Vcc=Vp=3.0V, Ta=25°C), Max. 10 µA(Vcc=Vp=3.0V)
• Dual modulus prescaler : 6000MHz prescaler(16/17 or 32/33, and 1/4divider)
•
1500MHz prescaler(4/5 or 8/9, and 1/4divider)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 5-bit swallow counter: 0 to 31
- Binary 13-bit programmable counter: 3 to 8191
• On-chip phase comparator for fast lock and low noise
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to 85°C
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20-pad, Plastic BCC
(LCC-20P-M05)
1
Jun. 2001
Edition 0.2
MB15F76UL
n
PIN ASSIGNMENT
Data
OSCIN
GND Clock
finIF
1
XfinIF
2
GNDIF
3
VccIF
4
PSIF
5
VpIF
6
20 19 18 17
TOP
VIEW
7
8
9 10
DoIF
DoRF
VpRF
LD/fout
LCC-20P-M05
2
16
LE
15
finRF
14
Xfin RF
13
GNDRF
12
VCCRF
11
PSRF
Jun. 2001
Edition 0.2
n
MB15F76UL
PIN DESCRIPTIONS
Pin
No.
Pin
name
I/O
1
fin IF
I
Prescaler input pin for the IF-PLL section.
Connection to an external VCO should be AC coupling.
2
Xfin IF
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
3
GNDIF
-
Ground for the IF-PLL section.
4
Vcc I F
-
Power supply voltage input pin for the IF-PLL section(except for the
charge pump circuit), the shift register and the oscillator input buffer.
When power is OFF, latched data of IF-PLL is lost.
5
PSIF
I
Power saving mode control for the IF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PSIF = ”H” ; Normal mode PSI F = ”L” ; Power saving mode
6
Vp I F
-
Power supply voltage input pin for the IF-PLL charge pump.
7
Do IF
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
8
LD/fout
O
Lock detect signal output(LD)/ phase comparator monitoring outut
(fout). The output signal is selected by a LDS bit in a serial data.
LDS bit = "1" ; outputs fout signal LDS bit = "0" ; outputs LD sihnal
9
DoR F
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
10
VpRF
-
Power supply voltage input pin for the RF-PLL charge pump.
11
PS R F
I
Power saving mode control for the RF-PLL section. This pin must be
set at ”L” Power-ON. (Open is prohibited.)
PSRF = ”H” ; Normal mode PSR F = ”L” ; Power saving mode
12
VccRF
-
Power supply voltage input pin for the RF-PLL section(except for the
charge pump circuit).
13
GNDR F
-
Ground for the RF-PLL section.
14
XfinR F
I
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
15
finR F
I
Prescaler input pin for the RF-PLL.
Connction to an external VCO should be AC coupling.
16
LE
I
Load enable signal input (with the schmitt trigger circuit.)
When LE is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data.
Descriptions
17
Data
I
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
18
Clock
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the
clock.
19
OSCIN
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
20
GND
-
Ground for OSC input buffer and the shift registor circuit.
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Jun. 2001
Edition 0.2
MB15F76UL
n
BLOCK DIAGRAM
VCCIF
(4)
PS IF (5)
3-bit latch
Intermittent
mode
control
LDS
(IF–PLL)
SW IF FC IF
5-bit latch
13-bit latch
Binary 5-bit
swallow counter
Binary 13-bit
programmable
counter (IF–PLL)
(IF–PLL)
fp IF
Vp I F
(6)
GNDI F
(3)
Phase
comp.
Charge Current
pump Switch
(IF–PLL)
(IF–PLL)
(7) DoIF
Prescaler
(IF–PLL)
4/5,8/9
finIF (1)
XfinIF (2)
2-bit latch
14-bit latch
1-bit latch
1/4divider
T1
T2
Lock
Det.
(IF–PLL)
C/P
setting
current
Binary 14–bit programmable ref.
counter(IF–PLL)
LD IF
fr I F
OSCin(19)
Fast
lock
tuning
AND
OR
T1
finRF (15)
T2
1/4divider
XfinRF (14)
2-bit latch
Binary 14-bit programmable ref.
counter (RF–PLL)
C/P
setting
current
14-bit latch
1-bit latch
Prescaler
Selector
LD
frIF
frRF
(8) LD/fout
fp IF
fp RF
Lock
Det.
fr R F
(RF–PLL)
(RF–PLL)
64/65,
128/129
LDS SW RF FCRF
PS RF
(11)
Intermittent
mode
control
Binary 5-bit
swallow counter
(RF–PLL)
3-bit latch
5-bit latch
Binary 13-bit
programmable
counter (RF–PLL)
Phase
comp.
(RF–PLL)
fp RF
Fast
lock
tuning
Charge Current
pump
Switch
(RF–PLL)
13-bit latch
(RF–PLL)
LE (16)
Schmitt
circuit
Data (17)
Schmitt
circuit
Clock (18)
Schmitt
circuit
Latch selector
C
N
C
N
1
2
23-bit shift
register
(20)
GND
4
(12)
VccRF
(13)
(10)
GNDRF
Vp RF
(9) Do RF
Jun. 2001
Edition 0.2
n
MB15F76UL
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
VC C
–0.5 to +4.0
V
Vp
Vcc to +4.0
V
VI
–0.5 to VC C +0.5
V
VO
GND to V cc
V
LD/fout
VDO
GND to Vp
V
Do
Tstg
–55 to +125
°C
Power supply voltage
Input voltage
Output voltage
Storage temperature
Remark
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Remark
3.6
V
VCCRF = VCCIF
3.0
3.6
V
GND
–
VC C
V
–40
–
+85
°C
Min.
Typ.
Max.
VC C
2.7
3.0
Vp
Vcc
Input voltage
VI
Operating temperature
Ta
Power supply voltage
Handling Precautions
(1)
VccRF,VpRF,VccIF and VpIF must supply equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to both Vcc RF,VpRF, VccIF and VpIF to keep them
equal. It is recommended that the non-use PLL is controlled by power saving function.
(2)
To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
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Jun. 2001
Edition 0.2
MB15F76UL
n
ELECTRICAL CHARACTERISTICS
(V C C = 2.7 to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
"H" level Input voltage
"L" level Input voltage
"L" level Input current
"H" level output voltage
mA
ICCRF
finR F =4750MHz
Vcc R F=VpR F =3.0V
–
7.0
–
mA
IPSIF
PSIF=PSRF = ”L”
–
0.1 *2
10
µA
IPSRF
PSIF=PSRF = ”L”
–
0.1
10
µA
fin IF *3
fin IF
IF PLL
100
–
1500
MHz
finR F *3
finR F
RF PLL
2000
–
6000
MHz
OSC IN
fosc
3
–
40
MHz
finIF
Pfin IF
IF PLL, 50 Ω system
-15
–
+2
dBm
finR F
PfinR F
RF PLL, 50 Ω system
-10
–
+2
dBm
OSC IN
VOSC
0.5
–
VC C
Vp-p
Data,
Clock,
LE
VIH
Vcc ×
0.7+0.4
–
–
–
–
Vcc×
0.3-0.4
Data,
Clock,
LE, PS
OSC IN
VIL
–
–
Schmitt trigger input
Schmitt trigger input
"L" level output voltage
High impedance
cutoff current
"H"level Output current
"L" level Output current
*2
VIH
–
Vcc×
0.7
–
–
VIL
–
–
–
Vcc×
0.3
IIH *4
–
–1.0
–
+1.0
IIL *4
–
–1.0
–
+1.0
IIH
–
0
–
+100
IIL *4
–
–100
–
0
VO H
VC C =Vp =3.0V, IO H =–1mA
Vcc –
0.4
–
–
VOL
VC C =Vp =3.0V, IOL =1mA
–
–
0.4
Do IF
Do R F
VD O H
VC C =Vp =3.0V, ID O H =-0.5mA
Vp –
0.4
–
–
VDOL
VC C =Vp =3.0V, IDOL =0.5mA
–
–
0.4
Do IF
Do R F
IOFF
VC C =Vp =3.0V,
VOFF =0.5V to V p–0.5V
–
–
2.5
IO H*4
VC C = Vp = 3.0V
–
–
-1.0
IO L
VC C = Vp = 3.0V
1.0
–
–
LD/fout
"L" level output voltage
"H" level output voltage
Unit
–
"L" level Input voltage
"H" level Input current
Max.
2.0
PS
"L" level Input current
Typ.
–
"H" level Input voltage
"H" level Input current
Min.
finIF =570MHz
Vcc I F=VpIF =3.0V
Power saving current *9
Input sensitivity
Value
ICCIF
Power supply current* 1
Operating frequency
Condition
LD/fout
V
V
µA
µA
V
V
nA
mA
(Continued)
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Jun. 2001
Edition 0.2
MB15F76UL
(Continued)
Ta =(V C C = 2.7 to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
"H"level Output current
ID O H*4
Do TX *8
Do RX
"L" level Output current
IDOL
Charge pump
current rate
Min.
Typ.
Max.
CS bit ="1"
-8.2
-6.0
-4.1
CS bit ="0"
-2.2
-1.5
-0.8
VC C =Vp
CS bit ="1"
=3.0 V
VDOL =Vp /2
CS bit ="0"
Ta= 25°C
4.1
6.0
8.2
0.8
1.5
2.2
VC C =Vp
=3.0 V
VD O H =Vp /2
Ta= 25°C
Unit
mA
ID O L/ID O H
ID O M T*5
VD O =Vp/2
–
3
–
%
vs VDO
IDOVD *6
0.5V < VDO < Vp-0.5V
–
10
–
%
vs Ta
IDOTA *7
-40°C < Ta < 85 °C,
VD O =Vp/2
–
5
–
%
Conditions; fosc=10MHz, Ta = 25°C, SW="L" in locking state.
Vcc I F=VpIF =VccRF =VpR F=3.0V, fosc=10MHz, Ta = 25°C, in power saving mode.
AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency.
The symbol "-"(minus) means direction of current flow.
Vcc=Vp=3.0V, Ta=25°C ( ||I3| - |I4|| ) / [( |I 3 | + |I4| )/2] x 100(%)
Vcc=Vp=3.0V, Ta=25°C [( ||I 2 | - |I 1 || ) /2 ] / [( |I 1 | + |I2 | )/2] x 100(%) (Applied to each I DOL , ID O H)
Vcc=Vp=3.0V, [(||IDO(85C) | - |I DO(-40C) ||) /2] / [(|I DO(85C) | + |I DO(-40C) |) /2] x 100(%) (Applied to each ID O L, ID O H )
When Charge pump current is measured, set LDS="0", T1="0" and T2="1".
PSIF=PSRF =GND (VIL=GND and VIH=Vcc for Clock, Data, LE)
I2
I3
IDOL
I1
IDOH
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
Value
Condition
I1
I4
I2
0.5
VP/2
Output voltage(V)
VP-0.5
VP
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Jun. 2001
Edition 0.2
MB15F76UL
n
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fVCO = {(P x N) + A} x 4 x fOSC ÷ R
fVCO :
P:
N:
A:
fOSC:
R:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of dual modulus prescaler (4 or 8 for IF-PLL, 16 or 32 for RF-PLL)
Preset divide ratio of binary 13-bit programmable counter (3 to 8,191)
Preset divide ratio of binary 5-bit swallow counter (0≤ A ≤ 31, condition;A < N)
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable
signal , the data stored in the shift register is transferred to one of latch of them depending upon the control bit data
setting.
Table1. Control Bit
Control bit
Destination of serial data
CN1
CN2
0
0
The programmable reference counter for the IF-PLL.
1
0
The programmable reference counter for the RF-PLL.
0
1
The programmable counter and the swallow counter for the IF-PLL
1
1
The programmable counter and the swallow counter for the RF-PLL
Shift Register Configuration
Programmable Reference Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20
21
22
23
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
C
S
X
X
X
X
CN1, 2
: Control bit
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, 2
: LD/fout output setting bit
CS
: Charge pump current select bit
X
: Dummy bits(Set "0" or "1")
NOTE: Data input with MSB first.
8
[Table. 1]
[Table. 2]
[Table. 3]
[Table. 8]
Jun. 2001
Edition 0.2
MB15F76UL
Programmable Counter
LSB
MSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
C
N
1
C
N
2
L
D
S
S
W
F
C
A
1
A
2
A
3
A
4
A
5
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
N
12
N
13
IF/RF IF/RF
CN1, 2
N1 to N13
A1 to A5
SWIF/RF
: Control bit
: Divide ratio setting bits for the programmable counter (3 to 8,191)
: Divide ratio setting bits for the swallow counter (0 to 31)
: Divide ratio setting bit for the prescaler
(4/5 or 8/9 for the SW IF , 16/17 or 32/33 for the SWRF)
FC IF/RF
: Phase control bit for the phase detector(IF : FC IF, RF : FC RF)
LDS
: LD/fout signal select bit
NOTE: Data input with MSB first.
[Table.
[Table.
[Table.
[Table.
1]
4]
5]
6]
[Table. 7]
[Table. 3]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 3 is prohibited.
Table.3 LD/fout output Selectable Bit Setting
LD/fout pin state
LDS
T1
T2
0
0
0
0
1
0
0
1
1
frIF
1
0
0
fr RF
1
1
0
fpIF
1
0
1
fp RF
1
1
1
LD output
fout
output
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Jun. 2001
Edition 0.2
MB15F76UL
Table.4 Binary 13-bit Programmable Counter Data Setting
Divide
ratio
(N)
N
13
N
12
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
3
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
8191
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 3 is prohibited.
Table.5 Binary 5-bit Swallow Counter Data Setting
Divide
ratio
(N)
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
1
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
31
1
1
1
1
1
Note: • Divide ratio (A) range = 0 to 31
Table. 6 Prescaler Data Setting
Prescaler
divide ratio
SW = ”1”
SW = ”0”
IF-PLL
4/5
8/9
RF-PLL
16/17
32/33
Table. 7 Phase Comparator Phase Switching Data Setting
FC IF,RF = 1
FC IF,RF = 0
1
DoIF,RF
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO polarity
1
2
Note: • Z = High–impedance
• Depending upon the VCO and LPF polarity,
FC bit should be set.
10
VCO Output
Frequency
2
VCO Input Voltage
Jun. 2001
Edition 0.2
MB15F76UL
Table. 8 Charge Pump Current Setting
CS
Current value
1
+ 6.0 mA
0
+ 1.5 mA
4. Power Saving Mode (Intermittent Mode Control Circuit)
Table 9. PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the single PLL, the lock detector, LD, remains high, indicating a locked condition.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal
from the phase detector when it returns to normal operation.
Note: When power (VCC ) is first applied, the device must be in standby mode, PS=Low, for at least 1µs.
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Jun. 2001
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MB15F76UL
Note: • PS pin must be set at “L” for Power ON.
OFF
ON
tv > 1µs
Vcc
Clock
Data
LE
tps > 100ns
PS
(1)
(2)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1µs later after power supply remains stable(Vcc > 2.2V).
(3) Relase power saving mode (PS: L → H) 100nS later after setting serial data.
12
(3)
Jun. 2001
Edition 0.2
n
MB15F76UL
SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit Invalid data
Data
LSB
MSB
Clock
LE
t2
t1
t4
t3
t5
t7
t6
On the rising edge of the clock, one bit of data is transferred into the shift register.
Parameter
Min.
t1
20
t2
Typ.
Max.
Unit
Parameter
Min.
–
–
ns
t5
100
20
–
–
ns
t6
t3
30
–
–
ns
t7
t4
30
–
–
ns
Typ.
Max.
Unit
–
–
ns
20
–
–
ns
100
–
–
ns
Note: LE should be "L" when the data is transferred into the shift register.
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MB15F76UL
n
PHASE DETECTOR OUTPUT WAVEFORM
fr IF/RF
fp IF/RF
tWU
tWL
LD
(FC bit = 1)
H
DoIF/RF
Z
L
(FC bit = 0)
DoIF/RF
Z
LD Output Logic Table
IF–PLL section
RF–PLL section
LD output
Locking state / Power saving state
Locking state / Power saving state
H
Locking state / Power saving state
Unlocking state
L
Unlocking state
Locking state / Power saving state
L
Unlocking state
Unlocking state
L
Note: • Phase error detection range = −2π to +2π
• Pulses on DoIF/RF signals are output to prevent dead zone.
• LD output becomes low when phase error is tW U or more.
• LD output becomes high when phase error is t W L or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency as follows.
tWU > 2/fosc: i.e. tW U > 200ns when foscin = 10 MHz
tWL < 4/fosc: i.e. t W L < 400ns when foscin = 10 MHz
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MB15F76UL
TEST CIRCUIT(Prescaler input/Programmable reference divider input sensitivity test)
Controller
S.G
S.G
50Ω
1000pF
1000pF
50Ω
1000pF
S.G
GND OSCIN Clock Data
finIF
1
XfinIF
2
GNDIF
3
VccIF
VccIF
0.1µ
(Divide ratio setting)
1000pF
16
LE
15
finRF
14
XfinRF
4
13
GNDRF
PSIF
5
12
VccRF
VpIF
6
11
PSRF
VpIF
0.1µ
20
19
18
17
MB15F76UL
MB15F74UL
7
8
9
10
DoIF LD/fout Do RF VpRF
VpRF
50Ω
1000pF
VccRF
0.1µ
0.1µ
Oscilloscope
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Edition 0.2
MB15F76UL
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APPLICATION EXAMPLE
1000pF
TCXO
From controller
GND OSCIN Clock Data
1000pF
1000pF
3.0V
0.1µ
finIF
1
XfinIF
2
GNDIF
3
VccIF
20
19
18
17
16
LE
15
finRF
14
XfinRF
4
13
GND RF
PSIF
5
12
VccRF
VpIF
6
11
PSRF
MB15F74UL
MB15F76UL
7
8
9
10
1000pF
3.0V
0.1µ
3.0V
0.1µ
1000pF
DoIF LD/fout DoRF VpRF
3.0V
0.1µ
LPF
VCO
Output
VCO
Output
Lock Det.
LPF
Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation
when open-circuited in the input).
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Jun. 2001
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MB15F76UL
PACKAGE DIMENSION
20 pin, Plastic BCC
(LCC-20P-M05)
* : These dimensions do not include resin protrusion.
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