Fujitsu MB90634A 16-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13601-5E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90630A Series
MB90632A/634A/P634A
■ DESCRIPTION
The MB90630A series are 16-bit microcontrollers designed for high speed real-time processing in consumer
product applications such as controlling video cameras, VCRs, or copiers. The series uses the F2MC*-16L CPU.
The chips incorporate an eight channels 10-bit A/D converter, two channels 8-bit D/A converter, UART two
channels, two channels serial interface, 8/16-bit up/down counter, 16-bit I/O timer (two channels input capture,
four channels output compare, and one channel 16-bit free-run timer).
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
F2MC-16L CPU
• Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication), maximum multiplier = 4
• Instruction set optimized for controller applications
Object code compatibility with F2MC-16(H)
Wide range of data types (bit, byte, word, and long word)
Improved instruction cycles provide increased speed
Additional addressing modes: 23 modes
High code efficiency
Access mothods (bank access, linear pointer)
(Continued)
■ PACKAGE
100-pin Plastic LQFP
100-pin Plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB90630A Series
(Continued)
High precision operations are enhanced by use of a 32-bit accumulator
Extended intelligent I/O service (access area extended to 64 KB)
Maximum memory space: 16 MB
• Enhanced high level language (C) and multitasking support insturctions
Use of a system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Improved execution speed: Four byte instruction queue
• Powerful interrupt function
• Automatic data transfer function that does not use insturction (IIOS)
Internal peripherals
• ROM:
32 Kbytes (MB90632A)
64 Kbytes (MB90634A)
One-time PROM: 64 Kbytes (MB90P634A)
• RAM:
1 Kbytes (MB90632A)
2 Kbytes (MB90634A)
3 Kbytes (MB90P634A)
• General-purpose ports: 82 ports max.
• 10-bit A/D converter (RC successive approximation): eight channels (10-bit resolution, conversion time =
5.2 µs at 4 MHz with a × 4 multiplier)
• 8-bit D/A converter two channels (8-bit resolution)
• UART (can also be used as a serial port) two channels
• I/O expansion serial interface two channels
• 8/16-bit PPG (can be set to either 8-bit × two channels or 16-bit × one channel) one channel
• 16-bit I/O timer one channel
(two channels input capture, four channels output compare, and one channel free-run timer)
• Clock output generator
• Timebase counter/watchdog timer (18-bit)
• Low-power consumption modes
• The device types are classified by the initial value of the oscillation stabilization delay time.
Oscillation stabilization delay time initial value = 2.05 ms: MB90630A series (MB90632A/634A/P634A)
• Package: LQFP-100 (QFP-100 planned)
• CMOS technology
2
MB90630A Series
■ PRODUCT LINEUP
Part number
Parameter
Classification
MB90P634A
MB90632A
OTPROM
MB90634A
Mask ROM
ROM size
64 Kbyte
32 Kbyte
64 Kbyte
RAM size
3 Kbyte
1 Kbyte
2 Kbyte
CPU functions
Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
Interrupt processing time
Ports
I/O ports (CMOS/TTL)
: 82 ports
Input pull-up resistors available
: 24 ports
Can be set as open-drain outputs : 8 ports
(
Package
: 340
: 8/16 bits
: 1/7 bytes
: 1/4/8/16/32 bits
: 62.5 ns/4 MHz (PLL multiplier = 4)
: 1000 ns/16 MHz (minimum)
)
FPT-100P-M05
FPT-100P-M06
A/D converter
10-bit resolution, 5.2 µs conversion time (at 4 MHz with a ×4 multiplier)
RC successive approximation, 8 channels (multiplexed inputs)
D/A converter
8-bit resolution
R-2R type, 2 channels (independent)
UART
Serial interface
8/16-bit PPG
8/16-bit up/down
counter
Full-duplex, double-buffered (8-bit), internal baud rate correction circuit that uses the
operating clock
NRZ-type transfer, supports MIDI frequencies, 2 channels
8-bit data register. LSB-first or MSB-first operation can be selected.
The transfer shift clock can be input externally.
The internal shift clock includes a built-in operating clock correction circuit. 1 channel
Can operate as two independent channels in 8-bit mode.
Can also be used as a single-channel 16-bit PPG. 1 channel
6 event inputs. Can operate as two independent 8-bit up/down counter channels. Can
also be used as a single-channel 16-bit counter. Includes reload and compare functions.
1 channel
16-bit I/O timer
Consists of 2 × input capture, 4 × output compare, and 1 × free-run timer. 1 channel
Timer functions
Timebase timer/watchdog timer (18-bit)
Low-power
consumption modes
Oscillation
stabilization delay
time
External interrupt
PLL function
Other
Includes sleep, stop, and hardware standby functions
The initial value of the oscillation stabilization delay time is 64 ms.
The oscillation stabilization delay time can also be set to 0 ms, 2.05 ms, 8.19 ms, or
64 ms (for an crystal oscillator).
The MB90630A series are for FAR oscillators.
8 inputs
External interrupt mode
(Interrupts can be generated from four different types of request signal)
Selectable multiplier: 1/2/3/4
(Set a multiplier that does not exceed the assured operation frequency range.)
VPP is shared with the MD2 pin
(for EPROM programming)
—
—
3
MB90630A Series
■ PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P21/A17
P20/A16
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
PA4
PA3/OUT3
PA2/OUT2
(TOP VIEW)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P71/SOT3
P72/SCK3
DVRH
DVSS
P73/DAO0
P74/DAO1
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
P52/AN2
P53/AN3
VSS
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P80/IRQ0
P81/IRQ1
MD0
MD1
MD2
HST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC
P45/SCK1
P46/ADTG
P47
P70/SIN3
(FPT-100P-M05)
4
RST
PA1/OUT1
PA0/OUT0
P97/IN1
P96/IN0
P95/ZIN1
P94/BIN1
P93/AIN1/IRQ7
P92/ZIN0
P91/BIN0
P90/AIN0/IRQ6
P67/PPG11
P66/PPG10
P65/CKOT
P64/PPG01
P63/PPG00
P62/SCK2
P61/SOT2
P60/SIN2
P87
P86
P85/IRQ5
P84/IRQ4
P83/IRQ3
P82/IRQ2
P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC
P45/SCK1
P46/ADTG
P47
P70/SIN3
P71/SOT3
P72/SCK3
DVRH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
(TOP VIEW)
(FPT-100P-M06)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA4
PA3/OUT3
PA2/OUT2
RST
PA1/OUT1
PA0/OUT0
P97/IN1
P96/IN0
P95/ZIN1
P94/BIN1
P93/AIN1/IRQ7
P92/ZIN0
P91/BIN0
P90/AIN0/IRQ6
P67/PPG11
P66/PPG10
P65/CKOT
P64/PPG01
P63/PPG00
P62/SCK2
P61/SOT2
P60/SIN2
P87
P86
P85/IRQ5
P84/IRQ4
P83/IRQ3
P82/IRQ2
HST
MD2
MB90630A Series
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DVSS
P73/DA00
P74/DA01
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
P52/AN2
P53/AN3
VSS
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P80/IRQ0
P81/IRQ1
MD0
MD1
5
MB90630A Series
■ PIN DESCRIPTION
Pin no.
1
2
Pin name
Function
LQFP*
QFP*
80
82
X0
A
Oscillator pin
81
83
X1
A
Oscillator pin
50
52
HST
C
Hardware standby input pin
75
77
RST
B
Reset input pin
83 to 90
85 to 92
P00 to P07
AD00 to AD07
91 to 98
93 to 100 P10 to P17
AD08 to AD15
99, 100,
1 to 6
1 to 8
P20 to P27
A16 to A23
7
9
P30
ALE
8
10
P31
RD
10
12
P32
WRL
11
13
P33
WRH
STBC: Incorporates standby control
*1: LQFP (FPT-100P-M05)
*2: QFP (FPT-100P-M06)
6
Circuit
type
D
General-purpose I/O ports
(STBC) Pull-up resistors can be set (RD07 to RD00 = “1”) using the
pull-up resistor setting register (RDR0). The setting does not
apply for ports set as outputs (D07 to D00 = “1”: invalid at the
output setting).
In external bus mode, the pins function as the lower data I/O or
lower address outputs (AD00 to AD07).
D
General-purpose I/O ports
(STBC) Pull-up resistors can be set (RD17 to RD10 = “1”) using the
pull-up resistor setting register (RDR1). The setting does not
apply for ports set as outputs (D17 to D10 = “1”: invalid at the
output setting).
In 16-bit external bus mode, the pins function as the upper data
I/O or middle address outputs (AD08 to AD15).
H
General-purpose I/O ports
(STBC) In external bus mode, pins for which the corresponding bit in
the HACR register is “0” function as the P20 to P27 pins.
In external bus mode, pins for which the corresponding bit in
the HACR register is “1” function as the upper address output
pins (A16 to A23).
H
General-purpose I/O port
(STBC) Functions as the ALE pin in external bus mode.
Functions as the address latch enable signal.
H
General-purpose I/O port
(STBC) Functions as the RD pin in external bus mode.
Functions as the read strobe output (RD).
H
General-purpose I/O port
(STBC) Functions as the WR pin in external bus mode if the WRE bit in
the EPCR register is “1”.
Functions as the lower data write strobe output (WRL).
H
General-purpose I/O port
(STBC) Functions as the WRH pin in 16-bit external bus mode if the
WRE bit in the EPCR register is “1”.
Functions as the upper data write strobe output (WRH).
(Continued)
MB90630A Series
Pin no.
LQFP*1
QFP*2
12
14
Pin name
P34
HRQ
13
14
15
16
17
18
19
Functions as the hold acknowledge output (HAK) pin.
P36
H
General-purpose I/O port
(STBC) Functions as the RDY pin in external bus mode if the RYE bit in
the EPCR register is “1”.
P37
P40
P41
SOT0
18
20
Functions as the hold request input pin (HRQ).
HAK
SIN0
17
H
General-purpose I/O port
(STBC) Functions as the HRQ pin in external bus mode if the HDE bit
in the EPCR register is “1”.
H
General-purpose I/O port
(STBC) Functions as the HAK pin in external bus mode if the HDE bit in
the EPCR register is “1”.
CLK
16
Function
P35
RDY
15
Circuit
type
P42
SCK0
STBC: Incorporates standby control
*1: LQFP (FPT-100P-M05)
*2: QFP (FPT-100P-M06)
Functions as the external ready input (RDY) pin.
H
General-purpose I/O port
(STBC) Functions as the CLK pin in external bus mode if the CKE bit in
the EPCR register is “1”.
Functions as the machine cycle clock output (CLK) pin.
G
General-purpose I/O port
(STBC) When UART0 is operating, the data at the pin is used as the
serial input (SIN0).
Can be set as an open-drain output port (OD40 = “1”) by the
open-drain control register (ODR4). The setting does not apply
for ports set as inputs (D40 = “0”: invalid at the input setting).
Functions as the UART0 serial input (SIN0).
F
General-purpose I/O port
(STBC) Functions as the SOT0 pin if the SOE bit in the UMC register is
“1”.
Can be set as an open-drain output port (OD41 = “1”) by the
open-drain control register (ODR4). The setting does not apply
for ports set as inputs (D41 = “0”: invalid at the input setting).
Functions as the UART0 serial data output pin (SOT0).
G
General-purpose I/O port
(STBC) When UART0 is operating in external shift clock mode, the
data at the pin is used as the clock input (SCK0). Also,
functions as the SCK0 pin if the SOE bit in the UMC register is
“1”.
Can be set as an open-drain output port (OD42 = “1”) by the
open-drain control register (ODR4). The setting does not apply
for ports set as inputs (D42 = “0”: invalid at the input setting).
Functions as the UART0 serial clock I/O pin (SCK0).
(Continued)
7
MB90630A Series
Pin no.
LQFP*1
QFP*2
19
21
Pin name
P43
SIN1
20
22
P44
SOT1
22
24
P45
SCK1
23
25
P46
ADTG
24
36 to 39,
41 to 44
25
26
P47
38 to 41, P50 to P57
43 to 46
AN0 to AN7
27
P70
SIN3
26
28
P71
SOT3
27
29
P72
SCK3
STBC: Incorporates standby control
*1: LQFP (FPT-100P-M05)
*2: QFP (FPT-100P-M06)
8
Circuit
type
Function
G
General-purpose I/O port
(STBC) When I/O expansion serial is operating, the data at the pin is
used as the serial input (SIN1).
Can be set as an open-drain output port (OD43 = “1”) by the
open-drain control register (ODR4). The setting does not apply
for ports set as inputs (D43 = “0”: invalid at the input setting).
Functions as the serial input for I/O expansion serial data.
F
General-purpose I/O port
(STBC) Functions as the SOT1 pin if the SOE bit in the UMC register is
“1”.
Can be set as an open-drain output port (OD44 = “1”) by the
open-drain control register (ODR4). The setting does not apply
for ports set as inputs (D44 = “0”: invalid at the input setting).
Functions as the output pin (SOT1) for I/O expansion serial
data.
G
General-purpose I/O port
(STBC) When I/O expansion serial is operating in external shift clock
mode, the data at the pin is used as the clock input (SCK1).
Also, functions as the SCK1 pin if the SOE bit in the UMC
register is “1”.
Can be set as an open-drain output port (OD45 = “1”) by the
open-drain control register (ODR4). The setting does not apply
for ports set as inputs (D45 = “0”: invalid at the input setting).
Functions as the I/O expansion serial clock I/O pin (SCK1).
F
General-purpose I/O port
(STBC) Can be set as an open-drain output port (OD46 = “1”) by the
open-drain control register (ODR4). The setting does not apply
for ports set as inputs (D46 = “0”: invalid at the input setting).
Functions as the external trigger input pin for the A/D
converter.
F
General-purpose I/O port
(STBC) Can be set as an open-drain output port (OD47 = “1”) by the
open-drain control register (ODR4). The setting does not apply
for ports set as inputs (D47 = “0”: invalid at the input setting).
K
General-purpose I/O ports
(STBC)
The pins are used as analog inputs (AN0 to AN7) when the A/D
converter is operating.
I
General-purpose I/O port
(STBC)
Functions as the UART1 serial input (SIN3).
H
General-purpose I/O port
(STBC)
Functions as the UART1 serial data output pin (SOT3).
I
General-purpose I/O port
(STBC)
Functions as the UART1 serial clock I/O pin (SCK0).
(Continued)
MB90630A Series
Pin no.
LQFP*1
QFP*2
30
32
Pin name
P73
Circuit
type
L
General-purpose I/O port
(STBC) Functions as a D/A output pin when DAE0 = “1” in the D/A
control register (DACR).
DAO0
31
33
P74
Functions as D/A output 0 when the D/A converter is operating.
L
General-purpose I/O port
(STBC) Functions as a D/A output pin when DAE1 = “1” in the D/A
control register (DACR).
DAO1
45
47
P80
IRQ0
46
48
P81
Functions as D/A output 1 when the D/A converter is operating.
I
I
IRQ1
51
53
P82
54
P83
I
55
P84
I
56
P85
IRQ5
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
Functions as external interrupt request I/O 3.
I
IRQ4
54
Functions as external interrupt request I/O 0.
Functions as external interrupt request I/O 2.
IRQ3
53
General-purpose I/O port
Functions as external interrupt request I/O 1.
IRQ2
52
Function
General-purpose I/O port
Functions as external interrupt request I/O 4.
I
General-purpose I/O port
Functions as external interrupt request I/O 5.
55
57
P86
H
General-purpose I/O port
(STBC) This applies in all cases.
56
58
P87
H
General-purpose I/O port
(STBC) This applies in all cases.
57
59
P60
E
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD60 = “1”) using the pull-up
resistor setting register (RDR6). The setting does not apply for
ports set as outputs (D60 = “1”: invalid at the output setting).
SIN2
58
60
P61
SOT2
STBC: Incorporates standby control
*1: LQFP (FPT-100P-M05)
*2: QFP (FPT-100P-M06)
Functions as a data input pin (SIN2) for I/O expansion serial.
D
General-purpose I/O port
(STBC) Functions as the SOT2 pin if the SOE bit in the UMC register is
“1”.
A pull-up resistor can be set (RD61 = “1”) using the pull-up
resistor setting register (RDR6). The setting does not apply for
ports set as outputs (D61 = “1”: invalid at the output setting).
Functions as an output pin (SOT2) for I/O expansion serial
data.
(Continued)
9
MB90630A Series
Pin no.
LQFP*1
QFP*2
59
61
Pin name
P62
Circuit
type
E
General-purpose I/O port
(STBC) When I/O expansion serial is operating in external shift clock
mode, the data at the pin is used as the clock input (SCK2).
Also, functions as the SCK2 pin if the SOE bit in the UMC
register is “1”. A pull-up resistor can be set (RD62 = “1”) using
the pull-up resistor setting register (RDR6). The setting does
not apply for ports set as outputs (D62 = “1”: invalid at the
output setting).
SCK2
60
62
P63
Functions as the I/O expansion serial clock I/O pin (SCK2).
D
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD63 = “1”) using the pull-up
resistor setting register (RDR6). The setting does not apply for
ports set as outputs (D63 = “1”: invalid at the output setting).
PPG00
61
63
P64
Functions as the PPG00 output when PPG output is enabled.
D
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD64 = “1”) using the pull-up
resistor setting register (RDR6). The setting does not apply for
ports set as outputs (D64 = “1”: invalid at the output setting).
PPG01
62
64
P65
Functions as the PPG01 output when PPG output is enabled.
D
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD65 = “1”) using the pull-up
resistor setting register (RDR6). The setting does not apply for
ports set as outputs (D65 = “1”: invalid at the output setting).
CKOT
63
65
P66
Functions as the CKOT output when CKOT is operating.
D
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD66 = “1”) using the pull-up
resistor setting register (RDR6). The setting does not apply for
ports set as outputs (D66 = “1”: invalid at the output setting).
PPG10
64
66
P67
Functions as the PPG10 output when PPG output is enabled.
D
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD67 = “1”) using the pull-up
resistor setting register (RDR6). The setting does not apply for
ports set as outputs (D67 = “1”: invalid at the output setting).
PPG11
65
66
67
68
P90
Functions as the PPG11 output when PPG output is enabled.
I
General-purpose I/O port
AIN0
Input to channel 0 of the 8/16-bit up/down timer.
IRQ6
Functions as an interrupt request input.
P91
I
General-purpose I/O port
(STBC)
Input to channel 0 of the 8/16-bit up/down timer.
BIN0
STBC: Incorporates standby control
*1: LQFP (FPT-100P-M05)
*2: QFP (FPT-100P-M06)
10
Function
(Continued)
MB90630A Series
(Continued)
Pin no.
LQFP*1
QFP*2
67
69
Pin name
P92
ZIN0
68
69
70
71
P93
72
73
74
75
P94
I
General-purpose I/O port
(STBC)
Input to channel 1 of the 8/16-bit up/down timer.
P95
P96
P97
PA0
OUT0
74
76
PA1
OUT1
76
78
PA2
OUT2
77
79
General-purpose I/O port
Functions as an interrupt request input.
IN1
73
I
IRQ7
IN0
72
I
General-purpose I/O port
(STBC)
Input to channel 0 of the 8/16-bit up/down timer.
Input to channel 1 of the 8/16-bit up/down timer.
ZIN1
71
Function
AIN1
BIN1
70
Circuit
type
PA3
OUT3
I
General-purpose I/O port
(STBC)
Input to channel 1 of the 8/16-bit up/down timer.
I
General-purpose I/O port
(STBC)
Trigger input for channel 0 of the input capture.
I
General-purpose I/O port
(STBC)
Trigger input for channel 1 of the input capture.
H
General-purpose I/O port
(STBC)
Event output for channel 0 of the output compare.
H
General-purpose I/O port
(STBC)
Event output for channel 1 of the output compare.
H
General-purpose I/O port
(STBC)
Event output for channel 2 of the output compare.
H
General-purpose I/O port
(STBC)
Event output for channel 3 of the output compare.
78
80
PA4
32
34
AVCC
—
A/D converter power supply pin
35
37
AVSS
—
A/D converter power supply pin
33
35
AVRH
—
A/D converter external reference power supply pin
34
36
AVRL
—
A/D converter external reference power supply pin
28
30
DVRH
—
D/A converter external reference power supply pin
29
31
DVSS
—
D/A converter power supply pin
47 to 49
49 to 51
C
Operating mode selection pins.
Connect directly to VCC or VSS.
21, 82
23, 84
VCC
—
Power supply (5.0 V) input pin
9, 40, 79 11, 42, 81 VSS
—
Power supply (0.0 V) input pin
MD0 to MD2
H
General-purpose I/O port
(STBC)
STBC: Incorporates standby control
*1: LQFP (FPT-100P-M05)
*2: QFP (FPT-100P-M06)
11
MB90630A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Oscillator feedback
Registance 1 MΩ (approx.)
X1
X0
Standby control signal
B
• Hysteresis input with pull-up
Registance 50 kΩ (approx.)
HYS
C
• Hysteresis input port
HYS
D
CTL
• Incorporates pull-up resistor control
(for input)
Registance 50 kΩ (approx.)
• CMOS level I/O
CMOS
E
CTL
• Incorporates pull-up resistor control
(for input)
Registance 50 kΩ (approx.)
• CMOS level output
• Hysteresis input
HYS
F
• CMOS level I/O
• Open-drain control signal
Open-drain control
signal
CMOS
(Continued)
12
MB90630A Series
(Continued)
Type
Circuit
Remarks
G
Open-drain control
signal
• CMOS level output
• Hysteresis input
• Incorporates open-drain control
HYS
H
• CMOS level I/O
CMOS
I
• CMOS level output
• Hysteresis input
HYS
K
• CMOS level I/O
• Analog input
CMOS
Analog input
L
• CMOS level I/O
• Analog output
• Shared with D/A outputs
D/A output
CMOS
M
CTL
• Incorporates pull-up resistor control
(for input)
Registance 50 kΩ (approx.)
• CMOS level output
• Hysteresis input
HYS
13
MB90630A Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latch-up occurs in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin
or if the voltage applied between VCC and VSS exceeds the rating. If latch-up occurs, the power supply current
increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are
not exceeded in circuit operation.
For the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage.
2. Treatment of Unused Pins
Leaving unused input pins unconnected can cause misoperation. Always pull-up or pull-down unused pins.
3. External Reset Input
To reliably reset the controller by inputting an “L” level to the RST pin, ensure that the “L” level is applied for at
least five machine cycles. Take particular note when using an external clock input.
4. VCC and VSS Pins
Ensure that all VCC pins are at the same voltage. The same applies for the VSS pins.
5. Precautions when Using an External Clock
Drive the X0 pin only when using an external clock.
• Using an external clock
MB90630A
X0
X1
6. A/D Converter Power Supply and the Turn-on Sequence for Analog Inputs
Always turn off the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) before
turning off the digital power supply (VCC).
When turning the power on or off, ensure that AVRH does not exceed AVCC.
Also, when using the analog input pins as input ports, ensure that the input voltage does not exceed AVCC.
7. Program Mode
All bits (64 K × 16 bits) in the MB90P634A are “1” on delivery from Fujitsu or after erasing. To write data,
selectively program the desired bits to “0”. The value “1” cannot be written electrically.
14
MB90630A Series
8. Recommended Screening Conditions
High temperature aging is recommended as the pre-assembly screening procedure.
9. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
10. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is
therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations
(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of 2 momentary fluctuation such as when power
is switched.
15
MB90630A Series
■ PROGRAMMING THE EPROM IN THE MB90P634A
In EPROM mode, the MB90P634A function as MBM27C1000 equivalents. By using a dedicated adapter socket,
the devices can be programmed using a standard EPROM programmer.
1. Pin Assignment in EPROM Mode
• Pins compatible with the MBM27C1000
MBM27C1000
MB90P634A
Pin number
Pin name
Pin number
Pin name
1
VPP
49
MD2 (VPP)
2
OE
10
P32
3
A15
98
P17
4
A12
95
P14
5
A07
6
P27
6
A06
5
P26
7
A05
4
P25
8
A04
3
P24
9
A03
2
P23
10
A02
1
P22
11
A01
100
P21
12
A00
99
P20
13
D00
83
P00
14
D01
84
P01
15
D02
85
P02
16
GND
—
—
32
VCC
—
—
31
PGM
11
P33
30
NC
—
—
29
A14
97
P16
28
A13
96
P15
27
A08
91
P10
26
A09
92
P11
25
A11
94
P13
24
A16
7
P30
23
A10
93
P12
22
CE
8
P31
21
D07
90
P07
(Continued)
16
MB90630A Series
(Continued)
MBM27C1000
MB90P634A
Pin number
Pin name
Pin number
Pin name
20
D06
89
P06
19
D05
88
P05
18
D04
87
P04
17
D03
86
P03
• Power supply and GND connection pins
Type
Pin number
Pin name
Power supply (VCC)
28
50
21, 82
DVRH
HST
VCC
GND
9
34
35
40
29
75
79
12
13
14
VSS
AVRL
AVSS
VSS
DVSS
RST
VSS
P34
P35
P36
17
MB90630A Series
• Pins other than MBM27C1000-compatible pins
Pin number
Pin name
Treatment
47
48
80
MD0
MD1
X0
Pull-up (4.7 kΩ)
81
X1
OPEN
15
16 to 20
22 to 24
25 to 27
30
31
36 to 39
41 to 44
45
46
51 to 56
57 to 64
65 to 72
73
74
76
77
78
P37
P40 to P44
P45 to P47
P70 to P72
P73
P74
P50 to P53
P54 to P57
P80
P81
P82 to P87
P60 to P67
P90 to P97
PA0
PA1
PA2
PA3
PA4
Connect pull-up resistors of
approximately 1 MΩ to each pin
2. EPROM Programmer Socket Adapter
Part no.
Package
MB90P634APFV SQFP-100
Compatible socket adapter
Sun Hayato Co., Ltd.
ROM-100SQF-32DP-16L
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
18
MB90630A Series
3. Programming Procedure
(1) Set the EPROM programmer for a MBM27C1000.
(2) Load the program data between 10000H and 1FFFFH in the EPROM programmer.
In the MB90P634A, ROM addresses FFFFFFH to FF0000H in operating mode correspond to addresses 1FFFFH
to 10000H in EPROM mode.
FFFFFF H
1FFFF H
FF0000 H
10000 H
Operating mode
EPROM mode
(3) Set the MB90P634A, in the adapter socket and connect the adapter socket to the EPROM programmer.
Take care to correctly align the device with the adapter.
(4) Perform programming.
(5) If programming cannot be performed successfully, connect a 0.1 µF or similar capacitor between VCC and
GND and between VPP and GND.
Note: As mask ROM products (MB90632A, 634A) do not support EPROM mode, data cannot be read using an
EPROM programmer. Performing a blank check for other than the above addresses results in either nonEPROM addresses being read or the blank check being unable to be performed.
19
MB90630A Series
■ BLOCK DIAGRAM
X0, 1
RST
HST
CPU
F2MC-16L series core
Clock control
circuit
4
Interrupt controller
RAM
2
8 + 8PPG
2
(Output switching) × 1 channel
ROM
SIN0, 3
SOT0, 3
SCK0, 3
SIN1, 2
SOT1, 2
SCK1, 2
F2MC-16 bus
Communications prescaler
2
2
2
UART × 2 channels
U/D counter
8 bits × 2
(16 bits × 1)
×2
AIN0, 1
BIN0, 1
ZIN0, 1
Prescaler
CKOT
8
2
2
2
IRQ0 to IRQ7
External interrupts
I/O expansion serial
interface × 2 channels
2
I/O timers
AVCC
2
AVRH, AVRL
AVSS
ADTG
8
AN0 to AN7
DAO0, 1
DVRH
DVSS
PPG00, 01
PPG10, 11
16-bit input capture × 2 channels
16-bit output capture × 4 channels
A/D converter
(10 bits)
3
16-bit free-run timer
2
D/A converter
(8 bits) × 2 channels
I/O ports
8
8
8
8
8
8
8
5
8
8
5
P00
to
P07
P10
to
P17
P20
to
P27
P30
to
P37
P40
to
P47
P50
to
P57
P60
to
P67
P70
to
P74
P80
to
P87
P90
to
P97
PA0
to
PA4
P00 to P07 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P10 to P17 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P60 to P67 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P40 to P47 (8 pins) : Incorporates an open-drain setting register
20
IN0, 1
OUT1 to OUT3
MB90630A Series
■ F2MC-16L CPU PROGRAMMING MODEL
• Dedicated Registers
AH
Accumulator
AL
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
USPCU
User stack upper register
SSPCU
System stack upper register
USPCL
User stack lower register
SSPCL
System stack lower register
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bits
16 bits
32 bits
• General-purpose Registers
Maximum 32 banks
R7
R6
RW7
R5
R4
RW6
R3
R2
RW5
R1
R0
RW4
RL3
RL2
RW3
RL1
RW2
RW1
RL0
RW0
000180H + RP × 10H →
16 bit
• Processor Status (PS)
ILM
RP
−
I
S
T
N
Z
V
C
CCR
21
MB90630A Series
■ MEMORY MAP
FFFFFF H
Single chip
Internal ROM/External bus
ROM area
ROM area
ROM area
(FF bank image)
ROM area
(FF bank image)
RAM
RAM
External ROM/External bus
Address 1#
FF0000 H
010000 H
Address 2#
004000 H
002000 H
Address 3#
000380 H
Registers
Registers
RAM
Registers
000180 H
000100 H
0000C0 H
Peripherals
Peripherals
Peripherals
000000 H
: Internal
Type
MB90632A
MB90634A
MB90P634A
22
Address #1
FF8000H
FF0000H
FF0000H
: External
Address #2
008000H
004000H
004000H
: No access
Address #3
000500H
000900H
000D00H
MB90630A Series
■ I/O MAP
Address
Register
Register Access
name
Resource
Initial value
00H
Port 0 data register
PDR0
R/W
Port 0
XXXXXXXX
01H
Port 1 data register
PDR1
R/W
Port 1
XXXXXXXX
02H
Port 2 data register
PDR2
R/W
Port 2
XXXXXXXX
03H
Port 3 data register
PDR3
R/W
Port 3
XXXXXXXX
04H
Port 4 data register
PDR4
R/W
Port 4
XXXXXXXX
05H
Port 5 data register
PDR5
R/W
Port 5
XXXXXXXX
06H
Port 6 data register
PDR6
R/W
Port 6
XXXXXXXX
07H
Port 7 data register
PDR7
R/W
Port 7
–––XXXXX
08H
Port 8 data register
PDR8
R/W
Port 8
XXXXXXXX
09H
Port 9 data register
PDR9
R/W
Port 9
XXXXXXXX
0AH
Port A data register
PDRA
R/W
Port A
–––XXXXX
Reserved area
0B to 0FH
10H
Port 0 direction register
DDR0
R/W
Port 0
0 00 00 00 0
11H
Port 1 direction register
DDR1
R/W
Port 1
0 00 00 00 0
12H
Port 2 direction register
DDR2
R/W
Port 2
0 00 00 00 0
13H
Port 3 direction register
DDR3
R/W
Port 3
0 00 00 00 0
14H
Port 4 direction register
DDR4
R/W
Port 4
0 00 00 00 0
15H
Port 5 direction register
DDR5
R/W
Port 5
0 00 00 00 0
16H
Port 6 direction register
DDR6
R/W
Port 6
0 00 00 00 0
17H
Port 7 direction register
DDR7
R/W
Port 7
– –– 00 00 0
18H
Port 8 direction register
DDR8
R/W
Port 8
0 00 00 00 0
19H
Port 9 direction register
DDR9
R/W
Port 9
0 00 00 00 0
1AH
Port A direction register
DDRA
R/W
Port A
– –– 00 00 0
1BH
Port 4 pin register
ODR4
R/W
Port 4
0 00 00 00 0
1CH
Port 0 resistance register
RDR0
R/W
Port 0
0 00 00 00 0
1DH
Port 1 resistance register
RDR1
R/W
Port 1
0 00 00 00 0
1EH
Port 6 resistance register
RDR6
R/W
Port 6
0 00 00 00 0
1FH
Analog input enable register
ADER
R/W
Port 5, A/D
1 11 11 11 1
20H
Serial mode register 0
SMR0
R/W
21H
Serial control register 0
SCR0
R/W
22H
Serial input register/
Serial output register 0
SIDR/
SODR0
R/W
00000000
UART0
00000100
XXXXXXXX
(Continued)
23
MB90630A Series
Address
Register
23H
Serial status register 0
24H
Serial mode control status register 0
25H
Serial mode control status register 0
26H
Register Access
name
SSR0
R/W
SMCS0
R/W
SMCS0
R/W
Serial data register 0
SDR0
R/W
27H
Clock division control register
CDCR
R/W
28H
Serial mode control status register 1
SMCS1
R/W
29H
Serial mode control status register 1
2AH
Serial data register 1
2B to 2FH
SMCS1
R/W
SDR1
R/W
Interrupt/DTP enable register
ENIR
R/W
31H
Interrupt/DTP source register
EIRR
R/W
Request level setting register
ELVR
R/W
33H
37H
38H
39H
UART0
0 00 01 –0 0
––––0000
I/O expansion serial
interface 0
00000010
XXXXXXXX
Communications
prescaler
0–––1111
––––0000
I/O expansion serial
interface 1
00000010
XXXXXXXX
00000000
DTP/External interrupts
XXXXXXXX
00000000
00000000
Reserved area
34 to 35H
36H
Initial value
Reserved area
30H
32H
Resource
Control status register
Data register
ADCS1
ADCS2
ADCR1
ADCR2
00000000
R/W
A/D converter
R
3AH
D/A converter data register 0
DAT0
R/W
3BH
D/A converter data register 1
DAT1
R/W
3CH
D/A control register 0
DACR0
R/W
3DH
D/A control register 1
DACR1
R/W
3EH
Clock control register
CLKR
R/W
00000000
XXXXXXXX
XXXXXXXX
XXXXXXXX
D/A converter
XXXXXXXX
–––––––0
–––––––0
CKOT output
–––––000
Reserved area
3FH
40H
Reload register L (channel 0)
PRLL0
R/W
XXXXXXXX
41H
Reload register H (channel 0)
PRLH0
R/W
XXXXXXXX
42H
Reload register L (channel 1)
PRLL1
R/W
XXXXXXXX
43H
Reload register H (channel 1)
PRLH1
R/W
44H
PPG0 operation mode control register
PPGC0
R/W
0X000XX1
45H
PPG1 operation mode control register
PPGC1
R/W
0X 0 0 0 0 0 1
46H
PPG0, 1 output control register
PPGOE
R/W
0 00 00 00 0
47 to 4FH
50H
8/16 bit PPG
XXXXXXXX
Reserved area
Lower compare register channel 0
OCCP0
R/W
16-bit I/O timer output
compare (channel 0 to 3)
XXXXXXXX
(Continued)
24
MB90630A Series
Address
Register
51H
Upper compare register channel 0
52H
Lower compare register channel 1
53H
Upper compare register channel 1
54H
Lower compare register channel 2
55H
Upper compare register channel 2
56H
Lower compare register channel 3
57H
Upper compare register channel 3
58H
Register Access
name
OCCP0
R/W
OCCP1
R/W
OCCP2
R/W
Resource
Initial value
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
16-bit I/O timer
Output compare
(channel 0 to 3)
XXXXXXXX
XXXXXXXX
OCCP3
R/W
Compare control status register channel 0
OCS0
R/W
–––00000
59H
Compare control status register channel 1
OCS1
R/W
0000––00
5AH
Compare control status register channel 2
OCS2
R/W
–––00000
5BH
Compare control status register channel 3
OCS3
R/W
0000––00
5C to 5FH
XXXXXXXX
Reserved area
R
XXXXXXXX
R
XXXXXXXX
60H
Lower input capture register channel 0
61H
Upper input capture register channel 0
62H
Lower input capture register channel 1
63H
Upper input capture register channel 1
64H
Input capture control status register
ICS
R/W
0 00 00 00 0
65H
Reserved area
—
—
––––––––
66H
Lower timer data register
TCDTL
R/W
67H
Upper timer data register
TCDTH
R/W
68H
Timer control status register
TCCS
R/W
69 to 6FH
IPCP0
IPCP1
Up/down count register channel 0
UDCR0
71H
Up/down count register channel 1
UDCR1
72H
Reload compare register channel 0
RCR0
73H
Reload compare register channel 1
RCR1
74H
Counter status register channel 0
CSR0
76H
77H
78H
79H
7AH
R
16-bit I/O timer
Input capture
(channel 0, 1)
16-bit I/O timer
Free-run timer
(channel 0, 1)
XXXXXXXX
XXXXXXXX
00000000
00000000
0 00 00 00 0
Reserved area
70H
75H
R
Reserved area
Counter control register channel 0
Counter status register channel 1
Reserved area
Counter control register channel 1
—
CCRL0
CCRH0
00000000
R
0 00 00 00 0
00000000
W
0 00 00 00 0
R/W
—
R/W
0 00 00 00 0
8/16-bit up/down
timer/counter
––––––––
–0000000
00000000
CSR1
R/W
0 00 00 00 0
—
—
––––––––
CCRL1
R/W
– 00 00 00 0
(Continued)
25
MB90630A Series
Address
7BH
Register
Counter control register
channel 1
7C to 87H
Register
name
Access
Resource
Initial value
CCRH1
R/W
8/16-bit up/down
timer/counter
–0000000
Reserved area
88H
Serial mode register 1
SMR1
R/W
89H
Serial control register 1
SCR1
R/W
8AH
Serial input register 1/serial
output register 1
8BH
Serial status register 1
8C to 9EH
SIDR1/
SODR1
R/W
SSR1
R/W
00000000
00000100
UART1
XXXXXXXX
0 00 01 –0 0
Reserved area (Accessing 90H to 9EH is prohibited.)
9FH
Delayed interrupt generation/
clear register
DIRR
R/W
Delayed interrupt
generation module
–––––––0
A0H
Low-power consumption mode
register
LPMCR
R/W
Low-power consumption
0 00 11 00 0
A1H
Clock selection register
CKSCR
R/W
Low-power consumption
1 10 01 10 0
A2 to A4H
Reserved area
A5H
Auto-ready function selection
register
ARSR
W
External pins
0011––00
A6H
External address output control
register
HACR
W
External pins
––––0000
A7H
Bus control signal selection
register
ECSR
W
External pins
00 0 0* 0 0–
A8H
Watchdog timer control register
WDTC
R/W
Watchdog timer
XXXXX111
A9H
Timebase timer control register
TBTC
R/W
Timebase timer
1 –– 00 10 0
AA to AFH
Reserved area
B0H
Interrupt control register 00
ICR00
R/W
00000111
B1H
Interrupt control register 01
ICR01
R/W
0 00 00 11 1
B2H
Interrupt control register 02
ICR02
R/W
0 00 00 11 1
B3H
Interrupt control register 03
ICR03
R/W
0 00 00 11 1
B4H
Interrupt control register 04
ICR04
R/W
0 00 00 11 1
B5H
Interrupt control register 05
ICR05
R/W
0 00 00 11 1
B6H
Interrupt control register 06
ICR06
R/W
B7H
Interrupt control register 07
ICR07
R/W
B8H
Interrupt control register 08
ICR08
R/W
0 00 00 11 1
B9H
Interrupt control register 09
ICR09
R/W
0 00 00 11 1
BAH
Interrupt control register 10
ICR10
R/W
0 00 00 11 1
BBH
Interrupt control register 11
ICR11
R/W
0 00 00 11 1
BCH
Interrupt control register 12
ICR12
R/W
0 00 00 11 1
BDH
Interrupt control register 13
ICR13
R/W
0 00 00 11 1
Interrupt controller
0 00 00 11 1
0 00 00 11 1
(Continued)
26
MB90630A Series
(Continued)
Address
Register
Register
name
Access
BEH
Interrupt control register 14
ICR14
R/W
BFH
Interrupt control register 15
ICR15
R/W
—
—
C0 to FFH
Reserved area
Resource
Interrupt controller
—
Initial value
00000111
00000111
—
Initial values
0: The initial value of this bit is “0”.
1: The initial value of this bit is “1”.
* : The initial value of this bit is “0” or “1”.
X: The initial value of this bit is undefined.
–: This bit is not used. The initial value is undefined.
Note: Areas below address 0000FFH not listed in the table are reserved areas. These addresses are accessed by
internal access. No access signals are output on the external bus.
27
MB90630A Series
■ INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER ASSIGNMENTS TO
INTERRUPT SOURCES
Interrupt vector
Interrupt control register
I2OS
support
Number
Address
ICR
Address
Reset
×
#08
FFFFDCH
—
—
INT 9 instruction
×
#09
FFFFD8H
—
—
Exception
×
Interrupt source
#10
FFFFD4H
—
—
A/D converter
#11
FFFFD0H
ICR00
0000B0H
DTP 0 (External interrupt 0)
#13
FFFFC8H
16-bit free-run timer (I/O timer) overflow
#14
FFFFC4H
ICR01
0000B1H
I/O expansion serial 1
#15
FFFFC0H
DTP 1 (External interrupt 1)
#16
FFFFBCH
ICR02
0000B2H
I/O expansion serial 2
#17
FFFFB8H
DTP 2 (External interrupt 2)
#18
FFFFB4H
ICR03
0000B3H
DTP 3 (External interrupt 3)
#19
FFFFB0H
8/16-bit PPG 0 counter borrow
#20
FFFFACH
ICR04
0000B4H
8/16-bit U/D counter 0 compare
#21
FFFFA8H
8/16-bit U/D counter 0 underflow/
overflow, up/down invert
#22
FFFFA4H
ICR05
0000B5H
8/16-bit PPG 1 counter borrow
#23
FFFFA0H
DTP 4/5 (External interrupt 4/5)
#24
FFFF9CH
ICR06
0000B6H
Output compare (channel 2) match (I/O timer)
#25
FFFF98H
Output compare (channel 3) match (I/O timer)
#26
FFFF94H
ICR07
0000B7H
DTP 6 (External interrupt 6)
#28
FFFF8CH
ICR08
0000B8H
8/16-bit U/D counter 1 compare
#29
FFFF88H
8/16-bit U/D counter 1 underflow/
overflow, up/down invert
#30
FFFF84H
ICR09
0000B9H
Input capture (channel 0) read (I/O timer)
#31
FFFF80H
Input capture (channel 1) read (I/O timer)
#32
FFFF7CH
ICR10
0000BAH
Output compare (channel 0) match (I/O timer)
#33
FFFF78H
Output compare (channel 1) match (I/O timer)
#34
FFFF74H
ICR11
0000BBH
DTP 7 (External interrupt 7)
#36
FFFF6CH
ICR12
0000BCH
UART0 receive complete
#37
FFFF68H
UART1 receive complete
#38
FFFF64H
ICR13
0000BDH
UART0 transmit complete
#39
FFFF60H
UART1 transmit complete
#40
FFFF5CH
ICR14
0000BEH
ICR15
0000BFH
Reserved
×
#41
FFFF58H
Delayed interrupt
×
#42
FFFF54H
: Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (no stop request).
: Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (stop request present).
: Indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal.
Note: For resources in which two interrupt sources share the same interrupt number, the I2OS interrupt clear signal
clears both interrupt request flags.
28
MB90630A Series
■ PERIPHERAL RESOURCES
1. Parallel Ports
(1) I/O Ports
Each port pin can be specified as either an input or output by its corresponding direction register when the pin
is not set for use by a peripheral. When a port is set as an input, reading the data register always reads the
value corresponding to the pin level. When a port is set as an output, reading the data register reads the data
register latch value. The same applies when reading using a read-modify-write instruction.
When used as control outputs, reading the data register reads the control output value, irrespective of the
direction register value.
Note that if a read-modify-write instruction (set bit or similar instruction) is used to set output data in the data
register before switching a pin from input to output, the instruction reads the input level at the pin and not the
data register latch value.
• Block Diagram
Internal data bus
↑
Data register read
Data register
Pin
↑
Data register write
Direction register
↑
Direction register write
↑
Direction register read
29
MB90630A Series
(2) Register Configuration
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address: 000000H
P07
P06
P05
P04
P03
P02
P01
P00
Address: 000001H
P17
P27
P37
P47
P15
P25
P14
P24
P13
P23
P12
P22
P11
P21
P10
Address: 000002H
Address: 000003H
P16
P26
P36
P46
P35
P45
P34
P44
P33
P43
P32
P42
P31
P41
P20
P30
P40
P57
P67
P56
P66
P55
P65
P54
P64
P53
P63
P52
P62
P51
P61
P50
P60
—
P87
—
P86
—
P85
P74
P84
P73
P83
P72
P82
P71
P81
P70
P80
P97
—
P96
—
P95
—
P94
PA4
P93
PA3
P92
PA2
P91
PA1
P90
PA0
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
bit
Address: 000004H
Address: 000005H
Address: 000006H
Address: 000007H
Address: 000008H
Address: 000009H
Address: 00000AH
bit
Address: 000010H
D07
D06
D05
D04
D03
D02
D01
D00
Address: 000011H
D17
D16
D15
D14
D13
D12
D11
D10
Address: 000012H
Address: 000013H
D27
D37
D26
D36
D25
D35
D24
D34
D23
D33
D22
D32
D21
D31
D20
D30
Address: 000014H
Address: 000015H
D47
D57
D67
D46
D56
D45
D55
D44
D54
D43
D53
D42
D52
D41
D51
D66
—
D65
—
D64
D74
D63
D73
D62
D72
D61
D71
D40
D50
D60
D97
—
D86
D96
—
D85
D95
—
D84
D94
DA4
D83
D93
DA3
D82
D92
DA2
D81
D91 D90
DA1 DA0
15
14
13
12
11
10
Address: 000016H
Address: 000017H
Address: 000018H
Address: 000019H
Address: 00001AH
bit
Address: 00001BH
bit
Address: 00001CH
Address: 00001DH
Address: 00001EH
bit
Address: 00001FH
30
—
D87
9
D70
D80
14/6
13/5
12/4
11/3
10/2
9/1
14
13
12
11
10
9
Port 4 pin register (ODR4)
8/0
RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00
RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10
RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60
15
Port 0 direction register (DDR0)
Port 1 direction register (DDR1)
Port 2 direction register (DDR2)
Port 3 direction register (DDR3)
Port 4 direction register (DDR4)
Port 5 direction register (DDR5)
Port 6 direction register (DDR6)
Port 7 direction register (DDR7)
Port 8 direction register (DDR8)
Port 9 direction register (DDR9)
Port A direction register (DDRA)
8
OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40
15/7
Port 0 data register (PDR0)
Port 1 data register (PDR1)
Port 2 data register (PDR2)
Port 3 data register (PDR3)
Port 4 data register (PDR4)
Port 5 data register (PDR5)
Port 6 data register (PDR6)
Port 7 data register (PDR7)
Port 8 data register (PDR8)
Port 9 data register (PDR9)
Port A data register (PDRA)
Port 0 resistor register (RDR0)
Port 1 resistor register (RDR1)
Port 6 resistor register (RDR6)
8
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Port 5 analog input enable register
(ADER)
MB90630A Series
(3) Register Details
• Port Data Registers
bit
PDR0
Address: 000000H
bit
PDR1
Address: 000001H
7
6
5
4
3
2
1
0
P07
P06
P05
P04
P03
P02
P01
P00
15
14
13
12
11
10
9
8
P17
P16
P15
P14
P13
P12
P11
P10
7
6
5
4
3
2
1
0
PDR2
Address: 000002H
P27
P26
P25
P24
P23
P22
P21
P20
bit
PDR3
Address: 000003H
15
14
13
12
11
10
9
8
P37
P36
P35
P34
P33
P32
P31
P30
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
bit
bit
PDR4
Address: 000004H
15
14
13
12
11
10
9
8
PDR5
Address: 000005H
P57
P56
P55
P54
P53
P52
P51
P50
bit
PDR6
Address: 000006H
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
bit
15
14
13
12
11
10
9
8
PDR7
Address: 000007H
—
—
—
P74
P73
P72
P71
P70
bit
PDR8
Address: 000008H
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
15
14
13
12
11
10
9
8
P97
P96
P95
P94
P93
P92
P91
P90
bit
bit
PDR9
Address: 000009H
bit
PDRA
Address: 00000AH
7
6
5
4
3
2
1
0
—
—
—
PA4
PA3
PA2
PA1
PA0
Initial value
Undefined
Access
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
Undefined
R/W*
* : The operation of reading or writing to I/O ports is slightly different from reading or writing to memory, as follows.
• Input mode
Read: Reads the corresponding pin level.
Write: Writes to the output latch.
• Output mode
Read: Reads the value of the data register latch.
Write: The value is output from the corresponding pin.
31
MB90630A Series
• Port Direction Registers
bit
DDR0
Address: 000010H
bit
DDR1
Address: 000011H
7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
15
14
13
12
11
10
9
8
D17
D16
D15
D14
D13
D12
D11
D10
7
6
5
4
3
2
1
0
DDR2
Address: 000012H
D27
D26
D25
D24
D23
D22
D21
D20
bit
DDR3
Address: 000013H
15
14
13
12
11
10
9
8
D37
D36
D35
D34
D33
D32
D31
D30
bit
bit
DDR4
Address: 000014H
bit
DDR5
Address: 000015H
bit
DDR6
Address: 000016H
bit
DDR7
Address: 000017H
bit
DDR8
Address: 000018H
7
6
5
4
3
2
1
0
D47
D46
D45
D44
D43
D42
D41
D40
15
14
13
12
11
10
9
8
D57
D56
D55
D54
D53
D52
D51
D50
7
6
5
4
3
2
1
0
D67
D66
D65
D64
D63
D62
D61
D60
15
14
13
12
11
10
9
8
—
—
—
D74
D73
D72
D71
D70
7
6
5
4
3
2
1
0
D87
D86
D85
D84
D83
D82
D81
D80
15
14
13
12
11
10
9
8
DDR9
Address: 000019H
D97
D96
D95
D94
D93
D92
D91
D90
bit
DDRA
Address: 00001AH
7
6
5
4
3
2
1
0
—
—
—
DA4
DA3
DA2
DA1
DA0
bit
Initial value
00000000B
Access
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
-----000B
R/W
00000000B
R/W
00000000B
R/W
---00000B
R/W
When pins are used as ports, the register bits control the corresponding pins as follows.
0: Input mode
1: Output mode
Bits are set to “0” by a reset.
32
MB90630A Series
• Port Resistance Registers
bit
RDR0
Address: 00001CH
bit
RDR1
Address: 00001DH
bit
RDR6
Address: 00001EH
7
6
5
4
3
2
1
0
RD07
RD06
RD05
RD04
RD03
RD02
RD01
RD00
15
14
13
12
11
10
9
8
RD17
RD16
RD15
RD14
RD13
RD12
RD11
RD10
7
6
5
4
3
2
1
0
RD67
RD66
RD65
RD64
RD63
RD62
RD61
RD60
Initial value
00000000B
00000000B
00000000B
• Block Diagram
Internal data bus
Pull-up resistor (approx. 50 kΩ)
Data register
Port I/O
Direction register
Resistance register
Notes: • Input resistance register R/W
Controls the pull-up resistor in input mode.
0: Pull-up resistor disconnected in input mode.
1: Pull-up resistor connected in input mode.
The setting has no meaning in output mode (pull-up resistor disconnected).
The direction register (DDR) sets input or output mode.
• The pull-up resistor is disconnected in hardware standby or stop mode (SPL = 1) (high impedance).
• This function is disabled when using an external bus. In this case, do not write to this register.
33
MB90630A Series
• Port Pin Register
bit
ODR4
Address: 00001BH
7
6
5
4
3
2
1
0
OD47
OD46
OD45
OD44
OD43
OD42
OD41
OD40
Initial value
00000000B
Internal data bus
• Block Diagram
Port I/O
Data register
Direction register
Pin register
Notes: • Pin register R/W
Performs open-drain control in output mode.
0: Operate as a standard output port in output mode.
1: Operate as an open-drain output port in output mode.
The setting has no meaning in input mode (output Hi-z).
The direction register (DDR) sets input or output mode
• The pull-up resistor is disconnected in hardware standby or stop mode (SPL = 1) (high impedance).
• This function is disabled when using an external bus. In this case, do not write to this register.
• Analog Input Enable Register
bit
ADER
Address: 00001FH
15
14
13
12
11
10
9
8
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Controls each port 5 pin as follows.
0: Port input mode
1: Analog input mode
Set to “1” by a reset.
34
Initial value
11111111B
MB90630A Series
2. UART
The UART is a serial I/O port that can be used for CLK asynchronous (start-stop synchronization) or CLK
synchronous communications. The UART has the following features.
• Full duplex, double buffered
• Supports asynchronous (start-stop synchronization) and CLK synchronous data transfer
• Supports multi-processor mode
• Built-in dedicated baud rate generator
Asynchronous: 9615, 31250, 4808, 2404, 1202 bps
CLK synchronous: 1 Mbps, 500 Kbps, 250 Kbps, 125 Kbps, and 62.5
•
•
•
•
For a 6, 8, 10, 12, or 16 MHz clock.
Supports flexible baud rate setting using an external clock
Error detect function (parity, framing, and overrun)
NRZ type transmission signal
Intelligent I/O service support
(1) Register Configuration
8
15
bit
Address: 000020H
000088H
bit
Address: 000021H
000089H
bit
Address: 000022H
00008AH
bit
Address: 000023H
00008BH
bit
Address: 000027H
7
0
CDCR
—
(R/W)
SCR
SMR
(R/W)
SSR
SIDR (R)/SODR (W)
(R/W)
8 bits
8 bits
7
6
5
4
3
2
1
0
MD1
MD0
CS2
CS1
CS0
Reserved
SCKE
SOE
15
14
13
12
11
10
9
8
PEN
P
SBL
CL
A/D
REC
RXE
TXE
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
15
14
13
12
11
10
9
8
PE
ORE
FRE
RDRF
TDRE
—
RIE
TIE
15
14
13
12
11
10
9
8
MD
—
—
—
DIV3
DIV2
DIV1
DIV0
Serial mode register 0, 1
(SMR0, 1)
Serial control register 0, 1
(SCR0, 1)
Serial input register/
Serial output register 0, 1
(SIDR/SODR0, 1)
Serial status register 0, 1
(SSR0, 1)
Clock division control register
(CDCR)
35
MB90630A Series
(2) Block Diagram
Control signals
Reception interrupt
(to CPU)
SCK0, 1
Dedicated baud rate generator
Upper 8/16-bit PPG timer
(Connected internally)
Transmission clock
pulses
Clock select
circuit
Transmission interrupt
(to CPU)
Reception clock
pulses
External clock
SIN0, 1
Reception control
circuit
Transmission control
circuit
Start bit counter
Transmission start
circuit
Reception bit
counter
Transmission bit
counter
Reception parity
counter
Transmission parity
counter
SOT0, 1
Reception status
detection circuit
Reception error
occurrence signal
for I2OS
(to CPU)
Reception shifter
Transmission shifter
Start of
transmission
End of
reception
SODR
SIDR
F2MC-16 bus
SMR
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signals
36
MB90630A Series
3. I/O Expansion Serial Interface
This block consists of an 8-bit serial I/O interface that can perform clock synchronous data transfer. Either LSBfirst or MSB-first data transfer can be selected.
The following two serial I/O operation modes are available.
• Internal shift clock mode: Data transfer is synchronized with the internal clock.
• External shift clock mode: Data transfer is synchronized with the clock input from the external pin (SCK). By
manipulating the general-purpose port that shares the external pin (SCK), this
mode also enables the data transfer operation to be driven by CPU instructions.
(1) Register Configuration
bit
Address: 000025H
000029H
15
14
SMD2 SMD1
bit
Address: 000024H
000028H
bit
Address: 000026H
00002AH
13
12
11
10
9
8
SMD0
SIE
SIR
BUSY
STOP
STRT
7
6
5
4
3
2
1
0
—
—
—
—
MODE
BDS
SOE
SCOE
Serial mode control status
registers 0, 1 (SMCS0, 1)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Serial data registers 0, 1
(SDR0, 1)
(2) Register Details
• Serial Mode Control Status Register (SMCS)
bit
SMCS
Address: 000025H
000029H
bit
SMCS
Address: 000024H
000028H
15
14
13
12
11
10
9
8
SMD2 SMD1
SMD0
SIE
SIR
BUSY
STOP
STRT
(R/W)
(R/W)
(R/W)
7
6
5
4
3
2
1
0
—
—
—
—
MODE
BDS
SOE
SCOE
(R/W)
(R/W)
(R/W)
(R/W)
(R/W) (R/W*1)
(R)
Initial value
00000010B
(R/W) (R/W*2)
Initial value
----0000 B
*1: Only “0” can be written.
*2: Only “1” can be written. Reading always returns “0”.
This register controls the transfer operation mode of the serial I/O. The following describes the function of each
bit.
(a) [bit 3] Serial mode selection bit (MODE)
This bit selects the conditions for starting operation from the halted state. Changing the mode during operation
is prohibited.
MODE
Operation
0
Start when STRT is set to “1”. [Initial value]
1
Start on reading from or writing to the serial data register.
The bit is initialized to “0” by a reset. The bit is readable and writable. Set to “1” when using the intelligent I/O
service.
37
MB90630A Series
(b) [bit 2] Transfer direction selection bit (BDS: Bit Direction Select)
Selects as follows at the time of serial data input and output whether the data are to be transferred in the
order from LSB to MSB or vice versa.
MODE
Operation
0
LSB-first [Initial value]
1
MSB-first
(3) Block Diagram
Internal data bus
(MSB-first) D0 to D7
D7 to D0 (LSB-first)
Transfer direction selection
SIN1, 2
Read
Write
SDR (Serial data register)
SOT1, 2
SCK1, 2
Control circuit
Shift clock counter
Internal clock
2
1
0
SMD2 SMD1 SMD0
SIE
SIR
BUSY STOP STRT MODE BDS
Interrupt
request
Internal data bus
38
SOE SCOE
MB90630A Series
4. A/D Converter
The A/D converter converts analog input voltages to digital values. The A/D converter has the following features.
• Conversion time: Minimum of 5.2 µs per channel (for a 16 MHz machine clock)
• Uses RC-type successive approximation conversion with a sample and hold circuit.
• 10-bit resolution
• Eight program-selectable analog input channels
Single conversion mode
: Selectively convert a one channel.
Scan conversion mode
: Continuously convert multiple channels. Maximum of 8 programselectable channels.
Continuous conversion mode : Repeatedly convert specified channels.
Stop conversion mode
: Convert one channel then halt until the next activation. (Enables
synchronization of the conversion start timing.)
• An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D
conversion. This interrupt can activate I2OS to transfer the result of A/D conversion to memory and is suitable
for continuous operation.
• Activation by software, external trigger (falling edge), or timer (rising edge) can be selected.
(1) Register Configuration
The A/D converter has the following registers.
8
15
7
0
ADCS2
ADCS1
ADCR2
ADCR1
8 bits
bit
Address: 000036H
bit
Address: 000037H
bit
Address: 000038H
bit
Address: 000039H
8 bits
7
6
5
4
3
2
1
0
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
15
14
13
12
11
10
9
8
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
DA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
—
—
—
—
—
—
9
8
Control status register
(ADCS1, ADCS2)
Data register
(ADCR1, ADCR2)
39
MB90630A Series
(2) Block Diagram
AV CC
AVRH
AVRL
AV SS
D/A converter
MPX
Input circuit
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Successive
approximation register
Data bus
Comparator
Decoder
Sample and
hold circuit
Data register
ADCR1, 2
A/D control register 1
A/D control register 2
ADCS1, 2
Trigger activation
ADTG
Timer activation
PPG01
Operating clock
φ
40
Prescaler
MB90630A Series
5. D/A Converter
This block is an R-2R type D/A converter with 8-bit resolution. The device contains two D/A converters. The
D/A control register controls the output of the two D/A converters independently.
(1) Register Configuration
bit
Address: 00003AH
bit
Address: 00003BH
bit
Address: 00003CH
bit
Address: 00003DH
7
6
5
4
3
2
1
0
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
15
14
13
12
11
10
9
8
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
DAE0
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
DAE1
D/A converter data register 0
(DAT0)
D/A converter data register 0
(DAT1)
D/A control register 0
(DACR0)
D/A control register 1
(DACR1)
(2) Block Diagram
F2MC-16 bus
DA DA DA DA DA DA DA DA
17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA
07 06 05 04 03 02 01 00
DVR
DVR
DA07
DA17
2R
DA16
2R
DA15
R
R
R
2R
R
2R
R
DA05
DA01
DA11
2R
DA10
2R
DA06
R
DA00
2R 2R
2R 2R
DAE1
Standby control
DAE0
Standby control
DA output
channel 1
DA output
channel 0
41
MB90630A Series
6. 8/16-bit PPG
This block is an 8-bit reload timer module. The block performs PPG output in which the pulse output is controlled
by the operation of the timer.
The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two
external pulse output pins, and two interrupt outputs. The PPG has the following functions.
• 8-bit PPG output in two channels independent operation mode:
Two independent PPG output channels are available.
• 16-bit PPG output operation mode
: One 16-bit PPG output channel is available.
• 8+8-bit PPG output operation mode
: Variable-period 8-bit PPG output operation is available by using the
output of channel 0 as the clock input to channel 1.
• PPG output operation
: Outputs pulse waveforms with variable period and duty ratio. Can be
used as a D/A converter in conjunction with an external circuit.
(1) Register Configuration
PPG0 operation mode control
Address:
channel 0 000044H
Read/write
Initial value
PPG1 operation mode control
Address:
channel 1 000045H
Read/write
Initial value
6
5
4
3
2
1
0
PEN0
—
PE00
PIE0
PUF0
—
—
Reserved
(R/W)
(0)
(—)
(X)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(—)
(X)
(—)
(X)
(—)
(1)
15
14
13
12
11
10
9
8
PEN1
—
PE10
PIE1
PUF1
MD1
MD0
Reserved
(R/W)
(0)
(—)
(X)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(—)
(1)
PPG0, 1 output control register
7
6
5
4
3
2
1
0
Address: channel 0,1 000046H
PCS2
PCS1
PCS0
PCM2
PCM1
PCM0
PE11
PE01
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Read/write
Initial value
Reload register H
Address:
channel 0 000041H
channel 1 000043H
Read/write
Initial value
Reload register L
Address:
42
7
channel 0 000040H
channel 1 000042H
Read/write
Initial value
15
14
13
12
11
10
9
PPGC0
PPGC1
PPGOE
8
PRLH0, 1
(R/W)
(X)
7
(R/W)
(X)
6
(R/W)
(X)
5
(R/W)
(X)
4
(R/W)
(X)
3
(R/W)
(X)
2
(R/W)
(X)
1
(R/W)
(X)
0
PRLL0, 1
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
MB90630A Series
(2) Block Diagram
• 8/16-bit PPG (channel 0)
PPG00 output enable
Peripheral clock divided by 16
Peripheral clock divided by 8
Peripheral clock divided by 4
Peripheral clock divided by 2
Peripheral clock
PPG00
PPG01 output enable
PPG01
A/D converter
PPG0
output latch
Invert
Clear
PEN0
S
R Q
PCNT (Down-counter)
Count clock
selection
Timebase counter output
Main clock divided by 512
L/H select
IRQ
Reload
channel 1-borrow
L/H selector
PRLL0
PRLBH0
PIE 0
PRLH0
PUF0
L-side data bus
H-side data bus
PPGC0
(Operation mode control)
43
MB90630A Series
• 8/16-bit PPG (channel 1)
PPG10 output enable
Peripheral clock divided by 16
Peripheral clock divided by 8
Peripheral clock divided by 4
Peripheral clock divided by 2
Peripheral clock
PPG11 output enable
PPG10
PPG11
UART
PPG1
output latch
Invert
Clear
Count clock
selection
PEN1
S
R Q
PCNT (Down-counter)
IRQ
channel 0-borrow
Timebase counter output
Main clock divided by 512
L/H select
Reload
L/H selector
PRLL1
PRLBH1
PIE
PRLH1
PUF
L-side data bus
H-side data bus
PPGC1
(Operation mode control)
44
MB90630A Series
7. 8/16-bit Up/Down Counter/Timer
This block is an up/down counter/timer and consists of six event input pins, two 8-bit up/down counters, two 8bit reload/compare registers, and their control circuits.
(1) Main Functions
• The 8-bit count register can count in the range 0 to 256D
(or 0 to 65535D in 1 × 16-bit operation mode).
• The count clock selection can select between four different count modes.
Count modes
Timer mode
Up/down counter mode
Phase difference count mode (× 2)
Phase difference count mode (× 8)
• Two different internal count clocks are available in timer mode.
Count clock (at 16 MHz operation)
125 ns (8 MHz: Divide by 2)
1.0 µs (1 MHz: Divide by 8)
• In up/down count mode, you can select which edge to detect on the external pin input signal.
Detected edge
Detect falling edges
Detect rising edges
Detect both rising and falling edges
Edge detection disabled
• Phase difference count mode is suitable for motor encoder counting. By inputting the A, B, and Z phase outputs
from the encoder, a high-precision rotational angle, speed, or similar count can be implemented simply.
• Two different functions can be selected for the ZIN pin.
ZIN pin
Counter clear function
Gate function
• Compare and reload functions are available and can be used either independently or together. A variablewidth up/down count can be performed by activating both functions.
Compare/reload function
Compare function (Output an interrupt when a compare
occurs.)
Compare function (Output an interrupt and clear the
counter when a compare occurs.)
Reload function (Output an interrupt and reload when
an underflow occurs.)
Compare/reload function
(Output an interrupt and clear the counter when a
compare occurs. Output an interrupt and reload when
an underflow occurs.)
Compare/reload disabled
• Whether or not to generate an interrupt when a compare, reload (underflow), or overflow occurs can be set
independently.
• The previous count direction can be determined from the count direction flag.
• An interrupt can be generated when the count direction changes.
45
MB90630A Series
(2) Register Configuration
The 8/16-bit up/down counter/timer has the following registers.
8
15
0
UDCR1
UDCR0
RCR1
RCR0
Reversed area
CSR0
CCRH0
CCRL0
Reversed area
CSR1
CCRH1
CCRL1
8 bits
8 bits
7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
15
14
13
12
11
10
9
8
D17
D16
D15
D14
D13
D12
D11
D10
7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
15
14
13
12
11
10
9
8
Address: 000073H
D17
D16
D15
D14
D13
D12
D11
D10
bit
Address: 000074H
000078H
7
6
5
4
3
2
1
0
CSTR
CITE
UDIE
CMPF
OVFF
UDFF
UDF1
UDF0
7
6
5
4
3
2
1
0
—
CTUT
UCRE
RLDE
15
14
13
12
CFIE
CLKS
bit
Address: 000070H
bit
Address: 000071H
bit
Address: 000072H
bit
bit
Address: 000076H
00007AH
bit
Address: 000077H
bit
Address: 00007BH
46
7
M16E CDCF
7
6
5
4
—
CDCF
CFIE
CLKS
UDCC CGSC CGE1
11
10
CMS1 CMS0
3
2
CMS1 CMS0
CGE0
9
8
CES1
CES0
1
0
CES1
CES0
Up/down count register channel 0
(UDCR0)
Up/down count register channel 1
(UDCR1)
Reload compare register channel 0
(RCR1)
Reload compare register channel 1
(RCR1)
Counter status register channel 0, 1
(CSR0, 1)
Counter status register channel 0, 1
(CCRL0, 1)
Counter control register channel 0
(CCRH0)
Counter control register channel 1
(CCRH1)
MB90630A Series
(3) Block Diagram
• 8/16-bit Up/Down Counter/Timer (channel 0)
Data bus
8 bits
RCR0 (reload/compare regiater 0)
CGE1 CGE0 C/GS
ZIN0
Edge or level detection
UDCC
CTUT
Reload control
UCRE
RLDE
Counter clear
8 bits
UDCR0 (Up/down count regiater 0)
Carry
CES1 CES0
CMS1 CMS0
CITE
AIN0
BIN0
Up/down count
clock selection
Prescaler
CMPF
UDFF OVFF
UDIE
Count clock
UDF1 UDF0 CDCF CFIE
CSTR
Interrupt output
CLKS
47
MB90630A Series
• 8/16-bit Up/Down Counter/Timer (channel 1)
Data bus
8 bits
RCR1 (reload/compare register 1)
CGE1 CGE0 C/GS
ZIN1
Edge or level detection
UDCC
CTUT
Reload control
UCRE
RLDE
Counter clear
8 bits
UDCR1 (Up/down count register 1)
CMPF
UDFF OVFF
CMS1 CMS0 CES1 CES0 EN16
CITE
Carry
Count clock
AIN1
BIN1
Up/down count
clock selection
Prescaler
CLKS
48
UDF1 UDF0 CDCF CFIE
CSTR
Interrupt output
UDIE
MB90630A Series
8. Clock Output Control Register
The clock output outputs the divided machine clock.
(1) Register Configuration
bit
Clock control register
Address:
0003EH
Read/write
Initial value
7
6
5
4
3
2
1
0
—
—
—
—
CKEN
FRQ2
FRQ1
FRQ0
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
CLKR
(a) [bit 3] CKEN
CKOT output enable bit
MODE
Operation
0
Operate as a standard port.
1
Operate as the CKOT output.
(b) [bits 2, 1, 0] FRQ2, FRQ1, FRQ0
These bits select the output frequency of the clock.
FRQ2
FRQ1
FRQ0
Output clock
φ = 16 MHz
φ = 8 MHz
φ = 4 MHz
0
0
0
1
φ/2
125 ns
250 ns
500 ns
0
0
1
φ/22
250 ns
500 ns
1 µs
0
1
0
φ/23
500 ns
1 µs
2 µs
0
1
1
4
φ/2
1 µs
2 µs
4 µs
1
0
0
φ/25
2 µs
4 µs
8 µs
1
0
1
φ/26
4 µs
8 µs
16 µs
1
1
0
φ/2
8 µs
16 µs
32 µs
1
1
1
φ/28
16 µs
32 µs
64 µs
7
49
MB90630A Series
9. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16L CPU to activate the intelligent I/O service or interrupt processing. Two request levels
(“H” and “L”) are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts
on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types.
(1) Register Configuration
bit
Address: 000030H
bit
Address: 000031H
bit
Address: 000032H
bit
Address: 000033H
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
Interrupt/DTP enable register
(ENIR)
Interrupt/DTP source register
(EIRR)
Request level setting register
(ELVR)
Request level setting register
(ELVR)
(2) Block Diagram
F2MC-16 bus
4
4
4
8
50
Interrupt/DTP enable register
Gate
Request F/F
Interrupt/DTP source register
Request level setting register
Edge detect circuit
4
Request input
MB90630A Series
10. 16-bit I/O Timer
The 16-bit I/O timer consists of one 16-bit free-run timer, four output compare, and two input capture modules.
Based on the 16-bit free-run timer, these functions can be used to generate two independent waveform outputs
and to measure input pulse widths and external clock periods.
(1) A Summary of Each Function
• 16-bit free-run timer (× 1)
The 16-bit free-run timer consists of a 16-bit up-counter, a control register, and a prescaler. The output of the
timer/counter is used as the base time for the input capture and output compare.
(a) The operating clock for the counter can be selected from four different clocks.
Four internal clocks (φ/4, φ/16, φ/32, φ/64)
(b) Interrupts can be generated when a counter value overflow or compare match with compare register 0 occurs
(the appropriate mode must be set for a compare match).
(c) The counter can be initialized to 0000H by a reset, software clear, or compare match with compare register 0.
• Output compare (× 4)
The output compare consists of two 16-bit compare registers, compare output latches, and control registers.
The modules can invert the output level and generate an interrupt when the 16-bit free-run timer value matches
the compare register value.
(a) The four compare registers can be operated independently.
Each compare register has a corresponding output pin and interrupt flag.
(b) The four compare registers can be paired to control the output pins.
Invert the output pins using the four compare registers.
(c) Initial values can be set for the output pins.
(d) An interrupt can be generated when a compare match occurs.
• Input capture (× 2)
The input capture consists of two independent external input pins, their corresponding capture registers, and a
control register. The value of the 16-bit free-run timer can be stored in the capture register and an interrupt
generated when the specified edge is detected on the signal from the external input pin.
(a) The edge to detect on the external input signal is selectable.
Detection of rising edges, falling edges, or either edge can be specified.
(b) The two input capture channels can operate independently.
(c) An interrupt can be generated on detection of the specified edge on the external input signal.
The input capture interrupt can activate the intelligent I/O service.
51
MB90630A Series
(2) Register Configuration for the Entire 16-bit I/O Timer
• 16-bit free-run timer
bit
0
15
000066H
Timer data register
TCDT
000068H
Timer control status register
TCCS
• 16-bit output compare
bit
0
15
000050, 52, 54, 56H
Compare register channel 0 to 3
OCCP0 to 3
000058, 5AH
OCS1/3
Compare control status register
channel 0, 2
OCS0/2
• 16-bit input capture
bit
0
15
000060, 62H
Input capture register channel 0, 2
IPCP0 to 1
000064H
Input capture control status register
ICS
• Overall Block Diagram of the 16-bit I/O timer
To each block
Control logic
Interrupt
16-bit free-run timer
16-bit timer
Clear
Output compare 0
Compare register 0
TQ
OUT 0
TQ
OUT 1
TQ
OUT 2
TQ
OUT 3
bus
Output compare 1
Compare register 1
Output compare 2
Compare register 2
Output compare 3
Compare register 3
Input capture 0
52
Capture register 0
Edge selection
IN 0
Capture register 1
Edge selection
IN 1
MB90630A Series
(3) 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up-counter and a control status register. The count value of the
timer is used as the base time for the input capture and output compare.
(a) The count clock can be selected from four different clocks.
(b) Interrupts can be generated when a counter value overflow occurs.
(c) Depending on the mode setting, the counter can be initialized when a match occurs with compare register
0 of the output compare.
• Register Configuration
bit
0
15
000066H
Timer data register
TCDT
Timer/counter control status register
TCCS
000068H
• Block Diagram
Interrupt request
IVFE STOP MODE CLR
bus
IVF
CLK1 CLK0
φ
Divider
Comparator 0
16-bit up-counter
Clock
Count value output T15 to T00
53
MB90630A Series
• Register Details
Data Register
bit
Address:
000067H
Read/write
Initial value
bit
Address:
000066H
Read/write
Initial value
15
14
13
12
11
10
9
8
T15
T14
T13
T12
T11
T10
T09
T08
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
2
1
0
T07
T06
T05
T04
T03
T02
T01
T00
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
The count value of the 16-bit free-run timer can be read from this register. The count is cleared to “0000H” by a
reset. Writing to this register sets the timer value. However, only write to the register when the timer is halted
(STOP = “1”). Always use word access.
The 16-bit free-run timer is initialized by the following.
(a) Reset
(b) The clear bit (CLR) of the control status register
(c) A match between the timer/counter value and compare register 0 of the output compare (if the appropriate
mode is set)
54
MB90630A Series
(4) Output Compare
The output compare consists of 16-bit compare registers, compare output pins, and a control register. The
module can invert the output level and generate an interrupt when the 16-bit free-run timer value matches a
compare register value.
(a) The two compare registers can be operated independently.
The output compare can also be set to control pin output using two compare registers.
(b) The initial value of the output pins can be set.
(c) An interrupt can be generated when a compare match occurs.
• Register Configuration
bit
15
0
000050, 52, 54, 56H
bit
000058, 59, 5A, 5BH
Compare registers channel 0 to 3
OCCP0 to 3
15
0
OCSX
Compare control status registers
channel 0 to 3
X = 0 to 3
OCSX
• Block Diagram
16-bit timer/counter value (T15 to T00)
TQ
Compare control
OTEO
OUT0
(OUT2)
OTE1
OUT1
(OUT3)
Compare regiater 0 (2)
CMOD
bus
16-bit timer/counter value (T15 to T00)
TQ
Compare control
Compare regiater 1 (3)
ICP1
Controller
Control blocks
ICP0
ICE1
ICE0
Compare 1 interrupt (3)
Compare 0 interrupt (2)
55
MB90630A Series
(5) Input Capture
The function of this module is to store the value of the 16-bit free-run timer in a register when the specified edge
(rising, falling, or either edge) is detected on the external input signal. The module can also generate an interrupt
on detection of the edge. The input capture contains input capture data registers and a control register. Each
input capture has a corresponding external input pin.
(a) Three different types of edge detection can be selected.
Rising edges (↑), falling edges (↓), or either edge (↑ ↓).
(b) An interrupt can be generated on detection of the specified edge on the external input.
• Register Configuration (for the entire input capture)
bit
15
000060, 62H
0
Input capture data register
X = 0 to 1
IPCX
7
bit
0
000064H
Input capture control status register
X = 0 to 1
ICSX
• Block Diagram
Capture data register 0
Edge detection
IN 0
EG11 EG10 EG01 EG00
bus
16-bit timer/counter value (T15 to T00)
Capture data register 1
ICP1
Edge detection
ICP0
ICE1
IN 1
ICE0
Interrupt
Interrupt
56
MB90630A Series
• Register Details
Input capture data register
bit
15
14
13
12
11
10
9
8
000060, 62H
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
Read/write
Initial value
bit
Read/write
Initial value
7
6
5
4
3
2
1
0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
The 16-bit free-run timer value is stored in these registers when the specified edge is detected on the input
waveform from the corresponding external pin. (Always use word access. Writing is prohibited.)
57
MB90630A Series
11. Watchdog Timer
The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase
counter as its clock source, a control register, and a watchdog reset controller. The following block diagram
shows the structure of both the watchdog timer and timebase timer (see “12. Timebase Timer”).
(1) Block Diagram
WTE
Output enable
WT1
WT0
Selector
Reset
control
2-bit counter
Reset
Timebase counter
1
2
f/2
1
212
.........
1
213
1
214
1
215
1
216
1
217
1
218
Clear
Power-on reset
STOP mode
Clear
control
TBIE
IRQ
TBOF
Selectror
TBR
Clear
TBC1
2
I OS
TBC0
1/2 16 to 1/2 18 (Timebase division output)
OSC1
Oscillation stabilization delay completion signal
Selectror
OSC0
(2) Register Configuration
bit
Address: 0000A8H
58
7
6
5
4
3
2
1
0
PONR
STBR
WRST
ERST
SRST
WTE
WT1
WT0
Watchdog timer control register
(WDTC)
MB90630A Series
12. Timebase Timer
The timebase timer consists of an 18-bit timebase counter (which divides the system clock) and a control register.
The carry signal of the timebase counter can generate a fixed period interrupt.
All bits of the timebase counter are cleared to zero at power-on, when stop mode is set, or by software (by
writing “0” to the TBR bit). The timebase counter continuously increments while an oscillation is input.
The timebase counter is also used as the clock source for the watchdog timer and as a timer for the oscillation
stabilization delay time.
(1) Block Diagram
See “(1) Block diagram” in “11. Watchdog Timer” for the block diagram of the timebase timer.
(2) Register Configuration
bit
Address: 0000A9H
15
14
13
12
11
10
9
8
Reserved
—
—
TBIE
TBCF
TBR
TBC1
TBC0
Timebase timer control register
(TBTC)
(3) Register Details
• TBTC (Timebase timer control register)
bit
Address: 0000A9H
15
14
13
12
11
10
9
8
Reserved
—
—
TBIE
TBCF
TBR
TBC1
TBC0
(R/W)
(R/W)
(W)
(R/W)
(R/W)
(W)
Initial value
X--00000B
(a) [bit 15] Reserved
A reserved bit. Always set to “1” when writing data to the register.
(b) [bit 12] TBIE
Interval interrupt enable bit for the timebase timer. The interrupt is enabled when TBIE is “1” and disabled
when TBIE is “0”. Initialized to “0” by a reset. The bit is readable and writable.
(c) [bit 11] TBOF
Interrupt request flag for the timebase timer. An interrupt request is generated if TBCF goes to “1” when
TBIE is “1”. The bit is set to “1” at fixed intervals set by the TBC1 and 0 bits. Clear by writing “0”, transition
to stop or hardware standby mode, or a reset. Writing “1” has no meaning.
Read as “1” by read-modify-write instructions.
(d) [bit 10] TBR
Clears all bits of the timebase counter to “0”. Writing “0” to the TBR bit clears the timebase counter. Writing
“1” to the TBR bit is meaningless. Reading from the TBR bit results in “1”.
(e) [bit 9, 8] TBC1, 0
Set a timebase timer interval. The bits are initialized to “00” by resetting. These bits are readable and writable.
Setting of timebase timer interval
TBC1
TBC0
Interval time when base
frequency is 4 MHz
0
0
1.024 ms
0
1
4.096 ms
1
0
16.384 ms
1
1
131.072 ms
59
MB90630A Series
13. External Bus Pin Control Circuit
The external bus pin control circuit controls the external bus pins required to extend the CPU’s address/data
bus outside the device.
(1) Register Configuration
bit
Auto-ready function selection register
0000A5H
Address:
Read/write
Initial value
bit
External address output control register
Address:
0000A6H
Read/write
Initial value
bit
Bus control signal selection register
0000A7H
Address:
Read/write
Initial value
15
14
13
12
11
10
9
8
ICR1
ICR0
HMR1
HMR0
—
—
LMR1
LMR0
(W)
(0)
(W)
(0)
(W)
(1)
(W)
(1)
(—)
(—)
(—)
(—)
(W)
(0)
(W)
(0)
7
6
5
4
3
2
1
0
E23
E22
E21
E20
E19
E18
E17
E16
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
15
14
13
12
11
10
9
8
CKE
RYE
HDE
ICBS
HMBS
WRE
LMBS
—
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(1/0)
(W)
(0)
(W)
(0)
(—)
(—)
HACR
EPCR
(2) Block Diagram
P0
P0 data
P0 direction
RB
Data control
Address control
Access control
60
Access control
P1
P2
P3
P3
P0
ARSR
MB90630A Series
4. Low-Power Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization
Delay Time, and Clock Multiplier Function)
The following operation modes are available: PLL clock mode, PLL sleep mode, timer mode, main clock mode,
main sleep mode, stop mode, and hardware standby mode. Operation modes other than PLL clock mode are
classified as low power consumption modes.
In main clock mode and main sleep mode, the device operates on the main clock only (OSC oscillator clock).
The PLL clock (VCO oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the
operating clock.
In PLL sleep mode and main sleep mode, the CPU’s operating clock only is stopped and other elements continue
to operate.
In timer mode, only the timebase timer operates.
Stop mode and hardware standby mode stop the oscillator. These modes maintain existing data with minimum
power consumption.
The CPU intermittent operation function provides an intermittent clock to the CPU when register, internal
memory, internal resource, or external bus access is performed. This function reduces power consumption by
lowering the CPU execution speed while still providing a high-speed clock to internal resources.
The PLL clock multiplier ratio can be set to 1, 2, 3, or 4 by the CS1, 0 bits.
The WS1, 0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from stop
mode or hardware standby mode.
(1) Register Configuration
bit
Low-power consumption mode register
Address:
0000A0H
Read/write
Initial value
bit
Clock select register
Address:
0000A1H
Read/write
Initial value
7
6
5
4
3
2
1
0
STP
SLP
SPL
RST
Reserved
CG1
CG0
Reserved
(W)
(0)
(W)
(0)
(R/W)
(0)
(W)
(1)
(—)
(1)
(R/W)
(0)
(R/W)
(0)
(—)
(0)
15
14
13
12
11
10
9
8
Reserved
MCM
WS1
WS0
Reserved
MCS
CS1
CS0
(—)
(1)
(R)
(1)
(R/W)
(1)
(R/W)
(1)
(—)
(1)
(R/W)
(1)
(R/W)
(0)
(R/W)
(0)
LPMCR
CKSCR
61
MB90630A Series
(2) Block Diagram
• Low-Power Consumption Control Circuit and Clock Generator
CKSCR
MCM
MCS
Main clock
(OSC oscillator)
PLL multiplier
circuit
1 2 3 4 1/2
CPU clock
CPU clock
generator
CKSCR
CS1
CS0
CPU
clock selector
0/9/17/33
intermittent cycle selection
LPMCR
F2MC-16 bus
CG1
CG0
Cycle selection
circuit for the CPU
intermittent
operation function
LPMCR
SLP
STP
Peripheral
clock
generator
Standby control
circuit
RST release HSTactivate
Peripheral clock
HST pin
CKSCR
OSC1
OSC0
Interrupt request
or RST
Oscillation
stabilization
delay time
selector
24
213
215
218
Clock input
Timebase clock
Timebase timer
2
12
2
14
2
16
19
2
LPMCR
SPL
LPMCR
RST
Pin high impedance control circuit
Internal reset
generator
Pin HI-Z
RST pin
Internal RST
To watchdog timer
WDGRST
62
MB90630A Series
• State Transition Diagram for Clock Selection
Power-on
Main
MCS=1
MCM=1
CS1/0=XX
(1)
Main→PLLX
MCS=0
MCM=1
(6) CS1/0=XX
(2)
(3)
(7)
(7)
PLL1→Main
MCS=1
MCM=0
CS1/0=00
PLL2→Main
MCS=1
(7) MCM=0
CS1/0=01
PLL3→Main
(7) MCS=1
MCM=0
CS1/0=10
PLL4→Main
MCS=1
MCM=0
CS1/0=11
(4) (6)
PLL 2
multiplier
MCS=0
MCM=0
CS1/0=01
(6)
(5)
(6)
(6)
PLL 1
multiplier
MCS=0
MCM=0
CS1/0=00
PLL 3
multiplier
MCS=0
MCM=0
CS1/0=10
PLL 4
multiplier
MCS=0
MCM=0
CS1/0=11
(1) MCS bit cleared
(2) PLL clock oscillation stabilization delay complete and CS1/0=“00”
(3) PLL clock oscillation stabilization delay complete and CS1/0=“01”
(4) PLL clock oscillation stabilization delay complete and CS1/0=“10”
(5) PLL clock oscillation stabilization delay complete and CS1/0=“11”
(6) MCS bit set (including a hardware standby or watchdog reset)
(7) PLL clock and main clock synchronized timing
63
MB90630A Series
5. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to
the F2MC-16L CPU can be generated and cleared by software using this module.
(1) Register Configuration
Address:
bit
15
14
13
12
11
10
9
8
00009FH
—
—
—
—
—
—
—
R0
Delayed interrupt request register
(DIRR)
(2) Register Details
Delayed interrupt request register (DIRR)
Address:
bit
15
14
13
12
11
10
9
8
00009FH
—
—
—
—
—
—
—
R0
Initial value
-------0B
(R/W)
The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register
generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register
is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However,
considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for
register access.
(3) Block Diagram
F2MC-16 bus
Delayed interrupt generate/clear decoder
64
Interrupt latch
MB90630A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Symbol
Parameter
Value
Unit
Min.
Max.
VSS – 0.3
VSS + 7.0
V
AV *
VSS – 0.3
VSS + 7.0
V
AVRH, AVRL*1
VSS – 0.3
VSS + 7.0
V
VPP
VSS – 0.3
—
V
Input voltage*
VI
VSS – 0.3
VCC + 0.3
V
Output voltage*2
VO
VSS – 0.3
VCC + 0.3
V
IOL
—
15
mA
IOLAV
—
50
mA
“L” level total (maximum) output current ΣIOL
—
100
mA
“L” level total (average) output current*5 ΣIOLAV
—
50
mA
VCC
CC 1
Power supply voltage
Program voltage
2
“L” level (maximum) output current*3
“L” level (average) output current*
4
“H” level (maximum) output current*
IOH
—
–15
mA
“H” level (average) output current*4
IOHAV
—
–50
mA
“H” level total (maximum) output current ΣIOH
—
–100
mA
3
“H” level total (average) output current*
ΣIOHAV
—
–50
mA
Power consumption
Pd
—
+400
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
5
*1:
*2:
*3:
*4:
*5:
Remarks
AVCC, AVRH, and AVRL must not exceed VCC. Similarly, it must not exceed AVRH and AVRL.
VI and VO must not exceed VCC + 0.3 V.
The maximum output current must not be exceeded at any individual pin.
The average output current is the rating for the current from an individual pin averaged over 100 ms.
The average total output current is the rating for the current from all pins averaged over 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
65
MB90630A Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Power supply voltage
“H” level input voltage
“L” level input voltage
Operating temperature
Symbol
Value
Unit
Remarks
Min.
Max.
2.7
5.5
V
For normal operation
2.7
5.5
V
To maintain statuses in stop mode
VIH
0.7 VCC
VCC + 0.3
V
Other than VIHS
VIHS
0.8 VCC
VCC + 0.3
V
Hysteresis inputs
VIHM
VCC – 0.3
VCC + 0.3
V
VIL
VSS – 0.3
0.3 VCC
V
Other than VILS
VILS
VSS – 0.3
0.2 VCC
V
Hysteresis inputs
VILM
VSS – 0.3
VSS + 0.3
V
–40
+85
°C
VCC
TA
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
66
MB90630A Series
3. DC Characteristics
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
name
VIH
“H” level input voltage
VIHS
—
VIL
VILS
—
“H” level output voltage VOH
—
—
“L” level output voltage VOL
Pull-up resistor
Rpull
RST
ICC
ICCS
Power supply current*2
VCC
ICC
ICCS
VCC
Max.
0.7 VCC
—
VCC + 0.3
V
0.8 VCC
—
VCC + 0.3
V
VCC – 0.3
—
VCC + 0.3
V
0.7 VCC
—
VCC + 0.3
V
0.8 VCC
—
VCC + 0.3
V
VSS – 0.3
—
VSS + 0.3
V
VCC = +4.5
V±10%
IOH = –4.0 mA
VCC – 0.5
—
—
V
VCC = +2.7 V
IOH = –1.6 mA
VCC – 0.3
—
—
V
VCC = +4.5
V±10%
IOH = –4.0 mA
—
—
0.4
V
VCC = +2.7 V
IOH = –2.0 mA
—
—
0.4
V
22
—
110
kΩ
—
60
80
mA
—
20
35
mA
—
15
40
mA
—
10
15
mA
—
—
20
µA
—
10
—
pF
–10
—
10
µA
—
0.1
10
µA
VCC = +5.0
V±10%
VCC = +5.0
V±10%
—
VCC = +5.0
V±10%
FC = 16 MHz
VCC = +3.0
V±10%
FC = 10 MHz
VCC = +5.0
V±10%
ICCH
Input pin capacitance
CIN
Other
than VCC
and VSS
Input leak current
IIL
P73, 74
P86, 87
Leak current for
open-drain outputs
Ileak
P50 to
P57
Unit Remarks
Typ.
—
VILM
Value
Min.
—
VIHM
“L” level input voltage
Condition
—
VCC = 5.5 V
VSS < VI < VCC
—
*1
*1
*1: Hysteresis input pins: RST, HST
*2: Current values are provisional and are subject to change without notice to allow for improvements to the
characteristics and similar.
67
MB90630A Series
4. AC Characteristics
(1) Clock Timing
• When VCC = 5.0 V±10%
(VCC = 4.5 V to +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Symbol
Pin
name
Clock frequency
FC
X0, X1
—
3
16
MHz
Clock cycle time
tC
X0, X1
—
62.5
333
ns
Input clock pulse width
PWH, PWL
X0
—
10
—
ns
Input clock rise time and
fall time
tcr, tcf
X0
—
—
5
ns
Internal operating clock
frequency
fCP
—
—
1.5
16
MHz
Internal operating clock
cycle time
tCP
—
—
62.5
333
ns
Parameter
The duty ratio should
be in the range 30 to
70%
• When VCC = 2.7 V (min.)
(VCC = 4.5 V to +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Symbol
Pin
name
Clock frequency
FC
X0, X1
—
3
10
MHz
Clock cycle time
tC
X0, X1
—
100
333
ns
Input clock pulse width
PWH, PWL
X0
—
20
—
ns
Input clock rise time and
fall time
tcr, tcf
X0
—
—
5
ns
Internal operating clock
frequency
fCP
—
—
1.5
8
MHz
Internal operating clock
cycle time
tCP
—
—
100
333
ns
Parameter
• Clock Timing
tC
0.8 V CC
0.2 V CC
P WL
P WH
t cf
68
t cr
The duty ratio should
be in the range 30 to
70%
MB90630A Series
• PLL Operation Assurance Range
Relationship between the internal operating clock frequency and suply voltage
Normal operation range
VCC Voltage (V)
5.5
4.5
3.3
PLL operation assurance range
2.7
1.5
8
3
16
Internal clock FCP (MHz)
Relationship between the oscillation frequency and internal operating clock frequency
Multiply Multiply
by 4
by 3
16
No multiplier
Internal clock FCP (MHz)
Multiply
by 2
Multiply by 1
12
9
8
4
3 4
8
16
24
32
Oscillation clock FC (MHz)
Note: Low voltage operation down to 2.7 V is also assured for the evaluation tools.
The AC characteristics are for the following measurement reference voltages.
• Input Signal Waveform
Hysteresis input pins
• Output Signal Waveform
Output pins
0.8 V CC
2.4 V
0.2 V CC
0.8 V
Other than hysteresis or MD input pins
0.7 V CC
0.3 V CC
69
MB90630A Series
(2) Clock Output Timing
Symbol
Parameter
Cycle time
tCYC
CLK ↑ → CLK↓
tCHCL
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Pin
name
VCC = 5.0
V±10%
CLK
62.5
—
ns
20
—
ns
t CYC
t CHCL
2.4 V
2.4 V
CLK
0.8 V
(3) Reset and Hardware Standby Inputs
Parameter
Reset input time
Symbol
Pin
name
tRSTL
RST
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
4
—
Machine
cycle
4
—
Machine
cycle
—
Hardware standby input time
tHSTL
HST
t RSTL, t HSTL
RST
HST
0.2 V CC
70
0.2 V CC
MB90630A Series
(4) Power-on Reset
Parameter
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
Symbol
Power supply rising time
tR
VCC
Power supply cut-off time
tOFF
VCC
—
—
30
ms
1
—
ms
Note: The above values are the values required for a power-on reset.
tR
V CC
2.25 V
0.2 V
Abrupt changes in the power supply voltage may cause a power-on reset.
When changeing the power supply voltage during operation, suppress variations in the voltage and
ensure that the voltage rises smoothly, as shown in the following figure. Also, do not use the PLL
clock when varying the voltage. However, the supply voltage can be changed when using the PLL
clock if the voltage drops by less than 1 mV/s.
5.0 V
V CC
2.7 V
Holding RAM data
The gradient should be no
more than 50 mV/ms.
V SS
71
MB90630A Series
(5) Bus Timing (Read)
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
Symbol
Parameter
ALE pulse width
tLHLL
ALE
tCP/2 –20
—
Valid address → ALE ↓ time
tAVLL
Multiplexed
address
tCP/2 –25
—
ALE ↓ → address valid time
tLLAX
Multiplexed
address
tCP/2 –15
—
Valid address → RD ↓ time
tAVRL
Multiplexed
address
tCP –15
—
Valid address→ valid data input
tAVDV
Multiplexed
address
—
5 tCP/2 –60
ns
RD pulse width
tRLRH
RD
3 tCP/2 –20
—
ns
RD ↓ → valid data input
tRLDV
—
3 tCP/2 –60
ns
RD ↑ → data hold time
tRHDX
0
—
ns
Valid address → valid data input
tAVDV
0
—
ns
RD ↑ → ALE ↑ time
tRHLH
RD, ALE
tCP/2 –15
—
ns
RD ↑ → address valid time
tRHAX
Address, RD
tCP/2 –10
—
ns
Valid address → CLK ↑ time
tAVCH
Address, CLK
tCP/2 –20
—
ns
RD ↓ → CLK ↑ time
tRLCH
RD, CLK
tCP/2 –20
—
ns
D15 to D00
t RLCH
2.4 V
t AVLL
ALE
ns
—
t AVCH
CLK
ns
2.4 V
t LLAX
t RHLH
2.4 V
0.8 V
2.4 V
t LHLL
2.4 V
t AVRL
t RLRH
2.4 V
RD
0.8 V
t RHAX
A19 to
A16
2.4 V
0.8 V
2.4 V
0.8 V
t RLDV
t AVDV
AD15 to
AD00
72
2.4 V
Address
0.8 V
t RHDX
2.4 V
0.7 V CC
0.8 V
0.3 V CC
Read data
0.7 V CC
0.3 V CC
MB90630A Series
(6) Bus Timing (Write)
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin name
Condition
Value
Min.
Max.
Unit
Valid address → WR ↓ time
tAVWL
A19 to A00
tCP–15
—
ns
Valid address → RD ↓ time
tAVRL
A23 to A00
tCP/2 –15
—
ns
WR pulse width
tWLWH
WR
3 tCP/2 –20
—
ns
RD pulse width
tRLRH
RD
3 tCP/2 –20
—
ns
Valid data output → WR ↑
time
tDVWH
D15 to D00
3 tCP/2 –20
—
ns
WR ↑ → data hold time
tWHDX
D15 to D00
20
—
ns
WR ↑ → address valid time
tWHAX
A19 to A00
tCP/2 –10
—
ns
WR ↑ → ALE ↑ time
tWHLH
WR, ALE
tCP/2 –15
—
ns
WR ↓ → CLK ↑ time
tWLCH
WRL, WRH,
CLK
tCP/2 –20
—
ns
—
Remarks
t WLCH
2.4 V
CLK
t WHLH
2.4 V
ALE
t AVWL
t WLWH
2.4 V
WR
(WRL, WRH)
0.8 V
t WHAX
A19 to
A16
2.4 V
2.4 V
0.8 V
0.8 V
t DVWH
AD15 to
AD00
2.4 V
0.8 V
Address
2.4 V
0.8 V
Write data
t WHDX
2.4 V
0.8 V
73
MB90630A Series
(7) Ready Input Timing
Parameter
Symbol
RDY setup time
tRYHS
RDY hold time
tRYHH
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Max.
Pin name
RDY
VCC = 5.0 V ±10%
45
—
ns
VCC = 3.0 V ±10%
70
—
ns
—
0
—
ns
Note: Use the auto-ready function if the RDY setup time is too short.
2.4 V
CLK
2.4 V
ALE
RD/WR
RDY (When one wait
states are inserted)
RDY (When wait states
are not inserted)
74
t RYHS
t RYHS
0.2 VCC
0.2 VCC
t RYHS
t RYHH
0.8 VCC
0.8 VCC
MB90630A Series
(8) Hold Timing
Parameter
Symbol
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Condition
Unit
Remarks
Min.
Max.
Pin floating → HAK ↓ time
tXHAL
HAK
—
30
tCP
ns
HAK ↑ → pin valid time
tHAHV
HAK
—
tCP
2 tCP
ns
Note: After reading HRQ, more than one cycle is required before changing HAK.
HRQ
HAK
t XHAL
Pin
t HAHV
High impedance
75
MB90630A Series
(9) UART Timing
Parameter
Pin
Symbol name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOV
Valid SIN → SCK ↑
SCK ↑ → valid SIN hold time
tIVSH
tSHIX
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK ↓ → SOT delay time
tSLOV
Valid SIN → SCK ↑
SCK ↑ → valid SIN hold time
tIVSH
tSHIX
—
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
—
8 tCP
—
ns
VCC = +5.0 V ±10%
–80
80
ns
VCC = +3.0 V ±10%
–120
120
ns
VCC = +5.0 V ±10%
100
—
ns
VCC = +3.0 V ±10%
200
—
ns
VCC = +5.0 V ±10%
60
—
ns
VCC = +3.0 V ±10%
120
—
ns
—
4 tCP
—
ns
—
4 tCP
—
ns
VCC = +5.0 V ±10%
—
150
ns
VCC = +3.0 V ±10%
—
200
ns
VCC = +5.0 V ±10%
60
—
ns
VCC = +3.0 V ±10%
120
—
ns
VCC = +5.0 V ±10%
60
—
ns
VCC = +3.0 V ±10%
120
—
ns
Notes: • These are the AC characteristics for CLK synchronous mode.
• CL is the load capacitance connected to the pin at testing.
• tCP is the machine cycle period (unit: ns).
76
CL = 80 pF+1TTL
for the internal
shift clock mode
output pin
CL = 80 pF+1TTL
for the external
shift clock mode
output pin
MB90630A Series
• Internal Shift Clock Mode
t SCYC
2.4 V
SCK
0.8 V
t SLOV
0.8 V
2.4 V
0.8 V
SOT
t IVSH
t SHIX
0.8 V CC
0.2 V CC
SIN
0.8 V CC
0.2 V CC
• External Shift Clock Mode
t SLSH
t SHSL
SCK
0.2 V CC
t SLOV
SOT
0.2 V CC
2.4 V
0.8 V
t IVSH
SIN
0.8 V CC
0.8 V CC
0.8 V CC
0.2 V CC
t SHIX
0.8 V CC
0.2 V CC
77
MB90630A Series
(10) I/O Extended Serial Timing
Parameter
Pin
Symbol name
Serial clock cycle time
tSCYC
—
SCK ↓ → SOT delay time
tSLOV
—
Valid SIN → SCK ↑
tIVSH
—
SCK ↑ → valid SIN hold
time
tSHIX
—
Serial clock “H” pulse
width
tSHSL
—
Serial clock “L” pulse
width
tSLSH
—
SCK ↓ → SOT delay time
tSLOV
—
Valid SIN →SCK ↑
tIVSH
SCK ↑ → valid SIN hold
time
tSHIX
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
—
8 tCP
—
ns
VCC = +5.0 V ±10%
—
80
ns
VCC = +3.0 V ±10%
—
160
ns
—
tCP
—
ns
—
tCP
—
ns
VCC = +5.0 V ±10%
230
—
ns
VCC = +3.0 V ±10%
460
—
ns
VCC = +5.0 V ±10%
230
—
ns
VCC = +3.0 V ±10%
460
—
ns
—
2 tCP
—
ns
—
—
tCP
—
ns
—
—
2 tCP
—
ns
Notes: • These are the AC characteristics for CLK synchronous mode.
• CL is the load capacitance connected to the pin at testing.
• tCP is the machine cycle period (unit: ns).
• The values in the table are target values.
78
CL = 80 pF+1TTL
for the internal
shift clock mode
output pin
CL = 80 pF+1TTL
for the external
shift clock mode
output pin
Max. 2 MHz
MB90630A Series
• Internal Shift Clock Mode
t SCYC
2.4 V
SCK
0.8 V
t SLOV
0.8 V
2.4 V
0.8 V
SOT
t IVSH
t SHIX
0.8 V CC
0.2 V CC
SIN
0.8 V CC
0.2 V CC
• External Shift Clock Mode
t SLSH
t SHSL
SCK
0.2 V CC
t SLOV
SOT
0.2 V CC
2.4 V
0.8 V
t IVSH
SIN
0.8 V CC
0.8 V CC
0.8 V CC
0.2 V CC
t SHIX
0.8 V CC
0.2 V CC
79
MB90630A Series
(11) Timer Output Timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
SCK ↑ → TOUT change
time
tTO
Pin name
Condition
Value
Unit
Min.
Max.
VCC = +5.0 V ±10%
30
—
ns
PPG00 to PPG11 VCC = +3.0 V ±10%
80
—
ns
OUT0 to OUT3
Remarks
2.4 V
CLK
OUT0 to OUT3
PPG0 to PPG1
2.4 V
0.8 V
t TO
(12) Trigger Input Timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Input pulse width
Symbol
tTRGH
tTRGL
Pin name
Condition
ATG,
IRQ0 to IRQ7
IN0, IN1
—
0.8 V CC
Min.
Max.
5 tCP
—
Unit
ns
0.8 V CC
ATG,
IRQ0 to IRQ7
IN0, IN1
0.2 V CC
t TRGH
80
Value
0.2 V CC
t TRGL
Remarks
MB90630A Series
(13) Up/down Counter
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin name
Condition
Value
Min.
Max.
Unit
AIN input “1” pulse
width
tAHL
8 tCYL
—
ns
AIN input “0” pulse
width
tALL
8 tCYL
—
ns
BIN input “1” pulse
width
tBHL
8 tCYL
—
ns
BIN input “0” pulse
width
tBLL
8 tCYL
—
ns
AIN ↑ → BIN ↑ time
tAUBU
4 tCYL
—
ns
BIN ↑ → AIN ↓ time
tBUAD
4 tCYL
—
ns
AIN ↓ → BIN ↓ time
tADBD
4 tCYL
—
ns
BIN ↓ → AIN ↑ time
tBDAU
4 tCYL
—
ns
BIN ↑ → AIN ↑ time
tBUAU
4 tCYL
—
ns
AIN ↑ → BIN ↓ time
tAUBD
4 tCYL
—
ns
BIN ↓ → AIN ↓ time
tBDAD
4 tCYL
—
ns
AIN ↓ → BIN ↑ time
tADBU
4 tCYL
—
ns
ZIN input “1” pulse
width
tZHL
4 tCYL
—
ns
ZIN input “0” pulse
width
tZLL
4 tCYL
—
ns
AIN0, AIN1
BIN0, BIN1
—
Remarks
ZIN0, ZIN1
81
MB90630A Series
t AHL
AIN
t ALL
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
t AUBU
t BUAD
t ADBD
0.8 VCC
BIN
0.2 VCC
t BDAU
0.8 VCC
0.2 VCC
t BHL
t BLL
t BHL
BIN
0.8 VCC
t BLL
0.8 VCC
0.8 VCC
0.2 VCC
t BUAU
t AUBD
0.2 VCC
t BDAD
0.8 VCC
BIN
t ADBU
0.8 VCC
0.2 VCC
t AHL
0.8 VCC
ZIN
0.2 VCC
t ALL
0.8 VCC
t ZHL
t ZLL
0.2 VCC
82
0.2 VCC
0.2 VCC
MB90630A Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +2.7 V to +5.5 V, AVSS = VSS = 0.0 V, 2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C)
Value
Symbol
Pin name
Unit
Parameter
Min.
Typ.
Max.
Resolution
—
—
—
10
10
bit
Total error
—
—
—
—
±3.0
LSB
Linearity error
—
—
—
—
±2.0
LSB
Differential linearity error
—
—
—
—
±1.5
LSB
Zero transition error
VOT
AN0 to AN7
–1.5
+0.5
+2.5
LSB
Full scale transition error
VFST
AN0 to AN7
AVRH –3.5
AVRL –1.5
AVRH +0.5
LSB
1
—
—
µs
8.12*2
—
—
µs
5.12*
Conversion time
—
—
Analog port input current
IAIN
AN0 to AN7
—
—
10
µA
Analog input voltage
VAIN
AN0 to AN7
AVRL
—
AVRH
V
—
AVRH
AVRL + 2.7
—
AVCC
V
—
AVRL
0
—
AVRH – 2.7
V
IA
AVCC
—
5
—
mA
IAH
AVCC
—
—
3
5*
µA
Reference voltage
Power supply current
Reference voltage supply
current
IR
AVRH
—
200
—
µA
IRH
AVRH
—
—
5*3
µA
Variation between channels
—
AN0 to AN7
—
—
4
LSB
*1: For VCC = +5.0 V ±10% and a 16 MHz machine clock
*2: For VCC = +3.0 V ±10% and an 8 MHz machine clock
*3: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = +5.0 V).
Notes: • The error increases proportionally as |AVRH – AVRL| decreases.
• The output impedance of the external circuits connected to the analog inputs should be in the following
range.
Output impedance of external circuit < approx. 10 kΩ
• If the output impedance of the external circuit is too high, the sampling time for the analog voltage may
be too short. (Sampling time = 3.8 µs (corresponds to 16 MHz internal operation if the multiplier is 4.))
• Model of the Analog Input Circuit
Sample and hold circuit C 0
Analog input
Comparator
R ON1
R ON2
RON1 = 1.5 kΩ (approx.) (VCC = 5.0 V)
RON2 = 0.5 kΩ (approx.) (VCC = 5.0 V)
RON3 = 0.5 kΩ (approx.) (VCC = 5.0 V)
RON4 = 0.5 kΩ (approx.) (VCC = 5.0 V)
C0 = 60 pF (approx.)
C1 = 4 pF (approx.)
R ON3
R ON4
C1
Note: The above values are for reference only.
83
MB90630A Series
6. A/D Converter Glossary
• Resolution
The change in analog voltage that can be recognized by the A/D converter.
If the resolution is 10 bits, the analog voltage can be resolved into 210 = 1024 steps.
• Total error
The deviation between the actual and logic value attributable to offset error, gain error, non-linearity error, and
noise.
• Linearity error
The deviation between the actual conversion characteristic of the device and the line linking the zero transition
point (00 0000 0000 ↔ 00 0000 0001) and the full scale transition point (11 1111 1110 ↔ 11 1111 1111).
• Differential linearity error
The variation from the ideal input voltage required to change the output code by 1 LSB.
Digital output
11 1111 1111
11 1111 1110
•
•
•
•
•
•
•
•
•
•
•
(1LSB × N + V OT)
Linearity error
00 0000 0010
00 0000 0001
00 0000 0000
Analog input
V OT
1LSB =
V NT V (N+1)T
V FST – V OT
1022
Linearity error =
V NT – (1LSB × N + V OT )
1LSB
Differential linearity error =
84
[LSB]
V(N+1)T – V NT
– 1 [LSB]
1LSB
V FST
MB90630A Series
7. 8-bit D/A Converter Electrical Characteristics
Parameter
Symbol Pin name
(VCC = 2.7 to 5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Unit
Remarks
Min.
Typ.
Max.
Resolution
—
—
—
8
8
bit
Differential linearity error
—
—
–0.9
—
0.9
LSB
Absolute accuracy
—
—
—
—
1.2
%
Conversion time
—
—
—
10
20
µS
The load
capacitance = 20
pF
Analog reference power
supply voltage
—
DVRH
VSS + 1.7
—
VCC
V
DVSS = VSS = 0.0 V
Reference power supply
current (when operating)
ID
DVRH
—
1.0
1.5
Current
mA consumption at
conversion
Reference power supply
current (when stopped)
IDH
DVRH
—
—
10
µA
Analog output impedance
—
DA0
—
28
—
kΩ
Current
consumption
when stopped
Note: DVSS must be connected at VSS = 0.0 V.
85
MB90630A Series
■ EXAMPLE CHARACTERISTICS
(1) “H” Level Output Voltage
VOH – IOH
VOH (V)
1.0
0.9 TA = +25°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–2
–4
–6
(2) “L” Level Output Voltage
VCC = +2.7 V
VCC = +3.0 V
VCC = +3.5 V
VCC = +4.0 V
VCC = +4.5 V
VCC = +5.0 V
–8
IOH (mA)
(3) “H” Level Input Voltage/“L” Level Input Voltage
(CMOS Input)
VIN – VCC
VIN (V)
5.0
TA = +25°C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2
3
4
5
6
VCC (V)
V OL (V)
1.0
0.9 TA = +25°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2
4
VOL – IOL
VCC = +2.7 V
VCC = +3.0 V
VCC = +3.5 V
VCC = +4.0 V
VCC = +4.5 V
VCC = +5.0 V
6
8
IOL (mA)
(4) “H” Level Input Voltage/“L” Level Input Voltage
(Hysteresis Input)
VIN (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2
VIN – VCC
TA = +25°C
VIHS
VILS
3
4
5
VIHS : Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS : Threshold when input voltage in hysteresis
characteristics is set to “L” level
86
6
VCC (V)
MB90630A Series
(5) Power Supply Current (fCP = Internal Operating Clock Frequency)
ICC (mA)
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
ICC–VCC
TA = +25°C
fcp = 16 MHz
fcp = 12.5 MHz
fcp = 8 MHz
fcp = 4 MHz
3.0
IA (mA)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
5.0
6.0
VCC (V)
ICCS (mA)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
3.0
ICCS–VCC
TA = +25°C
fcp = 16 MHz
fcp = 12.5 MHz
fcp = 8 MHz
fcp = 4 MHz
4.0
5.0
6.0
VCC (V)
IA–AVCC
IR (mA)
0.30
TA = +25°C
fCP = 16 MHz
IR–AVR
TA = +25°C
fCP = 16 MHz
0.20
0.10
0
3.0
4.0
5.0
6.0
AVCC (V)
3.0
4.0
5.0
6.0
AVR (V)
(5) Pull-up Resistance
R–VCC
R (kΩ)
1000
TA = +25°C
100
10
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
87
MB90630A Series
■ INSTRUCTIONS (340 INSTRUCTIONS)
Table 1
Explanation of Items in Tables of Instructions
Item
Mnemonic
Meaning
Upper-case letters and symbols: Represented as they appear in assembler.
Lower-case letters:
Replaced when described in assembler.
Numbers after lower-case letters: Indicate the bit width within the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
m : When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
RG
B
Operation
Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the “~” column.
Indicates the operation of instruction.
LH
Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers “0”.
X : Extends with a sign before transferring.
– : Transfers nothing.
AH
Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
– : No transfer.
Z : Transfers 00H to AH.
X : Transfers 00H or FFH to AH by signing and extending AL.
I
S
T
N
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
– : No change.
S : Set by execution of instruction.
R : Reset by execution of instruction.
Z
V
C
RMW
88
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
– : Instruction is not a read-modify-write instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
MB90630A Series
Table 2
Explanation of Symbols in Tables of Instructions
Symbol
A
Meaning
32-bit accumulator
The bit length varies according to the instruction.
Byte : Lower 8 bits of AL
Word : 16 bits of AL
Long : 32 bits of AL:AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Compact direct addressing
addr16
addr24
ad24 0 to 15
ad24 16 to 23
Direct addressing
Physical direct addressing
Bit 0 to bit 15 of addr24
Bit 16 to bit 23 of addr24
io
imm4
imm8
imm16
imm32
ext (imm8)
disp8
disp16
bp
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
(Continued)
89
MB90630A Series
(Continued)
Symbol
Meaning
rel
Branch specification relative to PC
ear
eam
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
Register list
Table 3
Code
00
01
02
03
04
05
06
07
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Effective Address Fields
Address format
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Number of bytes in address
extension *
Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the
left
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
—
0
0
1
2
0
0
2
2
Note: The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)
column in the tables of instructions.
90
MB90630A Series
Table 4
Number of Execution Cycles for Each Type of Addressing
(a)
Code
Operand
Number of execution cycles
for each type of addressing
Number of register
accesses for each type of
addressing
Listed in tables of instructions
Listed in tables of instructions
00 to 07
Ri
RWi
RLi
08 to 0B
@RWj
2
1
0C to 0F
@RWj +
4
2
10 to 17
@RWi + disp8
2
1
18 to 1B
@RWj + disp16
2
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5
Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
(b) byte
Operand
(c) word
(d) long
Number Number
Number Number
Number Number
of
of
of
of cycles access
of cycles access
of cycles access
Internal register
+0
1
+0
1
+0
2
Internal memory even address
Internal memory odd address
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
+1
1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+1
1
+4
2
+8
4
Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6
Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
—
+2
External data bus (16 bits)
—
+3
External data bus (8 bits)
+3
—
Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
• Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
91
MB90630A Series
Table 7
Mnemonic
#
~
Transfer Instructions (Byte) [41 Instructions]
R
G
B
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
A, #imm4
3
2
4
3
2
1
2
2
2+ 3+ (a)
3
2
2
2
3
2
10
3
1
1
0
0
1
1
0
0
0
0
2
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
3
2
A, dir
4
3
A, addr16
2
2
A, Ri
2
2
A, ear
2+ 3+ (a)
A, eam
3
2
A, io
2
2
A, #imm8
3
2
A, @A
5
A,@RWi+disp8 2
10
A, @RLi+disp8 3
0
0
1
1
0
0
0
0
1
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
/MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
@A, T
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
3
4
2
2
3+ (a)
3
10
3
4+ (a)
4
5+ (a)
2
5
5
2
4+ (a)
3
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
4
2
2+ 5+ (a)
7
2
2+ 9+ (a)
2
0
4
2
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ←
((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ←
((RWi)+disp8)
byte (A) ←
((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi) +disp8) ←
(A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
0
2× (b) byte ((A)) ← (AH)
0
2× (b)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
L A
H H
I
S T N Z V C RM
W
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– *
– *
– *
– *
– *
– *
– *
– *
– *
– R
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
X
X
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
92
MB90630A Series
Table 8
Mnemonic
#
Transfer Instructions (Word/Long Word) [38 Instructions]
~
R
G
B
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
A, dir
A, addr16
A, SP
A, RWi
A, ear
A, eam
A, io
A, @A
A, #imm16
A, @RWi+disp8
A, @RLi+disp8
2
3
3
4
1
1
1
2
2
2
2+ 3+ (a)
2
3
2
3
3
2
2
5
3
10
0
0
0
1
1
0
0
0
0
1
2
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
dir, A
addr16, A
SP, A
RWi, A
ear, A
eam, A
io, A
@RWi+disp8, A
@RLi+disp8, A
RWi, ear
RWi, eam
ear, RWi
eam, RWi
RWi, #imm16
io, #imm16
ear, #imm16
eam, #imm16
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
3
4
1
2
2
3+ (a)
3
5
10
3
4+ (a)
4
5+ (a)
2
5
2
4+ (a)
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
(0)
(c)
0
(c)
0
(c)
0
(c)
MOVW AL, AH
/MOVW @A, T
2
3
0
(c)
XCHW
XCHW
XCHW
XCHW
2
4
2+ 5+ (a)
2
7
2+ 9+ (a)
A, ear
A, eam
RWi, ear
RWi, eam
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)
+disp8)
word (A) ← ((RLi)
+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi) +disp8) ←
(A)
word ((RLi) +disp8) ←
(A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
2
0
0 2× (c) word ((A)) ← (AH)
4
0
2 2× (c)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
L A
H H
I
S T N Z V C RM
W
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
2
4
2
2+ 5+ (a) 0
5
3
0
0
(d)
0
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
MOVL ear, A
MOVL eam, A
2
4
2
2+ 5+ (a) 0
0
(d)
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
93
MB90630A Series
Table 9
Mnemonic
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
R
G
L A
H H
I
S T N Z V C RM
W
0
0
byte (A) ← (A) +imm8
0
(b) byte (A) ← (A) +(dir)
1
0
byte (A) ← (A) +(ear)
0
(b) byte (A) ← (A) +(eam)
2
0
byte (ear) ← (ear) + (A)
0 2× (b) byte (eam) ← (eam) + (A)
0
0
byte (A) ← (AH) + (AL) + (C)
1
0
byte (A) ← (A) + (ear) + (C)
0
(b) byte (A) ← (A) + (eam) + (C)
0
0
byte (A) ← (AH) + (AL) + (C)
0
0
(decimal)
0
(b) byte (A) ← (A) –imm8
1
0
byte (A) ← (A) – (dir)
0
(b) byte (A) ← (A) – (ear)
2
0
byte (A) ← (A) – (eam)
0 2× (b) byte (ear) ← (ear) – (A)
0
0
byte (eam) ← (eam) – (A)
1
0
byte (A) ← (AH) – (AL) – (C)
0
(b) byte (A) ← (A) – (ear) – (C)
0
0
byte (A) ← (A) – (eam) – (C)
byte (A) ← (AH) – (AL) – (C)
(decimal)
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
0
0
word (A) ← (AH) + (AL)
1
0
word (A) ← (A) +(ear)
0
(c) word (A) ← (A) +(eam)
0
0
word (A) ← (A) +imm16
2
0
word (ear) ← (ear) + (A)
0 2× (c) word (eam) ← (eam) + (A)
1
0
word (A) ← (A) + (ear) + (C)
0
(c) word (A) ← (A) + (eam) + (C)
0
0
word (A) ← (AH) – (AL)
1
0
word (A) ← (A) – (ear)
0
(c) word (A) ← (A) – (eam)
0
0
word (A) ← (A) –imm16
2
0
word (ear) ← (ear) – (A)
0 2× (c) word (eam) ← (eam) – (A)
1
0
word (A) ← (A) – (ear) – (C)
0
(c) word (A) ← (A) – (eam) – (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
#
~
ADD
A,#imm8
ADD
A, dir
ADD
A, ear
ADD
A, eam
ADD
ear, A
ADD
eam, A
ADDC A
ADDC A, ear
ADDC A, eam
ADDDC A
SUB
A,
#imm8
SUB
A, dir
SUB
A, ear
SUB
A, eam
SUB
ear, A
SUB
eam, A
SUBC A
SUBC A, ear
SUBC A, eam
SUBDC A
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
ADDW A
ADDW A, ear
ADDW A, eam
ADDW
A,
#imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW
A,
#imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
ADDL
ADDL
ADDL
#imm32
SUBL
SUBL
SUBL
#imm32
2
6
2
2+ 7+ (a) 0
5
4
0
2
6
2
2+ 7+ (a) 0
5
4
0
A, ear
A, eam
A,
A, ear
A, eam
A,
B
0
(d)
0
0
(d)
0
Operation
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) +imm32
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) –imm32
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
94
MB90630A Series
Table 10
Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
Mnemonic
#
~
R
G
B
Operation
L A
H H
I
S
T
N
Z
V
C RM
W
INC
INC
ear
eam
2
2
2
0
byte (ear) ← (ear) +1
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DEC
DEC
ear
eam
2
3
2
0
byte (ear) ← (ear) –1
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCW
INCW
ear
eam
2
3
2
0
word (ear) ← (ear) +1
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECW ear
DECW eam
2
3
2
0
word (ear) ← (ear) –1
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCL
INCL
ear
eam
2
7
4
0
long (ear) ← (ear) +1
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECL
DECL
ear
eam
2
7
4
0
long (ear) ← (ear) –1
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11
Mnemonic
#
Compare Instructions (Byte/Word/Long Word) [11 Instructions]
~
R
G
B
Operation
L A
H H
I
S
T
N
Z
V
C RM
W
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
1
2
2
2+ 3+ (a)
2
2
0
1
0
0
0
0
(b)
0
byte (AH) – (AL)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
A, ear
A, eam
A, #imm16
1
1
2
2
2+ 3+ (a)
3
2
0
1
0
0
0
0
(c)
0
word (AH) – (AL)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL
CMPL
CMPL
A, ear
A, eam
A, #imm32
2
6
2
2+ 7+ (a) 0
5
3
0
0
(d)
0
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
95
MB90630A Series
Table 12
Mnemonic
Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
#
~
R
G
B
0 word (AH) /byte (AL)
Quotient → byte (AL) Remainder →
0 byte (AH)
word (A)/byte (ear)
*6 Quotient → byte (A) Remainder →
byte (ear)
0 word (A)/byte (eam)
Quotient → byte (A) Remainder →
*7 byte (eam)
long (A)/word (ear)
Quotient → word (A) Remainder →
0 word (ear)
0 long (A)/word (eam)
(b) Quotient → word (A) Remainder →
word (eam)
0
0 byte (AH) *byte (AL) → word (A)
(c) byte (A) *byte (ear) → word (A)
byte (A) *byte (eam) → word (A)
DIVU
A
1
*1
0
DIVU
ear
A,
2
*2
1
2+ *3
0
DIVU
eam
A,
2
*4
1
DIVUW A,
ear
2+ *5
0
DIVUW A,
eam
1 *8
2 *9
2+ *10
0
1
0
MULU
MULU
ear
MULU
eam
1 *11
2 *12
2+ *13
0
1
0
A
A,
A,
MULUW A
MULUW A,
ear
MULUW A,
eam
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
*10:
*11:
*12:
*13:
Operation
L A
H H
I
S
T
N
Z
V
C RM
W
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (AH) *word (AL) → long (A)
word (A) *word (ear) → long (A)
word (A) *word (eam) → long (A)
3 when the result is zero, 7 when an overflow occurs, and 15 normally.
4 when the result is zero, 8 when an overflow occurs, and 16 normally.
6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.
4 when the result is zero, 7 when an overflow occurs, and 22 normally.
6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.
(b) when the result is zero or when an overflow occurs, and 2 × (b) normally.
(c) when the result is zero or when an overflow occurs, and 2 × (c) normally.
3 when byte (AH) is zero, and 7 when byte (AH) is not zero.
4 when byte (ear) is zero, and 8 when byte (ear) is not zero.
5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.
3 when word (AH) is zero, and 11 when word (AH) is not zero.
4 when word (ear) is zero, and 12 when word (ear) is not zero.
5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
96
MB90630A Series
Table 13
Mnemonic
#
~
Logical 1 Instructions (Byte/Word) [39 Instructions]
R
G
B
Operation
L A
H H
I
S
T
N
Z
V
C RM
W
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
0
1
0
0
(b)
2
0
0 2× (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
0
1
0
0
(b)
2
0
0 2× (b)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
XOR
XOR
XOR
XOR
XOR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
0
1
0
0
(b)
2
0
0 2× (b)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
NOT
NOT
NOT
A
ear
eam
1
2
0
0
byte (A) ← not (A)
2
3
2
0
byte (ear) ← not (ear)
2+ 5+ (a) 0 2× (b) byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
0
0
1
0
0
(c)
2
0
0 2× (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ORW
ORW
ORW
ORW
ORW
ORW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
0
0
1
0
0
(c)
2
0
0 2× (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
XORW
XORW
XORW
XORW
XORW
XORW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
0
0
1
0
0
(c)
2
0
0 2× (c)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
NOTW A
NOTW ear
NOTW eam
1
2
0
0
word (A) ← not (A)
2
3
2
0
word (ear) ← not (ear)
2+ 5+ (a) 0 2× (c) word (eam) ← not (eam)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
97
MB90630A Series
Table 14
Logical 2 Instructions (Long Word) [6 Instructions]
#
R
G
B
Operation
ANDL A, ear
ANDL A, eam
2
6
2
2+ 7+ (a) 0
0
(d)
ORL
ORL
A, ear
A, eam
2
6
2
2+ 7+ (a) 0
XORL A, ea
XORL A, eam
2
6
2
2+ 7+ (a) 0
Mnemonic
~
Table 15
Mnemonic
L A
H H
I
S
T
N
Z
V
C RM
W
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
0
(d)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
0
(d)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
Sign Inversion Instructions (Byte/Word) [6 Instructions]
#
~
R
G
B
Operation
2
0
0
byte (A) ← 0 – (A)
NEG
A
1
NEG
NEG
ear
eam
2
3
2
0
byte (ear) ← 0 – (ear)
2+ 5+ (a) 0 2× (b) byte (eam) ← 0 – (eam)
2
0
1
NEGW ear
NEGW eam
2
3
2
0
word (ear) ← 0 – (ear)
2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam)
Table 16
Mnemonic
NRML A, R0
0
word (A) ← 0 – (A)
NEGW A
L A
H H
I
S
T
N
Z
V
C RM
W
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
Normalize Instruction (Long Word) [1 Instruction]
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift until first
digit is “1”
byte (R0) ← Current shift
count
L A
H H
I
S
T
N
Z
V
C RM
W
–
–
–
–
–
*
–
–
–
–
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
98
MB90630A Series
Table 17
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
#
~
R
G
B
RORCA
ROLC A
2
2
2
2
0
0
0
0
RORCear
RORCeam
ROLC ear
ROLC eam
2
3
2+ 5+
2 (a)
2+ 3
5+
2 (a)
2
2
*1
*1
*1
2
0
0 2× (b)
2
0
0 2× (b)
1
1
1
0
0
0
1
1
1
2
2
2
0
0
0
0
0
0
2
2
2
*1
*1
*1
1
1
1
0
0
0
2
2
2
*2
*2
*2
1
1
1
0
0
0
Mnemonic
ASR A, R0
LSR A, R0
LSL A, R0
ASRWA
LSRWA/SHRW
A
LSLW A/SHLW
A
ASRWA, R0
LSRWA, R0
LSLW A, R0
ASRL A, R0
LSRL A, R0
LSLL A, R0
L A
H H
I
S T N Z V C RM
W
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with
carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
–
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
* *
* R
– *
*
*
*
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
Operation
byte (A) ← Arithmetic right barrel shift (A,
R0)
byte (A) ← Logical right barrel shift
(A, R0)
byte (A) ← Logical left barrel shift (A,
R0)
word (A) ← Arithmetic right shift (A, 1
bit)
word (A) ← Logical right shift (A, 1
bit)
word (A) ← Logical left shift (A, 1 bit)
word (A) ← Arithmetic right barrel shift (A,
R0)
word (A) ← Logical right barrel shift
(A, R0)
word (A) ← Logical left barrel shift (A,
R0)
long (A) ← Arithmetic right shift (A,
R0)
long (A) ← Logical right barrel shift
(A, R0)
long (A) ← Logical left barrel shift (A,
R0)
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
99
MB90630A Series
Table 18
Mnemonic
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
rel
rel
rel
rel
Branch 1 Instructions [31 Instructions]
#
~
RG
B
Operation
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(c)
0
(d)
0
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or
(Z) = 1
Branch when ((V) xor (N)) or
(Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
1
3
2
2+
2
2+
4
2
3
3
4+ (a)
5
6+ (a)
4
0
0
1
0
2
0
0
CALL
CALL
CALL
CALLV
CALLP
@ear *4
@eam *4
addr16 *5
#vct4 *5
@ear *6
2
2+
3
1
2
6
7+ (a)
6
7
10
1
(c)
0 2× (c)
0
(c)
0 2× (c)
2 2× (c)
CALLP @eam *6
2+ 11+ (a)
CALLP addr24 *7
4
*1:
*2:
*3:
*4:
*5:
*6:
*7:
10
0
*2
0 2× (c)
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ←
(ear +2)
word (PC) ← (eam), (PCB) ←
(eam +2)
word (PC) ← ad24 0 to 15,
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call instruction
word (PC) ← (ear) 0 to 15
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15
(PCB) ← (eam) 16 to 23
word (PC) ← addr0 to 15,
(PCB) ← addr16 to 23
L A
H H
I
S T N Z V C RM
W
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4 when branching, 3 when not branching.
(b) + 3 × (c)
Read (word) branch address.
W: Save (word) to stack; R: read (word) branch address.
Save (word) to stack.
W: Save (long word) to W stack; R: read (long word) R branch address.
Save (long word) to stack.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
100
MB90630A Series
Table 19
Mnemonic
#
~ RG
Branch 2 Instructions [19 Instructions]
B
3 *1
4 *1
0
0
0
0
CBNE ear, #imm8, rel 4 *2
CBNE eam, #imm8,
4+ *3
9
5 *4
rel*
5+ *3
CWBNEear, #imm16,
rel
CWBNEeam, #imm16, 3 *5
rel*9
3+ *6
DBNZ ear, rel
1
0
1
0
0
(b)
0
(c)
3 *5
2
3+ *6
2
2
3
4
1
1
20
16
17
20
15
0
0
0
0
0
2
6
0
(c)
1
5
0
(c)
1
1
4
6
0
0
(c)
(d)
CBNE A, #imm8, rel
CWBNEA, #imm16, rel
DBNZ
eam, rel
2
2
DWBNZ ear, rel
DWBNZ eam, rel
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
LINK
#local8
UNLINK
RET *7
RETP *8
Operation
Branch when byte (A) ≠
imm8
Branch when word (A) ≠
imm16
Branch when byte (ear) ≠
imm8
Branch when byte (eam) ≠
0 imm8
Branch when word (ear) ≠
2× (b) imm16
Branch when word (eam) ≠
imm16
0
Branch when byte (ear) =
2× (c) (ear) – 1, and (ear) ≠ 0
Branch when byte (eam) =
(eam) – 1, and (eam) ≠ 0
8× (c)
6× (c) Branch when word (ear) =
6× (c) (ear) – 1, and (ear) ≠ 0
8× (c) Branch when word (eam) =
6× (c) (eam) – 1, and (eam) ≠ 0
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
L A
H H
I
S
T
N
Z
V
C RM
W
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
S
S
S
S
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
At constant entry, save old
frame pointer to stack, set
–
new frame pointer, and
–
allocate local pointer area
At constant entry, retrieve
old frame pointer from stack.
Return from subroutine
Return from subroutine
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
5 when branching, 4 when not branching
13 when branching, 12 when not branching
7 + (a) when branching, 6 + (a) when not branching
8 when branching, 7 when not branching
7 when branching, 6 when not branching
8 + (a) when branching, 7 + (a) when not branching
Retrieve (word) from stack
Retrieve (long word) from stack
In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
101
MB90630A Series
Table 20
Mnemonic
Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
#
~
RG
B
Operation
L A
H H
I
S T N Z V C RM
W
PUSHW
PUSHW
PUSHW
PUSHW
A
AH
PS
rlst
1
1
1
2
4
4
4
*3
0
0
0
*5
(c)
(c)
(c)
*4
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
4
*2
0
0
0
*5
(c)
(c)
(c)
*4
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)), (SP) ← (SP) +2n
–
–
–
–
*
–
–
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
–
–
JCTX
@A
1
14
0 6× (c) Context switch instruction
–
–
*
*
*
*
*
*
*
–
AND
OR
CCR, #imm8
CCR, #imm8
2
2
3
3
0
0
0
0
byte (CCR) ← (CCR) and imm8
byte (CCR) ← (CCR) or imm8
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
2
2
2
2
0
0
0
0
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
3
2+ 2+ (a)
2
1
2+ 1+ (a)
1
1
0
0
0
0
0
0
word (RWi) ←ear
word (RWi) ←eam
word(A) ←ear
word (A) ←eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
2
3
3
3
0
0
0
0
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
2
2
*1
1
0
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
Z
–
*
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No operation
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV RP, #imm8
MOV ILM, #imm8
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
NOP
ADB
DTB
PCB
SPB
NCC
CMR
A, brgl
brg2, A
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR
: 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
102
MB90630A Series
Table 21
Bit Manipulation Instructions [21 Instructions]
L A
H H
I
S T N Z V C RM
W
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
0 2× (b) bit (dir:bp) b ← (A)
0 2× (b) bit (addr16:bp) b ← (A)
0 2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
7
7
7
0 2× (b) bit (dir:bp) b ← 1
0 2× (b) bit (addr16:bp) b ← 1
0 2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
3
4
3
7
7
7
0 2× (b) bit (dir:bp) b ← 0
0 2× (b) bit (addr16:bp) b ← 0
0 2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 0
Branch when (addr16:bp) b = 0
Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 1
Branch when (addr16:bp) b = 1
Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
0 2× (b) Branch when (addr16:bp) b = 1, –
bit = 1
0
–
*5
Wait until (io:bp) b = 1
0
–
*5
Wait until (io:bp) b = 0
–
–
–
–
–
*
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Mnemonic
#
~
RG
B
MOVB A, dir:bp
MOVB A,
addr16:bp
MOVB A, io:bp
3
4
3
5
5
4
0
0
0
(b)
(b)
(b)
3
4
3
7
7
6
3
4
3
MOVB dir:bp, A
MOVB addr16:bp,
A
MOVB io:bp, A
SETB dir:bp
SETB addr16:bp
SETB io:bp
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
BBC
BBC
rel
BBC
dir:bp, rel
addr16:bp,
BBS
BBS
rel
BBS
dir:bp, rel
addr16:bp,
5
*3
io:bp, rel
3
*4
3
*4
io:bp, rel
SBBS addr16:bp,
rel
Operation
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
WBTS io:bp
WBTC io:bp
*1:
*2:
*3:
*4:
*5:
8 when branching, 7 when not branching
7 when branching, 6 when not branching
10 when condition is satisfied, 9 when not satisfied
Undefined count
Until condition is satisfied
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
103
MB90630A Series
Table 22
Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
Mnemonic
#
~
R
G
B
Operation
SWAP
SWAPW/XCHW AL, AH
EXT
EXTW
ZEXT
ZEXTW
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
0
0
0
0
0
0
byte (A) 0 to 7 ↔ (A) 8 to 15
word (AH) ↔ (AL)
byte sign extension
word sign extension
byte zero extension
word zero extension
Table 23
Mnemonic
#
~
R
G B
MOVS/MOVSI
MOVSD
2
2
*2
*2
*5
*5
SCEQ/SCEQI
SCEQD
2
2
*1
*1
*5
*5
FISL/FILSI
2 6m +6 *5
L A
H H
I
S
T
N
Z
V
C RM
W
–
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
L A
H H
I
S
T
N
Z
V
C RM
W
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
*
*
–
–
–
–
*
–
X
–
Z
–
–
–
–
–
–
String Instructions [10 Instructions]
Operation
*3 Byte transfer @AH+ ← @AL+, counter
*3 = RW0
Byte transfer @AH– ← @AL–, counter
*4 = RW0
*4
Byte retrieval (@AH+) – AL, counter =
*3 RW0
Byte retrieval (@AH–) – AL, counter =
RW0
Byte filling @AH+ ← AL, counter =
RW0
MOVSW/
MOVSWI
MOVSWD
SCWEQ/
SCWEQI
SCWEQD
2
2
*2
*2
*8
*8
2
2
*1
*1
*8
*8
2 6m +6 *8
FILSW/FILSWI
*6 Word transfer @AH+ ← @AL+, counter
*6 = RW0
Word transfer @AH– ← @AL–, counter
*7 = RW0
*7
Word retrieval (@AH+) – AL, counter =
*6 RW0
Word retrieval (@AH–) – AL, counter =
RW0
Word filling @AH+ ← AL, counter =
RW0
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case
*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately
for each.
*4: (b) × n
*5: 2 × (RW0)
*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately
for each.
*7: (c) × n
*8: 2 × (RW0)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
104
MB90630A Series
■ ORDERING INFORMATION
Model
Package
MB90632APFV
MB90634APFV
MB90P634APFV
100-pin Plastic LQFP
(FPT-100P-M05)
MB90632APF
MB90634APF
MB90P634APF
100-pin Plastic QFP
(FPT-100P-M06)
Remarks
MB90P634A supports ES alone.
105
MB90630A Series
■ PACKAGE DIMENSIONS
100-pin Plastic LQFP
(FPT-100P-M05)
+0.20
16.00±0.20(.630±.008)SQ
75
1.50 –0.10
14.00±0.10(.551±.004)SQ
76
(Mounting
height)
(Mouting
height)
+.008
.059 –.004
51
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
100
0.15(.006)
26
0.15(.006)MAX
LEAD No.
1
"B"
25
0.40(.016)MAX
"A"
+0.08
0.50(.0197)TYP
0.18 –0.03
+.003
.007 –.001
+0.05
0.08(.003)
0.127 –0.02
M
Details of "B" part
+.002
.005 –.001
0.10±0.10
(STAND OFF)
(.004±.004)
0.50±0.20(.020±.008)
0.10(.004)
C
0~10°
1995 FUJITSU LIMITED F100007S-2C-3
100-pin Plastic QFP
(FPT-100P-M06)
Dimensions in mm (inches)
23.90±0.40(.941±.016)
3.35(.132)MAX
(Mounting height)
(Mounting height)
0.05(.002)MIN
(STAND OFF)
20.00±0.20(.787±.008)
80
51
81
50
14.00±0.20
(.551±.008)
12.35(.486)
REF
17.90±0.40
(.705±.016)
16.30±0.40
(.642±.016)
INDEX
31
100
"A"
LEAD No.
1
30
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.13(.005)
0.15±0.05(.006±.002)
M
Details of "A" part
0.25(.010)
Details of "B" part
"B"
0.10(.004)
18.85(.742)REF
22.30±0.40(.878±.016)
C
106
1994 FUJITSU LIMITED F100008-3C-2
0.30(.012)
0.18(.007)MAX
0.53(.021)MAX
0
10°
0.80±0.20
(.031±.008)
Dimensions in mm (inches)
MB90630A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka,
Nakahara-ku, Kawasaki-shi,
Kanagawa 211-8588, Japan
Tel: +81-44-754-3763
Fax: +81-44-754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0004
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
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