Fujitsu MB90653A 16-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13607-3E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90650A Series
MB90652A/653A/P653A/654A/F654A
■ DESCRIPTION
The MB90650A series are 16-bit microcontrollers designed for high speed real-time processing in consumer
product applications such as controlling celluar phones, CD-ROMs, or VTRs. Based on the F2MC*1-16L CPU
core, an F2MC-16L is used as the CPU. This CPU includes high-level language-support instructions and robust
task switching instructions, and additional addressing modes. In order to reduce the consumption current, dualclock (main/sub) is used. Furthermore, low consumption power supply is achieved by using stop mode, sleep
mode, watch mode, pseudo-watch mode, CPU intermittent operation mode.
Microcontrollers in this series have built-in peripheral resources including 10-bit A/D converter, 8-bit D/A
converter, UART, 8/16-bit PPG, 8/16-bit up/down counter/timer, I2C interface*2, 8/16-bit I/O timer (input capture,
output compare, and 16-bit free-run timer).
*1:F2MC stands for FUJITSU Flexible Microcontroller.
*2:Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.
■ FEATURES
F2MC-16L CPU
• Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4
• Instruction set optimized for controller applications
Object code compatibility with F2MC-16(H)
(Continued)
■ PACKAGE
100-pin plastic LQFP
100-pin plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB90650A Series
(Continued)
Wide range of data types (bit, byte, word, and long word)
Improved instruction cycles provide increased speed
Additional addressing modes: 23 modes
High code efficiency
Access methods (bank access, linear pointer)
High precision operations are enhanced by use of a 32-bit accumulator
Extended intelligent I/O service (access area extended to 64 Kbytes)
Maximum memory space: 16 Mbytes
• Enhanced high level language (C) and multitasking support instructions
Use of a system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Improved execution speed: Four byte instruction queue
• Powerful interrupt function
• Automatic data transfer function that does not use instruction (extended I2OS)
2
MB90650A Series
■ PRODUCT LINEUP
Part number
MB90652A
MB90653A
MB90P653A
MB90V650A
MB90654A
MB90F654A
Item
Classification
ROM size
RAM size
Power supply
voltage
CPU functions
Ports
A/D converter
D/A converter
8/16-bit up/down
counter/timer
I2C interface
UART
I/O extended serial
interface
8/16-bit PPG
16-bit I/O timer
DTP/external
interrupt
Timer functions
DTMF generator
Low-power
consumption modes
PLL function
Other
Package
Mask ROM product
64 Kbytes
3 Kbytes
OTPROM product For evaluation
128 Kbytes
5 Kbytes
2.2 V to 3.6 V
—
Mask ROM
FLASH product
product
256 Kbytes
8 Kbytes
2.7 V to 5.5 V
2.2 V to 3.6 V
2.4 V to 3.6 V
The number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
I/O ports (N-channel open-drain):
I/O ports (CMOS):
340
8/16 bits
1 to 7 bytes
1/4/8/16/32 bits
62.5 ns/4 MHz (PLL multiplier = 4)
1.0 µs/16 MHz (minimum)
4
75 (Input pull-up resistors available: 24/
Can be set as N-channel open-drain: 8)
Total:
79
Analog inputs : 8 channels
Analog inputs: 8 channels
Analog inputs : 8 channels
10-bit resolution
10-bit resolution
10-bit resolution
Conversion time : minimum
Conversion time : minimum 12.25
Conversion time : minimum
6.13 µs/16 MHz
µs/8 MHz
6.13 µs/16 MHz
2 channels (independent),
8-bit resolution, R-2R type
16 bits × 1 channel/8 bits × 2 channels selectable
Includes reload and compare functions.
1 channel
Master mode/slave mode available
1 channel
Clock synchronous communication
Clock asynchronous communication
8 bits × 2 channels
LSB-first or MSB-first operation selecable
8 bits × 2 channels/16 bits × 1 channel selectable
1 channel
(Input capture × 2 channels, output compare × 4 channels, and free-run timer × 1 channel)
8 inputs
Timebase timer (18-bit)/watchdog timer (18-bit)/watch timer (15-bit)
Supports every ITU-T (CCITT) tone for output (Internal 16 MHz shall be used for
DTMF generator).
CPU intermittent operation mode, sub clock mode, stop mode, sleep mode,
watch mode, pseudo-watch mode
Selectable multiplier: 1/2/3/4
(Set a multiplier that does not exceed the assured operation frequency range.)
VPP is shared with
the MD2 pin
—
—
(for EPROM
programming)
FPT-100P-M05, FPT-100P-M06
PGA-256C-A02 FPT-100P-M05, FPT-100P-M06
Notes: • MB90V650A device is assured only when operate with the tools, under the condition of power supply
voltage: 2.7 V to 3.3 V, operating temparature: 0°C to 70°C and operating frequency: 1.5 MHz to 8MHz
• For more information about each package, see seciton “PACKAGE DIMENSIONS”.
3
MB90650A Series
■ PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P21/A17
P20/A16
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC1
X1
X0
VSS
X0A
X1A
PA2/OUT2
(Top view)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P71/SCL
P72
DVRH
DVSS
P73/DA00
P74/DA01
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
P52/AN2
P53/AN3
VSS
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P80/IRQ0
P81/IRQ1
MD0
MD1
MD2
TEST
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC2
P45/SCK1
P46/ADTG
P47
P70/SDA
(FPT-100P-M05)
4
RST
PA1/OUT1
PA0/OUT0
P97/IN1
P96/IN0
P95/ZIN1
P94/BIN1
P93/AIN1/IRQ7
P92/ZIN0
P91/BIN0
P90/AIN0/IRQ6
P67/PPG11
P66/PPG10
P65/CKOT
P64/PPG01
P63/PPG00
P62/SCK2
P61/SOT2
P60/SIN2
DTMF
P86/OUT3
P85/IRQ5
P84/IRQ4
P83/IRQ3
P82/IRQ2
MB90650A Series
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
X0A
X1A
PA2/OUT2
RST
PA1/OUT1
PA0/OUT0
P97/IN1
P96/IN0
P95/ZIN1
P94/BIN1
P93/AIN1/IRQ7
P92/ZIN0
P91/BIN0
P90/AIN0/IRQ6
P67/PPG11
P66/PPG10
P65/CKOT
P64/PPG01
P63/PPG00
P62/SCK2
P61/SOT2
P60/SIN2
DTMF
P86/OUT3
P85/IRQ5
P84/IRQ4
P83/IRQ3
P82/IRQ2
TEST
MD2
DVSS
P73/DA00
P74/DA01
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
P52/AN2
P53/AN3
VSS
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P80/IRQ0
P81/IRQ1
MD0
MD1
P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC2
P45/SCK1
P46/ADTG
P47
P70/SDA
P71/SCL
P72
DVRH
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC1
X1
X0
VSS
(Top view)
(FPT-100P-M06)
5
MB90650A Series
■ PIN DESCRIPTION
Pin no.
Pin name
Function
QFP*2
80
82
X0
A
Crystal oscillator pin
81
83
X1
A
Crystal oscillator pin
77
79
X1A
B
Crystal oscillatort pins (32 kHz)
78
80
X0A
B
Crystal oscillatort pins (32 kHz)
47 to 49
49 to 51
MD0 to MD2
D
Operating mode selection pins
Connect directly to VCC or VSS.
50
52
TEST
D
Test input pin
This pin must always be fixed to “H”.
75
77
RST
C
Reset input pin
83 to 90
85 to 92
P00 to P07
AD00 to AD07
91 to 98
93 to 100 P10 to P17
AD08 to AD15
99,
100,
1 to 6
1,
2,
3 to 8
P20,
P21,
P22 to P27
A16,
A17,
A18 to A23
7
9
P30
ALE
8
10
P31
RD
10
12
P32
WRL
*1: FPT-100P-M05
*2: FPT-100P-M06
6
Circuit
type
LQFP*1
E
General-purpose I/O ports
(STBC) Pull-up resistors can be set (RD07 to RD00 = “1”) using the
pull-up resistor setting register (RDR0).
The setting does not apply for ports set as outputs (D07 to D00
= “1”: invalid at the output setting).
In external bus mode, the pins function as the lower data I/O or
lower address outputs (AD00 to AD07).
E
General-purpose I/O ports
(STBC) Pull-up resistors can be set (RD17 to RD10 = “1”) using the
pull-up resistor setting register (RDR1).
The setting does not apply for ports set as outputs (D17 to D10
= “1”: invalid at the output setting).
In 16-bit external bus mode, the pins function as the upper data
I/O or middle address outputs (AD08 to AD15).
I
General-purpose I/O ports
(STBC) In external bus mode, pins for which the corresponding bit in
the HACR register is “0” function as the P20 to P27 pins.
In external bus mode, pins for which the corresponding bit in
the HACR register is “1” function as the upper address output
pins (A16 to A23).
I
General-purpose I/O port
(STBC) Functions as the ALE pin in external bus mode.
Functions as the address latch enable signal.
I
General-purpose I/O port
(STBC) Functions as the RD pin in external bus mode.
Functions as the read strobe output (RD).
I
General-purpose I/O port
(STBC) Functions as the WRL pin in external bus mode if the WRE bit
in the ECSR register is “1”.
Functions as the lower data write strobe output (WRL).
(Continued)
MB90650A Series
Pin no.
LQFP*1
QFP*2
11
13
Pin name
P33
WRH
12
14
P34
HRQ
13
14
15
16
17
18
19
I
General-purpose I/O port
(STBC) Functions as the HRQ pin in external bus mode if the HDE bit
in the ECSR register is “1”.
Functions as the hold request input pin (HRQ).
Functions as the hold acknowledge output (HAK) pin.
P36
I
General-purpose I/O port
(STBC) Functions as the RDY pin in external bus mode if the RYE bit in
the ECSR register is “1”.
P37
P40
P41
SOT0
*1: FPT-100P-M05
*2: FPT-100P-M06
Functions as the upper data write strobe output (WRH).
HAK
SIN0
17
I
General-purpose I/O port
(STBC) Functions as the WRH pin in 16-bit external bus mode if the
WRE bit in the ECSR register is “1”.
I
General-purpose I/O port
(STBC) Functions as the HAK pin in external bus mode if the HDE bit in
the ECSR register is “1”.
CLK
16
Function
P35
RDY
15
Circuit
type
Functions as the external ready input (RDY) pin.
I
General-purpose I/O port
(STBC) Functions as the CLK pin in external bus mode if the CKE bit in
the ECSR register is “1”.
Functions as the machine cycle clock output (CLK) pin.
H
General-purpose I/O port
(STBC) When UART0 is operating, the data at the pin is used as the
serial input (SIN0).
Can be set as an open-drain output port (OD40 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D40 = “0”:
invalid at the input setting).
Functions as the UART0 serial input (SIN0).
G
General-purpose I/O port
(STBC) Functions as the SOT0 pin if the SOE bit in the UMC register is
“1”.
Can be set as an open-drain output port (OD41 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D41 = “0”:
invalid at the input setting).
Functions as the UART0 serial data output pin (SOT0).
(Continued)
7
MB90650A Series
Pin no.
LQFP*1
QFP*2
18
20
Pin name
P42
Circuit
type
H
General-purpose I/O port
(STBC) When UART0 is operating in external shift clock mode, the
data at the pin is used as the clock input (SCK0).
Also, functions as the SCK0 pin if the SOE bit in the UMC
register is “1”.
Can be set as an open-drain output port (OD42 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D42 = “0”:
invalid at the input setting).
SCK0
19
21
P43
Functions as the UART0 serial clock I/O pin (SCK0).
H
General-purpose I/O port
(STBC) When I/O extended serial is operating, the data at the pin is
used as the serial input (SIN1).
Can be set as an open-drain output port (OD43 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D43 = “0”:
invalid at the input setting).
SIN1
20
22
P44
Functions as the serial input for I/O extended serial data.
G
General-purpose I/O port
(STBC) Functions as the SOT1 pin if the SOE bit in the UMC register is
“1”.
Can be set as an open-drain output port (OD44 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D44 = “0”:
invalid at the input setting).
SOT1
22
24
P45
Functions as the output pin (SOT1) for I/O extended serial
data.
H
General-purpose I/O port
(STBC) When I/O extended serial is operating in external shift clock
mode, the data at the pin is used as the clock input (SCK1).
Also, functions as the SCK1 pin if the SOE bit in the UMC
register is “1”.
Can be set as an open-drain output port (OD45 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D45 = “0”:
invalid at the input setting).
SCK1
23
25
P46
Functions as the I/O extended serial clock I/O pin (SCK1).
G
General-purpose I/O port
(STBC) Can be set as an open-drain output port (OD46 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D46 = “0”:
invalid at the input setting).
ADTG
24
26
P47
Function
Functions as the external trigger input pin for the A/D
converter.
K
Open-drain type general-purpose I/O port
(NMOS/H)
(STBC)
*1: FPT-100P-M05
*2: FPT-100P-M06
8
(Continued)
MB90650A Series
Pin no.
LQFP*1
36 to 39,
41 to 44
QFP*2
Pin name
38 to 41, P50 to P53,
43 to 46 P54 to P57
AN0 to AN3,
AN4 to AN7
57
59
P60
SIN2
58
60
P61
SOT2
59
61
P62
SCK2
60
62
P63
PPG00
61
63
P64
PPG01
*1: FPT-100P-M05
*2: FPT-100P-M06
Circuit
type
Function
L
General-purpose I/O ports
(STBC)
The pins are used as analog inputs (AN0 to AN7) when the A/D
converter is operating.
F
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD60 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D60 = “1”:
invalid at the output setting).
Functions as a data input pin (SIN2) for I/O extended serial.
E
General-purpose I/O port
(STBC) Function as the SOT2 pin if the SOE bit in the UMC register is
“1”.
A pull-up resistor can be set (RD61 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D61 = “1”:
invalid at the output setting).
Functions as an output pin (SOT2) for I/O extended serial data.
F
General-purpose I/O port
(STBC) When I/O extended serial is operating in external shift clock
mode, the data at the pin is used as the clock input (SCK2).
Also, functions as the SCK2 pin if the SOE bit in the UMC
register is “1”.
A pull-up resistor can be set (RD62 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D62 = “1”:
invalid at the output setting).
Functions as the I/O extended serial clock I/O pin (SCK2).
E
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD63 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D63 = “1”:
invalid at the output setting).
Functions as the PPG00 output when PPG output is enabled.
E
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD64 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D64 = “1”:
invalid at the output setting).
Functions as the PPG01 output when PPG output is enabled.
(Continued)
9
MB90650A Series
Pin no.
LQFP*1
QFP*2
62
64
Pin name
P65
Circuit
type
E
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD65 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D65 = “1”:
invalid at the output setting).
CKOT
63
65
P66
Functions as the CKOT output when CKOT is operating.
E
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD66 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D66 = “1”:
invalid at the output setting).
PPG10
64
66
P67
Functions as the PPG10 output when PPG output is enabled.
E
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD67 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D67 = “1”:
invalid at the output setting).
PPG11
25
27
P70
SDA
26
28
P71
SCL
Functions as the PPG11 output when PPG output is enabled.
K
Open-drain type I/O port
(NMOS/H)
2
(STBC) I C interface data I/O pin
This function is valid when I2C interface operations are
enabled.
Set port output to Hi-Z (PDR = 1) during I2C interface
operations.
K
Open-drain type I/O port
(NMOS/H)
2
(STBC) I C interface clock I/O pin
This function is valid when I2C interface operations are
enabled.
Set port output to Hi-Z (PDR = 1) during I2C interface
operations.
27
29
P72
K
Open-drain type I/O port
(STBC)
30
32
P73
M
Open-drain type I/O port
(STBC) Functions as a D/A output pin when DAE0 = “1” in the D/A
control register (DACR).
DA00
31
33
P74
Functions as D/A output 0 when the D/A converter is operating.
M
General-purpose I/O port
(STBC) Functions as a D/A output pin when DAE1 = “1” in the D/A
control register (DACR).
DA01
45
47
P80
IRQ0
*1: FPT-100P-M05
*2: FPT-100P-M06
10
Function
Functions as D/A output 1 when the D/A converter is operating.
J
General-purpose I/O port
Functions as external interrupt request I/O 0.
(Continued)
MB90650A Series
Pin no.
LQFP*1
QFP*2
46
48
Pin name
P81
Circuit
type
J
IRQ1
51
53
P82
54
P83
J
55
P84
J
56
P85
J
57
P86
J
66
67
68
P90
I
General-purpose I/O port
(STBC) This applies in all cases.
69
69
70
71
72
Functions as an interrupt request input.
P91
P92
P93
73
74
75
General-purpose I/O port
Functions as an interrupt request input.
P94
P95
P96
P97
PA0
OUT0
*1: FPT-100P-M05
*2: FPT-100P-M06
J
IRQ7
IN1
73
J
General-purpose I/O port
(STBC)
Input to channel 0 of the 8/16-bit up/down counter/timer
Input to channel 1 of the 8/16-bit up/down counter/timer
IN0
72
General-purpose I/O port
J
(STBC) Input to channel 0 of the 8/16-bit up/down counter/timer
AIN1
ZIN1
71
General-purpose I/O port
IRQ6
BIN1
70
J
Input to channel 0 of the 8/16-bit up/down counter/timer
ZIN0
68
Event output for channel 3 of the output compare
AIN0
BIN0
67
General-purpose I/O port
Functions as external interrupt request I/O 5.
OUT3
65
General-purpose I/O port
Functions as external interrupt request I/O 4.
IRQ5
55
General-purpose I/O port
Functions as external interrupt request I/O 3.
IRQ4
54
General-purpose I/O port
Functions as external interrupt request I/O 2.
IRQ3
53
General-purpose I/O port
Functions as external interrupt request I/O 1.
IRQ2
52
Function
J
General-purpose I/O port
(STBC)
Input to channel 1 of the 8/16-bit up/down counter/timer
J
General-purpose I/O port
(STBC)
Input to channel 1 of the 8/16-bit up/down counter/timer
J
General-purpose I/O port
(STBC)
Trigger input for channel 0 of the input capture
J
General-purpose I/O port
(STBC)
Trigger input for channel 1 of the input capture
I
General-purpose I/O port
(STBC)
Event output for channel 0 of the output compare
(Continued)
11
MB90650A Series
(Continued)
Pin no.
LQFP*1
QFP*2
74
76
Pin name
PA1
OUT1
76
78
PA2
OUT2
Circuit
type
I
General-purpose I/O port
(STBC)
Event output for channel 1 of the output compare
I
General-purpose I/O port
(STBC)
Event output for channel 2 of the output compare
82
84
VCC1
—
Power supply (3.0 V) input pin
21
23
VCC2
—
Power supply (3.0 V/5.0 V) input pin
9,
40,
79
11,
42,
81
VSS
32
34
AVCC
—
A/D converter power supply pin
33
35
AVRH
—
A/D converter external reference power supply pin
34
36
AVRL
—
A/D converter external reference power supply pin
35
37
AVSS
—
A/D converter power supply pin
28
30
DVRH
—
D/A converter external reference power supply pin
29
31
DVSS
—
D/A converter power supply pin
56
58
DTMF
N
DTMF output pin
Power supply (0.0 V) input pin
—
*1: FPT-100P-M05
*2: FPT-100P-M06
Note: STBC = Incorporates standby control
NMOS = N-ch open-drain output
12
Function
MB90650A Series
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
• Oscillation feedback resistance :
Approx. 1 MΩ
X1
X0
Standby control signal
B
• Oscillation feedback resistance :
Approx. 10 MΩ
X1A
X0A
Standby control signal
C
• Hysteresis input with pull-up
Resistance approx. 50 kΩ
R
Hysteresis input
R
D
• Hysteresis input port
Hysteresis input
R
E
CTL
• Incorporates pull-up resistor control
(for input)
• CMOS level I/O
Resistance approx. 50 kΩ
CMOS
R
F
CTL
• Incorporates pull-up resistor control
(for input)
• CMOS level output
• Hysteresis input
Resistance approx. 50 kΩ
Hysteresis input
R
(Continued)
13
MB90650A Series
Type
Circuit
Remarks
G
Open-drain control
signal
• CMOS level I/O
• Incorporates open-drain control
CMOS
R
H
Open-drain control
signal
• CMOS level output
• Hysteresis input
• Incorporates open-drain control
Hysteresis input
R
I
• CMOS level I/O
CMOS
R
J
• CMOS level output
• Hysteresis input
Hysteresis input
R
K
• Hysteresis input
• N-ch open-drain output
Digital output
Hysteresis input
R
L
• CMOS level I/O
• Analog input
CMOS
R
Analog input
(Continued)
14
MB90650A Series
(Continued)
Type
Circuit
Remarks
M
• CMOS level I/O
• Analog output
• Shared with D/A outputs
D/A output
CMOS
R
N
• DTMF analog output
R
R
R
15
MB90650A Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latch-up occurs in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin
or if the voltage applied between VCC and VSS exceeds the rating.
If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements.
Therefore, ensure that maximum ratings are not exceeded in circuit operation.
For the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage.
2. Treatment of Unused Pins
Leaving unused input pins unconnected can cause misoperation. Always pull-up or pull-down unused pins.
3. External Reset Input
To reliably reset the controller by inputting an “L” level to the RST pin, ensure that the “L” level is applied for at
least five machine cycles. Take particular note when using an external clock input.
4. VCC and VSS Pins
Ensure that all VCC pins are at the same voltage. The same applies for the VSS pins.
5. Precautions when Using an External Clock
Drive the X0 pin only when using an external clock.
• Using an external clock
MB90650A Series
X0
X1
6. A/D Converter Power Supply and the Turn-on Sequence for Analog Inputs
Always turn off the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) before
turning off the digital power supply (VCC).
When turning the power on or off, ensure that AVRH does not exceed AVCC.
Also, when using the analog input pins as input ports, ensure that the input voltage does not exceed AVCC.
7. Turn-on Sequence for D/A Converter Power Supply
Always turn on the D/A converter power supply (DVR), after turning off the digital power supply (VCC).
And in the turning off the power supply sequence always turn off the digital power supply (VCC) after turning off
the D/A converter power supply (DVR).
16
MB90650A Series
8. Initializing
In this device there are some kinds of inner resisters which are initializid only by power on reset. It is possible
to initialize these resisters by turning on the power supply again.
9. Power Supply Pins
When there are several VCC and VSS pins, those pins that should have the same electric potential are connected
within the device when the device is designed in order to prevent misoperation, such as latchup. However, all
of those pins must be connected to the power supply and ground externally in order to reduce unnecessary
emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the
total output current standards.
In addition, give a due consideration to the connection in that current supply be connected to VCC and VSS with
the lowest possible impedance.
Finally, it is recommended to connect a capacitor of about 0.1 µF between VCC and VSS near this device as a
bypass capacitor.
10.Crystal Oscillation Circuit
Noise in the vicinity of the X0 and X1 pins will cause this device to operate incorrectly. Design the printed circuit
board so that the bypass capacitor connecting X0, X1 and the crystal oscillator (or ceramic oscillator) to ground
is located as close to the device as possible, and that the wiring does not closs the other wirings.
In addition, because printed circuit board artwork in which the area around the X0 and X1 pins is surrounded
by ground provides stable operation, such an arrangement is strongly recommended.
11. About 2 Power Supplies
The MB90650A series usually uses the 3-V power supply as the main power source. With Vcc1 = 3 V and Vcc2
= 5 V, however, it can interface with P20 to P27, P30 to P37, P40 to P47, and P70 to P72 for the 5-V power
supply separately from the 3-V power supply. Note, however, that the analog power supplies such as A/D and
D/A can be used only as 3-V power supplies.
17
MB90650A Series
■ PROGRAMMING FOR MB90P653A
In EPROM mode, the MB90P653A functions equivalent to the MBM27C1000/1000A. This allows the EPROM
to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter (do not
use the electronic signature mode).
1. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (128 K × 8 bits) in the MB90P653A are in the “1”
state. Data is written to the ROM by selectively programming “0” into the desired bit locations. Bits cannot be
set to “1” electrically.
2. Programming Procedure
(1) Set the EPROM programmer to MBM27C1000/1000A.
(2) Load program data into the EPROM programmer at 00000H to 1FFFFH.
Note that ROM addresses FE0000H to FFFFFFH in the operation mode in the MB90P653A series assign to
00000H to 1FFFFH in the EPROM mode (on the EPROM programmer).
Normal operating mode
EPROM mode
FFFFFF H
1FFFF H
PROM
PROM
00000 H
FE0000 H
010000 H
PROM
Mirror
004000 H
000000 H
The 00 bank PROM mirror is 48 Kbytes. (This is a mirror for FF4000H to FFFFFFH.)
(3) Mount the MB90P653A on the adapter socket, then fit the adapter socket onto the EPROM programmer.
When mounting the device and the adapter socket, pay attention to their mounting orientations.
(4) Start programming the program data to the device.
(5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 µF between VCC and GND,
between VPP and GND.
Note: The mask ROM products (MB90653A, MB90652A) does not support EPROM mode. Data cannot, therefore,
be read by the EPROM programmer.
18
MB90650A Series
3. EPROM Programmer Socket Adapter
Part no.
Package
Compatible
socket
adapter
Sun Hayato
Co., Ltd.
MB90652APFV MB90653APFV MB90P653APFV MB90652APF MB90653APF MB90P653APF
LQFP-100
QFP-100
ROM-100SQF-32DP-16L
ROM-100QF-32DP-16L
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
4. Recommended Screening Conditions
High temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yeild
MB90P653A cannot be write tested for all bits due to their nature. Therefore the write yield cannot always be
guaranteed to be 100%.
19
MB90650A Series
6. EPROM Mode Pin Assignments
• MBM27C1000/1000A compatible pins
MBM27C1000/1000A
1
Pin no.
MB90P653A
Pin name
Pin no.
Pin name
VPP
MD2
32
VCC
VCC
2
OE
P32
31
PGM
P33
3
A15
P17
30
N.C.
—
4
A12
P14
29
A14
P16
5
A07
P27
28
A13
6
A06
P26
27
A08
7
A05
P25
26
A09
8
A04
P24
25
A11
9
A03
P23
24
A16
10
A02
P22
23
A10
11
A01
P21
22
CE
P31
12
A00
P20
21
D07
P07
13
D00
P00
20
D06
P06
14
D01
P01
19
D05
P05
15
D02
P02
18
D04
P04
16
GND
VSS
17
D03
P03
• Non-MBM27C1000/1000A compatible pins
Pin no.
See “PIN
ASSIGNMENT”
20
MBM27C1000/1000A
Pin name
Treatment
MD0
MD1
X0
X0A
Connect a pull-up
resistor of 4.7 kΩ.
X1 to X1A
OPEN
AVCC
AVRH
P37
P40 to P47
P50 to P57
P60 to P67
P70 to P74
P80 to P86
P90 to P97
PA0 to PA2
N.C.
TEST
Pin name
P15
P10
P11
P13
P30
P12
• Power supply, GND connection pins
Classification
Power supply
GND
Connect a pull-up
resistor of about
1 MΩ to each pin.
Pin no.
See “PIN ASSIGNMENT”
Pin name
See “PIN ASSIGNMENT”
Pin no.
MB90P653A
Pin no.
Pin name
See
“PIN ASSIGNMENT”
HST
VCC
DVRH
See
“PIN ASSIGNMENT”
P34
P35
P36
RST
AVRL
AVSS
DVSS
VV
MB90650A Series
■ BLOCK DIAGRAM
X0, X1
RST
X0A, X1A
CPU
F2MC-16L family core
Clock control
circuit
5
Interrupt controller
RAM
2
8/16-bit PPG
2
(Output switching) × 1 channel
ROM
8/16-bit up/down
counter/timer
8 bits × 2 channels
(16 bits × 1 channel)
SIN0
SOT0
SCK0
Internal data bus
Communications prescaler
UART
SIN1, SIN2
SOT1, SOT2
SCK1, SCK2
2
2
2
DA00, DA01
DVRH
DVSS
2
2
2
DTP/external interrupt
I/O extended serial
interface × 2 channels
16-bit input capture × 2 channels
2
16-bit output compare × 4 channels
A/D converter
(10 bits)
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
CKOT
Prescaler
16-bit I/O timers
AVCC
AVRH, AVRL
AVSS
ADTG
AN0 to AN7
PPG00, PPG01
PPG10, PPG11
6
2
2
4
IRQ0 to IRQ5
IRQ6, IRQ7
IN0, IN1
OUT1 to OUT3
16-bit free-run timer × 1 channel
8
DTMF
DTMF
2
D/A converter
(8 bits)
I2C interface
SCL
SDA
I/O ports
Other pins
TEST, AD00 to AD15,
A16 to A23, ALE, RD,
WRL, WRH, HRQ,
HAK, RDY, CLK, N.C.,
MD0 to MD2, VCC, VSS
8
8
8
8
8
8
8
5
7
8
3
P00
to
P07
P10
to
P17
P20
to
P27
P30
to
P37
P40
to
P47
P50
to
P57
P60
to
P67
P70
to
P74
P80
to
P86
P90
to
P97
PA0
to
PA2
P00 to P07 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P10 to P17 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P60 to P67 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P40 to P46 (7 pins) : Incorporates an open-drain setting register
P47, P70 to P72 (4 pins) : Open-drain
21
MB90650A Series
■ MEMORY MAP
• MB90652, MB90653, MB90P653
FFFFFFH
Single chip mode
Internal ROM/external bus mode
ROM area
ROM area
ROM area
(FF bank image)
ROM area
(FF bank image)
RAM
RAM
External ROM/external bus mode
Address #1
FE0000H
010000H
Address #2
004000H
002000H
Address #3
Registers
Registers
RAM
Registers
000100H
0000C0H
Peripherals
Peripherals
Peripherals
000000H
Type
MB90652
MB90653
MB90P653
Address #1 *
FF0000H
FE0000H
FE0000H
Address #2 *
004000H
004000H
004000H
Address #3 *
000CFFH
0014FFH
0014FFH
: Internal access memory
: External access memory
: No access
* : Address #1, #2, and #3 are different owing to their devices respectively.
Notes: While the ROM data image of bank FF can be seen in the upper portion of bank 00, this is done only to permit
effective use of the C compiler’s small model. Because the lower 16 bits are the same, it is possible to
reference tables in ROM without declaring the “far” specification in the pointer.
For example, to access to 00C000H is to access to the ROM content of FFC000H in practice.
Because the ROM area of FF bank exceeds 48 Kbytes, all the area can be seen in bank 00.
So, the image for FF4000H to FFFFFFH can be seen in bank 00, while FE0000H to FF3FFFH can only be
seen in bank FF and FE.
22
MB90650A Series
• MB90654A, MB90F654A
FFFFFFH
ROM area
010000H
ROM area
(FF bank image)
ROM area
(FF bank image)
002100H
RAM
Registers
RAM
Registers
RAM
Registers
000100H
0000C0H
Peripherals
Peripherals
Peripherals
000000H
Type
MB90654A*
MB90F654A*
Address #1
FC0000H
FC0000H
Address #2
004000H
004000H
Address #3
0020FFH
0020FFH
: Internal access memory
: External access memory
: No access
* : In the MB90654A and MB90F654A, RAM area 2000H is 2100H.
Notes: While the ROM data image of bank FF can be seen in the upper portion of bank 00, this is done only to permit
effective use of the C compiler’s small model. Because the lower 16 bits are the same, it is possible to
reference tables in ROM without declaring the “far” specification in the pointer.
For example, to access to 00C000H is to access to the ROM content of FFC000H in practice.
Because the ROM area of FF bank exceeds 48 Kbytes, all the area can be seen in bank 00.
So, the image for FF4000H to FFFFFFH can be seen in bank 00, while FE0000H to FF3FFFH can only be
seen in bank FF and FE.
23
MB90650A Series
■ F2MC-16L CPU PROGRAMMING MODEL
• Dedicated registers
AH
Accumulator
AL
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
USPCU
User stack upper register
SSPCU
System stack upper register
USPCL
User stack lower register
SSPCL
System stack lower register
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bits
16 bits
32 bits
• General-purpose registers
Maximum 32 banks
R7
R6
RW7
R5
R4
RW6
R3
R2
RW5
R1
R0
RW4
RL3
RL2
RW3
RL1
RW2
RW1
RL0
RW0
000180H + RP × 10H →
16 bits
• Processor status (PS)
ILM
RP
—
I
S
T
N
CCR
24
Z
V
C
MB90650A Series
■ I/O MAP
Address
Register
Register
name
Read/
write
Resource name
Initial value
00H
Port 0 data register
PDR0
R/W
Port 0
XXXXXXXXB
01H
Port 1 data register
PDR1
R/W
Port 1
XXXXXXXXB
02H
Port 2 data register
PDR2
R/W
Port 2
XXXXXXXXB
03H
Port 3 data register
PDR3
R/W
Port 3
XXXXXXXXB
04H
Port 4 data register
PDR4
R/W
Port 4
1XXXXXXXB
05H
Port 5 data register
PDR5
R/W
Port 5
XXXXXXXXB
06H
Port 6 data register
PDR6
R/W
Port 6
XXXXXXXXB
07H
Port 7 data register
PDR7
R/W
Port 7
–––XX111 B
08H
Port 8 data register
PDR8
R/W
Port 8
–XXXXXXXB
09H
Port 9 data register
PDR9
R/W
Port 9
XXXXXXXXB
0AH
Port A data register
PDRA
R/W
Port A
–––––XXX B
0BH to 0FH
(Reserved area)
10H
Port 0 direction register
DDR0
R/W
Port 0
0 00 0 00 00 B
11H
Port 1 direction register
DDR1
R/W
Port 1
0 00 0 00 00 B
12H
Port 2 direction register
DDR2
R/W
Port 2
0 00 0 00 00 B
13H
Port 3 direction register
DDR3
R/W
Port 3
0 00 0 00 00 B
14H
Port 4 direction register
DDR4
R/W
Port 4
– 00 0 00 00 B
15H
Port 5 direction register
DDR5
R/W
Port 5
0 00 0 00 00 B
16H
Port 6 direction register
DDR6
R/W
Port 6
0 00 0 00 00 B
17H
Port 7 direction register
DDR7
R/W
Port 7
– –– 0 0– –– B
18H
Port 8 direction register
DDR8
R/W
Port 8
– 00 0 00 00 B
19H
Port 9 direction register
DDR9
R/W
Port 9
0 00 0 00 00 B
1AH
Port A direction register
DDRA
R/W
Port A
– –– – –0 00 B
1BH
Port 4 pin register
ODR4
R/W
Port 4
– 00 0 00 00 B
1CH
Port 0 resistance register
RDR0
R/W
Port 0
0 00 0 00 00 B
1DH
Port 1 resistance register
RDR1
R/W
Port 1
0 00 0 00 00 B
1EH
Port 6 resistance register
RDR6
R/W
Port 6
0 00 0 00 00 B
1FH
Analog input enable register
ADER
R/W
Port 5, A/D
1 11 1 11 11 B
20H
Serial mode register 0
SMR0
R/W
21H
Serial control register 0
SCR0
R/W
22H
Serial input register/
serial output register 0
SIDR/
SODR0
R/W
00000000B
UART0
00000100B
XXXXXXXXB
(Continued)
25
MB90650A Series
Address
Register
23H
Serial status register 0
24H
Serial mode control status register 0
25H
Serial mode control status register 0
26H
Register
name
Read/
write
Resource name
Initial value
SSR0
R/W
UART0
0 00 0 1– 00 B
SMCS0
R/W
SMCS0
R/W
Serial data register 0
SDR0
R/W
27H
Clock division control register
CDCR
R/W
28H
Serial mode control status register 1
SMCS1
R/W
29H
Serial mode control status register 1
2AH
Serial data register 1
2BH to 2FH
SMCS1
R/W
SDR1
R/W
Interrupt/DTP enable register
ENIR
R/W
31H
Interrupt/DTP source register
EIRR
R/W
Request level setting register
ELVR
R/W
33H
0 00 0 00 10 B
XXXXXXXXB
Communications prescaler
0–––1111B
––––0000B
I/O extended serial
interface 1
0 00 0 00 10 B
XXXXXXXXB
(Reserved area)
30H
32H
––––0000B
I/O extended serial
interface 0
34H to 35H
00000000B
DTP/external interrupts
0 00 0 00 00 B
00000000B
00000000B
(Reserved area)
36H
Control status register 1
ADCS1
37H
Control status register 2
ADCS2
38H
Data register 1
ADCR1
39H
Data register 2
ADCR2
3AH
D/A converter data register 0
DAT0
R/W
3BH
D/A converter data register 1
DAT1
R/W
3CH
D/A control register channel 0
DACR0
R/W
3DH
D/A control register channel 1
DACR1
R/W
3EH
Clock control register
CLKR
R/W
3FH
00000000B
R/W
A/D converter
R
0 00 0 00 00 B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
D/A converter
XXXXXXXXB
–––––––0B
–––––––0B
Clock output control
register
––––0000B
(Reserved area)
40H
Reload register lower channel 0
PRLL0
R/W
XXXXXXXXB
41H
Reload register upper channel 0
PRLH0
R/W
XXXXXXXXB
42H
Reload register lower channel 1
PRLL1
R/W
XXXXXXXXB
43H
Reload register upper channel 1
PRLH1
R/W
XXXXXXXXB
44H
PPG0 operation mode control register
channel 0
PPGC0
R/W
45H
PPG1 operation mode control register
channel 1
PPGC1
R/W
0X 0 0 0 0 0 1 B
46H
PPG0, PPG1 output control register
channel 0, channel 1
PPGOE
R/W
00000000B
47H to 4FH
50H
8/16-bit PPG
0X000XX1 B
(Reserved area)
Lower compare register channel 0
OCCP0
R/W
16-bit I/O timer output
compare (channel 0 to
channel 3)
XXXXXXXXB
(Continued)
26
MB90650A Series
Address
Register
51H
Upper compare register channel 0
52H
Lower compare register channel 1
53H
Upper compare register channel 1
54H
Lower compare register channel 2
55H
Upper compare register channel 2
56H
Lower compare register channel 3
57H
Upper compare register channel 3
58H
Register
name
Read/
write
OCCP0
R/W
OCCP1
R/W
OCCP2
R/W
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit I/O timer
Output compare
(channel 0 to channel 3)
XXXXXXXXB
XXXXXXXXB
OCCP3
R/W
Compare control status register channel 0
OCS0
R/W
0000––00B
59H
Compare control status register channel 1
OCS1
R/W
–––00000B
5AH
Compare control status register channel 2
OCS2
R/W
0000––00B
5BH
Compare control status register channel 3
OCS3
R/W
–––00000B
5CH to 5FH
(Reserved area)
60H
Lower input capture register channel 0
61H
Upper input capture register channel 0
62H
Lower input capture register channel 1
63H
Upper input capture register channel 1
64H
Input capture control status register
65H
66H
IPCP0
IPCP1
ICS0, 1
Lower timer data register
Upper timer data register
68H
Timer control status register
69H to 6FH
TCDTL
R
XXXXXXXXB
16-bit I/O timer
Input capture
(channel 0, channel 1)
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
0 00 00 0 00 B
R/W
TCCS
R/W
00000000B
16-bit I/O timer
Free-run timer
00000000B
0 00 00 0 00 B
(Reserved area)
UDCR0
71H
Up/down count register channel 1
UDCR1
72H
Reload compare register channel 0
RCR0
73H
Reload compare register channel 1
RCR1
74H
Counter status register channel 0
CSR0
75H
00000000B
R
W
0 00 00 0 00 B
8/16-bit up/down
counter/timer
00000000B
0 00 00 0 00 B
R/W
0 00 00 0 00 B
(Reserved area)
Counter control register channel 0
Counter status register channel 1
79H
7AH
R
R/W
Up/down count register channel 0
78H
R
TCDTH
70H
77H
R
(Reserved area)
67H
76H
XXXXXXXXB
CCRL0
CCRH0
CSR1
R/W
00001000B
8/16-bit up/down
counter/timer
R/W
0 00 00 0 00 B
0 00 00 0 00 B
(Reserved area)
Counter control register channel 1
CCRL1
R/W
8/16-bit up/down
counter/timer
00000000B
(Continued)
27
MB90650A Series
Address
7BH
Register
Counter control register channel 1
7CH to 7FH
80H
81H
82H
83H
84H
Register
name
Read/
write
Resource name
Initial value
CCRH1
R/W
8/16-bit up/down
counter/timer
X0001000B
(Reserved area)
00000000B
2
IBSR
R
2
IBCR
R/W
2
ICCR
R/W
2
IADR
R/W
– XXXXXXXB
2
IDAR
R/W
XXXXXXXXB
I C bus status register
I C bus control register
I C bus clock control register
I C bus address register
I C bus data register
85H to 87H
0 00 00 0 00 B
2
I C interface
–– 0XXXXXB
(Reserved area)
88H
DTMF control register
DTMC
—
—
00000000B
89H
DTMF data register
DTMD
—
—
0 0 0 X0 0 0 0 B
8A to 9EH
(Reserved area) (Accessing 90H to 9EH is prohibited)
DIRR
R/W
Delayed interrupt
generation module
–––––––0B
Low-power consumption mode
control register
LPMCR
R/W
Low-power consumption
mode
00011000B
Clock selection register
CKSCR
R/W
Low-power consumption
mode
11111100B
9FH
Delayed interrupt generation/
release register
A0H
A1H
A2H to A4H
(Reserved area)
A5H
Auto-ready function selection register
ARSR
W
External bus pin control circuit
0011––00B
A6H
External address output control
register
HACR
W
External bus pin control circuit
00000000B
A7H
Bus control signal selection register
ECSR
W
External bus pin control circuit
0000*00–B
A8H
Watchdog timer control register
WDTC
R/W
Watchdog timer
XXXXX111 B
A9H
Timebase timer control register
TBTC
R/W
Timebase timer
1– – 00 0 00 B
AAH
Watch timer control register
WTC
R/W
Watch timer
1X– 00000 B
ABH to AFH
(Reserved area)
(Continued)
28
MB90650A Series
(Continued)
Address
Register
Register
name
Read/
write
Resource name
Initial value
B0H
Interrupt control register 00
ICR00
R/W
00000111B
B1H
Interrupt control register 01
ICR01
R/W
0 00 00 1 11 B
B2H
Interrupt control register 02
ICR02
R/W
0 00 00 1 11 B
B3H
Interrupt control register 03
ICR03
R/W
0 00 00 1 11 B
B4H
Interrupt control register 04
ICR04
R/W
0 00 00 1 11 B
B5H
Interrupt control register 05
ICR05
R/W
0 00 00 1 11 B
B6H
Interrupt control register 06
ICR06
R/W
0 00 00 1 11 B
B7H
Interrupt control register 07
ICR07
R/W
B8H
Interrupt control register 08
ICR08
R/W
B9H
Interrupt control register 09
ICR09
R/W
0 00 00 1 11 B
BAH
Interrupt control register 10
ICR10
R/W
0 00 00 1 11 B
BBH
Interrupt control register 11
ICR11
R/W
0 00 00 1 11 B
BCH
Interrupt control register 12
ICR12
R/W
0 00 00 1 11 B
BDH
Interrupt control register 13
ICR13
R/W
0 00 00 1 11 B
BEH
Interrupt control register 14
ICR14
R/W
0 00 00 1 11 B
BFH
Interrupt control register 15
ICR15
R/W
0 00 00 1 11 B
C0H to FFH
Interrupt controller
0 00 00 1 11 B
0 00 00 1 11 B
(External area)
About Programming
R/W : Readable and writable
R : Read only
W : Write only
Explanation of initial values
0: The initial value of this bit is “0”.
1: The initial value of this bit is “1”.
* : The initial value of this bit is “0” or “1”.
X: The initial value of this bit is undefined.
–: This bit is not used. The initial value is undefined.
Note: Areas below address 0000FFH not listed in the table are reserved areas. These addresses are accessed by
internal access. No access signals are output on the external bus.
29
MB90650A Series
■ INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER ASSIGNMENTS TO
INTERRUPT SOURCES
Interrupt vector
Interrupt control register
I2OS
support
Number
Address
Number
Address
Reset
×
#08
FFFFDCH
—
—
INT 9 instruction
×
#09
FFFFD8H
—
—
Exception
×
—
—
ICR00
0000B0H
ICR01
0000B1H
ICR02
0000B2H
ICR03
0000B3H
ICR04
0000B4H
ICR05
0000B5H
ICR06
0000B6H
ICR07
0000B7H
ICR08
0000B8H
ICR09
0000B9H
ICR10
0000BAH
ICR11
0000BBH
ICR12
0000BCH
Interrupt source
#10
FFFFD4H
#11
FFFFD0H
#12
FFFFCCH
DTP/external interrupt 0 (External interrupt 0)
#13
FFFFC8H
16-bit free-run timer (I/O timer) overflow
#14
FFFFC4H
I/O extended serial interface 1
#15
FFFFC0H
DTP/external interrupt 1 (External interrupt 1)
#16
FFFFBCH
I/O extended serial interface 2
#17
FFFFB8H
DTP/external interrupt 2 (External interrupt 2)
#18
FFFFB4H
DTP/external interrupt 3 (External interrupt 3)
#19
FFFFB0H
8/16-bit PPG 0 counter borrow
#20
FFFFACH
8/16-bit up/down counter/timer 0 compare
#21
FFFFA8H
8/16-bit up/down counter/timer 0
underflow/overflow, up/down invert
#22
FFFFA4H
8/16-bit PPG 1 counter borrow
#23
FFFFA0H
DTP/external interrupt 4/5 (External interrupt 4/5)
#24
FFFF9CH
Output compare (channel 2) match (I/O timer)
#25
FFFF98H
Output compare (channel 3) match (I/O timer)
#26
FFFF94H
#27
FFFF90H
DTP/external interrupt 6 (External interrupt 6)
#28
FFFF8CH
8/16-bit up/down counter/timer 1 compare
#29
FFFF88H
8/16-bit up/down counter/timer 1
underflow/overflow, up/down invert
#30
FFFF84H
Input capture (channel 0) read (I/O timer)
#31
FFFF80H
Input capture (channel 1) read (I/O timer)
#32
FFFF7CH
Output compare (channel 0) match (I/O timer)
#33
FFFF78H
Output compare (channel 1) match (I/O timer)
#34
FFFF74H
#35
FFFF70H
DTP/external interrupt 7 (External interrupt 7)
#36
FFFF6CH
UART0 receive complete
#37
FFFF68H
ICR13
0000BDH
UART0 transmit complete
#39
FFFF60H
ICR14
0000BEH
ICR15
0000BFH
A/D converter
Timebase timer interval interrupt
Watch prescaler
Completion of flash memory write/erase
×
×
×
I C interface
×
#41
FFFF58H
Delayed interrupt generation module
×
#42
FFFF54H
2
: Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal.
: Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (stop request present).
: Indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal.
Note: For resources in which two interrupt sources share the same interrupt number, the I2OS interrupt clear signal
clears both interrupt request flags.
30
MB90650A Series
■ PERIPHERAL RESOURCES
1. Parallel Ports
(1) I/O Ports
Each port pin can be specified as either an input or output by its corresponding direction register when the pin
is not set for use by a peripheral. When a port is set as an input, reading the data register always reads the
value corresponding to the pin level. When a port is set as an output, reading the data register reads the data
register latch value. The same applies when reading using a read-modify-write instruction.
When used as control outputs, reading the data register reads the control output value, irrespective of the
direction register value.
Note that if a read-modify-write instruction (set bit or similar instruction) is used to set output data in the data
register before switching a pin from input to output, the instruction reads the input level at the pin and not the
data register latch value.
• Block diagram
Internal data bus
↑
Data register read
Data register
Pin
↑
Data register write
Direction register
↑
Direction register write
↑
Direction register read
31
MB90650A Series
(2) Port Direction Registers
• Port 0 data register (PDR0)
Address : 000000H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
P07
P06
P05
P04
P03
P02
P01
P00
XXXXXXXXB
R/W*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
Access
P17
P16
P15
P14
P13
P12
P11
P10
XXXXXXXXB
R/W*
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
P27
P26
P25
P24
P23
P22
P21
P20
XXXXXXXXB
R/W*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
Access
P37
P36
P35
P34
P33
P32
P31
P30
XXXXXXXXB
R/W*
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
P47
P46
P45
P44
P43
P42
P41
P40
1XXXXXXXB
R/W*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
Access
P57
P56
P55
P54
P53
P52
P51
P50
XXXXXXXXB
R/W*
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
P67
P66
P65
P64
P63
P62
P61
P60
XXXXXXXXB
R/W*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
Access
—
—
—
P74
P73
P72
P71
P70
- - - XX111B
R/W*
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
—
P86
P85
P84
P83
P82
P81
P80
- XXXXXXXB
R/W*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
Access
P97
P96
P95
P94
P93
P92
P91
P90
XXXXXXXXB
R/W*
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
—
—
—
—
—
PA2
PA1
PA0
- - - - - XXXB
R/W*
• Port 1 data register (PDR1)
Address : 000001H
• Port 2 data register (PDR2)
Address : 000002H
• Port 3 data register (PDR3)
Address : 000003H
• Port 4 data register (PDR4)
Address : 000004H
• Port 5 data register (PDR5)
Address : 000005H
• Port 6 data register (PDR6)
Address : 000006H
• Port 7 data register (PDR7)
Address : 000007H
• Port 8 data register (PDR8)
Address : 000008H
• Port 9 data register (PDR9)
Address : 000009H
• Port A data register (PDRA)
Address : 00000AH
R/W : Readable and writable
— : Unused
X : Indeterminate
* : The operation of reading or writing to I/O ports is slightly different from reading or writing to memory, as follows.
• Input mode
Read: Reads the corresponding pin level.
Write: Writes to the output latch.
• Output mode
Read: Reads the value of the data register latch.
Write: The value is output from the corresponding pin.
32
MB90650A Series
(3) Port Direction Registers
• Port 0 direction register (DDR0)
Address : 000010H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
D07
D06
D05
D04
D03
D02
D01
D00
00000000B
R/W*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
Access
D17
D16
D15
D14
D13
D12
D11
D10
00000000B
R/W*
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
D27
D26
D25
D24
D23
D22
D21
D20
00000000B
R/W*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
Access
D37
D36
D35
D34
D33
D32
D31
D30
00000000B
R/W*
• Port 1 direction register (DDR1)
Address : 000011H
• Port 2 direction register (DDR2)
Address : 000012H
• Port 3 direction register (DDR3)
Address : 000013H
• Port 4 direction register (DDR4)
Address : 000014H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
—
D46
D45
D44
D43
D42
D41
D40
-0000000B
R/W*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
Access
D57
D56
D55
D54
D53
D52
D51
D50
00000000B
R/W*
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
D67
D66
D65
D64
D63
D62
D61
D60
00000000B
R/W*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
Access
—
—
—
D74
D73
—
—
—
---00---B
R/W*
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
—
D86
D85
D84
D83
D82
D81
D80
-0000000B
R/W*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
Access
D97
D96
D95
D94
D93
D92
D91
D90
00000000B
R/W*
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Access
—
—
—
—
—
DA2
DA1
DA0
-----000B
R/W*
• Port 5 direction register (DDR5)
Address : 000015H
• Port 6 direction register (DDR6)
Address : 000016H
• Port 7 direction register (DDR7)
Address : 000017H
• Port 8 direction register (DDR8)
Address : 000018H
• Port 9 direction register (DDR9)
Address : 000019H
• Port A direction register (DDRA)
Address : 00001AH
R/W : Readable and writable
— : Unused
33
MB90650A Series
(Continued)
* : The operation of reading or writing to I/O ports is slightly different from reading or writing to memory, as follows.
• Input mode
Read: Reads the corresponding pin level.
Write: Writes to the output latch.
• Output mode
Read: Reads the value of the data register latch.
Write: The value is output from the corresponding pin.
When pins are used as ports, the register bits control the corresponding pins as follows.
0: Input mode
1: Output mode
Bits are set to “0” by a reset.
• P47, P70 to P72
No DDR for this port. Data is always available in this port, so when using P70 and P71 as I2C pin, set PDR
value to “1”. (Otherwise when using P70 and P71 by themselves, turn off the I2C.)
As this port is open-drain output style, so when using this port as an input port, in order to turn off the output
transister, set the output data resister value to “1” and add the pull up resister to the external pin.
34
MB90650A Series
(4) Port Resistance Registers
• Register configuration
• Port 0 resistance register (RDR0)
Address : 00001CH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value Access
RD07
RD06
RD05
RD04
RD03
RD02
RD01
RD00
00000000B R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value Access
RD17
RD16
RD15
RD14
RD13
RD12
RD11
RD10
00000000B R/W
• Port 1 resistance register (RDR1)
Address : 00001DH
• Port 6 resistance register (RDR6)
Address : 00001EH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value Access
RD67
RD66
RD65
RD64
RD63
RD62
RD61
RD60
00000000B R/W
R/W : Readable and writable
• Block diagram
Internal data bus
Pull-up resistor (approx. 50 kΩ)
Data register
Port I/O
Direction register
Resistance register
Notes: • Input resistance register R/W
Controls the pull-up resistor in input mode.
0: Pull-up resistor disconnected in input mode.
1: Pull-up resistor connected in input mode.
The setting has no meaning in output mode (pull-up resistor disconnected).
The direction register (DDR) sets input or output mode.
• The pull-up resistor is disconnected in hardware standby or stop mode (SPL = 1) (high impedance).
• This function is disabled when using an external bus mode. In this case, do not write to this register.
35
MB90650A Series
(5) Port Pin Register
• Register configuration
• Port 4 pin register (ODR4)
bit 7
Address : 00001BH
—
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OD46 OD45 OD44 OD43 OD42 OD41 OD40
Initial value Access
-0000000B R/W
R/W : Readable and writable
— : Unused
Internal data bus
• Block diagram
Port I/O
Data register
Direction register
Pin register
Notes: • Pin register R/W
Performs open-drain control in output mode.
0: Operate as a standard output port in output mode.
1: Operate as an open-drain output port in output mode.
The setting has no meaning in input mode (output Hi-z).
The direction register (DDR) sets input or output mode.
• This function is disabled when using an external bus mode. In this case, do not write to this register.
(6) Analog Input Enable Register
• Register configuration
• Analog input enable register (ADER)
bit 15
Address : 00001FH
R/W : Readable and writable
36
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
R/W
Controls each port 5 pin as follows.
0: Port input mode
1: Analog input mode
Set to “1” by a reset.
bit 14
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value Access
1 1 1 1 1 1 1 1 B R/W
MB90650A Series
2. UART
The UART is a serial I/O port that can be used for CLK asynchronous (start-stop synchronization) or CLK
synchronous communications. The UART has the following features.
•
•
•
•
Full duplex, double buffered
Supports asynchronous (start-stop synchronization) and CLK synchronous data transfer
Supports multi-processor mode
Built-in dedicated baud rate generator
Asynchronous : 9615 bps, 31250 bps, 4808 bps, 2404 bps and 1202 bps
For a 6, 8, 10, 12, or 16 MHz
CLK synchronous : 1 Mbps, 500 kbps, 250 kbps, 125 kbps, 115.2 kbps and 62.5 kbps clock.
•
•
•
•
Supports flexible baud rate setting using an external clock
Error detect function (parity, framing, and overrun)
NRZ type transmission signal
Intelligent I/O service support
(1) Register Configuration
bit 15
bit 8 bit 7
bit 0
CDCR
—
SCR
SMR
SSR
SIDR (R) /SODR (W)
8 bits
8 bits
• Serial mode register 0 (SMR0)
Address : 000020H
• Serial control register 0 (SCR0)
Address : 000021H
bit 7
bit 6
bit 5
bit 4
bit 3
MD1
MD0
CS2
CS1
R/W
R/W
R/W
bit 15
bit 14
PEN
P
R/W
R/W
• Serial input register/serial output register 0 (SIDR/SODR0)
bit 7
Address : 000022H
• Serial status register 0 (SSR0)
Address : 000023H
• Clock division control register (CDCR)
Address : 000027H
R/W :
R :
W :
— :
X :
bit 6
bit 2
bit 1
bit 0
Initial value
CS0 Reserved SCKE
SOE
00000000B
R/W
R/W
R/W
R/W
R/W
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
SBL
CL
A/D
REC
RXE
TXE
00000100B
R/W
R/W
R/W
W
R/W
R/W
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXXB
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
PE
ORE
FRE
RDRF TDRE
—
RIE
TIE
00001-00B
R
R
R
R
R
—
R
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
MD
—
—
—
DIV3
DIV2
DIV1
DIV0
0---1111B
R/W
—
—
—
R/W
R/W
R/W
R/W
Readable and writable
Read only
Write only
Unused
Indeterminate
37
MB90650A Series
(2) Block Diagram
Control signals
Reception interrupt
(to CPU)
SCK0, SCK1
Dedicated baud rate generator
16-bit timer 0
(Connected internally)
Transmission clock
pulses
Clock select
circuit
Transmission interrupt
(to CPU)
Reception clock
pulses
External clock
SIN0
Reception control
circuit
Transmission control
circuit
Start bit detection
circuit
Transmission start
circuit
Reception bit
counter
Transmission bit
counter
Reception parity
counter
Transmission parity
counter
SOT0, SOT1
Reception status
determination circuit
Reception error
occurrence signal
for I2OS
(to CPU)
Reception shifter
Transmission shifter
Start of
transmission
End of
reception
SODR
SIDR
Internal data bus
SMR
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signals
38
MB90650A Series
3. I/O Extended Serial Interface
I/O extended serial interface consists of an 8-bit serial I/O interface that can perform clock synchronous data
transfer. Either LSB-first or MSB-first data transfer can be selected.
The following two serial I/O operation modes are available.
• Internal shift clock mode: Data transfer is synchronized with the internal clock.
• External shift clock mode: Data transfer is synchronized with the clock input from the external pin (SCK). By
manipulating the general-purpose port that shares the external pin (SCK), this
mode also enables the data transfer operation to be driven by CPU instructions.
(1) Register Details
• Serial mode control status register 0, 1 (SMCS0, SMCS1)
bit 15
Address : 000025H
000029H
Address : 000024H
000028H
bit 14
bit 13
SMD2 SMD1 SMD0
bit 12
bit 11
bit 10
SIE
SIR
BUSY STOP STRT
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
—
—
—
—
—
bit 7
bit 9
bit 8
Initial value
00000010B
R
R/W
R/W
bit 3
bit 2
bit 1
bit 0
Initial value
—
MODE
BDS
SOE
SCOE
----0000B
—
—
R/W
R/W
R/W
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
*1
*2
• Serial data register 0, 1 (SDR0, SDR1)
Address : 000026H
00002AH
R/W :
R :
— :
X :
Readable and writable
Read only
Unused
Indeterminate
*1: Only “0” can be written.
*2: Only “1” can be written. Reading always returns “0”.
This register controls the transfer operation mode of the serial I/O. The following describes the function of each bit.
bit 3: Serial mode selection bit (MODE)
This bit selects the conditions for starting operation from the halted state. Changing the mode during
operation is prohibited
MODE
Operation
0
Start when STRT is set to “1”. [Initial value]
1
Start on reading from or writing to the serial data register.
The bit is initialized to “0” by a reset. The bit is readable and writable. Set to “1” when using the intelligent I/O
service.
bit 2: Transfer direction selection bit (BDS: Bit Direction Select)
Selects as follows at the time of serial data input and output whether the data are to be transferred in
the order from LSB to MSB or vice versa.
MODE
Operation
0
LSB-first [Initial value]
1
MSB-first
39
MB90650A Series
(2) Block Diagram
Internal data bus
(MSB-first) D0 to D7
D7 to D0 (LSB-first)
Transfer direction selection
SIN1, SIN2
Read
Write
SDR (Serial data register)
SOT1, SOT2
SCK1, SCK2
Control circuit
Shift clock counter
Internal clock
2
1
0
SMD2 SMD1 SMD0
SIE
SIR
BUSY STOP STRT MODE BDS
Interrupt
request
Internal data bus
40
SOE SCOE
MB90650A Series
4. A/D Converter
The A/D converter converts analog input voltages to digital values. The A/D converter has the following features.
Conversion time: Minimum of 5.2 µs per channel (for a 16 MHz machine clock)
Uses RC-type successive approximation conversion with a sample and hold circuit.
10-bit resolution
Eight program-selectable analog input channels
Single conversion mode:
Selectively convert a one channel.
Scan conversion mode:
Continuously convert multiple channels. Maximum of 8 programselectable channels.
Continuous conversion mode : Repeatedly convert specified channels.
Stop conversion mode:
Convert one channel then halt until the next activation. (Enables
synchronization of the conversion start timing.)
• An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D
conversion. This interrupt can activate I2OS to transfer the result of A/D conversion to memory and is suitable
for continuous operation.
• Activation by software, external trigger (falling edge), or timer (rising edge) can be selected.
•
•
•
•
(1) Register Configuration
bit 15
bit 8 bit 7
bit 0
ADCS2
ADCS1
ADCR2
ADCR1
8 bits
8 bits
• Control status register 1 (ADCS1)
bit 7
Address : 000036H
• Control status register 2 (ADCS2)
Address : 000037H
• Data register 1 (ADCR1)
Address : 000038H
• Data register 2 (ADCR2)
Address : 000039H
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
Initial value
MD1
MD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
BUSY
INT
INTE
PAUS STS1
STS0
STRT
DA
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
7
6
5
4
3
2
1
0
XXXXXXXXB
R
R
R
R
R
R
R
R
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
—
—
—
—
—
—
9
8
XXXXXXXXB
R
R
R
R
R
R
R
R
00000000B
R/W : Readable and writable
R : Read only
X : Indeterminate
41
MB90650A Series
(2) Block Diagram
AVCC
AVRH
AVRL
AVSS
D/A converter
MPX
Input circuit
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Successive
approximation register
Internal data bus
Comparator
Decoder
Sample and
hold circuit
Data register
ADCR1, ADCR2
A/D control register 1
A/D control register 2
Timer activation
PPG01
Operating clock
φ
42
ADCS1, ADCS2
Trigger activation
ADTG
Prescaler
MB90650A Series
5. D/A Converter
D/A converter is an R-2R type D/A converter with 8-bit resolution. The device contains two D/A converters. The
D/A control register controls the output of the two D/A converters independently.
(1) Register Configuration
• D/A converter data register 0 (DAT0)
Address : 00003AH
• D/A converter data register 1 (DAT1)
Address : 00003BH
• D/A control register channel 0 (DACR0)
Address : 00003CH
• D/A control register channel 1 (DACR1)
Address : 00003DH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
—
—
—
—
—
—
—
DAE0
-------0B
—
—
—
—
—
—
—
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
—
—
—
—
—
—
—
DAE1
-------0B
—
—
—
—
—
—
—
R/W
R/W : Readable and writable
— : Unused
X : Indeterminate
43
MB90650A Series
(2) Block Diagram
Internal data bus
DA DA DA DA DA DA DA DA
17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA
07 06 05 04 03 02 01 00
DVR
DVR
DA07
DA17
2R
DA16
2R
DA15
R
R
2R
44
R
2R
R
2R
R
DA05
DA01
DA11
DA10
2R
DA06
R
DA00
2R 2R
DAE1
Standby control
2R 2R
DAE0
Standby control
DA output
channel 1
DA output
channel 0
MB90650A Series
6. 8/16-bit PPG
8/16-bit PPG is an 8-bit reload timer module. The block performs PPG output in which the pulse output is
controlled by the operation of the timer.
The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two
external pulse output pins, and two interrupt outputs. The PPG has the following functions.
• 8-bit PPG output in two channels independent operation mode:
Two independent PPG output channels are available.
• 16-bit PPG output operation mode : One 16-bit PPG output channel is available.
• 8 + 8-bit PPG output operation mode : Variable-period 8-bit PPG output operation is available by using the
output of channel 0 as the clock input to channel 1.
• PPG output operation :
Outputs pulse waveforms with variable period and duty ratio. Can be
used as a D/A converter in conjunction with an external circuit.
(1) Register Configuration
• PPG0 operation mode control register channel 0 (PPGC0)
Address : 000044H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
PEN0
—
PE00
PIE0
PUF0
—
—
Reserved
0X000XX1 B
R/W
—
R/W
R/W
R/W
—
—
—
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
PEN1
—
PE10
PIE1
PUF1
MD1
MD0 Reserved
R/W
—
R/W
R/W
R/W
R/W
R/W
—
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11
PE01
00000000B
• PPG1 operation mode control register channel 1 (PPGC1)
Address : 000045H
Initial value
0X000001B
• PPG0, PPG1 output control register channel 0, channel 1 (PPGOE)
bit 7
Address : 000046H
R/W
bit 6
R/W
bit 5
R/W
R/W
R/W
R/W
R/W
R/W
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
• Reload register upper channel 0, channel 1 (PRLH0, PRLH1)
bit 15
bit 14
Address : 000041H
000043H
Initial value
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
• Reload register lower channel 0, channel 1 (PRLL0, PRLL1)
bit 7
bit 6
Address : 000040H
000042H
Initial value
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
X : Indeterminate
45
MB90650A Series
(2) Block Diagram
• 8/16-bit PPG (channel 0)
PPG00 output enable
Peripheral clock divided by 16
Peripheral clock divided by 8
Peripheral clock divided by 4
Peripheral clock divided by 2
Peripheral clock
PPG00
PPG01 output enable
PPG01
A/D converter
PPG0
output latch
Invert
Clear
PEN0
S
R Q
PCNT (Down-counter)
Count clock
selection
Timebase counter output
Main clock divided by 512
L/H select
IRQ
Reload
Channel 1-borrow
L/H selector
PRLL0
PRLBH0
PIE0
PRLH0
PUF0
L-side data bus
H-side data bus
PPGC0
(Operation mode control)
46
MB90650A Series
• 8/16-bit PPG (channel 1)
PPG10 output enable
Peripheral clock divided by 16
Peripheral clock divided by 8
Peripheral clock divided by 4
Peripheral clock divided by 2
Peripheral clock
PPG11 output enable
PPG10
PPG11
UART
PPG1
output latch
Invert
Clear
Count clock
selection
PEN1
S
R Q
PCNT (Down-counter)
IRQ
Channel 0-borrow
Timebase counter output
Main clock divided by 512
L/H select
Reload
L/H selector
PRLL1
PRLBH1
PIE
PRLH1
PUF
L-side data bus
H-side data bus
PPGC1
(Operation mode control)
47
MB90650A Series
7. 8/16-bit Up/Down Counter/Timer
8/16-bit up/down counter/timer is an up/down counter/timer and consists of six event input pins, two 8-bit up/
down counters, two 8-bit reload/compare registers, and their control circuits.
(1) Main Functions
• The 8-bit count register can count in the range 0 to 256 (or 0 to 65535 in 1 × 16-bit operation mode).
• The count clock selection can select between four different count modes.
Count modes
Timer mode
Up/down counter mode
Phase difference count mode (× 2)
Phase difference count mode (× 8)
• Two different internal count clocks are available in timer mode.
Count clock (at 16 MHz operation)
125 ns (8 MHz: Divide by 2)
0.5 µs (1 MHz: Divide by 8)
• In up/down count mode, you can select which edge to detect on the external pin input signal.
Detected edge
Detect falling edges
Detect rising edges
Detect both rising and falling edges
Edge detection disabled
• Phase difference count mode is suitable for motor encoder counting. By inputting the A, B, and Z phase outputs
from the encoder, a high-precision rotational angle, speed, or similar count can be implemented simply.
• Two different functions can be selected for the ZIN pin.
ZIN pin
Counter clear function
Gate function
• Compare and reload functions are available and can be used either independently or together. A variablewidth up/down count can be performed by activating both functions.
Compare/reload function
Compare function (Output an interrupt when a compare
occurs.)
Compare function (Output an interrupt and clear the
counter when a compare occurs.)
Reload function (Output an interrupt and reload when
an underflow occurs.)
Compare/reload function
(Output an interrupt and clear the counter when a
compare occurs. Output an interrupt and reload when
an underflow occurs.)
Compare/reload disabled
• Whether or not to generate an interrupt when a compare, reload (underflow), or overflow occurs can be set
independently.
• The previous count direction can be determined from the count direction flag.
• An interrupt can be generated when the count direction changes.
48
MB90650A Series
(2) Register Configuration
bit 15
bit 8 bit 7
bit 0
UDCR1
UDCR0
RCR1
RCR0
(Reversed area)
CSR0
CCRH0
CCRL0
(Reversed area)
CSR1
CCRH1
CCRL1
8 bits
8 bits
• Up/down count register channel 0 (UDCR0)
Address : 000070H
• Up/down count register channel 1 (UDCR1)
Address : 000071H
• Reload compare register channel 0 (RCR0)
Address : 000072H
• Reload compare register channel 1 (RCR1)
Address : 000073H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D07
D06
D05
D04
D03
D02
D01
D00
00000000B
R
R
R
R
R
R
R
R
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
D17
D16
D15
D14
D13
D12
D11
D10
00000000B
R
R
R
R
R
R
R
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D07
D06
D05
D04
D03
D02
D01
D00
00000000B
W
W
W
W
W
W
W
W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
D17
D16
D15
D14
D13
D12
D11
D10
00000000B
W
W
W
W
W
W
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
CMPF OVFF UDFF UDF1
UDF0
00000000B
W
W
• Counter status register channel 0, channel 1 (CSR0, CSR1)
bit 7
bit 6
bit 5
CSTR
CITE
UDIE
R/W
R/W
• Counter control register channel 0, channel 1 (CCRL0, CCRL1)
R/W
R/W
R/W
R/W
R
R
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address : 000074H
000078H
bit 7
Address : 000076H
00007AH
• Counter control register channel 0 (CCRH0)
Address : 000077H
• Counter control register channel 1 (CCRH1)
Address : 00007BH
R/W :
R :
W :
– :
X :
–
bit 6
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
–
R/W
bit 15
bit 14
M16E CDCF
R/W
Initial value
00001000B
00000000B
R/W
R/W
R/W
R/W
R/W
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
CFIE
CLKS CMS1 CMS0 CES1
CES0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
–
CDCF
CFIE
CLKS CMS1 CMS0 CES1
CES0
X0001000B
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Readable and writable
Read only
Write only
Unused
Indeterminate
49
MB90650A Series
(3) Block Diagram
• 8/16-bit up/down counter/timer (channel 0)
Internal data bus
8 bits
RCR0 (Reload/compare register 0)
CGE1 CGE0 C/GS
ZIN0
Edge or level detection
UDCC
CTUT
Reload control
UCRE
RLDE
Counter clear
8 bits
UDCR0 (Up/down count register 0)
Carry
CES1 CES0
UDFF OVFF
CMS1 CMS0
CITE
AIN0
BIN0
Up/down count
clock selection
Prescaler
CLKS
50
Count clock
UDF1 UDF0 CDCF CFIE
CSTR
Interrupt output
UDIE
CMPF
MB90650A Series
• 8/16-bit up/down counter/timer (channel 1)
Internal data bus
8 bits
RCR1 (Reload/compare register 1)
CGE1 CGE0 C/GS
ZIN1
Edge or level detection
CTUT
Reload control
UCRE
RLDE
Counter clear
UDCC
8 bits
UDCR1 (Up/down count register 1)
CMPF
UDFF OVFF
CMS1 CMS0 CES1 CES0 EN16
CITE
Carry
UDIE
Count clock
AIN1
BIN1
Up/down count
clock selection
UDF1 UDF0 CDCF CFIE
Prescaler
CSTR
Interrupt output
CLKS
51
MB90650A Series
8. Clock Output Control Register
Clock output control register outputs the divided machine clock.
(1) Register Configuration
• Clock control register (CLKR)
Address : 00003EH
bit 7
bit 6
bit 5
bit 4
—
—
—
—
bit 0
Initial value
CKEN FRQ2 FRQ1 FRQ0
----0000B
bit 3
R/W
bit 2
R/W
bit 1
R/W
R/W
R/W : Readable and writable
— : Unused
bit 3: Clock output enable bit (CKEN)
MODE
Operation
0
Operate as a standard port.
1
Operate as the clock output.
bit 2 to bit 0: Clock output frequency select bit (FRQ2 to FRQ0)
52
FRQ2
FRQ1
FRQ0
Output clock
φ = 16 MHz
φ = 8 MHz
φ = 4 MHz
0
0
0
φ/2
125 ns
250 ns
500 ns
0
0
1
2
φ/2
250 ns
500 ns
1 µs
0
1
0
φ/23
500 ns
1 µs
2 µs
0
1
1
φ/24
1 µs
2 µs
4 µs
1
0
0
5
φ/2
2 µs
4 µs
8 µs
1
0
1
φ/26
4 µs
8 µs
16 µs
1
1
0
φ/27
8 µs
16 µs
32 µs
1
1
1
φ/2
16 µs
32 µs
64 µs
1
8
MB90650A Series
9. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16L CPU to activate the intelligent I/O service or interrupt processing. Two request levels
(“H” and “L”) are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts
on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types.
(1) Register Configuration
• Interrupt/DTP enable register (ENIR)
Address : 000030H
• Interrupt/DTP source register (EIRR)
Address : 000031H
• Request level setting register (ELVR)
Address : 000032H
Address : 000033H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
(2) Block Diagram
4
Internal data bus
Interrupt/DTP enable register
4
Gate
Request F/F
Edge detect circuit
4
Request input
4
Interrupt/DTP source register
8
Request level setting register
53
MB90650A Series
10. 16-bit I/O Timer
The 16-bit I/O timer consists of one 16-bit free-run timer, two output compare, and two input capture modules.
Based on the 16-bit free-run timer, these functions can be used to generate two independent waveform outputs
and to measure input pulse widths and external clock periods.
• Register configuration
• 16-bit free-run timer
bit 15
bit 0
TCDTL : 000066H
TCDTH : 000067H
TCDT
Timer data register lower, upper (TCDTL, TCDTH)
TCCS : 000068H
Timer control status register (TCCS)
TCCS
• 16-bit output compare
OCCP0
OCCP1
OCCP2
OCCP3
:
:
:
:
OCS0
OCS1
OCS2
OCS3
000058H
000059H
00005AH
00005BH
:
:
:
:
000050H, 51H
000052H, 53H
000054H, 55H
000056H, 57H
bit 15
bit 0
OCCP
Compare register channel 0 to channel 3
lower, upper (OCCP0 to OCCP3)
OCS
Compare control status register
channel 0 to channel 3 (OCS0 to OCS3)
• 16-bit input capture
bit 15
bit 0
IPCP0 : 000060H, 61H
IPCP1 : 000062H, 63H
Input capture register channel 0, channel 1
lower, upper (IPCP0, IPCP1)
IPCP
ICS0, 1 : 000064H
ICS
Input capture control status register (ICS0, 1)
• Block diagram
To each block
Control logic
Interrupt
16-bit free-run timer
16-bit timer
Internal data bus
Clear
Output compare 0
Compare register 0
TQ
OUT0
TQ
OUT1
TQ
OUT2
TQ
OUT3
Output compare 1
Compare register 1
Output compare 2
Compare register 2
Output compare 3
Compare register 3
Input capture 0
54
Capture register 0
Edge selection
IN0
Capture register 1
Edge selection
IN1
MB90650A Series
(1) 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up-counter, a control register, and a prescaler. The output of the
timer/counter is used as the base time for the input capture and output compare.
• The operating clock for the counter can be selected from four different clocks.
Four internal clocks (φ/4, φ/16, φ/32, φ/64)
• Interrupts can be generated when a counter value overflow or compare match with compare register 0 occurs
(the appropriate mode must be set for a compare match).
• The counter can be initialized to 0000H by a reset, software clear, or compare match with compare register 0.
• Register details
• Upper timer data register (TCDTH)
Address : 000067H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
T15
T14
T13
T12
T11
T10
T09
T08
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Lower timer data register (TCDTL)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
T07
T06
T05
T04
T03
T02
T01
T00
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address : 000066H
R/W : Readable and writable
The count value of the 16-bit free-run timer can be read from this register. The count is cleared to “0000B” by a
reset. Writing to this register sets the timer value. However, only write to the register when the timer is halted
(STOP = “1”). Always use word access.
The 16-bit free-run timer is initialized by the following.
• Reset
• The clear bit (CLR) of the control status register
• A match between the timer/counter value and compare register 0 of the output compare (if the appropriate
mode is set)
• Block diagram
Interrupt request
Internal data bus
IVF
IVFE STOP MODE CLR
CLK1 CLK0
φ
Divider
Comparator 0
16-bit up-counter
Clock
Count value output T15 to T00
55
MB90650A Series
(2) Output Compare
The output compare consists of two 16-bit compare registers, compare output latches, and control registers.
The modules can invert the output level and generate an interrupt when the 16-bit free-run timer value matches
the compare register value.
• The four compare registers can be operated independently.
Each compare register has a corresponding output pin and interrupt flag.
• The four compare registers can be paired to control the output pins.
Invert the output pins using the four compare registers.
• Initial values can be set for the output pins.
• An interrupt can be generated when a compare match occurs.
• Register configuration
• Upper compare register channel 0 to channel 3 (OCCP0 to OCCP3)
OCCP0
OCCP1
OCCP2
OCCP3
:
:
:
:
000051H
000053H
000055H
000057H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
XXXXXXXXB
C15
C14
C13
C12
C11
C10
C09
C08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXXB
• Lower compare register channel 0 to channel 3 (OCCP0 to OCCP3)
bit 7
bit 6
bit 5
OCCP0 : 000050H
OCCP1 : 000052H
C07
C06
C05
OCCP2 : 000054H
OCCP3 : 000056H
R/W
R/W
R/W
C04
C03
C02
C01
C00
R/W
R/W
R/W
R/W
R/W
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
CMOD OTE1 OTE0
OTDI
OTD0
---00000B
• Compare control status register channel 0 to channel 3 (OCS0 to OCS3)
bit 15
bit 14
bit 13
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
ICP1
ICP0
ICE1
ICE0
—
—
CST1 CST0
0000--00B
R/W
R/W
R/W
R/W
—
—
OCS1 : 000059H
OCS3 : 00005BH
OCS0 : 000058H
OCS2 : 00005AH
R/W : Readable and writable
— : Unused
X : Indeterminate
56
R/W
R/W
MB90650A Series
• Block diagram
16-bit timer/counter value (T15 to T00)
TQ
Compare control
OTEO
OUT0
(OUT2)
OTE1
OUT1
(OUT3)
Compare register 0 (2)
Internal data bus
CMOD
16-bit timer/counter value (T15 to T00)
TQ
Compare control
Compare register 1 (3)
ICP1
Controller
Control blocks
ICP0
ICE1
ICE0
Compare 1 interrupt (3)
Compare 0 interrupt (2)
57
MB90650A Series
(3) Input Capture
The input capture consists of two independent external input pins, their corresponding capture registers, and
a control register. The value of the 16-bit free-run timer can be stored in the capture register and an interrupt
generated when the specified edge is detected on the signal from the external input pin.
• The edge to detect on the external input signal is selectable.
Detection of rising edges, falling edges, or either edge can be specified.
• The two input capture channels can operate independently.
• An interrupt can be generated on detection of the specified edge on the external input signal.
The input capture interrupt can activate the intelligent I/O service.
• Register details
• Input capture register channel 0, channel 1 (IPCP0, IPCP1)
IPCP0 : 000061H
IPCP1 : 000063H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
XXXXXXXXB
R
R
R
R
R
R
R
R
IPCP0 : 000060H
IPCP1 : 000062H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
XXXXXXXXB
R
R
R
R
R
R
R
R
• Input capture control status register (ICS0, 1)
000064H
bit 7
bit 6
bit 5
bit 4
ICP1
ICP0
ICE1
ICE0
R/W
R/W
R/W
R/W
bit 0
Initial value
EG11 EG10 EG01 EG00
00000000B
bit 3
R/W
bit 2
R/W
bit 1
R/W
R/W
R/W : Readable and writable
R : Read only
X : Indeterminate
The 16-bit free-run timer value is stored in these registers when the specified edge is detected on the input
waveform from the corresponding external pin. (Always use word access. Writing is prohibited.)
• Block diagram
Internal data bus
Capture data register 0
Edge detection
EG11 EG10 EG01 EG00
16-bit timer/counter value (T15 to T00)
Capture data register 1
ICP1
Edge detection
ICP0
IN0
ICE1
IN1
ICE0
Interrupt
Interrupt
58
MB90650A Series
11. Watchdog Timer, Timebase Timer, and Watch Timer
The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase
timer or the 15-bit watch timer as aclock source, a control register, and a watchdog reset controller.
The timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. Note that the timebase
timer uses the main clock, regardless of the setting of the MCS bit and SCS bit in CKSCR.
The watch timer consists of a 15-bit timer and a circuit that controls interval interrupts. Note that the watch timer
uses the sub clock, regardless of the setting of the MCS bit SCS bit in CKSCR.
(1) Register Configuration
• Watchdog timer control register (WDTC)
Address : 0000A8H
bit 3
bit 2
bit 1
bit 0
Initial value
WRST ERST SRST
WTE
WT1
WT0
XXXXX111B
R
W
W
W
bit 12
bit 11
bit 10
—
TBIE
TBOF
TBR
—
R/W
R/W
W
bit 7
bit 6
bit 5
bit 4
PONR
—
R
—
R
R
bit 15
bit 14
bit 13
—
—
• Timebase timer control register (TBTC)
Address : 0000A9H Reserved
—
bit 8
Initial value
TBC1 TBC0
1--00000B
bit 9
R/W
R/W
• Watch timer control register (WTC)
bit 7
Address : 0000AAH
WDCS SCE
R/W
R/W :
R :
W :
— :
X :
bit 6
R
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
WTIE WTOF WTR WTC2 WTC1 WTC0 1 X 0 0 0 0 0 0 B
R/W
R/W
R
R/W
R/W
R/W
Readable and writable
Read only
Write only
Unused
Indeterminate
59
MB90650A Series
(2) Block Diagram
Main clock
TBTC
TBC1
Selector
TBC0
212
214
216
219
TBTRES
Clock input
Timebase timer
212
214
216
219
TBR
TBIE
AND
Q
S
R
TBOF
Timebase
interrupt
WDTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watchdog reset
generator
CLR
WDGRST
To internal reset
generator
Internal data bus
WTE
WTC
AND
SCM
WDCS
SCE
Power-on reset
sub clock stops
S
Q R
WTC1
WTC0
Selector
WTR
WTIE
210
213
214
215
210 213
214 215
Watch timer
Clock input
WTRES
AND
Q
S
R
Sub clock
WTOF
Timer
interrupt
WDTC
PONR
From power-on generation
WRST
60
ERST
RST pin
SRST
From RST bit in
the STBYC register
MB90650A Series
12. I2C Interface
The I2C interface is a serial I/O port that supports the Inter-IC bus and operates as a master/slave device on
the I2C bus. This module has the following features:
•
•
•
•
•
•
•
Master/slave transmission/reception
Arbitration function
Clock synchronization function
Slave address/general call address detection function
Transfer direction detection function
Start condition repeat generation and detection function
Bus error detection function
(1) Register Configuration
• I2C bus status register (IBSR)
Address : 000080H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
00000000B
R
R
R
R
R
R
R
R
• I2C bus control register (IBCR)
Address : 000081H
bit 15
bit 14
bit 13
bit 12
bit 11
BER
BEIE
SCC
MSS
ACK
R/W
R/W
R/W
R/W
R/W
bit 9
bit 8
Initial value
GCAA INTE
INT
00000000B
bit 10
R/W
R/W
R/W
• I2C bus clock control register (ICCR)
Address : 000082H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
—
—
EN
CS4
CS3
CS2
CS1
CS0
--0XXXXXB
—
—
R/W
R/W
R/W
R/W
R/W
R/W
• I2C bus address register (IADR)
Address : 000083H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
—
A6
A5
A4
A3
A2
A1
A0
-XXXXXXXB
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• I2C bus data register (IDAR)
Address : 000084H
R/W
R
—
X
:
:
:
:
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXXB
Readable and writable
Read only
Unused
Indeterminate
61
MB90650A Series
(2) Block Diagram
ICCR
I2C enable
EN
Peripheral clock
Clock divider 1
ICCR
5
6
7
8
CS4
Clock selection 1
CS3
Clock divider 2
CS2
2 4 8
CS1
CS0
16
32
Sync
64 128 256
Clock selection 2
Shift clock edge
change timing
IBSR
Bus busy
BB
Repeat start
RSC
Last bit
LRB
TRX
Error
First byte
AL
Internal data bus
Start/stop
condition generation
Transmit/receive
FBT
Arbitration lost detection
IBCR
BER
SCL
BEIE
Interrupt request
INTE
INT
End
IBCR
SCC
MSS
ACK
GCAA
Start
Master
ACK enable
Start/stop
condition generation
GC-ACK enable
IDAR
IBSR
Slave
AAS
GCA
Global call
Slave address
comparison
IADR
62
Shift clock generation
IRQ
SDA
MB90650A Series
13. External Bus Pin Control Circuit
The external bus pin control circuit controls the external bus pins required to extend the CPU’s address/data
bus outside the device.
(1) Register Configuration
• Auto-ready function selection register (ARSR)
Address : 0000A5H
bit 15
bit 14
ICR1
ICR0 HMR1 HMR0
W
bit 13
W
bit 12
W
bit 11
bit 10
—
—
—
—
W
bit 8
Initial value
LMR1 LMR0
0011--00B
bit 9
W
W
• External address output control register (HACR)
Address : 0000A6H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
E23
E22
E21
E20
E19
E18
E17
E16
00000000 B
W
W
W
W
W
W
W
W
• Bus control signal selection register (ECSR)
bit 15
bit 14
bit 13
bit 12
CKE
RYE
HDE
ICBS HMBS WRE
W
W
W
Address : 0000A7H
W
bit 11
W
bit 10
W
bit 9
bit 8
Initial value
LMBS
—
0000*00- B
W
—
W : Write only
— : Unused
* : “1” or “0”
(2) Block Diagram
P0
P0 data
P1
P2
P3
P3
P0
P0 direction
RB
Data control
Address control
Access control
Access control
63
MB90650A Series
14. Low-power Consumption Mode (CPU Intermittent Operation Function, Oscillation
Stabilization Delay Time, Clock Multiplier Function)
The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode, pseudo-watch
mode, main clock mode, main sleep mode, main watch mode, main stop mode, sub clock mode, sub sleep
mode, sub watch mode, and sub stop mode. Aside from the PLL clock mode, all of the other operating modes
are low-power consumption modes.
In main clock mode and main sleep mode, the main clock (main OSC oscillation clock) and the sub clock (sub
OSC oscillation clock) operate. In these modes, the main clock divided by 2 is used as the operation clock, the
sub clock (sub OSC oscillation clock) is used as the timer clock, and the PLL clock (VCO oscillation clock) is
stopped.
In sub clock mode and sub sleep mode, only the sub clock operates. In these modes, the sub clock is used as
the operation clock, and the main clock and PLL clock are stopped.
In PLL sleep mode and main sleep mode, only the CPU’s operation clock is stopped; all clocks other than the
CPU clock operate.
In pseudo-watch mode, only the watch timer and timebase timer operate.
In PLL watch mode, main watch mode, and sub watch mode, only the watch timer operates. In this mode, only
the sub clock is used for operation, while the main clock and the PLL clock are stopped (the difference between
the PLL watch mode, the main watch mode and the sub watch mode is that it resumes operation after an interrupt
in the PLL clock mode, the main clock mode, and the sub clock mode respectively, and there is no reference
concerning about clock mode operation).
The main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to retain
data while consuming the least amount of power. (The difference between the main stop mode and the sub stop
mode is that it resumes operation in the main clock mode and the sub clock mode respectively, and there is no
reference concerning about stop mode operation).
The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing
registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower power
consumption by reducing the execution speed of the CPU while supplying a high-speed clock and using on-chip
resources.
The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. These clocks
are divided by 2 to be used as a machine clock.
The WS1 and WS0 bits can be used to set the main clock oscillation stabilization delay time for when stop mode
is woken up.
64
MB90650A Series
(1) Register Configuration
• Low-power consumption mode control register (LPMCR)
Address : 0000A0H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
STP
SLP
SPL
RST
TMD
CG1
CG0
—
00011000B
W
W
R/W
W
W
R/W
R/W
• Clock selection register (CKSCR)
Address : 0000A1H
R/W
R
W
—
:
:
:
:
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
SCM
MCM
WS1
WS0
SCS
MCS
CS1
CS0
11111100B
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Readable and writable
Read only
Write only
Unused
65
MB90650A Series
(2) Block Diagram
• Low-power consumption control circuit and clock generator
CKSCR
Sub clock divided by 4
(OSC oscillation)
SCM
Sub clock
SCS
switching control
CKSCR
MCM
MCS
Main clock
(OSC oscillation)
PLL multiplier
circuit
1
2
3
4
CPU
system clock
generation
CKSCR
CS1
CPU
CS0
Clock selector
1/2 S
CPU clock
0/9/17/33
intermittent cycle selection
LPMCR
CG1
Internal data bus
CG0
LPMCR
CPU intermittent
operation function
Cycle count
selection circuit
Peripheral
clock
generation
SCM
SLP
STP
Peripheral clock
SLEEP
Standby
controller
TMD
RST
MSTP
Main OSC stop
STOP
Sub OSC stop
cancel
Interrupt request
or RST
CKSCR
WS1
WS0
Oscillation
stabilization
delay time
selector
24
213
215
218
Clock input
Timebase timer
LPMCR
SPL
LPMCR
RST
Pin high-impedance controller
Internal reset
generator
212 214 216 219
Pin Hi-Z
RST pin
Internal RST
To watchdog timer
WDGRST
66
MB90650A Series
• State transition diagram for clock selection (1)
Power-on
Main → PLL×
SCS = 1, MSC = 0
SCM = 1, MCM = 1
CS1/0 = ××
Main
SCS = 1, MCS = 1 <1>
SCM = 1, MCM = 1
CS1/0 = ××
<2>
<3>
<7>
PLL1 → Main
SCS = 0 or MCS = 0
SCM = 1, MCM = 0
<7> CS1/0 = 00
<4>
PLL 1 multiplier
SCS = 1, MSC = 0
<6> SCM = 1, MCM = 0
CS1/0 = 00
<7>
Sub → PLL×
SCS = 1, MCS = 0
SCM = 0, MCM = 1 <9>
CS1/0 = ××
<8>
PLL2 → Main
SCS = 0 or MCS = 1
SCM = 1, MCM = 0 <6>
CS1/0 = 01
<7> PLL3 → Main
SCS = 0 or MCS = 1
SCM = 1, MCM = 0
CS1/0 = 10
<8>
PLL 2 multiplier
SCS = 1, MSC = 0
SCM = 1, MCM = 0
CS1/0 = 01
<5> PLL 3 multiplier
SCS = 1, MSC = 0
SCM = 1, MCM = 0
<6>
CS1/0 = 10
<8>
Main → Sub
SCS = 0, MCS = ×
MCM = 1
SCM = 1
<8>
PLL4 → Main
SCS = 0 or MCS = 1
SCM = 1, MCM = 0
CS1/0 = 11
<6>
PLL 4 multiplier
SCS = 1, MSC = 0
SCM = 1, MCM = 0
CS1/0 = 11
<1> MCS bit cleared and SCS bit set
<2> PLL clock oscillation stabilization delay complete and CS1/0 = 00
<3> PLL clock oscillation stabilization delay complete and CS1/0 = 01
<4> PLL clock oscillation stabilization delay complete and CS1/0 = 10
<5> PLL clock oscillation stabilization delay complete and CS1/0 = 11
<6> MCS bit set or SCS bit cleared
<7> PLL clock and main clock synchronized timing and SCS = 1
<8> PLL clock and main clock synchronized timing and SCS = 0
<9> Main clock oscillation stabilization delay complete and MCS = 0
67
MB90650A Series
• State transition diagam for clock selection (2)
Power-on
Main → Sub
SCS = 0
SCM = 1
MCM = 1
<1>
Main
SCS = 1, MCS = 1
SCM = 1
MCM = 1
<2>
<4>
PLL× → Sub
SCS = 0, MCS = ×
SCM = 1, MCM = 0
CS1/0 = ××
<5>
Main → PLL×
SCS = 1, MCS = 0
SCM = 1, MCM = 1
CS1/0 = ××
<6>
Sub → Main
SCS = 1
SCM = 0
MCM = 1
<3>
Sub
SCS = 0
SCM = 0
MCM = 1
<1> SCS bit cleared
<2> Sub clock edge detection timing
<3> SCS bit set
<4> Main clock oscillation stabilization delay complete and MCS = 1
<5> PLL clock and main clock synchronized timing and SCS = 0
<6> Main clock ascillation stabilization delay complete and MCS = 0
68
MB90650A Series
15. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to
the F2MC-16L CPU can be generated and cleared by software using this module.
(1) Register Details
• Delayed interrupt generation /release register (DIRR)
Address : 00009FH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
—
—
—
—
—
—
—
R0
-------0B
R/W
R/W : Readable and writable
— : Unused
The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register
generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register
is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However,
considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for
register access.
Internal data bus
(2) Block Diagram
Delayed interrupt generation/release decoder
Interrupt latch
69
MB90650A Series
16. DTMF Generator
The DTMF (dual tone multifrequency) generator is a module that can generate a series of audio tones as heard
from a push-button telephone or a radio transceiver with a keypad. It has the following features:
Capable of generating DTMF tones continuously (or even a single tone)
Capable of generating all CCITT tones: 0 to 9, *, #, A to D
(1) Register list
• DTMF control register (DTMC)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 1
bit 0
Initial value
—
00000000B
—
CSL2
CSL1
CSL0
CDIS
RDIS OUTE
—
R/W
R/W
R/W
R/W
R/W
R/W
—
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
—
—
—
—
—
—
—
—
Address : 000088H
• DTMF data register (DTMD)
bit 2
Address : 000089H
DDAT3 DDAT2 DDAT1 DDAT0
R/W
R/W
R/W
Initial value
000X0000B
R/W
R/W : Read/write enabled
— : Unused
X : Undefined
(2) Block diagram
Clock pulse
Frequency divider
Frequency
select
COL staircase
generator
Voltage data
DTMF
ROW/COL
decoder
ROW staircase
generator
Adder
Frequency
select
Preset counter
Count clock
Terminate
Frequency
divider
Internal clock
Control signal generator
DTMF control register (DTMC)
DTMF data register (DTMD)
Internal bus
70
Frequency
select
MB90650A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Symbol
Parameter
VCC1
VSS – 0.3
VSS + 4.0
V
VCC2
VSS – 0.3
VSS + 7.0
V
MB90652A/653A/654A,
MB90F654A
VSS – 0.3
VSS + 7.0
V
MB90P653A
VSS – 0.3
VSS + 4.0
V
MB90652A/653A/654A,
MB90F654A
*1
VSS – 0.3
VSS + 7.0
V
MB90P653A
VSS – 0.3
VSS + 4.0
V
MB90652A/653A/654A,
MB90F654A
VSS – 0.3
VSS + 7.0
V
MB90P653A
VSS – 0.3
VSS + 4.0
V
MB90652A/653A/654A,
MB90F654A
VSS – 0.3
VSS + 7.0
V
MB90P653A
VSS – 0.3
VSS + 4.0
V
MB90652A/653A/654A,
MB90F654A
*2
VSS – 0.3
VSS + 7.0
V
MB90P653A
VSS – 0.3
VSS + 4.0
V
MB90652A/653A/654A,
MB90F654A
*2
VSS – 0.3
VSS + 7.0
V
MB90P653A
—
10
mA
MB90652A/653A/654A,
MB90F654A
*3
—
15
mA
MB90P653A
—
3
mA
MB90652A/653A/654A,
MB90F654A
*4
—
4
mA
MB90P653A
—
60
mA
MB90652A/653A/654A,
MB90F654A
—
100
mA
MB90P653A
—
30
mA
MB90652A/653A/654A,
MB90F654A
*5
—
50
mA
MB90P653A
—
–10
mA
MB90652A/653A/654A,
MB90F654A
*3
—
–15
mA
MB90P653A
AVCC
Power supply voltage
AVRH
AVRL
DVRH
VI
VO
“L” level maximum
output current
IOL
“L” level average output current
IOLAV
“L” level total maximum
output current
Remarks
Max.
VCC
Output voltage
Unit
Min.
(VCC1 = VCC2)
Input voltage
Value
ΣIOL
“L” level total average
output current
ΣIOLAV
“H” level maximum
output current
IOH
*1
*2,*6
*2,*6
*3
*4
*5
*3
(Continued)
71
MB90650A Series
(Continued)
(VSS = AVSS = 0.0 V)
Parameter
“H” level average
output current
Symbol
IOHAV
Value
Unit
Remarks
Min.
Max.
—
–3
mA
MB90652A/653A/654A,
MB90F654A
*4
—
–4
mA
MB90P653A
—
–60
mA
MB90652A/653A/654A,
MB90F654A
—
–100
mA
MB90P653A
“H” level total maximum
output current
ΣIOH
“H” level total average
output current
ΣIOHAV
—
–30
mA
Power consumption
PD
—
200
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
*4
*5
*1: AVCC, AVRH, AVRL and DVRH must not exceed VCC (VCC1 and VCC2 are contained) . Similarly, AVRL must not
exceed AVRH.
*2: VI and VO must not exceed VCC (VCC1 and VCC2 are contained) + 0.3 V.
*3: Maximum output current specifies the peak value or one corresponding pin.
*4: The average output current is the rating for the current from an individual pin averaged over 100 ms.
*5: The average total output current is the rating for the current from all pins averaged over 100 ms.
*6: Applies to the P47 and P70 to P72 on the MB90652A/653A/654A and MB90F654A.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
72
MB90650A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter
Symbol
2.2
3.6
V
For normal operation
(MB90652A/653A/654A)
2.7
3.6
V
For normal operation (MB90P653A)
2.4
3.6
V
For normal operation (MB90F654A)
2.2
5.5
V
For normal operation
(MB90652A/653A/654A)
2.7
5.5
V
For normal operation (MB90P653A)
2.4
5.5
V
For normal operation (MB90F654A)
1.8
3.6
V
To maintain statuses in stop mode
(MB90652A/653A/654A)
1.8
5.5
V
To maintain statuses in stop mode
(MB90P653A)
1.8
3.6
V
To maintain statuses in stop mode
(MB90F654A)
1.8
5.5
V
To maintain statuses in stop mode
(MB90652A/653A/654A)
1.8
5.5
V
To maintain statuses in stop mode
(MB90P653A)
1.8
5.5
V
To maintain statuses in stop mode
(MB90F654A)
VIH
0.7 VCC
VCC + 0.3
V
Pins other than VIHS and VIHM
VIHS
0.8 VCC
VCC + 0.3
V
Hysteresis input pins
VIHM
VCC – 0.3
VCC + 0.3
V
MD pin input
VIHT
2.4
VCC + 0.3
V
TTL input pins
VIL
VSS – 0.3
0.3 VCC
V
PIns other than VILS and VILM
VILS
VSS – 0.3
0.2 VCC
V
Hysteresis input pins
VILM
VSS – 0.3
VSS + 0.3
V
MD pin input
VILT
VSS – 0.3
0.8
V
TTL input pins
TA
–40
+85
°C
Power supply voltage
VCC1
VCC2
Operating temperature
Remarks
Max.
VCC2
“L” level input voltage
Unit
Min.
VCC1
“H” level input voltage
Value
Note: I2C must be used at above 2.7 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
73
MB90650A Series
3. DC Characteristics
Parameter
“H” level
output
voltage*2
(MB90652A/653A/654A: VCC = 2.2 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
(MB90P653A: VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
(MB92F654A: VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Remarks
Min.
Typ. Max.
VCC2 = 4.5 V,
Pins except IOH = –4.0 mA
P47,
P70 to P72 VCC = 2.7 V,
IOH = –1.6 mA
VCC2– 0.5
—
—
V
When the 5-V power
supply is used
VCC1– 0.3
—
—
V
When the 3-V power
supply is used
*1
VCC2 = 4.5 V,
IOL = 4.0 mA
—
—
0.4
V
When the 5-V power
supply is used
VCC = 2.7 V,
IOL = 2.0 mA
—
—
0.4
V
When the 3-V power
supply is used
–10
—
10
µA
40
80
400
kΩ MB90P653A
20
65
200
kΩ
—
0.1
10
µA
—
10
20
mA
MB90652A/653A/654A:
During normal operation
—
17
24
mA
MB90652A/653A/654A:
In A/D operation
—
19
26
mA
MB90652A/653A/654A:
In D/A operation
ICCS
—
2.5
5
mA
MB90652A/653A/654A:
During sleep
ICC
—
20
27
mA
MB90P653A:
During normal operation
—
24
31
mA
MB90P653A:
In A/D operation
—
26
33
mA
MB90P653A:
In D/A operation
—
4.2
10
mA
MB90P653A:
During sleep
VOH
“L” level output
VOL
voltage*2
All output
pins
Input leakage
IIL
current
Except P50
VCC = 3.3 V,
to P57,
VSS < VI < VCC
P90, P91
Pull-up resistor RPULL
Open-drain
output leakage Ileak
current
—
P40 to P47,
P70 to P72
When VCC = 3.0 V,
TA = +25°C
—
ICC
ICC
—
ICC
Power supply
current
ICC
—
ICC
ICCS
When VCC = 3.0 V
Internal 8 MHz
operation
When VCC = 3.0 V
Internal 8 MHz
operation
MB90652A/653A/654A,
MB90F654A
* 1 : P40 to P46 are N-ch open-drain pins to be controlled and are usually used as CMOS devices.
* 2 : When the device is used with dual power supplies, the P20 to P27, P30 to P37, P40 to P47, and P70 to P72
are the 5 V pins and the rest are the 3 V pins.
(Continued)
74
MB90650A Series
(Continued)
Parameter
Symbol
(MB90652A/653A/654A: VCC = 2.2 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
(MB90P653A: VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
(MB90F654A: VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Condition
Unit
Remarks
Min.
Typ. Max.
ICC
—
20
35
mA
MB90652A/653A/654A:
During normal operation
ICC
—
27
45
mA
MB90F654A:
During normal operation
—
33
50
mA
MB90F654A:
Flash write/erase
ICC
—
31
41
mA
MB90652A/653A/654A:
In A/D operation
ICC
—
34
42
mA
MB90652A/653A/654A:
In D/A operation
—
4.8
10
mA
MB90652A/653A/654A:
During sleep
—
6.2
12
mA
MB90F654A:
During sleep
—
0.1
20
µA
MB90652A/653A/654A:
During stop
—
0.2
40
µA
MB90F654A:
During stop
—
16
140
MB90652A/653A/654A,
µA MB90F654A:
In sub operation
—
4.4
6
mA
MB90P653A:
In sub operation
—
10
30
µA
MB90652A/653A/654A:
In watch mode
—
15
30
µA
MB90F654A:
In watch mode
—
15
60
µA
MB90P653A:
In watch mode
—
10
80
pF
ICC
—
ICCS
—
ICCS
Power supply
current
ICCH
—
ICCH
ICCL
—
ICCL
When VCC = 3.0 V
Internal 16 MHz
operation
When VCC = 3.0 V
Internal 16 MHz
operation
TA = +25°C
When VCC = 3.0 V
VCC = 3.0 V,
TA = +25°C
External 32 kHz
operation
(Internal 8 MHz
operation)
ICCT
ICCT
—
VCC = 3.0 V,
TA = +25°C
External 32 kHz
operation
ICCT
Input
capacitance
CIN
Except AVCC,
AVSS, VCC,
VSS
—
Note: VCC = VCC1 = VCC2
75
MB90650A Series
4. AC Characteristics
(1) Clock Timing
Parameter
Symbol
Clock frequency
Clock cycle time
FCH
—
32
MHz
—
3
—
16
MHz MB90P653A
—
—
32.768
—
kHz
—
31.25
—
333
ns
MB90652A/653A/
654A,MB90F654A
—
62.5
—
333
ns
MB90P653A
—
—
30.5
—
µs
—
5
—
—
ns
MB90652A/653A/
654A,MB90F654A *2
—
10
—
—
ns
MB90P653A
X0A
—
—
15.2
—
µs
X0
—
—
—
5
ns
—
1.5
—
16
MHz
—
1.5
—
8
MHz MB90P653A
X0, X1
tC
X0, X1
X0A, X1A
Input clock rise
tcr
time and fall time tcf
fCP
MB90652A/653A/
654A,MB90F654A
3
X0A, X1A
PWH
P
Input clock pulse WL
width
PWLH
PWLL
Condition
—
FCL
tCL
Internal
operating clock
frequency
Pin
name
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Min.
Typ.
Max.
X0
—
fCPL
—
—
—
8.192
—
kHz
Internal
operating clock
cycle time
tCP
—
—
62.5
—
666
ns
tCPL
—
—
—
122.1
—
µs
Frequency
fluctuation ratio
∆f
—
—
—
—
5
%
*2
*2
External clock
MB90652A/653A/
654A,MB90F654A
When locked
*1
*1: The frequency fluction ratio indicates the maximum fluctuation ratio from the set center frequency while locked
when using the PLL multiplier.
+
∆f =
α
fO
+α
× 100 (%)
Center frequency
fO
–α
–
Because the PLL frequency fluctuates around the set frequency with a certain cycle [approximately CLK × (1 CYC
to 50 CYC)], the worst value is not maintained for long. (The pulse, if featured with the long period, would produce
practically no error.)
*2: The duty ratio should be in the range 30% to 70%.
Note: VCC = VCC1 = VCC2
76
MB90650A Series
•Main clock timing condition (X0, X1)
tC
0.8 VCC
0.2 VCC
X0
PWL
PWH
tcf
tcr
• Subclock timing condition (X0A, X1A )
tCL
0.8 VCC
0.2 VCC
X0A
PWHL
PWLL
77
MB90650A Series
• PLL operation assurance range
Power supply voltage (VCC)
Relationship between the internal operating clock frequency and power supply voltage
(MB90652A/653A/654A, MB90F654A)
(V)
Normal operation range
3.6
PLL operation assurance range
2.7
2.5
2.2
1
3
5
16
(MHz)
Internal clock (fCP)
Power supply voltage (VCC)
Relationship between the internal oprating clock frequency and power supply voltage
(MB90P653A)
(V)
Normal operation range
3.6
PLL operation
assurance range
2.7
1.5
3
8
(MHz)
Internal clock (fCP)
Relationship between the oscillation frequency and internal operating clock frequency
(MHz)
16
Multiply Multiply
by 4
by 3
Multiply
by 2
Internal clock (fCP)
12
Multiply by 1
9
8
4
3 4
78
No multiplier
8
16
Oscillation clock (FC)
24
32
(MHz)
MB90650A Series
The AC characteristics are for the following measurement reference voltages.
• Input signal waveform
Hysteresis input pins
• Output signal waveform
Output pins
0.8 VCC
2.4 V
0.2 VCC
0.2 V
Other than hysteresis or MD input pins
0.7 VCC
0.3 VCC
79
MB90650A Series
(2) Clock Output Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Pin
Symbol name
Parameter
Cycle time
tCYC
CLK ↑ → CLK↓
CLK
tCHCL
—
tCP
VCC = 3.0 V
±10%
CLK
—
ns
tCP / 2 – 20 tCP / 2 + 20
ns
tCP / 2 – 64 tCP / 2 + 64
ns
In the external
frequency of
5 MHz
tCP: See “(1) Clock Timing.”
Note: VCC = VCC1 = VCC2
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
(3) Reset Input Specifications
Parameter
Reset input time
Symbol
tRSTL
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Pin
name
RST
—
16 tCP
—
ns
tCP: See “(1) Clock Timing.”
Note: VCC = VCC1 = VCC2
t RSTL
RST
0.2 VCC
0.2 VCC
• AC characteristics measurement conditions
Pin
CL : Load capacitance at testing
CL
80
CLK, ALE: CL = 30 pF
AD15 to AD00 (address/data bus), RD, WR: CL = 80 pF
MB90650A Series
(4) Power on Supply Specifications (Power-on Reset)
Symbol
Parameter
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Max.
Pin name
Power supply rising time
tR
VCC
—
—
30
ms
*
Power supply cut-off time
tOFF
VCC
—
1
—
ms
Due to
repeat
operation
* : When the power rising, VCC must be less than 0.2 V.
Notes: • The above standards are the values needed in order to activate a power-on reset.
• Activate a power-on reset by turning on the power supply again this in device.
• VCC = VCC1 = VCC2
tR
VCC
2.7 V
0.2 V
tOFF
Abrupt changes in the power supply voltage may cause a power-on reset.
When changing the power supply voltage during operation, suppress variations in the voltage and
ensure that the voltage rises smoothly, as shown in the following figure.
Main power supply voltage
VCC
Sub-power supply voltage
Holding RAM data
It is recommended that the rate of
increase in the voltage be kept to
no more than 50 mV/ms.
VSS
81
MB90650A Series
(5) Bus Read Timing
Parameter
Pin name
tCP /2 – 20
—
ns
MASK/FLASH
tCP / 2 – 35
—
ns
MB90P653A
tCP / 2 – 25
—
ns
MASK/FLASH
tCP / 2 – 40
—
ns
MB90P653A
—
tCP / 2 – 15
—
ns
Multiplexed
address
—
tCP – 15
—
ns
tAVDV
Multiplexed
address
—
—
5 tCP / 2 – 60
ns
MASK/FLASH
—
5 tCP / 2 – 80
ns
MB90P653A
RD pulse width
tRLRH
RD
—
3 tCP / 2 – 20
—
ns
RD ↓ → valid data input
tRLDV
D15 to D00
—
—
5 tCP / 2 – 60
ns
MASK/FLASH
—
5 tCP / 2 – 80
ns
MB90P653A
RD ↑ → data hold time
tRHDX
D15 to D00
—
0
—
ns
RD ↑ → ALE ↑ time
tRHLH
RD, ALE
—
tCP / 2 – 15
—
ns
RD ↑ → address valid time
tRHAX
Address,
RD
—
tCP / 2 – 10
—
ns
Valid address → CLK ↑ time tAVCH
Address,
CLK
—
tCP / 2 –20
—
ns
RD ↓ → CLK ↑ time
RD, CLK
—
tCP / 2 – 20
—
ns
ALE pulse width
tLHLL
ALE
—
Valid address → ALE ↓ time tAVLL
Multiplexed
address
—
ALE ↓ → address valid time
tLLAX
Multiplexed
address
Valid address → RD ↓ time
tAVRL
Valid address → valid data
input
tCP: See “(1) Clock Timing.”
Note: VCC = VCC1 = VCC2
82
Symbol
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
tRLCH
MB90650A Series
tAVCH
tRLCH
2.4 V
CLK
tAVLL
2.4 V
ALE
2.4 V
tRHLH
tLLAX
2.4 V
2.4 V
0.8 V
tLHLL
tAVRL
tRLRH
2.4 V
RD
0.8 V
tRHAX
A23 to
A16
2.4 V
0.8 V
2.4 V
0.8 V
tRLDV
tAVDV
D15 to
D00
2.4 V
0.8 V
Address
tRHDX
2.4 V
0.8 V
0.7 VCC
0.3 VCC
Read data
0.7 VCC
0.3 VCC
83
MB90650A Series
(6) Bus Write Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol Pin name Condition
Value
Min.
Max.
Unit
Remarks
Valid address → WR ↓ time tAVWL
A23 to A00
—
tCP – 15
—
ns
WR pulse width
tWLWH
WR
—
3 tCP / 2 – 20
—
ns
Valid data output → WR ↑
time
tDVWH
D15 to D00
—
3 tCP / 2 – 20
—
ns
WR ↑ → data hold time
tWHDX
D15 to D00
—
20
—
ns
MASK/FLASH
30
—
ns
MB90P653A
WR ↑ → address valid time tWHAX
A23 to A00
—
tCP / 2 – 10
—
ns
WR ↑ → ALE ↑ time
tWHLH
WR, ALE
—
tCP / 2 – 15
—
ns
WR ↓ → CLK ↑ time
tWLCH
WR, ALE
—
tCP / 2 – 20
—
ns
tCP: See “(1) Clock Timing.”
Note: VCC = VCC1 = VCC2
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR
(WRL, WRH)
0.8 V
tWHAX
A23 to
A16
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
D15 to
D00
84
2.4 V
0.8 V
2.4 V
Address
0.8 V
tWHDX
Write data
2.4 V
0.8 V
MB90650A Series
(7) Ready Input Timing
Parameter
Symbol
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Pin name
RDY setup time
tRYHS
RDY
RDY hold time
tRYHH
RDY
—
45
—
ns
MASK/FLASH
—
70
—
ns
MB90P653A
—
0
—
ns
Notes: • Use the auto-ready function if the RDY setup time is too short
• VCC = VCC1 = VCC2.
2.4 V
CLK
2.4 V
ALE
RD/WR
RDY (When
wait states are
not inserted)
RDY (When
one wait states
are inserted)
tRYHS
tRYHH
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tRYHS
85
MB90650A Series
(8) Hold Timing
Parameter
Symbol
Pin name
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Pin floating → HAK ↓ time
tXHAL
HAK
—
30
tCP
ns
HAK ↑ → pin valid time
tHAHV
HAK
—
tCP
2 tCP
ns
tCP: See “(1) Clock Timing.”
Notes: • After reading HRQ, more than one cycle is required before changing HAK.
• VCC = VCC1 = VCC 2
2.4 V
HAK
0.8 V
tHAHV
tXHAL
Pin
86
High impedance
MB90650A Series
(9) UART Timing
Parameter
Serial clock cycle time
Symbol
Pin
name
tSCYC
—
SCK ↓ → SOT delay time tSLOV
—
Valid SIN → SCK ↑
tIVSH
—
SCK ↑ → valid SIN hold
time
tSHIX
Serial clock “H” pulse
width
Serial clock “L” pulse
width
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
8 tCP
—
ns
–80
80
ns
MASK/FLASH
–120
120
ns
MB90P653A
100
—
ns
MASK/FLASH
200
—
ns
MB90P653A
—
tCP
—
ns
tSHSL
—
4 tCP
—
ns
tSLSH
—
4 tCP
—
ns
SCK ↓ → SOT delay time tSLOV
—
—
150
ns
MASK/FLASH
—
200
ns
MB90P653A
Valid SIN → SCK ↑
tIVSH
—
60
—
ns
MASK/FLASH
120
—
ns
MB90P653A
SCK ↑ → valid SIN hold
time
tSHIX
—
60
—
ns
MASK/FLASH
120
—
ns
MB90P653A
CL = 80 pF + 1 TTL
for the internal shift
clock mode output
pin
CL = 80 pF + 1 TTL
for the external
shift clock mode
output pin
Notes: • These are the AC characteristics for CLK synchronous mode.
• CL is the load capacitance connected to the pin at testing.
• tCP is the machine cycle period (unit: ns).
• VCC = VCC1 = VCC 2
87
MB90650A Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
tSLOV
0.8 V
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 VCC
0.2 VCC
SIN
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.2 VCC
tSLOV
SOT
0.2 VCC
2.4 V
0.8 V
tIVSH
SIN
88
0.8 VCC
0.8 VCC
SCK
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
MB90650A Series
(10) I/O Extended Serial Timing
Parameter
Serial clock cycle time
Pin
Symbol name
tSCYC
—
SCK ↓ → SOT delay time tSLOV
—
Valid SIN → SCK ↑
tIVSH
—
SCK ↑ → valid SIN hold
time
tSHIX
—
Serial clock “H” pulse
width
tSHSL
—
Serial clock “L” pulse
width
tSLSH
—
SCK ↓ → SOT delay time tSLOV
—
Valid SIN →SCK ↑
tIVSH
SCK ↑ → valid SIN hold
time
tSHIX
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
8 tCP
—
ns
—
80
ns
MASK/FLASH
—
160
ns
MB90P653A
tCP
—
ns
tCP
—
ns
230
—
ns
MASK/FLASH
460
—
ns
MB90P653A
230
—
ns
MASK/FLASH
460
—
ns
MB90P653A
2 tCP
—
ns
—
tCP
—
ns
—
2 tCP
—
ns
CL = 80 pF + 1 TTL
for the internal shift
clock mode output
pin
CL = 80 pF + 1 TTL
for the external
shift clock mode
output pin
Notes: • These are the AC characteristics for CLK synchronous mode.
• CL is the load capacitance connected to the pin at testing.
• tCP is the machine cycle period (unit: ns).
• The values in the table are target values.
• VCC = VCC1 = VCC 2
89
MB90650A Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
tSLOV
0.8 V
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 VCC
0.2 VCC
SIN
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
SCK
0.2 VCC
tSLOV
SOT
0.2 VCC
2.4 V
0.8 V
tIVSH
SIN
90
0.8 VCC
0.8 V CC
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
MB90650A Series
(11) I2C Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Pin name
Condition
fSCL
—
Bus free time between stop
tBUS
and start conditions
—
Parameter
SCL clock frequency
Value
Unit
Min.
Max.
—
0
100
kHz
—
4.7
—
µs
—
—
4.0
—
µs
SCL clock L state hold time tLOW
—
—
4.7
—
µs
SCL clock H state hold
time
tHIGH
—
—
4.0
—
µs
Re-send start condition
setup time
tSUSTA
—
—
4.7
—
µs
Data hold time
tHDDAT
—
—
0
—
µs
Data setup time
tSUDAT
—
—
40
—
ns
SDA and SCL signal rising
tR
time
—
—
—
1000
ns
SDA and SCL signal falling
tF
time
—
—
—
300
ns
Stop condition setup time
—
—
4.0
—
µs
Hold time (re-send) start
tHDSTA
tSUSTO
Remarks
The first clock
pulse is
generated after
this period.
Note: VCC = VCC1 = VCC2
0.8 VCC
SDA
0.2 VCC
tBUS
tLOW
tR
tHDSTA
tF
0.8 VCC
SCL
0.2 VCC
tHDSTA tHDDAT
tHIGH
tSUDAT
tSUSTA
tSUSTO
91
MB90650A Series
5. A/D Converter Electrical Characteristics
(MB90652A/653A/654A: VCC = 2.2 V to 3.3V, VSS = AVSS =0.0V, 2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C)
(MB90F654A: VCC = 2.4 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C)
(MB90P653A: VCC = 2.7 V to 3.3 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C)
Value
Symbol
Pin name
Unit
Remarks
Parameter
Min.
Typ.
Max.
Resolution
—
—
—
10
10
bit
Total error
—
—
—
—
±3.0
LSB
Linearity error
—
—
—
—
±2.0
LSB
Differential
linearity error
—
—
—
—
±1.9
LSB
MASK/FLASH
—
—
±1.5
LSB
MB90P653A
Zero transition
voltage
VOT
AN0 to AN7
AVRL
– 1.5 LSB
AVRL
+ 0.5 LSB
AVRL
+ 2.5 LSB
mV
Full scale
transition voltage
VFST
AN0 to AN7
AVRH
– 4.5 LSB
AVRH
– 1.5 LSB
AVRH
+ 0.5 LSB
mV
6.125*1
—
—
µs
MASK/FLASH
*2
12.25
—
—
µs
MB90P653A
Conversion time
—
—
Analog port input
current
IAIN
AN0 to AN7
—
0.1
10
µA
Analog input
voltage
VAIN
AN0 to AN7
AVRL
—
AVRH
V
AVRH
AVRL + 2.7
—
AVCC
V
AVRL
0
—
AVRH –
2.7
V
—
mA
*3
Reference voltage
—
Power supply
current
IA
AVCC
—
3
IAH
AVCC
—
—
5
µA
Reference voltage
supply current
IR
AVRH
—
200
—
µA
IRH
AVRH
—
—
*3
5
µA
AN0 to AN7
—
—
4
LSB
Variation between
channels
—
*1: For a 16 MHz machine clock
*2: For an 8 MHz machine clock
*3: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = 3.0 V).
Notes: • The error increases proportionally as |AVRH – AVRL| decreases.
• The output impedance of the external circuits connected to the analog inputs should be in the following
range.
The output impedance of the external circuit should be less than approximately 7 kΩ.
When using an external capacitor, it is recommended to have several thousand times the capacitance of
the internal capacitor as a guid, if one takes into consideration the effect of the divided capacitance between
the external capacitor and the internal capacitor.
• If the output impedance of the external circuit is too high, the sampling time might be insufficient (sampling
time = 3.75 µs at a machine clock of 16 MHz).
• VCC = VCC1 = VCC2
(Continued)
92
MB90650A Series
(Continued)
• Analog input circuit model diagram
Sample hold circuit
C0
Analog input
Comparator
RON1
RON2
RON3
RON4
C1
RON1 :
RON2 :
RON3 :
RON4 :
Approx. 5 kΩ
Approx. 617 Ω
Approx. 617 Ω
Approx. 473 Ω
C0 : Approx. 35 pF
C1 : Approx. 2 pF
Note: Use the values shown as guids only.
93
MB90650A Series
6. D/A Converter Electrical Characteristics
(MB90652A/653A : VCC = 2.2 V to 3.3 V, VSS = DVSS = 0.0 V, 2.2 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
(MB90F654A : VCC = 2.4 V to 3.6 V, VSS = DVSS = 0.0 V, 2.4 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
(MB90P653A : VCC = 2.7 V to 3.3 V, VSS = DVSS = 0.0 V, 2.7 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
Pin
name
Min.
Typ.
Max.
Resolution
—
—
—
8
8
bit
Differential
linearity error
—
—
—
—
±0.9
LSB
Absolute
accuracy
—
—
—
—
1
%
Linearity error
—
—
—
—
±1.5
LSB
Conversion time
—
—
—
10.0
20.0
µs
2.2
—
VCC
V
MB90652A/653A/654A*2
2.4
—
VCC
V
MB90F654A
*2
2.7
—
VCC
V
MB90P653A
*2
—
100
—
µA
*3
—
—
5
µA
*4
—
28
—
kΩ
Analog
reference power
supply voltage
Reference
voltage supply
current
Analog output
impedance
*1:
*2:
*3:
*4:
—
DVRH
IDVR
IDVRS
—
DVRH
—
Conversion time is the value at the load capacitance = 20 pF.
DVRH – DVSS (AVSS)
Current value at conversion
Current value when stopped
Note: VCC = VCC1 = VCC2
94
Value
Symbol
Parameter
Unit
Remarks
*1
MB90650A Series
7. DTMF Electrical characteristics
(MB90652A/653A : VCC = 2.2 V to 3.3 V, VSS = DVSS = 0.0 V, 2.2 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
(MB90F654A : VCC = 2.4 V to 3.6 V, VSS = DVSS = 0.0 V, 2.4 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
(MB90P653A : VCC = 2.7 V to 3.3 V, VSS = DVSS = 0.0 V, 2.7 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min.
Typ. Max.
Output load
condition
DTMF output
offset voltage
(At signal output)
RO
30 k
—
—
Ω
VMOF
—
0.4
—
V
450
530
600
mVP-P
VCC = 3 V
TA = 25°C
Machine clock
f = 16 MHz
DTMF output
amplitude
(COL single tone)
VMFC
DTMF output
amplitude
(ROW single tone)
VMFOR
330
440
500
mVP-P
RMF
1.6
2.0
2.4
dB
COL/ROW level
difference
To be specified with DTMF
pin pull-down resistor
When DTMF terminal is
opened
RO = 200 kΩ
Note: VCC =VCC1 = VCC2
• Output level measurement circuit
VCC
X0
Low-pass filter
16MHz
DTMF
X1
Audio
Output level
Analizer
−48 dB / oct
VSS
RO
95
MB90650A Series
■ EXAMPLE CHARACTERISTICS
(1) “H” Level Output Voltage
(2) “L” Level Output Voltage
VOL vs. IOL
VOH vs. IOH
VOL (V)
1.0
TA = +25°C
0.9
VOH (V)
4.0
TA = +25°C
3.5
VCC = 3.6 V
3.0
VCC = 3.3 V
VCC = 3.0 V
2.5
VCC = 2.7 V
VCC = 2.5 V
VCC = 2.4 V
2.0
0.8
VCC = 2.4 V
0.7
VCC = 2.5 V
VCC = 2.7 V
0.6
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
0.5
0.4
1.5
0.3
1.0
0.2
0.5
0.1
0.0
0.0
–1
–2
–3
–4
1
–5
IOH (mA)
(3) “H” Level Input Voltage/“L” Level Input Voltage
(COMS Input)
2
3
4
5
IOL (mA)
(4) “H” Level Input Voltage/“L” Level Input Voltage
(Hysteresis Input)
VIN vs. VCC
VIN vs. VCC
VIN (V)
2.4
VIN (V)
2.4
TA = +25°C
TA = +25°C
2.2
2.2
2.0
VIH
VIL
1.8
VIHS
2.0
1.8
1.6
1.6
1.4
1.4
1.2
1.2
1.0
1.0
0.8
0.8
0.6
0.6
VILS
0.4
0.4
2.4
2.7
3.0
3.3
3.6
VCC (V)
VIH:
Threshold when input voltage is set to “H” level
VIL:
Threshold when input voltage is set to “L” level
2.4
2.7
3.0
3.3
3.6
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
96
MB90650A Series
(5) Power Supply Current (fCP = Internal Operating Clock Frequency)
• Mask ROM products
ICC vs. VCC
ICC (mA)
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
2.4
ICCS vs. VCC
ICCS (mA)
10
TA = +25°C
fCP = 16 MHZ
TA = +25°C
9
8
7
fCP = 16 MHZ
6
fCP = 10 MHZ
fCP = 8 MHZ
fCP = 5 MHZ
5
4
fCP = 10 MHZ
3
fCP = 8 MHZ
2
fCP = 5 MHZ
1
2.7
3
3.3
3.6
VCC (V)
0
2.4
2.7
ICCH vs. VCC
3.6
VCC (V)
ICCL (µA)
50
TA = +25°C
0.45
40
0.35
35
0.30
30
0.25
25
0.20
20
0.15
15
0.10
10
0.05
5
2.7
3
3.3
3.6
VCC (V)
TA = +25°C
45
0.40
0
2.4
2.7
IA vs. AVCC
3
3.3
3.6
VCC (V)
IR vs. AVCC
IA (mA)
4.0
IR (mA)
4.0
TA = +25°C
TA = +25°C
3.5
3.5
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
2.4
3.3
ICCL vs. VCC
ICCH (µA)
0.50
0.00
2.4
3
2.7
3
3.3
3.6
AVCC (V)
0.0
2.4
2.7
3
3.3
3.6
AVCC (V)
97
MB90650A Series
• OTPROM products
ICC vs. VCC
ICCS vs. VCC
ICC (mA)
60
TA = +25°C
55
50
fCP = 16 MHZ
45
40
35
fCP = 10 MHZ
30
fCP = 8 MHZ
25
20
fCP = 5 MHZ
15
10
5
0
2.4
2.7
3
3.3
3.6
VCC (V)
ICCS (mA)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2.4
TA = +25°C
fCP = 16 MHZ
fCP = 10 MHZ
fCP = 8 MHZ
fCP = 5 MHZ
2.7
ICCH vs. VCC
ICCH (µA)
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.4
98
3
3.3
3.6
VCC (V)
ICCL vs. VCC
ICCL (mA)
10
TA = +25°C
TA = +25°C
9
8
7
6
5
4
3
2
1
0
2.7
3
3.3
3.6
VCC (V)
2.4
2.7
3
3.3
3.6
VCC (V)
MB90650A Series
• FLAH products
ICC vs. VCC
ICC (mA)
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
2.4
ICCS vs. VCC
TA = +25 °C
ICCS (mA)
10
fCP = 16 MHZ
TA = +25 °C
9
7
fCP = 10 MHZ
6
fCP = 10 MHZ
fCP = 8 MHZ
5
fCP = 8 MHZ
4
fCP = 5 MHZ
fCP = 5 MHZ
3
2
1
2.7
3
3.3
3.6
VCC (V)
0
2.4
2.7
ICCH vs. VCC
ICCH (µA)
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
2.4
fCP = 16 MHZ
8
3
3.3
3.6
VCC (V)
ICCL vs. VCC
TA = +25 °C
ICCL (µA)
50
TA = +25 °C
45
40
35
30
25
20
15
10
5
2.7
3
3.3
3.6
VCC (V)
0
2.4
2.7
3
3.3
3.6
VCC (V)
99
MB90650A Series
(6) Pull-up Resistance
• OTPROM products
• Mask ROM products
R vs. VCC
R vs. VCC
R (kΩ)
1000
R (kΩ)
1000
TA = +25°C
TA = +25°C
100
100
10
2.4
2.7
3
3.3
3.6
VCC (V)
• FLASH products
R vs. VCC
R (kΩ)
1000
TA = +25 °C
100
10
2.4
2.7
3
3.3
3.6
VCC (V)
100
10
2.4
2.7
3
3.3
3.6
VCC (V)
MB90650A Series
■ INSTRUCTIONS (340 INSTRUCTIONS)
Table 1
Explanation of Items in Tables of Instructions
Item
Mnemonic
Meaning
Upper-case letters and symbols: Represented as they appear in assembler.
Lower-case letters:
Replaced when described in assembler.
Numbers after lower-case letters: Indicate the bit width within the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
m : When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
RG
B
Operation
Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the “~” column.
Indicates the operation of instruction.
LH
Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers “0”.
X : Extends with a sign before transferring.
– : Transfers nothing.
AH
Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
– : No transfer.
Z : Transfers 00H to AH.
X : Transfers 00H or FFH to AH by signing and extending AL.
I
S
T
N
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
– : No change.
S : Set by execution of instruction.
R : Reset by execution of instruction.
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
– : Instruction is not a read-modify-write instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
101
MB90650A Series
Table 2
Explanation of Symbols in Tables of Instructions
Symbol
A
Meaning
32-bit accumulator
The bit length varies according to the instruction.
Byte : Lower 8 bits of AL
Word : 16 bits of AL
Long : 32 bits of AL:AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Compact direct addressing
addr16
addr24
ad24 0 to 15
ad24 16 to 23
Direct addressing
Physical direct addressing
Bit 0 to bit 15 of addr24
Bit 16 to bit 23 of addr24
io
imm4
imm8
imm16
imm32
ext (imm8)
disp8
disp16
bp
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
(Continued)
102
MB90650A Series
(Continued)
Symbol
Meaning
rel
Branch specification relative to PC
ear
eam
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
Register list
Table 3
Code
00
01
02
03
04
05
06
07
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Effective Address Fields
Address format
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Number of bytes in address
extension *
Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the
left
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
—
0
0
1
2
0
0
2
2
Note: The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)
column in the tables of instructions.
103
MB90650A Series
Table 4
Number of Execution Cycles for Each Type of Addressing
(a)
Code
Operand
Number of execution cycles
for each type of addressing
Number of register
accesses for each type of
addressing
Listed in tables of instructions
Listed in tables of instructions
00 to 07
Ri
RWi
RLi
08 to 0B
@RWj
2
1
0C to 0F
@RWj +
4
2
10 to 17
@RWi + disp8
2
1
18 to 1B
@RWj + disp16
2
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5
Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
(b) byte
Operand
(c) word
(d) long
Number
of cycles
Number
of access
Number
of cycles
Number
of access
Number
of cycles
Number
of access
Internal register
+0
1
+0
1
+0
2
Internal memory even address
Internal memory odd address
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
+1
1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+1
1
+4
2
+8
4
Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6
Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
—
+2
External data bus (16 bits)
—
+3
External data bus (8 bits)
+3
—
Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
• Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
104
MB90650A Series
Table 7
Mnemonic
#
~
Transfer Instructions (Byte) [41 Instructions]
RG
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
A, #imm4
2
3
3
4
1
2
2
2
2+ 3+ (a)
2
3
2
2
2
3
3
10
1
1
0
0
1
1
0
0
0
0
2
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– *
– *
– *
– *
– *
– *
– *
– *
– *
– R
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
A, dir
2
3
A, addr16
3
4
A, Ri
2
2
A, ear
2
2
A, eam
2+ 3+ (a)
A, io
2
3
A, #imm8
2
2
A, @A
2
3
A,@RWi+disp8 2
5
A, @RLi+disp8 3
10
0
0
1
1
0
0
0
0
1
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
X
X
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi) +disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
2
4
2+ 5+ (a)
2
7
2+ 9+ (a)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
4
2
2
3+ (a)
3
10
3
4+ (a)
4
5+ (a)
2
5
5
2
4+ (a)
3
2
0
0 2× (b)
4
0
2 2× (b)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
105
MB90650A Series
Table 8
Mnemonic
#
Transfer Instructions (Word/Long Word) [38 Instructions]
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
A, dir
A, addr16
A, SP
A, RWi
A, ear
A, eam
A, io
A, @A
A, #imm16
A, @RWi+disp8
A, @RLi+disp8
2
3
3
4
1
1
1
2
2
2
2+ 3+ (a)
2
3
2
3
3
2
2
5
3
10
0
0
0
1
1
0
0
0
0
1
2
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
–
–
–
–
–
–
–
–
–
word (A) ← ((RWi) +disp8) –
word (A) ← ((RLi) +disp8) –
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
dir, A
addr16, A
SP, A
RWi, A
ear, A
eam, A
io, A
@RWi+disp8, A
@RLi+disp8, A
RWi, ear
RWi, eam
ear, RWi
eam, RWi
RWi, #imm16
io, #imm16
ear, #imm16
eam, #imm16
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
3
4
1
2
2
3+ (a)
3
5
10
3
4+ (a)
4
5+ (a)
2
5
2
4+ (a)
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
(0)
(c)
0
(c)
0
(c)
0
(c)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
–
–
–
–
–
–
–
word ((RWi) +disp8) ← (A) –
word ((RLi) +disp8) ← (A) –
word (RWi) ← (ear)
–
word (RWi) ← (eam)
–
word (ear) ← (RWi)
–
word (eam) ← (RWi)
–
word (RWi) ← imm16
–
word (io) ← imm16
–
word (ear) ← imm16
–
word (eam) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW @AL, AH
2
3
0
(c)
word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
XCHW
XCHW
XCHW
XCHW
2
4
2+ 5+ (a)
2
7
2+ 9+ (a)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A, ear
A, eam
RWi, ear
RWi, eam
2
0
0 2× (c)
4
0
2 2× (c)
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
2
4
2
2+ 5+ (a) 0
5
3
0
0
(d)
0
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
MOVL ear, A
MOVL eam, A
2
4
2
2+ 5+ (a) 0
0
(d)
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
106
MB90650A Series
Table 9
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
Mnemonic
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
ADDW A
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
#
~
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
A, ear
2
6
A, eam
2+ 7+ (a)
A, #imm32 5
4
A, ear
2
6
A, eam
2+ 7+ (a)
A, #imm32 5
4
RG
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
0
0
byte (A) ← (A) +imm8
0
(b) byte (A) ← (A) +(dir)
1
0
byte (A) ← (A) +(ear)
0
(b) byte (A) ← (A) +(eam)
2
0
byte (ear) ← (ear) + (A)
0 2× (b) byte (eam) ← (eam) + (A)
0
0
byte (A) ← (AH) + (AL) + (C)
1
0
byte (A) ← (A) + (ear) + (C)
0
(b) byte (A) ← (A) + (eam) + (C)
byte (A) ← (AH) + (AL) + (C) (decimal)
0
0
0
0
byte (A) ← (A) –imm8
0
(b) byte (A) ← (A) – (dir)
1
0
byte (A) ← (A) – (ear)
0
(b) byte (A) ← (A) – (eam)
2
0
byte (ear) ← (ear) – (A)
0 2× (b) byte (eam) ← (eam) – (A)
0
0
byte (A) ← (AH) – (AL) – (C)
1
0
byte (A) ← (A) – (ear) – (C)
0
(b) byte (A) ← (A) – (eam) – (C)
byte (A) ← (AH) – (AL) – (C) (decimal)
0
0
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
0
0
word (A) ← (AH) + (AL)
1
0
word (A) ← (A) +(ear)
0
(c) word (A) ← (A) +(eam)
0
0
word (A) ← (A) +imm16
2
0
word (ear) ← (ear) + (A)
0 2× (c) word (eam) ← (eam) + (A)
1
0
word (A) ← (A) + (ear) + (C)
0
(c) word (A) ← (A) + (eam) + (C)
0
0
word (A) ← (AH) – (AL)
1
0
word (A) ← (A) – (ear)
0
(c) word (A) ← (A) – (eam)
0
0
word (A) ← (A) –imm16
2
0
word (ear) ← (ear) – (A)
0 2× (c) word (eam) ← (eam) – (A)
1
0
word (A) ← (A) – (ear) – (C)
0
(c) word (A) ← (A) – (eam) – (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
2
0
0
2
0
0
0
(d)
0
0
(d)
0
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) +imm32
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) –imm32
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
107
MB90650A Series
Table 10
Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
Mnemonic
#
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
INC
INC
ear
eam
2
2
2
0
byte (ear) ← (ear) +1
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DEC
DEC
ear
eam
2
3
2
0
byte (ear) ← (ear) –1
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCW
INCW
ear
eam
2
3
2
0
word (ear) ← (ear) +1
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECW ear
DECW eam
2
3
2
0
word (ear) ← (ear) –1
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCL
INCL
ear
eam
2
7
4
0
long (ear) ← (ear) +1
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECL
DECL
ear
eam
2
7
4
0
long (ear) ← (ear) –1
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11
Mnemonic
#
Compare Instructions (Byte/Word/Long Word) [11 Instructions]
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
1
2
2
2+ 3+ (a)
2
2
0
1
0
0
0
0
(b)
0
byte (AH) – (AL)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
A, ear
A, eam
A, #imm16
1
1
2
2
2+ 3+ (a)
3
2
0
1
0
0
0
0
(c)
0
word (AH) – (AL)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL
CMPL
CMPL
A, ear
A, eam
A, #imm32
2
6
2
2+ 7+ (a) 0
5
3
0
0
(d)
0
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
108
MB90650A Series
Table 12
Mnemonic
Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
#
~
1
RG
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
DIVU
A
1
*
0
0 word (AH) /byte (AL)
–
–
–
–
–
–
–
*
*
–
DIVU
A, ear
2
*2
1
0 word (A)/byte (ear)
–
–
–
–
–
–
–
*
*
–
DIVU
A, eam 2+ *3
0
*6 word (A)/byte (eam)
–
–
–
–
–
–
–
*
*
–
*4
1
0 long (A)/word (ear)
–
–
–
–
–
–
–
*
*
–
DIVUW A, eam 2+ *5
0
*7 long (A)/word (eam)
–
–
–
–
–
–
–
*
*
–
MULU
MULU
MULU
0 0 byte (AH) *byte (AL) → word (A)
1 0 byte (A) *byte (ear) → word (A)
0 (b) byte (A) *byte (eam) → word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0 0 word (AH) *word (AL) → long (A)
1 0 word (A) *word (ear) → long (A)
0 (c) word (A) *word (eam) → long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DIVUW A, ear
2
A
1 *8
A, ear
2 *9
A, eam 2+ *10
MULUW A
1 *11
MULUW A, ear
2 *12
MULUW A, eam 2+ *13
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
*10:
*11:
*12:
*13:
Quotient → byte (AL) Remainder → byte (AH)
Quotient → byte (A) Remainder → byte (ear)
Quotient → byte (A) Remainder → byte (eam)
Quotient → word (A) Remainder → word (ear)
Quotient → word (A) Remainder → word (ear)
3 when the result is zero, 7 when an overflow occurs, and 15 normally.
4 when the result is zero, 8 when an overflow occurs, and 16 normally.
6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.
4 when the result is zero, 7 when an overflow occurs, and 22 normally.
6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.
(b) when the result is zero or when an overflow occurs, and 2 × (b) normally.
(c) when the result is zero or when an overflow occurs, and 2 × (c) normally.
3 when byte (AH) is zero, and 7 when byte (AH) is not zero.
4 when byte (ear) is zero, and 8 when byte (ear) is not zero.
5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.
3 when word (AH) is zero, and 11 when word (AH) is not zero.
4 when word (ear) is zero, and 12 when word (ear) is not zero.
5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
109
MB90650A Series
Table 13
Mnemonic
#
~
Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
0
1
0
0
(b)
2
0
0 2× (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
0
1
0
0
(b)
2
0
0 2× (b)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
XOR
XOR
XOR
XOR
XOR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
0
1
0
0
(b)
2
0
0 2× (b)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
NOT
NOT
NOT
A
ear
eam
1
2
0
0
byte (A) ← not (A)
2
3
2
0
byte (ear) ← not (ear)
2+ 5+ (a) 0 2× (b) byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
0
0
1
0
0
(c)
2
0
0 2× (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ORW
ORW
ORW
ORW
ORW
ORW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
0
0
1
0
0
(c)
2
0
0 2× (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
XORW
XORW
XORW
XORW
XORW
XORW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
0
0
1
0
0
(c)
2
0
0 2× (c)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
NOTW A
NOTW ear
NOTW eam
1
2
0
0
word (A) ← not (A)
2
3
2
0
word (ear) ← not (ear)
2+ 5+ (a) 0 2× (c) word (eam) ← not (eam)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
110
MB90650A Series
Table 14
Mnemonic
#
Logical 2 Instructions (Long Word) [6 Instructions]
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
ANDL A, ear
ANDL A, eam
2
6
2
2+ 7+ (a) 0
0
(d)
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
ORL
ORL
A, ear
A, eam
2
6
2
2+ 7+ (a) 0
0
(d)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
XORL A, ea
XORL A, eam
2
6
2
2+ 7+ (a) 0
0
(d)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
Table 15
Mnemonic
Sign Inversion Instructions (Byte/Word) [6 Instructions]
#
~
RG
B
Operation
2
0
0
byte (A) ← 0 – (A)
NEG
A
1
NEG
NEG
ear
eam
2
3
2
0
byte (ear) ← 0 – (ear)
2+ 5+ (a) 0 2× (b) byte (eam) ← 0 – (eam)
2
0
1
NEGW ear
NEGW eam
2
3
2
0
word (ear) ← 0 – (ear)
2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam)
Table 16
Mnemonic
#
~
NRML A, R0
2
1
*
RG
B
1
0
0
word (A) ← 0 – (A)
NEGW A
LH AH
I
S
T
N
Z
V
C
RMW
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
Normalize Instruction (Long Word) [1 Instruction]
Operation
LH AH
long (A) ← Shift until first digit is “1” –
byte (R0) ← Current shift count
–
I
S
T
N
Z
V
C
RMW
–
–
–
–
*
–
–
–
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
111
MB90650A Series
Table 17
Mnemonic
RORC A
ROLC A
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
#
~
RG
B
2
2
2
2
0
0
0
0
Operation
LH AH
I
S
T
N
Z
V
C RMW
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
2
3
2+ 5+ (a)
2
3
2+ 5+ (a)
2
0
0 2× (b)
2
0
0 2× (b)
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
–
*
–
*
2
2
2
*1
*1
*1
1
1
1
0
0
0
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A
1
LSRW A/SHRW A 1
LSLW A/SHLW A 1
2
2
2
0
0
0
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
–
–
–
–
–
–
–
–
–
–
–
–
* *
* R
– *
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
*1
*1
*1
1
1
1
0
0
0
word (A) ← Arithmetic right barrel shift (A, R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*2
*2
*2
1
1
1
0
0
0
long (A) ← Arithmetic right shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
RORC ear
RORC eam
ROLC ear
ROLC eam
ASR
LSR
LSL
A, R0
A, R0
A, R0
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
112
MB90650A Series
Table 18
Mnemonic
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
rel
rel
rel
rel
#
~
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
Branch 1 Instructions [31 Instructions]
RG
B
Operation
*
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
0
0
0
(c)
0
(d)
0
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
1
3
2
2+
2
2+
4
2
3
3
4+ (a)
5
6+ (a)
4
0
0
1
0
2
0
0
CALL
CALL
CALL
CALLV
CALLP
@ear *4
@eam *4
addr16 *5
#vct4 *5
@ear *6
2
2+
3
1
2
6
7+ (a)
6
7
10
1
(c)
0 2× (c)
0
(c)
0 2× (c)
2 2× (c)
CALLP @eam *6
2+ 11+ (a)
0
CALLP addr24 *7
4
0 2× (c)
*1:
*2:
*3:
*4:
*5:
*6:
*7:
10
*2
Branch when ((V) xor (N)) or (Z) = 1
Branch when ((V) xor (N)) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ← (ear +2)
word (PC) ← (eam), (PCB) ← (eam +2)
word (PC) ← ad24 0 to 15,
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call instruction
word (PC) ← (ear) 0 to 15,
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15,
(PCB) ← (eam) 16 to 23
word (PC) ← addr0 to 15,
(PCB) ← addr16 to 23
LH AH
I
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4 when branching, 3 when not branching.
(b) + 3 × (c)
Read (word) branch address.
W: Save (word) to stack; R: read (word) branch address.
Save (word) to stack.
W: Save (long word) to W stack; R: read (long word) R branch address.
Save (long word) to stack.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
113
MB90650A Series
Table 19
Mnemonic
#
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
CBNE
~ RG
Branch 2 Instructions [19 Instructions]
B
1
3 *
4 *1
0
0
0
0
*2
*3
*4
*3
1
0
1
0
0
(b)
0
(c)
2
0
ear, #imm8, rel
4
CBNE
eam, #imm8, rel* 4+
CWBNE ear, #imm16, rel 5
CWBNE eam, #imm16, rel*9 5+
9
Operation
I
S
T
N
Z
V
C RMW
Branch when byte (A) ≠ imm8
–
Branch when word (A) ≠ imm16 –
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Branch when byte (ear) ≠ imm8
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
S
S
S
S
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
At constant entry, save old
–
frame pointer to stack, set
new frame pointer, and
allocate local pointer area
At constant entry, retrieve
–
old frame pointer from stack.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Return from subroutine
Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DBNZ
ear, rel
3 *5
DBNZ
eam, rel
3+ *6
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
2 2× (b) Branch when byte (eam) =
(eam) – 1, and (eam) ≠ 0
DWBNZ ear, rel
3 *5
2
DWBNZ eam, rel
3+ *6
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
2
3
4
1
1
20
16
17
20
15
0
0
0
0
0
8× (c)
6× (c)
6× (c)
8× (c)
6× (c)
LINK
#local8
2
6
0
(c)
UNLINK
1
5
0
(c)
RET *7
RETP *8
1
1
4
6
0
0
(c)
(d)
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
LH AH
0
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
2 2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
–
–
5 when branching, 4 when not branching
13 when branching, 12 when not branching
7 + (a) when branching, 6 + (a) when not branching
8 when branching, 7 when not branching
7 when branching, 6 when not branching
8 + (a) when branching, 7 + (a) when not branching
Retrieve (word) from stack
Retrieve (long word) from stack
In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
114
MB90650A Series
Table 20
Mnemonic
Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
#
~
RG
B
Operation
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
1
1
1
2
4
4
4
*3
0
0
0
*5
(c)
(c)
(c)
*4
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
–
–
–
–
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
4
*2
0
0
0
*5
(c)
(c)
(c)
*4
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)), (SP) ← (SP) +2n
JCTX
@A
1
14
0 6× (c) Context switch instruction
AND CCR, #imm8
OR CCR, #imm8
2
2
3
3
0
0
MOV RP, #imm8
MOV ILM, #imm8
2
2
2
2
I
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
0
0
byte (CCR) ← (CCR) and imm8 –
byte (CCR) ← (CCR) or imm8 –
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
0
0
0
0
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVEA RWi, ear
2
3
MOVEA RWi, eam 2+ 2+ (a)
MOVEA A, ear
2
1
MOVEA A, eam
2+ 1+ (a)
1
1
0
0
0
0
0
0
word (RWi) ←ear
word (RWi) ←eam
word(A) ←ear
word (A) ←eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
2
3
3
3
0
0
0
0
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
2
2
*1
1
0
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
Z
–
*
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No operation
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
A, brgl
brg2, A
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
LH AH
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR
: 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
115
MB90650A Series
Table 21
Mnemonic
Bit Manipulation Instructions [21 Instructions]
#
~
RG
B
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
5
5
4
0
0
0
(b)
(b)
(b)
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
7
7
6
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
BBC
BBC
BBC
BBS
BBS
BBS
Operation
LH AH
I
S
T
N
Z
V
C RMW
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
0 2× (b) bit (dir:bp) b ← (A)
0 2× (b) bit (addr16:bp) b ← (A)
0 2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
7
7
7
0 2× (b) bit (dir:bp) b ← 1
0 2× (b) bit (addr16:bp) b ← 1
0 2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
3
4
3
7
7
7
0 2× (b) bit (dir:bp) b ← 0
0 2× (b) bit (addr16:bp) b ← 0
0 2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 0
Branch when (addr16:bp) b = 0
Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 1
Branch when (addr16:bp) b = 1
Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
SBBS addr16:bp, rel
5
*3
0 2× (b)
Branch when (addr16:bp) b = 1, bit = 1
–
–
–
–
–
–
*
–
–
*
WBTS io:bp
3
*4
0
*5
Wait until (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
WBTC io:bp
3
*4
0
*5
Wait until (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
*1:
*2:
*3:
*4:
*5:
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
8 when branching, 7 when not branching
7 when branching, 6 when not branching
10 when condition is satisfied, 9 when not satisfied
Undefined count
Until condition is satisfied
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
116
MB90650A Series
Table 22
Mnemonic
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
#
~ RG B
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Table 23
RG B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
–
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
byte (A) 0 to 7 ↔ (A) 8 to 15
word (AH) ↔ (AL)
byte sign extension
word sign extension
byte zero extension
word zero extension
–
*
–
X
–
Z
String Instructions [10 Instructions]
Operation
Mnemonic
#
~
MOVS/MOVSI
MOVSD
2
2
2
*
*2
5
*
*5
*
*3
Byte transfer @AH+ ← @AL+, counter = RW0
Byte transfer @AH– ← @AL–, counter = RW0
–
–
SCEQ/SCEQI
SCEQD
2
2
*1
*1
*5
*5
*4
*4
Byte retrieval (@AH+) – AL, counter = RW0
Byte retrieval (@AH–) – AL, counter = RW0
FISL/FILSI
2 6m +6 *5
*3
3
LH AH
I
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Byte filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSW/MOVSWI 2
MOVSWD
2
*2
*2
*8
*8
*6
*6
Word transfer @AH+ ← @AL+, counter = RW0
Word transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCWEQ/SCWEQI 2
SCWEQD
2
*1
*1
*8
*8
*7
*7
Word retrieval (@AH+) – AL, counter = RW0
Word retrieval (@AH–) – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
2 6m +6 *8
*6
Word filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
FILSW/FILSWI
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case
*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately
for each.
*4: (b) × n
*5: 2 × (RW0)
*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately
for each.
*7: (c) × n
*8: 2 × (RW0)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
117
MB90650A Series
■ ORDERING INFORMATION
Model
118
Package
MB90652APFV
MB90653APFV
MB90P653APFV
MB90654APFV
MB90F654APFV
100-pin plastic LQFP
(FPT-100P-M05)
MB90652APF
MB90653APF
MB90P653APF
MB90654APF
MB90F654APF
100-pin plastic QFP
(FPT-100P-M06)
Remarks
MB90650A Series
■ PACKAGE DIMENSIONS
100-pin plastic LQFP
(FPT-100P-M05)
+0.20
16.00±0.20(.630±.008)SQ
75
1.50 –0.10
+.008
76
(Mouting height)
.059 –.004
51
14.00±0.10(.551±.004)SQ
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
100
0.15(.006)
26
0.15(.006)MAX
LEAD No.
1
"B"
25
0.40(.016)MAX
"A"
+0.08
0.50(.0197)TYP
0.18 –0.03
+.003
.007 –.001
+0.05
0.08(.003)
0.127 –0.02
M
Details of "B" part
+.002
.005 –.001
0.10±0.10
(STAND OFF)
(.004±.004)
0.50±0.20(.020±.008)
0.10(.004)
C
0~10°
Dimensions in mm (inches)
1995 FUJITSU LIMITED F100007S-2C-3
100-pin plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
3.35(.132)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
20.00±0.20(.787±.008)
80
51
81
50
14.00±0.20
(.551±.008)
12.35(.486)
REF
17.90±0.40
(.705±.016)
16.30±0.40
(.642±.016)
INDEX
31
100
"A"
LEAD No.
1
30
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.13(.005)
0.15±0.05(.006±.002)
M
Details of "A" part
0.25(.010)
Details of "B" part
"B"
0.10(.004)
18.85(.742)REF
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F100008-3C-2
0.30(.012)
0.18(.007)MAX
0.53(.021)MAX
0
10°
0.80±0.20
(.031±.008)
Dimensions in mm (inches)
119
MB90650A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9910
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
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