FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13745-1E
16-bit Microcontroller
CMOS
F2MC-16LX MB90925 Series
MB90F927/F927S/V925-101/V925-102
■ DESCRIPTION
MB90925 series is a 16-bit general-purpose high-capacity microcontroller designed for vehicle meter control
applications etc.
The instruction set retains the same AT architecture as F2MC-8L and F2MC-16L series, with further refinements
including high-level language instructions, expanded addressing mode, enhanced signed multiplication and
division computation and bit processing.
In addition, a 32-bit accumulator is built in to enable long word processing.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Clock
Built-in PLL clock frequency multiplication circuit.
Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and
multiplication of 1 to 4 times of oscillation clock(for 4 MHz oscillation clock, 4 MHz to 16 MHz).
Operation by sub clock(up to 50 kHz : 100 kHz oscillation clock divided by 2).
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2007 FUJITSU LIMITED All rights reserved
MB90925 Series
• 16-bit input capture (4 channels)
Detects rising, falling, or both edges.
16-bit capture register × 4
Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.
• 16-bit reload timer (2 channels)
16-bit reload timer operation (select toggle output or one-shot output)
Event count function selection provided
• Real Time watch timer (main clock)
Operates directly from oscillator clock.
Interrupt can be generated by second/minute/hour/date counter overflow.
• 16-bit PPG (3 channels)
Output pins (3 channels) , external trigger input pin (1 channel)
Output clock frequencies : fCP, fCP/22, fCP/24, fCP/26
• Delay interrupt
Generates interrupt for task switching.
Interrupts to CPU can be generated/deleted by software setting.
• External interrupts (8 channels)
8-channel independent operation
Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.
• A/D converter
10-bit or 8-bit resolution × 8 channels (input multiplexed)
Conversion time : 2.6µs (at fCP = 16 MHz)
External trigger startup available (P50/INT0/ADTG)
Internal timer startup available (16-bit reload timer 1)
• UART(LIN/SCI) (2 channels)
Equipped with full duplex double buffer
Clock-asynchronous or clock-synchronous serial transfer is available
• SIO (1 channel)
Clock synchronized data transmission.
LSB-first or MSB-first data transfer selection is available.
• CAN interface
Conforms to CAN specifications version 2.0 Part A and B.
Automatic resend in case of error.
Automatic transfer in response to remote frame.
16 prioritized message buffers for data and ID
Multiple message support
Receiving filter has flexible configuration : Full bit compare/full bit mask/two partial bit masks
Supports up to 1 Mbps
CAN WAKEUP function (connects RX internally to INT0)
• LCD controller/driver (32 segment x 4 common)
Segment driver and command driver with direct LCD panel (display) drive capability
• Low voltage/Program looping detect reset
Automatic reset when low voltage is detected
Program looping detection function
(Continued)
2
MB90925 Series
(Continued)
• Stepping motor controller (4 channels)
High current output for each channel × 4
Synchronized 8/10-bit PWM for each channel × 2
• Sound generator
8-bit PWM signal mixed with tone frequency from 8-bit reload counter.
PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at fCP = 16 MHz)
Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1)
• Input/output ports
General-purpose input/output port (CMOS output)
- 70 ports (dual clock system)
- 72 ports (single clock system)
• Input level select function for port
Automotive/CMOS-Schmitt (initial level is Automotive in single chip mode)
• Flash memory security function
Protect the content of Flash memory (Flash memory product only)
3
MB90925 Series
■ PRODUCT LINEUP
Part number
MB90F927
MB90F927S
MB90V925-101
MB90V925-102
Parameter
Type
Flash memory product
CPU
System clock
F2MC-16LX CPU
PLL clock multiplier circuit ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)
Minimum instruction execution time 62.5 ns (with 4 MHz oscillation clock × 4)
Sub clock pin
(X0A, X1A)
Yes
ROM
Flash memory 64 Kbytes
External
RAM
4 Kbytes
13.5 Kbytes
I/O port
No
70 ports
32
UART
UART(LIN/SCI) 2 channels
CAN interface
1 channel
16-bit input capture
4 channels
16-bit reload timer
2 channels
16-bit free-run timer
1 channel
Real time watch timer
1 channel
16-bit PPG
3 channels
External interrupt
8 channels
8/10-bit A/D converter
8 channels
Yes
No
Stepping motor controller
4 channels
Sound generator
1 channel
Flash memory security
Operation voltage
Packages
70 ports
1 channel
LCD segment
LVD/CPU loop reset
Yes
72 ports
SIO
4
Evaluation product
Yes
No
3.7 V to 5.5 V
4.5 V to 5.5 V
QFP-100, LQFP-100
PGA-299
MB90925 Series
■ PIN ASSIGNMENTS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
COM1
COM0
P15/IN0
P14/IN1
P13/IN2
P12/TIN0/IN3
P11/TOT0
P10/PPG2
P07/PPG1/TIN1/SEG31
P06/PPG0/TOT1/SEG30
P05/SCK1/TRG/SEG29
P04/SOT1/SEG28
P03/SIN1/INT7/SEG27
P02/SCK0/INT6/SEG26
P01/SOT0/INT5/SEG25
P00/SIN0/INT4/SEG24
VCC
X1
X0
VSS
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P92/X0A
P93/X1A
P57/SGA
RST
P56/SGO/FRCK
P55/RX0
P54/TX0
DVSS
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
DVCC
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
DVCC
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DVSS
P53/INT3/SCK
MD2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V1
V2
V3
AVCC
AVRH
P50/INT0/ADTG
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
VSS
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P51/INT1/SI
P52/INT2/SO
MD0
MD1
COM2
COM3
P22/SEG0
P23/SEG1
P24/SEG2
P25/SEG3
P26/SEG4
P27/SEG5
P30/SEG6
P31/SEG7
VSS
P32/SEG8
P33/SEG9
P34/SEG10
P35/SEG11
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P44/SEG18
VCC
P45/SEG19
P46/SEG20
P47/SEG21
C
P90/SEG22
P91/SEG23
V0
(FPT-100P-M06)
5
MB90925 Series
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
COM3
COM2
COM1
COM0
P15/IN0
P14/IN1
P13/IN2
P12/TIN0/IN3
P11/TOT0
P10/PPG2
P07/PPG1/TIN1/SEG31
P06/PPG0/TOT1/SEG30
P05/SCK1/TRG/SEG29
P04/SOT1/SEG28
P03/SIN1/INT7/SEG27
P02/SCK0/INT6/SEG26
P01/SOT0/INT5/SEG25
P00/SIN0/INT4/SEG24
VCC
X1
X0
VSS
P92/X0A
P93/X1A
P57/SGA
(TOP VIEW)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P90/SEG22
P91/SEG23
V0
V1
V2
V3
AVCC
AVRH
P50/INT0/ADTG
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
VSS
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P51/INT1/SI
P52/INT2/SO
MD0
MD1
MD2
P53/INT3/SCK
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P22/SEG0
P23/SEG1
P24/SEG2
P25/SEG3
P26/SEG4
P27/SEG5
P30/SEG6
P31/SEG7
VSS
P32/SEG8
P33/SEG9
P34/SEG10
P35/SEG11
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P44/SEG18
VCC
P45/SEG19
P46/SEG20
P47/SEG21
C
(FPT-100P-M05)
6
RST
P56/SGO/FRCK
P55/RX0
P54/TX0
DVSS
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
DVCC
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
DVCC
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DVSS
MB90925 Series
■ PIN DESCRIPTIONS
Pin no.
Pin name
LQFP*1
QFP*2
80
82
X0
81
83
X1
78
80
77
79
75
77
I/O
circuit
type*3
A
85
General-purpose I/O port
X0A
A
Low speed oscillator input pin. If no oscillator is connected,
apply pull-down processing.
P93
G
General-purpose I/O port
X1A
A
Low speed oscillator output pin. If no oscillator is connected,
leave open.
RST
B
Reset input pin
SIN0
INT4
General-purpose input/output port
J
SOT0
INT5
E
SCK0
INT6
E
SIN1
INT7
J
SOT1
E
SCK1
TRG
SEG29
UART ch.1 serial data output pin
LCD controller/driver segment output
P05
90
INT7 external interrupt input pin
General-purpose input/output port
SEG28
88
UART ch.1 serial data input pin
LCD controller/driver segment output
P04
89
INT6 external interrupt input pin
General-purpose input/output port
SEG27
87
UART ch.0 serial clock input/output pin
LCD controller/driver segment output
P03
88
INT5 external interrupt input pin
General-purpose input/output port
SEG26
86
UART ch.0 serial data output pin
LCD controller/driver segment output
P02
87
INT4 external interrupt input pin
General-purpose input/output port
SEG25
85
UART ch.0 serial data input pin
LCD controller/driver segment output
P01
86
High speed oscillator output pin
G
SEG24
84
High speed oscillator input pin
P92
P00
83
Function
General-purpose input/output port
E
UART ch.1 serial clock input/output pin
16-bit PPG ch.0 to ch.2 external trigger input pin
LCD controller/driver segment output
(Continued)
7
MB90925 Series
Pin no.
LQFP*1
QFP*2
Pin name
I/O
circuit
type*3
P06
89
91
PPG0
TOT1
General-purpose input/output port
E
SEG30
92
PPG1
TIN1
93
92
94
P10
PPG2
P11
TOT0
E
95
TIN0
G
G
96 to 98
97 to 100
99, 100,
1, 2
P13 to P15
IN2 to IN0
COM0 to
COM3
G
3 to 8
7, 8,
10 to 15
9, 10,
12 to 17
16 to 20,
22 to 24
18 to 22,
24 to 26
26, 27
28, 29
SEG0 to
SEG5
G
I
E
E
36
INT0
ADTG
16-bit reload timer ch.0 TIN output pin
General-purpose input/output port
Input capture ch.2 to ch.0 trigger input pins
LCD controller/driver common output pins
LCD controller/driver segment output pins
LCD controller/driver segment output pins
LCD controller/driver segment output pins
General-purpose input/output port
E
P50
34
16-bit reload timer ch.0 TOT output pin
General-purpose input/output port
P90, P91
SEG22,
SEG23
General-purpose input/output port
General-purpose input/output port
E
P40 to P47
SEG14 to
SEG21
16-bit PPG ch.2 output pin
General-purpose input/output ports
P30 to P37
SEG6 to
SEG13
General-purpose input/output port
Input capture ch.3 trigger input pin
P22 to P27
1 to 6
16-bit reload timer ch.1 TIN output pin
General-purpose input/output port
IN3
94 to 96
16-bit PPG ch.1 output pin
LCD controller/driver segment output
P12
93
16-bit reload timer ch.1 TOT output pin
General-purpose input/output port
SEG31
91
16-bit PPG ch.0 output pin
LCD controller/driver segment output
P07
90
Function
LCD controller/driver segment output pins
General-purpose input/output port
G
INT0 external interrupt input pin
A/D converter external trigger input pin
(Continued)
8
MB90925 Series
Pin no.
LQFP*1
QFP*2
36 to 39,
41 to 44
38 to 41,
43 to 46
Pin name
I/O
circuit
type*3
P60 to P67
AN0 to
AN7
General-purpose input/output port
F
P51
45
47
INT1
K
50
52
INT2
General-purpose input/output port
G
SIO data output pin
P53
General-purpose input/output port
INT3
G
PWM1P0,
PWM1M0,
PWM2P0,
PWM2M0
General-purpose input/output port
H
P74 to P77
57 to 60
59 to 62
PWM1P1,
PWM1M1,
PWM2P1,
PWM2M1
64 to 67
PWM1P2,
PWM1M2,
PWM2P2,
PWM2M2
H
69 to 72
72
74
73
75
PWM1P3,
PWM1M3,
PWM2P3,
PWM2M3
P54
TX0
P55
RX0
Stepping motor controller ch.1 output pins
General-purpose input/output port
H
P84 to P87
67 to 70
Stepping motor controller ch.0 output pins
General-purpose input/output port
P80 to P83
62 to 65
INT3 external interrupt input pin
SIO clock input/output pin
P70 to P73
54 to 57
INT2 external interrupt input pin
SO
SCK
52 to 55
INT1 external interrupt input pin
SIO data input pin
P52
48
A/D converter input pins
General-purpose input/output port
SI
46
Function
Stepping motor controller ch.2 output pins
General-purpose input/output port
H
G
G
Stepping motor controller ch.3 output pins
General-purpose input/output port
CAN interface 0 TX output pin
General-purpose output port
CAN interface 0 RX input pin
(Continued)
9
MB90925 Series
(Continued)
Pin no.
LQFP*1
QFP*2
Pin name
I/O
circuit
type*3
P56
74
76
SGO
General-purpose input/output port
G
FRCK
P57
Function
Sound generator SGO output pin
Free-run timer clock input pin
78
28 to 31
30 to 33
V0 to V3
⎯
LCD controller /driver reference power supply pins
56, 66
58, 68
DVCC
⎯
Power supply input pins dedicated for high current output buffer
(pin numbers 54 to 57, 59 to 62, 64 to 67, 69 to 72) .
DVSS
⎯
Power supply GND pins dedicated for high current output buffer (pin
numbers 54 to 57, 59 to 62, 64 to 67, 69 to 72) .
51, 61, 71 53, 63, 73
SGA
G
General-purpose input/output port
76
Sound generator SGA output pin
32
34
AVCC
⎯
A/D converter dedicated power supply input pin
35
37
AVSS
⎯
A/D converter dedicated power supply GND pin
33
35
AVRH
⎯
A/D converter Vref + input pin
47,
48
49,
50
MD0,
MD1
C
Test mode input pins. Connect to VCC.
49
51
MD2
C/D*4
Test mode input pin. Connect to VSS.
25
27
C
⎯
External capacitor pin. Connect an 0.1 µF capacitor between this
pin and VSS.
21, 82
23, 84
VCC
⎯
Power supply input pins
VSS
⎯
Power supply GND pins
9, 40, 79 11, 42, 81
*1: FPT-100P-M05
*2: FPT-100P-M06
*3: For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”
*4: Type C in MB90F927 and MB90F927S, type D in MB90V925-101 and MB90V925-102.
10
MB90925 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
Xout
A
X0
• High-speed oscillation pin
Oscillation feedback resistance :
approx. 1 MΩ (X0, X1 : MAIN)
• Low-speed oscillation pin
Oscillation feedback resistance :
approx. 10 MΩ (X0A, X1A : SUB)
Standby control signal
B
Hysteresis input
C
Hysteresis input
Hysteresis input
D
E
P-ch
Pout
N-ch
Nout
LCDC output
Input dedicated pin (with pull-up resistance)
• Pull-up resistance attached :
approx. 50 kΩ
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
Input dedicated pin
Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
Input dedicated pin (with pull-down resistance)
• Pull-down resistance attached :
approx. 50 kΩ
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
LCDC output common generalpurpose port
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
Hysteresis input
Standby control signal or
LCDC output switching signal
Automotive input
Standby control signal or
LCDC output switching signal
(Continued)
11
MB90925 Series
Type
Circuit
P-ch
Pout
N-ch
Nout
Remarks
Analog input
F
A/D converter input common generalpurpose port
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
Hysteresis input
Standby control signal or
Analog input enable signal
Automotive input
Standby control signal or
Analog input enable signal
P-ch
Pout
N-ch
Nout
General-purpose port
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
G
Hysteresis input
Standby control signal
Automotive input
Standby control signal
P-ch
Pout high current output
N-ch
Nout high current output
H
Hysteresis input
High current output common generalpurpose port
• CMOS output
(IOH/IOL = ± 30 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
Standby control signal
Automotive input
Standby control signal
(Continued)
12
MB90925 Series
(Continued)
Type
Circuit
Remarks
LCDC output pin (COM pin)
P-ch
I
LCDC output
N-ch
P-ch
Pout
N-ch
Nout
LCDC output
J
Hysteresis input
Standby control signal or
LCDC output enable signal
Automotive input
Standby control signal or
LCDC output enable signal
LCDC output common generalpurpose port (serial input)
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• CMOS input (SIN)
(VIH/VIL = 0.7VCC/0.3VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
CMOS input (SIN)
Standby control signal or
LCDC output enable signal
K
P-ch
Pout
N-ch
Nout
Hysteresis input
Standby control signal
General-purpose port (serial input)
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• CMOS input (SIN)
(VIH/VIL = 0.7VCC/0.3VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
Automotive input
Standby control signal
CMOS input (SIN)
Standby control signal
13
MB90925 Series
■ HANDLING DEVICES
• Strictly observe maximum rated voltages (preventing latch-up)
In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are
applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between VCC and
VSS exceeds the rated voltage level. In a latch-up condition, the power supply current can increase dramatically
and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid
exceeding maximum ratings.
Also care must be taken when the analog system power supply is switched on or off to ensure that the analog
power supply (AVCC, AVRH) , the analog input voltages and the power supply voltage for the high current output
buffer pins (DVCC) do not exceed the digital power supply voltage (VCC) .
Once the digital power supply voltage (VCC) has been disconnected, the analog power supply (AVCC, AVRH) and
the power supply voltage for the high current output buffer pins (DVCC) may be turned on in any sequence.
• Stable supply voltage
Even within the warranted operating range of VCC power supply voltage, rapid fluctuations in the power supply
voltage can cause malfunctions. The recommended stability for ripple fluctuations (P-P value) at commercial
frequencies (50 Hz/60 Hz) should be within 10% of the standard VCC value, and voltage fluctuations that occur
during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less.
• Notes on energization Power-on procedures
In order to prevent the built-in step-down circuits from malfunctioning, the voltage rising time (0.2 V to 2.7 V)
during power-on should be attained within 50 µs.
• Treatment of unused pins
If unused input pins are left open, they may cause malfunctions or latch-up which may lead to permanent damage
to the semiconductor. Unused input pins should therefore be pulled up or pulled down through a resistor of at
least 2 kΩ.
Any unused input/output pins should be left open in output status, or if found set to input status, they should be
treated in the same way as input pins.
• Treatment of A/D converter power supply pins
Even if the A/D converter is not used, pins should be connected so that AVCC = VCC, and AVSS = AVRH = VSS.
• Notes on Using an external clock
Even when an external clock is used, an oscillation stabilization wait time is required following power-on reset
or release from sub clock mode or stop mode. Also, when an external clock is used, it should drive only the X0
pin and the X1 pin should be left open, as shown below.
X0
OPEN
X1
MB90925 Series
Sample external clock connection
14
MB90925 Series
• Power supply pins
Devices are designed to prevent problems such as latch-up when multiple VCC and VSS pins are used, by providing
internal connections between pins having the same potential. However, in order to reduce unwanted radiation,
to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output current
ratings, all VCC and VSS pins should always be connected externally to power supplies and ground respectively.
As shown in the figure below, all VCC pins must have the same potential and all VSS pins must be at the same
potential. If there are multiple VCC or VSS systems, the device will not operate properly even within the warranted
operating range.
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
Power supply input pins (VCC/VSS)
In addition, care must be given to connecting the VCC and VSS pins of this device to the current supply source
with as low impedance as possible. It is recommended that a 1.0 µF bypass capacitor be connected between
the VCC and VSS pins as close to the pins as possible.
• Turning-on sequence of power supply to A/D converter and analog inputs
The A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN7) must be applied after the digital
power supply (VCC) is switched on. When power is shut off, the A/D converter power supply and analog inputs
must be cut off before the digital power supply is switched off (VCC) . In both power-on and power-off, care should
be taken that AVRH does not exceed AVCC. Even when pins which double as analog input pins are used as input
ports, be sure that the input voltage does not exceed AVCC.
• Handling the power supply for high-current output buffer pins (DVCC, DVSS)
Always apply power supply to high-current output buffer pins (DVCC, DVSS) after the digital power supply (VCC) is
turned on. Also when switching the power off, always shut off the power supply to the high-current output buffer
pins (DVCC, DVSS) before switching off the digital power supply (VCC) . There is no problem if the high-current
output buffer pins and digital power supplies are turned off and on at the same time.
Even when the high-current output buffer pins are used as general-purpose ports, the power supply for high
current output buffer pins (DVCC, DVSS) should be applied to these pins.
• Pull-up/pull-down resistor
MB90925 series does not support internal pull-up/pull-down resistor. If necessary, use external components.
15
MB90925 Series
• Precautions for when not using a sub clock signal
If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave
the X1A pin open.
• Notes on operation when external clock is stopped
When there is no external oscillator or external clock input is stopped, performance of the operation by MB90925
series the internal oscillation circuit cannot be guaranteed.
16
MB90925 Series
■ BLOCK DIAGRAM
X0, X1
P92/X0A
P93/X1A
RST
Clock control
circuit
CPU
F2MC-16LX core
RAM 4 Kbytes*
Interrupt
controller
ROM 64 Kbytes*
Low voltage/
CPU operation
detection reset
CAN controller
P57/SGA
P56/SGO/FRCK
SIO
P55/RX0
P54/TX0
Prescaler (SIO)
F2MC-16LX BUS
Sound generator
P87/PWM2M3
Port 8
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P53/INT3/SCK
P52/INT2/SO
P86/PWM2P3
P82/PWM2P2
Port 5
P51/INT1/SI
P50/INT0/ADTG
External interrupt
(8 channels)
P81/PWM1M2
Stepping
motor
controller
0/1/2/3
P80/PWM1P2
P77/PWM2M1
P00/SIN0/INT4/SEG24
P76/PWM2P1
P01/SOT0/INT5/SEG25
P75/PWM1M1
P02/SCK0/INT6/SEG26
P74/PWM1P1
UART0/1
P73/PWM2M0
P03/SIN1/INT7/SEG27
P72/PWM2P0
P04/SOT1/SEG28
P05/SCK1/TRG/SEG29
P06/PPG0/TOT1/SEG30
Prescaler
0/1
Port 7
P71/PWM1M0
P70/PWM1P0
P07/PPG1/TIN1/SEG31
Port 6
Port 0
P67 to P60/
PPG0/1/2
AN7 to AN0
A/D converter
(8 channels)
AVCC/AVSS
AVRH
P10/PPG2
P11/TOT0
Port F
Port 9
P12/TIN0/IN3
P13/IN2
P14/IN1
P91, P90/
SEG23, SEG22
Reload timer
0/1
Port 4
P15/IN0
P47 to P40/
SEG21 to SEG14
Real-time
watch timer
Port 3
P37 to P30/
SEG13 to SEG6
ICU0/1/2/3
P27 to P22/
Port 2
SEG5 to SEG0
Free-run timer
* : Evaluation device (MB90V925-101/102)
No built-in ROM
Built-in RAM is 6 Kbytes.
LCD controller/
driver
COM3 to COM0
V3 to V0
17
MB90925 Series
■ MEMORY MAP
Single chip mode
(with ROM mirror function)
000000H
Peripheral area
0000D0H
000100H
Register
RAM area
Address #2
003900H
Peripheral area
004000H
ROM area
(FF bank image)
010000H
Address #1
ROM area
FFFFFFH
Part number
: Internal access memory
: Access prohibited
Address #1
Address #2
MB90F927/MB90F927S
FF0000H
001100H
MB90V925-101/MB90V925-102
F80000H
003700H
Note : To select models without the ROM mirror function, refer to the “ROM Mirror Function Selection Module” in
Hardware Manual. The image of the ROM data in the FF bank appears at the top of the 00 bank, in order
to enable efficient use of small C compiler models. The lower 16-bit address for the FF bank will be assigned
to the same address, so that tables in ROM can be referenced without declaring a “far” indication with the
pointer. For example when accessing the address 00C000H, the actual access is to address FFC000H in
ROM. Here the FF bank ROM area exceeds 48 Kbytes, so that it is not possible to see the entire area in the
00 bank image. Therefore because the ROM data from FF4000H to FFFFFFH will appear in the image from
004000H to 00FFFFH, it is recommended that the ROM data table be stored in the area from FF4000H to
FFFFFFH.
18
MB90925 Series
■ I/O MAP
• Other than CAN Interface
Address
Register name
Symbol Read/write
Resource name
Initial value
000000H Port 0 data register
PDR0
R/W
Port 0
XXXXXXXXB
000001H Port 1 data register
PDR1
R/W
Port 1
- - XX X XX X B
000002H Port 2 data register
PDR2
R/W
Port 2
X X X X X X - -B
000003H Port 3 data register
PDR3
R/W
Port 3
XXXXXXXXB
000004H Port 4 data register
PDR4
R/W
Port 4
XXXXXXXXB
000005H Port 5 data register
PDR5
R/W
Port 5
XXXXXXXXB
000006H Port 6 data register
PDR6
R/W
Port 6
XXXXXXXXB
000007H Port 7 data register
PDR7
R/W
Port 7
XXXXXXXXB
000008H Port 8 data register
PDR8
R/W
Port 8
XXXXXXXXB
000009H Port 9 data register
PDR9
R/W
Port 9
- - - -XXXXB
00000AH
to
00000FH
(Disabled)
000010H Port 0 direction register
DDR0
R/W
Port 0
0 0 0 0 0 0 0 0B
000011H Port 1 direction register
DDR1
R/W
Port 1
- - 0 0 0 0 0 0B
000012H Port 2 direction register
DDR2
R/W
Port 2
0 0 0 0 0 0 - -B *
000013H Port 3 direction register
DDR3
R/W
Port 3
0 0 0 0 0 0 0 0B *
000014H Port 4 direction register
DDR4
R/W
Port 4
0 0 0 0 0 0 0 0B
000015H Port 5 direction register
DDR5
R/W
Port 5
0 0 0 0 0 0 0 0B
000016H Port 6 direction register
DDR6
R/W
Port 6
0 0 0 0 0 0 0 0B
000017H Port 7 direction register
DDR7
R/W
Port 7
0 0 0 0 0 0 0 0B
000018H Port 8 direction register
DDR8
R/W
Port 8
0 0 0 0 0 0 0 0B
000019H Port 9 direction register
DDR9
R/W
Port 9
- - - - 0 0 0 0B
00001AH Analog input enable
ADER
R/W
Port 6, A/D
1 1 1 1 1 1 1 1B
00001BH
to
00001FH
(Disabled)
000020H A/D control status register lower
ADCS0
R/W
000021H A/D control status register higher
ADCS1
R/W
000022H A/D data register lower
ADCR0
R
000023H A/D data register higher
ADCR1
R
- - - - - - 0 0B
R/W
XXXXXXXXB
R/W
XXXXXXXXB
000024H
000025H
000026H
000027H
Compare clear register
Timer data register
CPCLR
TCDT
R/W
R/W
0 0 0 - - - - 0B
8/10-bit
A/D converter
16-bit free-run timer
0 0 0 0 0 0 0 -B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
000028H Timer control status register lower
TCCSL
R/W
0 0 0 0 0 0 0 0B
000029H Timer control status register higher
TCCSH
R/W
0 1 - 0 0 0 0 0B
(Continued)
19
MB90925 Series
Address
Symbol
Read/write
00002AH PPG0 control status register lower
PCNTL0
R/W
00002BH PPG0 control status register higher
PCNTH0
R/W
00002CH PPG1 control status register lower
PCNTL1
R/W
00002DH PPG1 control status register higher
PCNTH1
R/W
00002EH PPG2 control status register lower
PCNTL2
R/W
00002FH PPG2 control status register higher
PCNTH2
R/W
000030H External interrupt enable
ENIR
R/W
000031H External interrupt request
EIRR
R/W
000032H External interrupt level lower
ELVRL
R/W
000033H External interrupt level higher
ELVRH
R/W
0 0 0 0 0 0 0 0B
000034H Serial mode register 0
SMR0
R/W
0 0 0 0 0 0 0 0B
000035H Serial control register 0
SCR0
R/W
0 0 0 0 0 0 0 0B
RDR0/
TDR0
R/W
0 0 0 0 0 0 0 0B
SSR0
R/W
ECCR0
R/W
0 0 0 0 0 0 XXB
000039H Extended status control register
ESCR0
R/W
0 0 0 0 0 1 0 0B
00003AH Baud rate generator register 00
BGR00
R/W
0 0 0 0 0 0 0 0B
00003BH Baud rate generator register 01
BGR01
R/W
0 0 0 0 0 0 0 0B
000036H
Register name
Reception/transmission data
register 0
000037H Serial status register 0
000038H
Extended communication control
register 0
00003CH,
00003DH
Resource name
16-bit PPG0
16-bit PPG1
16-bit PPG2
Initial value
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 1B
0 0 0 0 0 0 0 0B
External interrupt
UART(LIN/SCI) 0
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 1 0 0 0B
(Disabled)
00003EH CAN wake-up control register
CWUCR
R/W
CAN
00003FH
(Disabled)
000040H
to
00004FH
Area reserved for CAN interface 0
- - - - - - - 0B
000050H
Timer control status register 0
lower
TMCSR0L
R/W
0 0 0 0 0 0 0 0B
000051H
Timer control status register 0
higher
TMCSR0H
R/W
16-bit reload timer 0 - - 1 0 0 0 0 0B
TMR0/
TMRLR0
R/W
000052H
000053H
Timer register 0/reload register 0
XXXXXXXXB
XXXXXXXXB
000054H
Timer control status register 1
lower
TMCSR1L
R/W
0 0 0 0 0 0 0 0B
000055H
Timer control status register 1
higher
TMCSR1H
R/W
16-bit reload timer 1 - - 1 0 0 0 0 0B
TMR1/
TMRLR1
R/W
000056H
000057H
Timer register 1/reload register 1
XXXXXXXXB
XXXXXXXXB
(Continued)
20
MB90925 Series
Address
Register name
Symbol Read/write
Resource name
Initial value
000058H LCD output control register 1
LOCR1
R/W
000059H LCD output control register 2
LOCR2
R/W
00005AH Sound control register lower
SGCRL
R/W
0 0 0 0 0 0 0 0B
00005BH Sound control register higher
SGCRH
R/W
0 - - - - 1 0 0B
00005CH Frequency data register
SGFR
R/W
00005DH Amplitude data register
SGAR
R/W
00005EH Decrement grade register
SGDR
R/W
XXXXXXXXB
00005FH Tone count register
SGTR
R/W
XXXXXXXXB
IPCP0
R
000060H
000061H
000062H
000063H
000064H
000065H
000066H
Input capture register 0
LCD
Sound generator
IPCP1
R
Input capture register 2
IPCP2
R
XXXXXXXXB
0 0 0 0 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Input capture 2/3
XXXXXXXXB
XXXXXXXXB
IPCP3
R
000068H Input capture control status 0/1
ICS01
R/W
Input capture 0/1
0 0 0 0 0 0 0 0B
000069H Input capture edge register 0/1
ICE01
R/W
Input capture 0/1
XXX0X0XXB
00006AH Input capture control status 2/3
ICS23
R/W
Input capture 2/3
0 0 0 0 0 0 0 0B
00006BH Input capture edge register 2/3
ICE23
R/W
Input capture 2/3
XXXXXXXXB
00006CH LCD control register lower
LCRL
R/W
0 0 0 1 0 0 0 0B
00006DH LCD control register higher
LCRH
R/W
LCD controller/
driver
LVRC
R/W
Low voltage/CPU operation detection reset
0 0 1 1 1 0 0 0B
ROMM
W
ROM mirror
X X X X X X X 1B
Stepping motor
controller 0
0 0 0 0 0 - - 0B
Stepping motor
controller 1
0 0 0 0 0 - - 0B
Stepping motor
controller 2
0 0 0 0 0 - - 0B
Stepping motor
controller 3
0 0 0 0 0 - - 0B
000067H
00006EH
Input capture register 3
0 0 0 0 0 0 0 0B
XXXXXXXXB
Input capture 0/1
Input capture register 1
1 1 1 1 1 1 1 1B
Low voltage/CPU operation
detection reset control register
00006FH ROM mirror
000070H
to
00007FH
000080H PWM control register 0
PWC0
PWC1
R/W
(Disabled)
PWC2
000085H
000086H PWM control register 3
R/W
(Disabled)
000083H
000084H PWM control register 2
0 0 0 0 0 0 0 0B
(Disabled)
000081H
000082H PWM control register 1
XXXXXXXXB
R/W
(Disabled)
PWC3
R/W
(Continued)
21
MB90925 Series
Address
Register name
Symbol Read/write
000087H
to
000089H
Resource name
Initial value
(Disabled)
00008AH A/D setting register 0
ADSR0
R/W
00008BH A/D setting register 1
ADSR1
R/W
00008CH Port input level select 0
PIL0
R/W
00008DH Port input level select 1
PIL1
R/W
00008EH
to
00009DH
A/D
Port Input Level Select
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
- - - 0 0 0 0 0B
(Disabled)
00009EH ROM correction control register PACSR
R/W
Address match
detection function
- - - - - 0 - 0B
00009FH Delay interrupt/release
DIRR
R/W
Delay interrupt
- - - - - - - 0B
0000A0H Power saving mode
LPMCR
R/W
0 0 0 1 1 0 0 0B
0000A1H Clock select
CKSCR
R/W
Power saving
control circuit
1 1 1 1 1 1 0 0B
0000A2H
to
0000A7H
(Disabled)
0000A8H Watchdog control
0000A9H
Time-base timer control register
0000AAH Watch timer control register
WDTC
R/W
Watchdog timer
X X X X X 1 1 1B
TBTC
R/W
Time-base timer
1 - - 0 0 1 0 0B
WTC
R/W
Watch timer
(sub clock)
1 X 0 0 0 0 0 0B
Flash memory interface
0 0 0 X 0 XX 0B
0000ABH
to
0000ADH
0000AEH Flash control register
(Disabled)
FMCS
0000AFH
R/W
(Disabled)
0000B0H Interrupt control register 00
ICR00
R/W
0 0 0 0 0 1 1 1B
0000B1H Interrupt control register 01
ICR01
R/W
0 0 0 0 0 1 1 1B
0000B2H Interrupt control register 02
ICR02
R/W
0000B3H Interrupt control register 03
ICR03
R/W
0 0 0 0 0 1 1 1B
0000B4H Interrupt control register 04
ICR04
R/W
0 0 0 0 0 1 1 1B
0000B5H Interrupt control register 05
ICR05
R/W
0 0 0 0 0 1 1 1B
0000B6H Interrupt control register 06
ICR06
R/W
0 0 0 0 0 1 1 1B
0000B7H Interrupt control register 07
ICR07
R/W
0 0 0 0 0 1 1 1B
0000B8H Interrupt control register 08
ICR08
R/W
0000B9H Interrupt control register 09
ICR09
R/W
0000BAH Interrupt control register 10
ICR10
R/W
0 0 0 0 0 1 1 1B
0000BBH Interrupt control register 11
ICR11
R/W
0 0 0 0 0 1 1 1B
0000BCH Interrupt control register 12
ICR12
R/W
0 0 0 0 0 1 1 1B
Interrupt controller
Interrupt controller
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
(Continued)
22
MB90925 Series
Address
Register name
Symbol
Read/write
0000BDH Interrupt control register 13
ICR13
R/W
0000BEH Interrupt control register 14
ICR14
R/W
0000BFH Interrupt control register 15
ICR15
R/W
0 0 0 0 0 1 1 1B
0000C0H Serial mode control register (lower)
SMCSL
R/W
- - - - 0 0 0 0B
0000C1H Serial mode control register (higher)
SMCSH
R/W
SDR
R/W
SDCR
R/W
0000C4H Serial mode register 1
SMR1
R/W
0 0 0 0 0 0 0 0B
0000C5H Serial control register 1
SCR1
R/W
0 0 0 0 0 0 0 0B
Reception/transmission
data register 1
RDR1/
TDR1
R/W
0 0 0 0 0 0 0 0B
SSR1
R/W
ECCR1
R/W
0 0 0 0 0 0 XXB
0000C9H Extended status control register 1
ESCR1
R/W
0 0 0 0 0 1 0 0B
0000CAH Baud rate generator register 10
BGR10
R/W
0 0 0 0 0 0 0 0B
0000CBH Baud rate generator register 11
BGR11
R/W
0 0 0 0 0 0 0 0B
0000CCH Watch timer control register lower
WTCRL
R/W
0000C2H Serial data register
0000C3H
0000C6H
Communication prescaler
control register
0000C7H Serial status register 1
0000C8H
Extended communication
control register 1
0000CDH Watch timer control register middle
WTCRM
R/W
0000CEH Watch timer control register higher
WTCRH
R/W
SCCR
W
0000CFH Sub clock control register
0000D0H
to
0000FFH
PADR0
PADR0
R/W
001FF2H ROM correction address 2
PADR0
R/W
001FF3H ROM correction address 3
PADR1
R/W
001FF4H ROM correction address 4
PADR1
R/W
001FF5H ROM correction address 5
PADR1
R/W
003900H
to
00391FH
003922H
003923H
003924H
003925H
0 0 0 0 0 1 1 1B
Interrupt controller
SIO
0 0 0 0 0 1 1 1B
0 0 0 0 0 0 1 0B
XXXXXXXXB
Communication
prescaler (SIO)
UART(LIN/SCI) 1
0 - - - 0 0 0 0B
0 0 0 0 1 0 0 0B
0 0 0 - - 0 0 0B
Real-time
watch timer
0 0 0 0 0 0 0 0B
- - - - 0 0 0 0B
Sub clock
R/W
001FF1H ROM correction address 1
003921H
Initial value
- - - - 0 0 0 0B
(Disabled)
001FF0H ROM correction address 0
003920H
Resource name
XXXXXXXXB
Address match
detection function
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address match
detection function
XXXXXXXXB
XXXXXXXXB
(Disabled)
PPG0 down counter register
PDCR0
R
PPG0 cycle setting register
PCSR0
W
PPG0 duty setting register
PDUT0
W
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
16-bit PPG 0
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
23
MB90925 Series
Address
Register name
003926H,
003927H
003928H
003929H
00392AH
00392BH
00392CH
00392DH
003931H
003932H
003933H
003934H
003935H
Read/write
Resource name
Initial value
(Disabled)
PPG1 down counter register
PDCR1
R
PPG1 cycle setting register
PCSR1
W
PPG1 duty setting register
PDUT1
W
00392EH,
00392FH
003930H
Symbol
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
16-bit PPG 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Disabled)
PPG2 down counter register
PDCR2
R
PPG2 cycle setting register
PCSR2
W
PPG2 duty setting register
PDUT2
W
003936H
to
003957H
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
16-bit PPG 2
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Disabled)
003958H
XXXXXXXXB
003959H Sub second data register
WTBR
R/W
XXXXXXXXB
00395AH
- - - XXXXXB
Real time
watch timer
00395BH Second data register
WTSR
R/W
00395CH Minute data register
WTMR
R/W
- - 0 0 0 0 0 0B
00395DH Hour data register
WTHR
R/W
- - - 0 0 0 0 0B
00395EH Day data register
WTDR
R/W
0 0 - 0 0 0 0 1B
00395FH
(Disabled)
003960H
to
LCD display RAM
00396FH
003970H
to
00397FH
003980H
- - 0 0 0 0 0 0B
VRAM
R/W
LCD controller/
driver
XXXXXXXXB
(Disabled)
XXXXXXXXB
PWM1 compare register 0
PWC10
R/W
PWM2 compare register 0
PWC20
R/W
003984H PWM1 select register 0
PWS10
R/W
- - 0 0 0 0 0 0B
003985H PWM2 select register 0
PWS20
R/W
- 0 0 0 0 0 0 0B
003981H
003982H
003983H
- - - - - - XXB
Stepping motor
controller 0
XXXXXXXXB
- - - - - - XXB
(Continued)
24
MB90925 Series
Address
Register name
003986H,
003987H
003988H
Symbol
Read/write
Resource name
Initial value
(Disabled)
XXXXXXXXB
PWM1 compare register 1
PWC11
R/W
PWM2 compare register 1
PWC21
R/W
00398CH PWM1 select register 1
PWS11
R/W
- - 0 0 0 0 0 0B
00398DH PWM2 select register 1
PWS21
R/W
- 0 0 0 0 0 0 0B
003989H
00398AH
00398BH
00398EH,
00398FH
003990H
- - - - - - XXB
Stepping motor
controller 1
XXXXXXXXB
- - - - - - XXB
(Disabled)
XXXXXXXXB
PWM1 compare register 2
PWC12
R/W
PWM2 compare register 2
PWC22
R/W
003994H PWM1 select register 2
PWS12
R/W
- - 0 0 0 0 0 0B
003995H PWM2 select register 2
PWS22
R/W
- 0 0 0 0 0 0 0B
003991H
003992H
003993H
003996H,
003997H
003998H
- - - - - - XXB
Stepping motor
controller 2
XXXXXXXXB
- - - - - - XXB
(Disabled)
XXXXXXXXB
PWM1 compare register 3
PWC13
R/W
PWM2 compare register 3
PWC23
R/W
00399CH PWM1 select register 3
PWS13
R/W
- - 0 0 0 0 0 0B
00399DH PWM2 select register 3
PWS23
R/W
- 0 0 0 0 0 0 0B
003999H
00399AH
00399BH
- - - - - - XXB
Stepping motor
controller 3
00399EH
to
0039FFH
(Disabled)
003A00H
to
003AFFH
Area reserved for CAN interface 0
003B00H
to
003BFFH
(Disabled)
003C00H
to
003CFFH
Area reserved for CAN interface 0
003D00H
to
003EFFH
(Disabled)
XXXXXXXXB
- - - - - - XXB
(Continued)
25
MB90925 Series
(Continued)
• Initial value symbols :
“0” : initial value 0
“1” : initial value 1
“X” : initial value undetermined
“-” : initial value undetermined (none)
• Write/read symbols :
“R/W” : read/write enabled
“R”
: read only
“W”
: write only
• Addresses in the area 0000H to 00FFH are reserved for the principal functions of the MCU. Read access
attempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited.
* : P22/SEG0 to P27/SEG5 and P30/SEG6 to P35/SEG11 initially will be LCD segment output as LCD output
control register LOCR1 (58H) is “11111111B” initially. To use port 2 and port 3 as the general-purpose input/
output ports, set LOCR1 to “00000000B” to disable the LCD segment output first.
26
MB90925 Series
• CAN Interface
Symbol
Read/
write
Message buffer valid area
BVALR
R/W
Transmission request register
TREQR
R/W
Transmission cancel register
TCANR
W
Transmission completed register
TCR
R/W
Receiving completed register
RCR
R/W
Remote request receiving register
RRTRR
R/W
Receiving overrun register
ROVRR
R/W
Receiving interrupt enable register
RIER
R/W
Control status register
CSR
R/W, R
Last event indicator register
LEIR
R/W
RX/TX error counter
RTEC
R
Bit timing register
BTR
R/W
IDE register
IDER
R/W
Transmission RTR register
TRTRR
R/W
Remote frame receiving wait register
RFWTR
R/W
Transmission interrupt enable register
TIER
R/W
Address
000040H
000041H
000042H
000043H
000044H
000045H
000046H
000047H
000048H
000049H
00004AH
00004BH
00004CH
00004DH
00004EH
00004FH
003C00H
003C01H
003C02H
003C03H
003C04H
003C05H
003C06H
003C07H
003C08H
003C09H
003C0AH
003C0BH
003C0CH
003C0DH
003C0EH
003C0FH
Register name
Initial value
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 - - - 0 0 0B
0 - - - - 0 - 1B
- - - - - - - -B
0 0 0 - 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
- 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(Continued)
27
MB90925 Series
Address
Register name
Symbol
Read/
write
XXXXXXXXB
003C10H
003C11H
003C12H
Initial value
Acceptance mask select register
AMSR
R/W
XXXXXXXXB
XXXXXXXXB
003C13H
XXXXXXXXB
003C14H
XXXXXXXXB
003C15H
003C16H
Acceptance mask register 0
AMR0
R/W
XXXXXXXXB
XXXXX- - -B
003C17H
XXXXXXXXB
003C18H
XXXXXXXXB
003C19H
003C1AH
Acceptance mask register 1
AMR1
R/W
003C1BH
⎯
R/W
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXXB
003A20H
003A22H
XXXXX- - -B
XXXXXXXXB
003A00H
to
General-purpose RAM
003A1FH
003A21H
XXXXXXXXB
ID register 0
IDR0
R/W
XXXXXXXXB
XXXXX- - -B
003A23H
XXXXXXXXB
003A24H
XXXXXXXXB
003A25H
003A26H
ID register 1
IDR1
R/W
XXXXXXXXB
XXXXX- - -B
003A27H
XXXXXXXXB
003A28H
XXXXXXXXB
003A29H
003A2AH
ID register 2
IDR2
R/W
XXXXXXXXB
XXXXX- - -B
003A2BH
XXXXXXXXB
003A2CH
XXXXXXXXB
003A2DH
003A2EH
ID register 3
IDR3
R/W
XXXXXXXXB
XXXXX- - -B
003A2FH
XXXXXXXXB
003A30H
XXXXXXXXB
003A31H
003A32H
003A33H
ID register 4
IDR4
R/W
XXXXXXXXB
XXXXX- - -B
XXXXXXXXB
(Continued)
28
MB90925 Series
Address
Register name
Symbol
Read/
write
XXXXXXXXB
003A34H
003A35H
003A36H
Initial value
ID register 5
IDR5
R/W
XXXXXXXXB
XXXXX- - -B
003A37H
XXXXXXXXB
003A38H
XXXXXXXXB
003A39H
003A3AH
ID register 6
IDR6
R/W
XXXXXXXXB
XXXXX- - -B
003A3BH
XXXXXXXXB
003A3CH
XXXXXXXXB
003A3DH
003A3EH
ID register 7
IDR7
R/W
XXXXXXXXB
XXXXX- - -B
003A3FH
XXXXXXXXB
003A40H
XXXXXXXXB
003A41H
003A42H
ID register 8
IDR8
R/W
XXXXXXXXB
XXXXX- - -B
003A43H
XXXXXXXXB
003A44H
XXXXXXXXB
003A45H
003A46H
ID register 9
IDR9
R/W
XXXXXXXXB
XXXXX- - -B
003A47H
XXXXXXXXB
003A48H
XXXXXXXXB
003A49H
003A4AH
ID register 10
IDR10
R/W
XXXXXXXXB
XXXXX- - -B
003A4BH
XXXXXXXXB
003A4CH
XXXXXXXXB
003A4DH
003A4EH
ID register 11
IDR11
R/W
XXXXXXXXB
XXXXX- - -B
003A4FH
XXXXXXXXB
003A50H
XXXXXXXXB
003A51H
003A52H
003A53H
ID register 12
IDR12
R/W
XXXXXXXXB
XXXXX- - -B
XXXXXXXXB
(Continued)
29
MB90925 Series
Address
Register name
Symbol
Read/
write
XXXXXXXXB
003A54H
003A55H
003A56H
Initial value
ID register 13
IDR13
R/W
XXXXXXXXB
XXXXX- - -B
003A57H
XXXXXXXXB
003A58H
XXXXXXXXB
003A59H
003A5AH
ID register 14
IDR14
R/W
XXXXXXXXB
XXXXX- - -B
003A5BH
XXXXXXXXB
003A5CH
XXXXXXXXB
003A5DH
003A5EH
ID register 15
IDR15
R/W
003A5FH
003A60H
003A61H
003A62H
003A63H
003A64H
003A65H
003A66H
003A67H
003A68H
003A69H
003A6AH
003A6BH
003A6CH
003A6DH
003A6EH
003A6FH
003A70H
003A71H
003A72H
003A73H
003A74H
003A75H
XXXXXXXXB
XXXXX- - -B
XXXXXXXXB
DLC register 0
DLCR0
R/W
DLC register 1
DLCR1
R/W
DLC register 2
DLCR2
R/W
DLC register 3
DLCR3
R/W
DLC register 4
DLCR4
R/W
DLC register 5
DLCR5
R/W
DLC register 6
DLCR6
R/W
DLC register 7
DLCR7
R/W
DLC register 8
DLCR8
R/W
DLC register 9
DLCR9
R/W
DLC register 10
DLCR10
R/W
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
(Continued)
30
MB90925 Series
Symbol
Read/
write
DLC register 11
DLCR11
R/W
DLC register 12
DLCR12
R/W
DLC register 13
DLCR13
R/W
DLC register 14
DLCR14
R/W
DLC register 15
DLCR15
R/W
003A80H
to
Data register 0 (8 bytes)
003A87H
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
003A88H
to
Data register 1 (8 bytes)
003A8FH
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
003A90H
to
Data register 2 (8 bytes)
003A97H
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
003A98H
to
Data register 3 (8 bytes)
003A9FH
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
003AA0H
to
Data register 4 (8 bytes)
003AA7H
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
003AA8H
to
Data register 5 (8 bytes)
003AAFH
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
003AB0H
to
Data register 6 (8 bytes)
003AB7H
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
003AB8H
to
Data register 7 (8 bytes)
003ABFH
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
003AC0H
to
Data register 8 (8 bytes)
003AC7H
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
003AC8H
to
Data register 9 (8 bytes)
003ACFH
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
Address
003A76H
003A77H
003A78H
003A79H
003A7AH
003A7BH
003A7CH
003A7DH
003A7EH
003A7FH
Register name
Initial value
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
- - - -XXXXB
(Continued)
31
MB90925 Series
(Continued)
Symbol
Read/
write
Initial value
003AD0H
to
Data register 10 (8 bytes)
003AD7H
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
003AD8H
to
Data register 11 (8 bytes)
003ADFH
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
003AE0H
to
Data register 12 (8 bytes)
003AE7H
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
003AE8H
to
Data register 13 (8 bytes)
003AEFH
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
003AF0H
to
Data register 14 (8 bytes)
003AF7H
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
003AF8H
to
Data register 15 (8 bytes)
003AFFH
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
Address
32
Register name
MB90925 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source
EI2OS
corresponding
Interrupt vector
Number
Address
Interrupt control register
ICR
Address
Priority
*2
High
Reset
×
#08
08H FFFFDCH
⎯
⎯
INT9 instruction
×
#09
09H FFFFD8H
⎯
⎯
Exception processing
×
#10
0AH FFFFD4H
⎯
⎯
CAN0 RX
×
#11
0BH FFFFD0H
CAN0 TX/NS
×
#12
0CH FFFFCCH
ICR00
0000B0H *1
( Reserved) *3
×
#13
0DH FFFFC8H
#14
0EH FFFFC4H
ICR01
0000B1H *1
Input capture 0
#15
0FH FFFFC0H
DTP/external interrupt - ch.0 detected
#16
10H FFFFBCH
ICR02
0000B2H *1
Reload timer 0
#17
11H
FFFFB8H
DTP/external interrupt - ch.1 detected
#18
12H
FFFFB4H
ICR03
0000B3H *1
Input capture 1
#19
13H
FFFFB0H
DTP/external interrupt - ch.2 detected
#20
14H FFFFACH
ICR04
0000B4H *1
Input capture 2
#21
15H
FFFFA8H
DTP/external interrupt - ch.3 detected
#22
16H
FFFFA4H
ICR05
0000B5H *1
Input capture 3
#23
17H
FFFFA0H
DTP/external interrupt - ch.4/ch.5
detected
#24
18H FFFF9CH
ICR06
0000B6H *1
PPG timer 0
#25
19H
FFFF98H
DTP/external interrupt - ch.6/ch.7
detected
#26
1AH
FFFF94H
ICR07
0000B7H *1
PPG timer 1
#27
1BH
FFFF90H
Reload timer 1
#28
1CH FFFF8CH
ICR08
0000B8H *1
PPG timer 2
#29
1DH FFFF88H
ICR09
0000B9H *1
ICR10
0000BAH *1
ICR11
0000BBH *1
ICR12
0000BCH *1
ICR13
0000BDH *1
ICR14
0000BEH *1
ICR15
0000BFH *1
SIO
*3
Real time watch timer
×
#30
1EH
FFFF84H
Free-run timer overflow
×
#31
1FH
FFFF80H
#32
20H FFFF7CH
A/D converter conversion end
Free-run timer clear
×
#33
21H
FFFF78H
Sound generator
×
#34
22H
FFFF74H
Time-base timer
×
#35
23H
FFFF70H
Watchdog (sub clock)
×
#36
24H FFFF6CH
UART 1 RX
#37
25H
FFFF68H
UART 1 TX
#38
26H
FFFF64H
UART 0 RX
#39
27H
FFFF60H
UART 0 TX
#40
28H FFFF5CH
Flash memory status
×
#41
29H
FFFF58H
Delay interrupt generator module
×
#42
2AH
FFFF54H
Low
(Continued)
33
MB90925 Series
(Continued)
: Usable, with EI2OS stop function
: Usable
: Usable when interrupt sources sharing ICR are not in use
× : Unusable
*1 : • Peripheral functions sharing the ICR register have the same interrupt level.
• If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other
cannot be used.
• When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services,
the interrupt from the other function cannot be used.
*2 : Priority applies when interrupts of the same level are generated.
*3 : SIO and CAN1 TX/NX will share IRQ3 in evaluation chip (MB90V925-101/102) .
34
MB90925 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage*1
Symbol
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
AVCC = VCC*2
AVRH
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVRH*2
DVCC
VSS − 0.3
VSS + 6.0
V
DVCC = VCC*2
VI
VSS − 0.3
VCC + 0.3
V
*3
VO
VSS − 0.3
VCC + 0.3
V
ICLAMP
− 400
+ 400
µA
*7
⎯
4
mA
*7
IOL1
⎯
15
mA
Other than P70 to P77 and P80 to P87
IOL2
⎯
40
mA
P70 to 77 and P80 to87
IOLAV1
⎯
4
mA
Other than P70 to P77 and P80 to P87
IOLAV2
⎯
30
mA
P70 to 77 and P80 to 87
ΣIOL1
⎯
100
mA
Other than P70 to P77 and P80 to P87
ΣIOL2
⎯
330
mA
P70 to 77 and P80 to 87
ΣIOLAV1
⎯
50
mA
Other than P70 to P77 and P80 to P87
ΣIOLAV2
⎯
250
mA
P70 to 77 and P80 to 87
I
OH1 4
⎯
−15
mA
Other than P70 to P77 and P80 to P87
I
OH2 4
⎯
−40
mA
P70 to 77 and P80 to 87
I
OHAV1 5
⎯
−4
mA
Other than P70 to P77 and P80 to P87
I
OHAV2 5
*
⎯
−30
mA
P70 to 77 and P80 to 87
ΣIOH1
⎯
−100
mA
Other than P70 to P77 and P80 to P87
ΣIOH2
⎯
−330
mA
P70 to 77 and P80 to 87
⎯
−50
mA
Other than P70 to P77 and P80 to P87
⎯
−250
mA
P70 to 77 and P80 to 87
Maximum clamp current
Total maximum clamp current Σ| ICLAMP |
“L” level maximum
output current*4
“L” level average output
current*5
“L” level maximum
total output current
“H” level maximum
output current
“H” level average
output current
“H” level maximum
total output current
“H” level average total
output current
*
*
*
ΣI
*
ΣI
*
OHAV1 6
OHAV2 6
Power consumption
PD
⎯
500
mW
Operating temperature
TA
−40
+105
°C
TSTG
−55
+150
°C
Storage temperature
Remarks
Max
1
“L” level average total
output current
Unit
Min
Input voltage*1
Output voltage*
Rating
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : AVCC, AVRH and DVCC shall never exceed VCC.
Also, AVRH shall never exceed AVCC.
*3 : The maximum current to/from and input are limited by some means with external components, the ICLAMP rating
supersedes the VI rating.
*4 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins.
*5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the
corresponding pins. The “average value” can be calculated from the formula of “operating current” times
“operating factor”.
(Continued)
35
MB90925 Series
(Continued)
*6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the
corresponding pins. The “average value” can be calculated from the formula of “operating current” times
“ operating factor”.
*7 : • Applicable to pins : P10 to P15, P50 to P57, P70 to P77, P80 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied, the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept +B
signal input.
• Sample recommended circuits :
• Input/Output equivalent circuits
Protective diode
VCC
P-ch
Limiting
resistance
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
36
MB90925 Series
2. Recommended Operating Conditions
(VSS = DVSS = AVSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min
Max
VCC
AVCC
DVCC
3.7
5.5
V
(MB90F927/MB90F927S)
Low voltage detection reset starts to work when power
supply voltage is 4.0 V ± 0.3 V.
4.3
5.5
V
Holding stop operation status
(MB90F927/MB90F927S)
Smoothing
capacitor*
CS
0.1
1.0
µF
Use a ceramic capacitor or other capacitor of equivalent
frequency characteristics. A bypass capacitor on the VCC pin
should have a capacitance greater than Cs.
Operating
temperature
TA
− 40
+ 105
°C
Power supply
voltage
* : For smoothing capacitor Cs connections, refer to the illustration below.
• C pin connection diagram
C
CS
VSS
DVSS
AVSS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
37
MB90925 Series
3. DC Characteristics
(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
Pin
name
Conditions
VIHA
⎯
⎯
VIHS2
⎯
⎯
Value
Min
Typ
Max
0.8 VCC
⎯
VCC + 0.3
0.8 VCC
⎯
VCC + 0.3
Unit
Remarks
V
Pin inputs if
Automotive input
levels are selected*1
V
Pin inputs if CMOS
hysteresis input
levels are selected*1
(0.8Vcc/0.2Vcc
CMOS hysteresis is
selected for P00,
P03 and P51)
“H” level
input voltage
VIHS1
⎯
⎯
0.7 VCC
⎯
VCC + 0.3
V
Pin inputs if 0.7Vcc/
0.3Vcc CMOS hysteresis input levels is
selected for P00,
P03 and P51.
VIHR
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
RST input pin
(CMOS hysteresis)
VIHM
⎯
⎯
VCC − 0.3
⎯
VCC + 0.3
V
MD pin*2
VILA
⎯
⎯
VSS − 0.3
⎯
0.5 VCC
V
Pin inputs if
Automotive input
levels are selected*1
V
Pin inputs if CMOS
hysteresis input
levels are selected*1
(0.8Vcc/0.2Vcc
CMOS hysteresis is
selected for P00,
P03 and P51)
VILS2
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
“L” level
input voltage
VILS1
⎯
⎯
VSS − 0.3
⎯
0.3 VCC
V
Pin inputs if 0.7Vcc/
0.3Vcc CMOS hysteresis input levels is
selected for P00,
P03 and P51.
VILR
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
RST input pin
(CMOS hysteresis)
VILM
⎯
⎯
VSS − 0.3
⎯
VSS + 0.3
V
MD pin*2
(Continued)
38
MB90925 Series
(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
Pin name
Unit
Remarks
Typ
Max
Operating frequency
FCP = 16 MHz,
normal operation
⎯
35
45
mA
Operating frequency
FCP = 16 MHz,
writing Flash memory
⎯
50
60
mA
Operating frequency
FCP = 16 MHz,
erasing Flash memory
⎯
50
60
Flash
mA memory
product
ICCS
Operating frequency
FCP = 16 MHz,
sleep mode
⎯
12
20
mA
ICTS
Operating frequency
FCP = 2 MHz,
time-base timer mode
⎯
0.4
1.0
mA
ICTSPLL
Operating frequency
FCP = 16 MHz,
PLL timer mode,
External frequency = 4MHz
⎯
4
7
mA
ICCL
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
sub clock operation
⎯
90
200
µA
⎯
60
150
µA
Power supply
current*3
VCC
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
sub sleep operation
ICCLS
Input
capacitance 1
Value
Min
ICC
Input leakage
current
Conditions
ICCT
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
watch mode
⎯
60
130
µA
ICCH
TA = + 25 °C,
stop mode
⎯
50
130
µA
IIL
All input pins
VCC = DVCC = AVCC = 5.5 V
VSS < VI < VCC
−5
⎯
+5
µA
CIN1
Other than
VCC, VSS,
DVCC, DVSS,
AVCC, AVSS, C,
P70 to P77,
P80 to P87
⎯
⎯
5
15
pF
(Continued)
39
MB90925 Series
(Continued)
Parameter
(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Symbol
Pin name
Conditions
Input capacitance 2
CIN2
P70 to P77,
P80 to P87
Pull-up resistance
RUP
RDOWN
Pull-down resistance
Value
Unit
Min
Typ
Max
⎯
⎯
15
45
pF
RST
⎯
25
50
100
kΩ
MD2
⎯
25
50
100
kΩ
Remarks
Except Flash
memory product
Output “H”
voltage 1
VOH1
Other than
P70 to P77,
P80 to P87
VCC = 4.5 V
IOH = −4.0 mA
VCC −
0.5
⎯
⎯
V
Output “H”
voltage 2
VOH2
P70 to P77,
P80 to P87
VCC = 4.5 V
VCC −
IOH = −30.0 mA 0.5
⎯
⎯
V
Output “L”
voltage 1
VOL1
Other than
P70 to P77,
P80 to P87
VCC = 4.5 V
IOL = 4.0 mA
⎯
⎯
0.4
V
Output “L”
voltage 2
VOL2
P70 to P77,
P80 to P87
VCC = 4.5 V
IOL = 30.0 mA
⎯
⎯
0.55
V
∆VOH2
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
(n = 0 to 3)
VCC = 4.5 V
IOH = 30.0 mA
VOH2 maximum
variation
0
⎯
90
mV *4
Large current
output drive
capacity variation 2
∆VOL2
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
(n = 0 to 3)
VCC = 4.5 V
IOH = 30.0 mA
VOL2 maximum
variation
0
⎯
90
mV *4
LCD internal divider
resistance
RLCD
V0 to V3
⎯
50
100
200
kΩ
Large current
output drive
capacity variation 1
COM0 to COM3
output impedance
RVCOM
COMn
(n = 0 to 3)
⎯
⎯
⎯
2.5
kΩ
SEG0 to SEG31
output impedance
RVSEG
SEGn
(n = 0 to 31)
⎯
⎯
⎯
15
kΩ
ILCDC
V0 to V3
COMm
(m = 0 to 3)
SEGn
(n = 0 to 31)
⎯
−5.0
⎯
+5.0
µA
LCD leakage
current
*1 : All input pins except X0, X0A, MD0, MD1, and MD2.
*2 : MD0, MD1, and MD2 pins.
*3 : Power supply current values assume external clock feed from the X1 pin and X1A pin. Users must be aware
that power supply current levels differ depending on whether an external clock or oscillator is used.
*4 : Defined as maximum variation in VOH2/VOL2 with all ch.0 PWM1P0/PWM1M0/PWM2P0/PWM2M0 simultaneously
ON. Similarly for other channels.
40
MB90925 Series
4. AC Characteristics
(1) Clock timing
(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
FC
Base oscillation
clock frequency
Input clock
rise and fall time
Conditions
Value
Unit
Remarks
Min
Typ
Max
4
⎯
12
MHz 1/2 (when PLL stops)
4
⎯
12
MHz PLL x 1
4
⎯
8
MHz PLL x 2
4
⎯
5.33
MHz PLL x 3
4
⎯
4
MHz PLL x 4
X0, X1
FLC
X0A, X1A
⎯
32.768
⎯
kHz
tCYL
X0, X1
⎯
250
⎯
ns
tLCYL
X0A, X1A
⎯
30.5
⎯
µs
PWH, PWL
X0
10
⎯
⎯
ns
PWLH, PWLL
X0A
⎯
15.2
⎯
µs
tcr, tcf
X0, X0A
⎯
⎯
5
ns
FCP
⎯
2
⎯
16
MHz
FLCP
⎯
⎯
8.192
⎯
kHz Using sub clock
tCP
⎯
62.5
—
500
ns
Using main clock
(PLL clock)
tLCP
⎯
⎯
122.1
⎯
µs
Using sub clock
Base oscillation
clock cycle time
Input clock pulse
width
Pin name
Internal operating
clock frequency
Internal operating
clock cycle time
⎯
Use duty ratio of
40 to 60% as a guideline
external
clock signal
Using main clock
(PLL clock)
• X0 clock timing
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tcf
tcr
• X0A clock timing
tLCYL
0.8 VCC
X0A
0.2 VCC
PWLL
PWLH
tcf
tcr
41
MB90925 Series
• Range of guaranteed operation
Relation between internal operating clock frequency and power supply voltage
Power supply voltage VCC (V)
guaranteed operation range
5.5
Guaranteed A/D converter
operation range
4.0
3.7
Guaranteed PLL
operation range
2
4
16
Internal operating clock frequency FCP (MHz)
Note : The MB90F927/ MB90F927S enters reset mode at power supply voltage below 4 V ± 0.3 V.
Guaranteed oscillation
frequency range
Internal clock
fcp (MHz)
16
x4
x3
x2
12
x1
8
x 1/2
(PLL off)
4
2
4
8
External clock Fc (MHz)
42
12
16
MB90925 Series
(2) Reset input
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Value
Symbol Pin name
Reset input time
tRSTL
RST
Unit
Remarks
Min
Max
500
⎯
ns
At normal operation
Oscillator oscillation
time* + 100 µs
⎯
ms
At stop mode,
sub clock mode,
sub sleep mode, and watch mode
100
⎯
µs
At time-base timer mode
*: Oscillator’s oscillation time is the time that the amplitude reaches 90%. The oscillation time of a crystal oscillator
is between several ms and tens of ms. The oscillation time of a ceramic oscillator is between hundreds of µs
and several ms. The oscillation time of an external clock is 0 ms.
• At normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
tRSTL
RST
0.2 Vcc
X0
Internal
operation
clock
0.2 Vcc
90 % of
amplitude
Oscillator
oscillation time
100 µs
Oscillation stabilization wait time
Execution of the instruction
Internal
reset
43
MB90925 Series
(3) Power-on reset
(VSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
Power supply rise time
Pin
Conditions
name
tR
Power supply start voltage
VOFF
Power supply attained voltage
VON
Power supply cutoff time
tOFF
VCC
⎯
Value
Unit
Min
Max
0.05
30
ms
⎯
0.2
V
2.7
⎯
V
50
⎯
ms
Remarks
Waiting time until
power-on
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Note : Extreme variations in power supply voltage may activate a power-on reset. As the illustration below shows,
when varying power supply voltage during operation, the use of a smooth voltage rise with suppressed
fluctuation is recommended. Also in this situation, the PLL clock on the device should not be used, however
it is permissible to use the PLL clock during a voltage drop of 1V/s or less.
5.0 V
VCC
A rise slope of 50 mV/ms or
less is recommended
3.0 V
0V
44
VSS
RAM data hold
MB90925 Series
(4) SIO timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SO delay time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SCK ↑ → valid SI hold time
tSHIX
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK ↓ → SO delay time
tSLOV
Valid SI → SCK ↑
tIVSH
SCK ↑ → valid SI hold time
tSHIX
Parameter
Value
Conditions
Internal shift clock mode
output pin CL = 80 pF +
1TTL
SCK, SI
SCK
External shift clock mode
output pin CL = 80 pF +
1TTL
SCK, SO
SCK, SI
Unit
Min
Max
8 tCP
⎯
ns
−80
+ 80
ns
100
⎯
ns
60
⎯
ns
4 tCP
⎯
ns
4 tCP
⎯
ns
⎯
150
ns
60
⎯
ns
60
⎯
ns
Notes : • AC ratings are for CLK synchronous mode.
• CL is load capacitance connected to pin during testing.
• tCP is internal operating clock cycle time. Refer to “ (1) Clock timing”.
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
SI
tSHIX
0.8 VCC
0.8 VCC
0.5 VCC
0.5 VCC
• External shift clock mode
tSLSH
SCK
tSHSL
0.8 VCC
0.5 VCC
0.8 VCC
0.5 VCC
tSLOV
2.4 V
SO
0.8 V
tIVSH
SI
tSHIX
0.8 VCC
0.8 VCC
0.5 VCC
0.5 VCC
45
MB90925 Series
(5) UART0/1 (LIN/SCI)
• Bit setting: ESCR0/1:SCES=0, ECCR0/1:SCDE=0
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK0, SCK1
SCK ↓ → SOT delay time
tSLOVI
SCK0, SCK1,
SOT0, SOT1
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
Serial clock “L” pulse width
tSLSH
Serial clock “H” pulse width
tSHSL
SCK ↓ → SOT delay time
tSLOVE
Valid SIN → SCK ↑
tIVSHE
SCK ↑ → valid SIN hold time
tSHIXE
SCK fall time
tF
SCK rise time
tR
SCK0, SCK1,
SIN0, SIN1
Conditions
Internal shift clock
mode output pins are
CL = 80 pF + 1TTL
SCK0, SCK1
SCK0, SCK1,
SOT0, SOT1
SCK0, SCK1,
SIN0, SIN1
SCK0, SCK1
External shift clock
mode output pins are
CL = 80 pF + 1TTL
Value
Max
5 tCP
⎯
ns
− 50
+ 50
ns
tCP + 80
⎯
ns
0
⎯
ns
tCP + 10
⎯
ns
3 tCP − tR
⎯
ns
⎯
2 tCP + 60
ns
30
⎯
ns
tCP + 30
⎯
ns
⎯
10
ns
⎯
10
ns
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock). Refer to “ (1) Clock timing”.
46
Unit
Min
MB90925 Series
• Internal shift clock mode
SCK
tSLSH
tSHSL
VIH
VIH
VIL
tR
tSLOVE
tF
VIH
VIL
2.4 V
SOT
0.8 V
tIVSHE
SIN
tSHIXE
VIH
VIH
VIL
VIL
• External shift clock mode
SCK
tSLSH
tSHSL
VIH
VIH
VIL
tF
VIH
VIL
tR
tSLOVE
2.4 V
SOT
0.8 V
tIVSHE
SIN
tSHIXE
VIH
VIH
VIL
VIL
47
MB90925 Series
• Bit setting: ESCR0/1:SCES=1, ECCR0/1:SCDE=0
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
48
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK0, SCK1
SCK ↑ → SOT delay time
tSLOVI
SCK0, SCK1,
SOT0, SOT1
Valid SIN → SCK ↓
tIVSHI
SCK ↓ → valid SIN hold time
tSHIXI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK ↑ → SOT delay time
tSLOVE
Valid SIN → SCK ↓
tIVSHE
SCK ↓ → valid SIN hold time
tSHIX
SCK fall time
tF
SCK rise time
tR
SCK0, SCK1,
SIN0, SIN1
Conditions
Internal shift clock
mode output pins are
CL = 80 pF + 1TTL
SCK0, SCK1
SCK0, SCK1,
SOT0, SOT1
SCK0, SCK1,
SIN0, SIN1
SCK0, SCK1
External shift clock
mode output pins are
CL = 80 pF + 1TTL
Value
Unit
Min
Max
5 tCP
⎯
ns
− 50
+ 50
ns
tCP + 80
⎯
ns
0
⎯
ns
3 tCP − tR
⎯
ns
tCP + 10
⎯
ns
⎯
2 tCP + 60
ns
30
⎯
ns
tCP + 30
⎯
ns
⎯
10
ns
⎯
10
ns
MB90925 Series
• Internal shift clock mode
SCK
tSCYC
2.4 V
2.4 V
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
SIN
tSLIXI
VIH
VIH
VIL
VIL
• External shift clock mode
tSHSL
SCK
VIH
tSLSH
VIH
VIL
tR
VIL
VIL
tF
tSHOVE
2.4 V
SOT
0.8 V
tIVSLE
SIN
tSLIXE
VIH
VIH
VIL
VIL
49
MB90925 Series
• Bit setting: ESCR0/1:SCES=0, ECCR0/1:SCDE=1
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK0, SCK1
SCK ↑ → SOT delay time
tSHOVI
SCK0, SCK1,
SOT0, SOT1
Valid SIN → SCK ↓
tIVSLI
SCK ↓ → valid SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
SCK0, SCK1,
SIN0, SIN1
Conditions
Internal clock operation
output pins are
CL = 80 pF + 1TTL
SCK0, SCK1,
SOT0, SOT1
Value
Max
5 tCP
⎯
ns
− 50
+ 50
ns
tCP + 80
⎯
ns
0
⎯
ns
3 tCP − 70
⎯
ns
Notes : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing”rating for tCP.
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSHOVI
tSOVLI
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SIN
50
tSLIXI
VIH
VIH
VIL
VIL
Unit
Min
MB90925 Series
• Bit setting: ESCR0/1:SCES=1, ECCR0/1:SCDE=1
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK0, SCK1
SCK ↓ → SOT delay time
tSLOVI
SCK0, SCK1,
SOT0, SOT1
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
SCK0, SCK1,
SIN0, SIN1
Conditions
Internal clock operation
output pins are
CL = 80 pF + 1TTL
SCK0, SCK1,
SOT0, SOT1
Value
Unit
Min
Max
5 tCP
⎯
ns
− 50
+ 50
ns
tCP + 80
⎯
ns
0
⎯
ns
3 tCP − 70
⎯
ns
Notes : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing”rating for tCP.
tSCYC
SCK
2.4 V
2.4 V
0.8 V
tSLOVI
tSOVHI
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSHI
SIN
tSHIXI
VIH
VIH
VIL
VIL
51
MB90925 Series
(6) Timer input timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH
tTIWL
TIN0, TIN1,
IN0 to IN3
⎯
Note : tCP is internal operating clock cycle time. Refer to “ (1) Clock timing”.
• Timer input timing
tTIWH
TIN0 , TIN1
IN0 to IN3
52
VIH
tTIWL
VIH
VIL
VIL
Value
Min
Max
4 tCP
⎯
Unit
ns
MB90925 Series
(7) Trigger input timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH,
tTRGL
INT0 to INT7
ADTG
Value
Unit
Min
Max
⎯
200
⎯
ns
⎯
tCP + 200
⎯
ns
Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock timing”.
• Trigger input timing
VIH
VIH
INT0 to INT7
VIL
VIL
tTRGH
tTRGL
53
MB90925 Series
(8) Low voltage detection
(VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol Pin name Conditions
Value
Min
Typ
Max
Remarks
Detection voltage
VDL
VCC
⎯
3.7
4.0
4.3
V
During voltage
drop
Hysteresis width
VHYS
VCC
⎯
0.1
⎯
⎯
V
During voltage
rise
Power supply voltage
fluctuation ratio
dV/dt
VCC
⎯
−0.1
⎯
+0.02
V/µs
Detection delay time
td
⎯
⎯
⎯
⎯
35
µs
Internal reset
VCC
dV
dt
VHYS
Vni
td
54
Unit
td
MB90925 Series
5. A/D Converter
(1) Electrical Characteristics
(VCC = AVCC = 5.0 V±10%, 3.0V ≤ AVRH-AVss, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
Pin name
Resolution
⎯
Total error
Value
Unit
Remarks
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
⎯
⎯
±3.0
LSB
Non-linear error
⎯
⎯
⎯
⎯
±2.5
LSB
Differential linear error
⎯
⎯
⎯
⎯
±1.9
LSB
Zero transition voltage
VOT
AN0 to AN7
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
V
Full scale transition
voltage
VFST
AN0 to AN7
AVRH −
3.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB
V
Sampling time
tSMP
⎯
⎯
16500
µs
Compare time
tCMP
⎯
⎯
⎯
µs
Analog port
input current
IAIN
AN0 to AN7
− 0.3
⎯
+0.3
µA
Analog input voltage
VAIN
AN0 to AN7
AVss
⎯
AVRH
V
AVRH
AVRH
AVss+2.7
⎯
AVCC
V
⎯
3.5
7.5
mA
⎯
⎯
5
µA
*
Reference voltage
Power supply current
IA
IAH
AVCC
1.4
2.0
0.5
1.2
1 LSB =
(AVRH − AVSS) /
1024
4.5 V ≤ AVcc ≤ 5.5 V
4.0 V ≤ AVcc ≤ 4.5 V
4.5 V ≤ AVcc ≤ 5.5 V
4.0 V ≤ AVcc ≤ 4.5 V
Reference voltage
supply current
IR
AVRH
⎯
600
900
µA
VAVRH = 5.0 V
IRH
AVRH
⎯
⎯
5
µA
*
Inter-channel variation
—
AN0 to AN7
⎯
⎯
4
LSB
* : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in
stop mode.
55
MB90925 Series
• Notes of the external impedance of the analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
MB90F927/MB90F927S
R
4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max)
C
16.0 pF (Max)
16.0 pF (Max)
MB90V925-101/102
4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max)
14.4 pF (Max)
14.4 pF (Max)
Note : The values are reference values.
56
MB90925 Series
• The relationship between the external impedance and minimum sampling time
• At 4.5 V ≤ AVcc ≤ 5.5 V
(External impedance = 0 kΩ to 20 kΩ)
MB90V925-101/102
100
90
80
70
60
50
40
30
20
10
0
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
MB90F927/F927S
0
5
10
15
20
25
30
35
MB90V925-101/102
20
18
16
14
12
10
8
6
4
2
0
MB90F927/F927S
0
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
Minimum sampling time [µs]
• At 4.0 V ≤ AVcc ≤ 4.5 V
(External impedance = 0 kΩ to 20 kΩ)
MB90V925-101/102
100
90
80
70
60
50
40
30
20
10
0
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
MB90F927/F927S
0
5
10
15
20
25
30
Minimum sampling time [µs]
35
MB90V925-101/102
20
18
16
14
12
10
8
6
4
2
0
MB90F927/F927S
0
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
• About errors
As |AVRH - AVSS| becomes smaller, values of relative errors grow larger.
57
MB90925 Series
(2) Definition of terms
Resolution :
Analog changes that are identifiable with the A/D converter.
Non-Linear error : The deviation of the straight line connecting the zero transition point
(“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point
(“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics.
Differential linear error : The deviation of input voltage needed to change the output code by 1 LSB from the
ideal value.
Total error :
The total error is defined as a difference between the actual value and the theoretical value,
which includes zero-transition error/full-scale transition error and linear error.
Total error
Digital output
3FFH
3FEH
3FDH
Actual conversion
value
1.5 LSB
{1 LSB x (N - 1) + 0.5 LSB}
004H
VNT
003H
Actual conversion
value
002H
(Measured value)
Ideal
characteristics
001H
0.5 LSB
AVSS
AVRH
Analog input
Total error for digital output N =
1 LSB(Ideal) =
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVRH − AVSS [V]
1024
[LSB]
N : A/D converter digital output value
VOT (Ideal) = AVss + 0.5 LSB [V]
VFST (Ideal) = AVRH − 1.5 LSB [V]
VNT : Voltage at a transition of digital output from (N - 1)H to NH
(Continued)
58
MB90925 Series
(Continued)
Non-Linear error
VFST
(Measured
value)
VNT
004H
(Measured value)
003H
V(N + 1)T
N - 1H
AVRH
AVss
AVRH
AVss
(Measured
value)
(Measured value)
Actual conversion
value
N - 2H
Ideal
characteristics
VOT (Measured value)
001H
NH
VNT
Actual conversion
value
002H
Actual conversion
value
N + 1H
Digital output
Digital output
Ideal
characteristics
Actual conversion
value
{1 LSB x (N -1)
+ VOT}
3FFH
3FEH
3FDH
Differential linear error
Analog input
Analog input
Non-Linear error of
digital output N
=
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
Differential linear error
V (N + 1) T − VNT
=
1 LSB
of digital output N
1 LSB =
VFST − VOT
1022
[LSB]
− 1 [LSB]
[V]
N
: A/D converter digital output value
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
6. Flash Memory Program/Erase Characteristics
Parameter
Chip erase time
Byte (8-bit width)
programming time
Erase/program cycle
Flash memory data
retention time
Conditions
Value
Unit
Remarks
Min
Typ
Max
⎯
1
15
s
Excludes pre-programming before
erase
⎯
32
3600
µs
Excludes system-level overhead
⎯
10000
⎯
⎯
cycle
Average
TA = + 85 °C
20
⎯
⎯
year *
TA = + 25 °C
VCC = 5.0 V
* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C)
59
MB90925 Series
■ ORDERING INFORMATION
Part number
60
Package
MB90F927PF-GE1
MB90F927SPF-GE1
100-pin plastic QFP
(FPT-100P-M06)
MB90F927PFV-GE1
MB90F927SPFV-GE1
100-pin plastic LQFP
(FPT-100P-M05)
MB90V925-101
MB90V925-102
299-pin ceramic PGA
(PGA-299C-A01)
Remarks
For evaluation
MB90925 Series
■ PACKAGE DIMENSIONS
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
M
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
2002 FUJITSU LIMITED F100008S-c-5-5
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
61
MB90925 Series
(Continued)
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.65g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M05)
100-pin plastic LQFP
(FPT-100P-M05)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
1
25
C
0.20±0.05
(.008±.002)
0.08(.003)
M
0.145±0.055
(.0057±.0022)
2003 FUJITSU LIMITED F100007S-c-4-6
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
62
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB90925 Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
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F0705