Cypress MB96330 F2mc-16fx 16-bit proprietary microcontroller Datasheet

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About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB96330 Series
F2MC-16FX 16-bit Proprietary
Microcontroller
MB96330 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The
CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new
16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the
same operation frequency, reduced power consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 48MHz
operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 20.8ns going together with
excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The
emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select
suitable operation frequencies for peripheral resources independent of the CPU speed.
Note: MB96F336 and MB96F338 devices are under development and specification is preliminary. These products under development
may change its specification without notice.
Features
Technology
■
On-chip voltage regulator
0.18m CMOS
■
CPU
Internal voltage regulator supports reduced internal MCU
voltage, offering low EMI and low power consumption figures
Low voltage reset
■
F2MC-16FX CPU
■
Up to 48 MHz internal, 20.8 ns instruction cycle time
■
Optimized instruction set for controller applications (bit, byte,
word and long-word data types; 23 different addressing modes;
barrel shift; variety of pointers)
■
Reset is generated when supply voltage is below minimum.
Code Security
■
Protects ROM content from unintended read-out
Memory Patch Function
■
8-byte instruction execution queue
■
Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit)
instructions available
System clock
■
Replaces ROM content
■
Can also be used to implement embedded debug support
DMA
■
On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
■
3 MHz - 16 MHz external crystal oscillator clock (maximum
frequency when using ceramic resonator depends on
Q-factor).
■
Automatic transfer function independent of CPU, can be
assigned freely to resources
Interrupts
■
Up to 48 MHz external clock
■
Fast Interrupt processing
■
32-100 kHz subsystem quartz clock
■
8 programmable priority levels
■
100kHz/2MHz internal RC clock for quick and safe startup,
oscillator stop detection, watchdog
■
Non-Maskable Interrupt (NMI)
■
Clock source selectable from main- and subclock oscillator
(part number suffix “W”) and on-chip RC oscillator,
independently for CPU and 2 clock domains of peripherals.
■
Low Power Consumption - 13 operating modes : (different Run,
Sleep, Timer modes, Stop mode)
■
Clock modulator
Cypress Semiconductor Corporation
Document Number: 002-04586 Rev. *A
•
Timers
■
Three independent clock timers (23-bit RC clock timer, 23-bit
Main clock timer, 17-bit Sub clock timer)
■
Watchdog Timer
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 13, 2016
MB96330 Series
CAN
Input Capture Units
■
Supports CAN protocol version 2.0 part A and B
■
16-bit wide
■
ISO16845 certified
■
Signals an interrupt upon external event
■
Bit rates up to 1 Mbit/s
■
Rising edge, falling edge or rising & falling edge sensitive
■
32 message objects
Output Compare Units
■
Each message object has its own identifier mask
■
Programmable FIFO mode (concatenation of message
objects)
■
Maskable interrupt
■
Disabled Automatic Retransmission mode for Time Triggered
CAN applications
Programmable Pulse Generator
■
Programmable loop-back mode for self-test operation
■
16-bit down counter, cycle and duty setting registers
■
Interrupt at trigger, counter borrow and/or duty match
■
PWM operation and one-shot operation
■
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock
as counter clock and Reload timer overflow as clock input
■
Can be triggered by software or reload timer
USART
■
Full duplex USARTs (SCI/LIN)
■
Wide range of baud rate settings using a dedicated reload timer
■
Special synchronous options for adapting to different
synchronous serial protocols
■
LIN functionality working either as master or slave LIN device
I 2C
■
Up to 400 kbps
■
Master and Slave functionality, 8-bit and 10-bit addressing
A/D converter
■
SAR-type
■
10-bit resolution
■
Signals interrupt on conversion end, single conversion mode,
continuous conversion mode, stop conversion mode, activation
by software, external trigger or reload timer
Reload Timers
■
■
■
16-bit wide
1/21,
Prescaler with
clock frequency
1/22,
1/23,
1/24,
1/25,
1/26
16-bit wide
■
Signals an interrupt when a match with 16-bit I/O Timer occurs
■
A pair of compare registers can be used to generate an output
signal.
Real Time Clock
■
Can be clocked either from sub oscillator (devices with part
number suffix “W”), main oscillator or from the RC oscillator
■
Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)
■
Read/write accessible second/minute/hour registers
■
Can signal interrupts every half
second/second/minute/hour/day
■
Internal clock divider and prescaler provide exact 1s clock
External Interrupts
■
Edge sensitive or level sensitive
■
Interrupt mask and pending bit per channel
■
Each available CAN channel RX has an external interrupt for
wake-up
■
Selected USART channels SIN have an external interrupt for
wake-up
of peripheral
Event count function
Free Running Timers
■
■
Signals an interrupt on overflow, supports timer clear upon
match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22,
1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency
Document Number: 002-04586 Rev. *A
Non Maskable Interrupt
■
Disabled after reset
■
Once enabled, can not be disabled other than by reset.
■
Level high or level low sensitive
■
Pin shared with external interrupt 0.
Page 2 of 122
MB96330 Series
External bus interface
Package
■
8-bit or 16-bit bidirectional data
■
■
Up to 24-bit addresses
Flash Memory
■
6 chip select signals
■
Multiplexed address/data lines
■
Non-multiplexed address/data lines
■
Wait state request
■
External bus master possible
■
Timing programmable
Alarm comparator
■
Monitors an external voltage and generates an interrupt in case
of a voltage lower or higher than the defined thresholds
■
Threshold voltages defined externally or generated internally
■
Status is readable, interrupts can be masked separately
I/O Ports
■
Virtually all external pins can be used as general purpose I/O
■
All push-pull outputs (except when used as I2C SDA/SCL line)
■
Bit-wise programmable as input/output or peripheral signal
■
Bit-wise programmable input enable
■
Bit-wise programmable input levels: Automotive /
CMOS-Schmitt trigger / TTL
■
Bit-wise programmable pull-up resistor
■
Bit-wise programmable output driving strength for EMI
optimization
Document Number: 002-04586 Rev. *A
144-pin plastic LQFP M08
■
Supports automatic programming, Embedded Algorithm
■
Write/Erase/Erase-Suspend/Resume commands
■
A flag indicating completion of the algorithm
■
Number of erase cycles: 10,000 times
■
Data retention time: 20 years
■
Erase can be performed on each sector individually
■
Sector protection
■
Flash Security feature to protect the content of the Flash
■
Low voltage detection during Flash erase
USB
■
USB function (corresponds to USB Full Speed)
■
USB Mini-HOST function
■
Supports up to 6 endpoints
Page 3 of 122
MB96330 Series
Contents
Product Lineup ................................................................. 5
Block Diagram ................................................................. 7
Pin Assignments .............................................................. 9
Pin Function Description ............................................... 11
Pin Circuit Type .............................................................. 14
I/O Circuit Type ............................................................... 15
Memory Map .................................................................... 19
RAMSTART/END and External Bus End Addresses ... 20
User ROM Memory Map For Flash Devices ................ 21
Serial Programming Communication Interface ........... 22
I/O Map ............................................................................. 23
Interrupt Vector Table .................................................... 63
Handling Devices ............................................................ 68
Latch-up prevention ................................................... 68
Unused pins handling ................................................ 68
External clock usage ................................................. 68
Unused sub clock signal ............................................ 69
Notes on PLL clock mode operation ......................... 69
Power supply pins (VCC/VSS) .................................. 69
Crystal oscillator and ceramic resonator circuit ......... 69
Document Number: 002-04586 Rev. *A
Turn on sequence of power supply to
A/D converter and analog inputs ............................... 69
Pin handling when not using the A/D converter ........ 69
Notes on Power-on .................................................... 69
Stabilization of power supply voltage ........................ 70
Serial communication ................................................ 70
Electrical Characteristics ............................................... 71
Absolute Maximum Ratings ....................................... 71
Recommended Operating Conditions ....................... 74
DC characteristics ..................................................... 75
AC Characteristics ..................................................... 82
USB Characteristics ................................................ 103
Analog Digital Converter ......................................... 106
Alarm Comparator ................................................... 110
Low Voltage Detector characteristics ...................... 112
FLASH memory program/erase characteristics ...... 114
Example Characteristics .............................................. 115
Package Dimension MB96(F)33x LQFP 144P ............ 116
Ordering Information .................................................... 117
Revision History ........................................................... 118
Major Changes .............................................................. 120
Document History ......................................................... 121
Page 4 of 122
MB96330 Series
1. Product Lineup
Features
MB96V300
Product type
Evaluation sample
MB96(F)33xY/R
MB96(F)33xU
Flash product: MB96F33x
Mask ROM product: MB9633x
Product options
YS
Low voltage reset persistently on / Single clock devices
RS
Low voltage reset can be disabled / Single clock devices
YW
NA
RW
Low voltage reset persistently on / Dual clock devices
Low voltage reset can be disabled / Dual clock devices
US
USB / Low voltage reset can be disabled / Single clock devices
UW
USB / Low voltage reset can be disabled / Dual clock devices
Flash/ROM
RAM
288KB
24KB
544KB
32KB
ROM/Flash memory
emulation by
external RAM,
92KB internal RAM
MB96F336U *1
MB96F338Y *1,
MB96F338R *1
MB96F338U *1
Package
BGA416
FPT-144P-M08
DMA
16 channels
10 channels
USART
10 channels
8 channels
I2C
2 channels
A/D Converter
40 channels
40 channels
36 channels
A/D Converter Reference
Voltage switch
yes
No
16-bit Reload Timer
6 channels + 1
channel (for PPG)
4 channels + 1 channel (for PPG)
16-bit Free-Running Timer
4 channels
16-bit Output Compare
12 channels
16-bit Input Capture
10 channels
16-bit Programmable Pulse
Generator
20 channels
CAN Interface
5 channels
USB
No
3 channels (1 channel for MB96F336U)
No
1 channel
External Interrupts
16 channels
Non-Maskable Interrupt
1 channel
Real Time Clock
1
Document Number: 002-04586 Rev. *A
Page 5 of 122
MB96330 Series
Features
MB96V300
MB96(F)33xY/R
MB96(F)33xU
I/O Ports
136
122 for part number with suffix “W”,
124 for part number with suffix “S”
118 for part number with suffix “W”,
120 for part number with suffix “S”
Alarm comparator
2 channels
External bus interface
Yes
Chip select
6 signals
Clock output function
2 channels
Low voltage reset
Yes
On-chip RC-oscillator
Yes
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
Document Number: 002-04586 Rev. *A
Page 6 of 122
MB96330 Series
2. Block Diagram
Block diagram of MB96(F)33xY/R
AD00 ... AD15
A0 ... A23
ALE
RDX
WRLX/WRX, WRHX
HRQ
HAKX
RDY
ECLK
LBX, UBX
CS0 ... CS5, CS0_R ...CS5_R
External Bus
Interface
CKOT0, CKOT0_R, CKOT1, CKOT1_R
CKOTX0, CKOTX1, CKOTX1_R
X0, X1
X0A, X1A *1
RSTX
NMI, NMI_R
MD0...MD2
Interrupt
Controller
16FX
CPU
Flash
Memory A
Memory Patch
Unit
Clock &
Mode Controller
16FX Core Bus (CLKB)
SCL0, SCL1
Peripheral
Bus Bridge
Peripheral
Bus Bridge
I2C
2 ch.
AVCC
AVSS
AVRH
AVRL
AN0 ... AN39
ADTG, ADTG_R
10-bit ADC
40 ch.
TIN0 ... TIN3
TIN0_R, TIN2_R
TIN3_R
TOT0 ... TOT3
TOT0_R, TOT2_R
TOT3_R
16-bit Reload
Timer
4 ch.
FRCK0
IN0 ... IN3
OUT0 ... OUT3
I/O Timer 0
ICU 0-3
OCU 0-3
FRCK1
IN4 ... IN7
IN4_R, IN5_R
OUT4 ... OUT7
OUT6_R, OUT7_R
I/O Timer 1
ICU 4-7
OCU 4-7
FRCK2_R
IN8, IN9
OUT8, OUT9
I/O Timer 2
ICU 8,9
OCU 8,9
OUT10_R, OUT11
I/O Timer 3
OCU 10,11
INT0...INT15
INT0_R...INT15_R
INT3_R1, INT5_R1
External
Interrupt
Peripheral Bus 2 (CLKP2)
SDA0, SDA1
Watchdog
Peripheral Bus 1 (CLKP1)
DMA
Controller
10ch
USART
8 ch.
Alarm
Comparator
2 ch.
16-bit PPG
20 ch.
RLT6
Real Time
Clock
RAM
Boot ROM
Voltage
Regulator
VCC
VSS
C
CAN
Interface
3 ch.
TX0 ... TX2, TX2_R
RX0 ... RX2, RX2_R
SIN0...SIN3, SIN5, SIN9
SIN2_R, SIN7_R ... SIN9_R
SOT0...SOT3, SOT5, SOT9
SOT2_R, SOT7_R ... SOT9_R
SCK0...SCK3, SCK5
SCK2_R, SCK7_R ... SCK9_R
ALARM0
ALARM1
TTG0 ... TTG15, TTG18
TTG8_R ... TTG11_R, TTG16_R ... TTG19_R
PPG0 ... PPG19
PPG0_R ... PPG11_R, PPG16R ... PPG19_R
WOT
*1: Available only on devices with suffix “W”
Document Number: 002-04586 Rev. *A
Page 7 of 8
MB96330 Series
Block diagram of MB96(F)33xU
AD00 ... AD15
A0 ... A23
ALE
RDX
WRLX/WRX, WRHX
HRQ
HAKX
RDY
ECLK
LBX, UBX
CS0 ... CS5, CS0_R ...CS5_R
External Bus
Interface
CKOT0, CKOT0_R, CKOT1, CKOT1_R
CKOTX0, CKOTX1, CKOTX1_R
X0, X1
X0A, X1A *1
RSTX
NMI, NMI_R
MD0...MD2
Interrupt
Controller
16FX
CPU
Memory Patch
Unit
Flash
Memory A
Clock &
Mode Controller
16FX Core Bus (CLKB)
Peripheral
Bus Bridge
I2C
2 ch.
AVCC
AVSS
AVRH
AVRL
AN0 ... AN35
ADTG, ADTG_R
10-bit ADC
36 ch.
TIN0 ... TIN3
TIN0_R, TIN2_R
TIN3_R
TOT0 ... TOT3
TOT0_R, TOT2_R
TOT3_R
16-bit Reload
Timer
4 ch.
FRCK0
IN0 ... IN3
OUT0 ... OUT3
I/O Timer 0
ICU 0-3
OCU 0-3
FRCK1
IN4 ... IN7
IN4_R, IN5_R
OUT4 ... OUT7
OUT6_R, OUT7_R
I/O Timer 1
ICU 4-7
OCU 4-7
FRCK2_R
IN8, IN9
OUT8, OUT9
I/O Timer 2
ICU 8,9
OCU 8,9
OUT10_R, OUT11
I/O Timer 3
OCU 10,11
INT0...INT15
INT0_R...INT15_R
INT3_R1, INT5_R1
External
Interrupt
USART
8 ch.
Alarm
Comparator
2 ch.
16-bit PPG
20 ch.
RLT6
Real Time
Clock
Peripheral
Bus Bridge
Peripheral Bus 3 (CLK3)
SCL0, SCL1
Peripheral
Bus Bridge
Peripheral Bus 2 (CLKP2)
SDA0, SDA1
Watchdog
Peripheral Bus 1 (CLKP1)
DMA
Controller
10ch
CAN
Interface
3 ch. *2
RAM
Boot ROM
Voltage
Regulator
VCC
VSS
C
USB
UDP
UDM
HCONX
VCC3
TX0 ... TX2, TX2_R *2
RX0 ... RX2, RX2_R *2
SIN0...SIN3, SIN5, SIN9
SIN2_R, SIN7_R ... SIN9_R
SOT0...SOT3, SOT5, SOT9
SOT2_R, SOT7_R ... SOT9_R
SCK0...SCK3, SCK5
SCK2_R, SCK7_R ... SCK9_R
ALARM0
ALARM1
TTG0 ... TTG15, TTG18
TTG8_R ... TTG11_R, TTG16_R ... TTG19_R
PPG0 ... PPG19
PPG0_R ... PPG11_R, PPG16R ... PPG19_R
WOT
*1: Available only on devices with suffix “W”
*2 : CAN1 and CAN2 not available on MB96F336U
Document Number: 002-04586 Rev. *A
Page 8 of 8
MB96330 Series
3. Pin Assignments
110
71
111
70
112
69
113
68
114
67
115
66
116
65
117
64
118
63
119
62
120
61
121
60
122
59
123
58
LQFP - 144
124
125
57
56
126
55
127
54
Package code (mold)
FPT-144P-M08
128
129
130
53
52
51
Vcc
P15_7/AN39
P15_6/AN38
P15_5/AN37
P15_4/AN36
P15_3/AN35
P15_2/AN34
P15_1/AN33
P15_0/AN32
P14_7/AN31
P14_6/AN30
P14_5/AN29
P14_4/AN28
P14_3/AN27
P14_2/AN26
P14_1/AN25
P14_0/AN24
P07_7/AN23/INT7/SIN9_R
P07_6/AN22/INT6/SOT9_R
P07_5/AN21/INT5/SCK9_R
P07_4/AN20/INT4
P07_3/AN19/INT3
P07_2/AN18/INT2
P07_1/AN17/INT1
131
50
132
49
133
48
134
47
135
46
136
45
137
44
AVcc
138
P06_7/AN7/PPG7
139
43
42
140
41
141
40
142
39
143
38
37
144
5
6
7
8
P06_6/AN6/PPG6
P06_5/AN5/PPG5/CS5_R
P06_4/AN4/PPG4/CS4_R
P06_3/AN3/PPG3/CS3_R
P06_2/AN2/PPG2/CS2_R
Vss
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
P06_0/AN0/PPG0/CS0_R
4
P07_0/AN16/INT0/NMI
AVss
AVRL
AVRH
P06_1/AN1/PPG1/CS1_R
Vcc
3
P13_4/PPG16
2
Vss
C
P11_7/IN5_R/A3
P12_0/RX2_R/INT6_R/A4
P12_1/TX2_R/A5
P12_2/PPG0_R/A6
P12_3/PPG1_R/A7
P12_4/PPG2_R/A8
P12_5/PPG3_R/A9
P12_6/PPG4_R/A10
P12_7/PPG5_R/A11
P13_0/PPG6_R/A12
P13_1/PPG7_R/A13
P13_2/TIN3_R/A14
1
P13_5 / PPG17
P13_6/PPG18/IN8
P13_7/PPG19/IN9
P04_2/IN6/RX1/INT9_R/TTG6/TTG14
P04_3/IN7/TX1/TTG7/TTG15
P04_4/SDA0/FRCK0/TIN0_R
P04_5/SCL0/FRCK1/TIN2_R
P04_6/SDA1
P04_7/SCL1
P05_0/AN8/ALARM0/SIN2/INT3_R1
P05_1/AN9/ALARM1/SOT2
P05_2/AN10/SCK2
P05_3/AN11/TIN3/WOT
P05_4/AN12/TOT3/INT2_R
P05_5/AN13/INT0_R/NMI_R
P05_6/AN14/INT4_R
P05_7/AN15/INT5_R/OUT10_R
P03_6/RDY/OUT6
P03_7/ECLK/OUT7
P11_4/OUT6_R/A0
P11_5/OUT7_R/A1
P11_6/IN4_R/A2
Vcc
108
106
104
102
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
107
105
103
101
72
109
P13_3/TOT3_R/A15
Vss
P00_1/AD01/INT9/SOT7_R/TTG9_R
P00_2/AD02/INT10/SIN7_R/TTG10_R
P00_3/AD03/INT11/SCK8_R/TTG11_R
P00_4/AD04/INT12/SOT8_R/PPG8_R
P00_5/AD05/INT13/SIN8_R/PPG9_R
P00_6/AD06/INT14/PPG10_R
P00_7/AD07/INT15/PPG11_R
P01_0/AD08/TIN1/CKOT1/TTG16_R
P01_1/AD09/TOT1/CKOTX1/TTG17_R
P01_2/AD10/SIN3/INT11_R/TTG18_R
P01_3/AD11/SOT3/TTG19_R
P01_4/AD12/SCK3/PPG16_R
P01_5/AD13/SIN2_R/INT7_R/PPG17_R
P01_6/AD14/SOT2_R/PPG18_R
P01_7/AD15/SCK2_R/PPG19_R
P02_0/A16/PPG12/CKOT1_R
P02_1/A17/PPG13
P02_2/A18/PPG14/CKOT0_R
P02_3/A19/PPG15
P02_4/A20/IN0/TTG0/TTG8
P02_5/A21/IN1/TTG1/TTG9/ADTG_R
P02_6/A22/IN2/TTG2/TTG10
P02_7/A23/IN3/TTG3/TTG11
P03_0/ALE/IN4/TTG4/TTG12/TOT0_R
P03_1/RDX/IN5/TTG5/TTG13/TOT2_R
P03_2/WR(L)X/INT10_R/RX2
P03_3/WRHX/TX2
P03_4/HRQ/OUT4
P03_5/HAKX/OUT5
Vss
X1
X0
MD2
MD1
MD0
Vss
Vcc
P00_0/AD00/INT8/SCK7_R/TTG8_R
P09_7/OUT3/CS0
P09_6/OUT2/CS1
P09_5/OUT1/CS2
P09_4/OUT0/CS3
P09_3/PPG11/CS4/FRCK2_R
P09_2/PPG10/CS5
P09_1/PPG9/LBX
P09_0/PPG8/UBX
P17_6/OUT11/TTG18/INT3_R
P17_4/SOT9/OUT9
P17_3/SIN9/OUT8
P10_4/SIN5/INT5_R1
P10_3/SOT5
P10_2/SCK5
P10_1/TX0
P10_0/RX0/INT8_R
P08_7/SCK1
P08_6 / SOT1
P08_5/SIN1/INT1_R
P08_4/SCK0/INT15_R
P08_3/SOT0/TOT2
P08_2/SIN0/TIN2/INT14_R
P08_1/TOT0/INT13_R/CKOT0
P08_0/TIN0/ADTG/INT12_R/CKOTX0
RSTX
X1A/P04_1 *1
X0A/P04_0 *1
Pin assignment of M96F33xY/R (FPT-144P-M08)
*1: Devices with suffix W: X0A, X1A
Devices with suffix S: P04_0, P04_1
(FPT-144P-M08)
Document Number: 002-04586 Rev. *A
Page 9 of 122
MB96330 Series
110
71
111
70
112
69
113
68
114
67
115
66
116
65
117
64
118
63
119
62
120
61
121
60
122
59
123
58
LQFP - 144
124
125
57
56
126
55
127
54
Package code (mold)
FPT-144P-M08
128
129
130
53
52
51
131
50
132
49
133
48
134
47
135
46
136
45
Vcc
UDM
UDP
Vcc3
HCONX
P15_3/AN35
P15_2/AN34
P15_1/AN33
P15_0/AN32
P14_7/AN31
P14_6/AN30
P14_5/AN29
P14_4/AN28
P14_3/AN27
P14_2/AN26
P14_1/AN25
P14_0/AN24
P07_7/AN23/INT7/SIN9_R
P07_6/AN22/INT6/SOT9_R
P07_5/AN21/INT5/SCK9_R
P07_4/AN20/INT4
P07_3/AN19/INT3
P07_2/AN18/INT2
P07_1/AN17/INT1
P07_0/AN16/INT0/NMI
AVss
AVRL
AVRH
137
44
AVcc
138
P06_7/AN7/PPG7
139
43
42
140
41
141
40
142
39
143
38
37
144
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
*1: Devices with suffix W: X0A, X1A
Devices with suffix S: P04_0, P04_1
P06_0/AN0/PPG0/CS0_R
4
P06_6/AN6/PPG6
P06_5/AN5/PPG5/CS5_R
P06_4/AN4/PPG4/CS4_R
P06_3/AN3/PPG3/CS3_R
P06_2/AN2/PPG2/CS2_R
Vss
P06_1/AN1/PPG1/CS1_R
Vcc
3
P13_4/PPG16
2
Vss
C
P11_7/IN5_R/A3
*2
P12_0/RX2_R/INT6_R/A4
*2
P12_1/TX2_R/A5
P12_2/PPG0_R/A6
P12_3/PPG1_R/A7
P12_4/PPG2_R/A8
P12_5/PPG3_R/A9
P12_6/PPG4_R/A10
P12_7/PPG5_R/A11
P13_0/PPG6_R/A12
P13_1/PPG7_R/A13
P13_2/TIN3_R/A14
1
P13_5 / PPG17
P13_6/PPG18/IN8
P13_7/PPG19/IN9
*2
P04_2/IN6/RX1/INT9_R/TTG6/TTG14
*2
P04_3/IN7/TX1/TTG7/TTG15
P04_4/SDA0/FRCK0/TIN0_R
P04_5/SCL0/FRCK1/TIN2_R
P04_6/SDA1
P04_7/SCL1
P05_0/AN8/ALARM0/SIN2/INT3_R1
P05_1/AN9/ALARM1/SOT2
P05_2/AN10/SCK2
P05_3/AN11/TIN3/WOT
P05_4/AN12/TOT3/INT2_R
P05_5/AN13/INT0_R/NMI_R
P05_6/AN14/INT4_R
P05_7/AN15/INT5_R/OUT10_R
P03_6/RDY/OUT6
P03_7/ECLK/OUT7
P11_4/OUT6_R/A0
P11_5/OUT7_R/A1
P11_6/IN4_R/A2
Vcc
108
106
104
102
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
107
105
103
101
72
109
P13_3/TOT3_R/A15
Vss
P00_1/AD01/INT9/SOT7_R/TTG9_R
P00_2/AD02/INT10/SIN7_R/TTG10_R
P00_3/AD03/INT11/SCK8_R/TTG11_R
P00_4/AD04/INT12/SOT8_R/PPG8_R
P00_5/AD05/INT13/SIN8_R/PPG9_R
P00_6/AD06/INT14/PPG10_R
P00_7/AD07/INT15/PPG11_R
P01_0/AD08/TIN1/CKOT1/TTG16_R
P01_1/AD09/TOT1/CKOTX1/TTG17_R
P01_2/AD10/SIN3/INT11_R/TTG18_R
P01_3/AD11/SOT3/TTG19_R
P01_4/AD12/SCK3/PPG16_R
P01_5/AD13/SIN2_R/INT7_R/PPG17_R
P01_6/AD14/SOT2_R/PPG18_R
P01_7/AD15/SCK2_R/PPG19_R
P02_0/A16/PPG12/CKOT1_R
P02_1/A17/PPG13
P02_2/A18/PPG14/CKOT0_R
P02_3/A19/PPG15
P02_4/A20/IN0/TTG0/TTG8
P02_5/A21/IN1/TTG1/TTG9/ADTG_R
P02_6/A22/IN2/TTG2/TTG10
P02_7/A23/IN3/TTG3/TTG11
P03_0/ALE/IN4/TTG4/TTG12/TOT0_R
P03_1/RDX/IN5/TTG5/TTG13/TOT2_R
*2
P03_2/WR(L)X/INT10_R/RX2
*2
P03_3/WRHX/TX2
P03_4/HRQ/OUT4
P03_5/HAKX/OUT5
Vss
X1
X0
MD2
MD1
MD0
Vss
Vcc
P00_0/AD00/INT8/SCK7_R/TTG8_R
P09_7/OUT3/CS0
P09_6/OUT2/CS1
P09_5/OUT1/CS2
P09_4/OUT0/CS3
P09_3/PPG11/CS4/FRCK2_R
P09_2/PPG10/CS5
P09_1/PPG9/LBX
P09_0/PPG8/UBX
P17_6/OUT11/TTG18/INT3_R
P17_4/SOT9/OUT9
P17_3/SIN9/OUT8
P10_4/SIN5/INT5_R1
P10_3/SOT5
P10_2/SCK5
P10_1/TX0
P10_0/RX0/INT8_R
P08_7/SCK1
P08_6 / SOT1
P08_5/SIN1/INT1_R
P08_4/SCK0/INT15_R
P08_3/SOT0/TOT2
P08_2/SIN0/TIN2/INT14_R
P08_1/TOT0/INT13_R/CKOT0
P08_0/TIN0/ADTG/INT12_R/CKOTX0
RSTX
X1A/(P04_1) *1
X0A/(P04_0) *1
Pin assignment of MB96F33xU (FPT-144P-M08) USB device
*2: TX1, RX1, TX2, RX2, TX2_R, RX2_R not available on MB96F336U
(FPT-144P-M08)
Document Number: 002-04586 Rev. *A
Page 10 of 122
MB96330 Series
4. Pin Function Description
Pin Function description (1 of 3)
Pin name
Feature
Description
ADn
External bus
External bus interface (non multiplexed mode) data input/output. External
bus interface (multiplexed mode) address output and data input/output
ADTG
ADC
A/D converter trigger input
ADTG_R
ADC
Relocated A/D converter trigger input
ALARMn
Alarm comparator
Alarm Comparator n input
ALE
External bus
External bus Address Latch Enable output
An
External bus
External bus non-multiplexed address output
ANn
ADC
A/D converter channel n input
AVCC
Supply
Analog circuits power supply
AVRH
ADC
A/D converter high reference voltage input
AVRL
ADC
A/D converter low reference voltage input
AVSS
Supply
Analog circuits power supply
C
Voltage regulator
Internally regulated power supply stabilization capacitor pin
CKOTn
Clock output function
Clock Output function n output
CKOTn_R
Clock output function
Relocated Clock Output function n output
CKOTXn
Clock output function
Clock Output function n inverted output
CKOTXn_R
Clock output function
Relocated Clock Output function n inverted output
ECLK
External bus
External bus clock output
CSn
External bus
External bus chip select n output
CSn_R
External bus
Relocated External bus chip select n output
FRCKn
Free Running Timer
Free Running Timer n input
FRCKn_R
Free Running Timer
Relocated Free Running Timer n input
HAKX
External bus
External bus Hold Acknowledge
HCONX
USB
USB connection to host or hub
HRQ
External bus
External bus Hold Request
INn
ICU
Input Capture Unit n input
INn_R
ICU
Relocated Input Capture Unit n input
INTn
External Interrupt
External Interrupt n input
INTn_R
External Interrupt
Relocated External Interrupt n input
LBX
External bus
External Bus Interface Lower Byte select strobe output
Document Number: 002-04586 Rev. *A
Page 11 of 122
MB96330 Series
Pin Function description (2 of 3)
Pin name
Feature
Description
MDn
Core
Input pins for specifying the operating mode.
NMI
External Interrupt
Non-Maskable Interrupt input
NMI_R
External Interrupt
Relocated Non-Maskable Interrupt input
OUTn
OCU
Output Compare Unit n waveform output
OUTn_R
OCU
Relocated Output Compare Unit n waveform output
Pxx_n
GPIO
General purpose IO
PPGn
PPG
Programmable Pulse Generator n output
PPGn_R
PPG
Relocated Programmable Pulse Generator n output
RDX
External bus
External bus interface read strobe output
RDY
External bus
External bus interface external wait state request input
RSTX
Core
Reset input
RXn
CAN
CAN interface n RX input
RXn_R
CAN
Relocated CAN interface n RX input
SCKn
USART
USART n serial clock input/output
SCKn_R
USART
Relocated USART n serial clock input/output
SCLn
I2C
I2C interface n clock I/O input/output
SDAn
I2C
I2C interface n serial data I/O input/output
SINn
USART
USART n serial data input
SINn_R
USART
Relocated USART n serial data input
SOTn
USART
USART n serial data output
SOTn_R
USART
Relocated USART n serial data output
TINn
Reload Timer
Reload Timer n event input
TINn_R
Reload Timer
Relocated Reload Timer n event input
TOTn
Reload Timer
Reload Timer n output
TOTn_R
Reload Timer
Relocated Reload Timer n output
TTGn
PPG
Programmable Pulse Generator n trigger input
TTGn_R
PPG
Relocated Programmable Pulse Generator n trigger input
TXn
CAN
CAN interface n TX output
TXn_R
CAN
Relocated CAN interface n TX output
UBX
External bus
External Bus Interface Upper Byte select strobe output
UDM
USB
USB minus
Document Number: 002-04586 Rev. *A
Page 12 of 122
MB96330 Series
Pin Function description (3 of 3)
Pin name
Feature
Description
UDP
USB
USB plus
VCC
Supply
Power supply
VCC3
Supply
USB Power supply
VSS
Supply
Power supply
WOT
RTC
Real Timer clock output
WRHX
External bus
External bus High byte write strobe output
WRLX/WRX
External bus
External bus Low byte / Word write strobe output
X0
Clock
Oscillator input
X0A
Clock
Subclock Oscillator input (only for devices with suffix “W”)
X1
Clock
Oscillator output
X1A
Clock
Subclock Oscillator output (only for devices with suffix “W”)
Document Number: 002-04586 Rev. *A
Page 13 of 122
MB96330 Series
5. Pin Circuit Type
FPT-144P-M08
Circuit type *1
Pin no.
MB96(F)33xY/R
MB96(F)33xU (USB device)
1
Supply
2
F
3 to 21
H
22 to 25
N
26 to 35
I
36, 37
Supply
38 to 43
I
44
Supply
45
G
46 to 47
Supply
48 to 67
I
68
I
O
69
I
Supply (3.3V)
70, 71
I
P
72, 73
Supply
74 to 76
C
77, 78
A
79
Supply
80, 81
B *2
80, 81
H *3
82
E
83 to 107
H
108, 109
Supply
110 to 143
H
144
Supply
*1: Please refer to 6.“I/O Circuit Type” for details on the I/O circuit types
*2: Devices with suffix “W”
*3: Devices without suffix “W”
Document Number: 002-04586 Rev. *A
Page 14 of 122
MB96330 Series
6. I/O Circuit Type
Type
Circuit
Remarks
X1
R
A
0
MRFBE
Xout
1
FCI
R
High-speed oscillation circuit:
• Programmable between oscillation mode (external
crystal or resonator connected to X0/X1 pins) and
Fast external Clock Input (FCI) mode (external clock
connected to X0 pin)
• Programmable feedback resistor = approx.
2 * 0.5 M. Feedback resistor is grounded in the
center when the oscillator is disabled or in FCI mode
X0
FCI or osc disable
Xout
X1A
R
B
Low-speed oscillation circuit:
• Programmable feedback resistor = approx.20MΩ
(X1A: 19.5MΩ, X0A: 0.5MΩ) Feedback resistor is
grounded in the center when the oscillator is
disabled
SRFBE
R
X0A
osc disable
C
E
R
Hysteresis
inputs
• Mask ROM and EVA device:
CMOS Hysteresis input pin
• Flash device:
CMOS input pin
• CMOS Hysteresis input pin
• Pull-up resistor value: approx. 50 k
Pull-up
Resistor
R
Document Number: 002-04586 Rev. *A
Hysteresis
inputs
Page 15 of 122
MB96330 Series
Type
Circuit
Remarks
F
• Power supply input protection circuit
ANE
G
AVR
• A/D converter ref+ (AVRH) power supply input pin
with protection circuit
• Flash devices do not have a protection circuit against
VCC for pins AVRH
ANE
pull-up control
Pout
Nout
R
H
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
Document Number: 002-04586 Rev. *A
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50k approx.
Page 16 of 122
MB96330 Series
Type
Circuit
Remarks
Pull-up control
Pout
Nout
R
I
Hysteresis input
Standby control
for input shutdown
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function.
• Programmable pull-up resistor: 50k approx.
• Analog input
Analog input
pull-up control
Pout
Nout
R
N
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
Document Number: 002-04586 Rev. *A
• CMOS level output (IOL = 3mA, IOH = -3mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50k approx.
Page 17 of 122
MB96330 Series
Type
Circuit
Remarks
pull-up control
Pout (Always disabled)
Nout
R
O
Standby control for
input shutdown
Hysteresis input
Standby control for
input shutdown
Hysteresis input
Standby control for
input shutdown
Automotive inputs
Standby control for
input shutdown
TTL input
HCONX
• Available only for device with suffix “U”
Analog input
D+ Input
D- Input
D+
P
D-
Differential
Input
USB IO cell: UDP and UDM
• Available only for device with suffix “U”
Direction
D+ output
D- output
Document Number: 002-04586 Rev. *A
Page 18 of 122
MB96330 Series
7. Memory Map
MB96V300B
MB96(F)33x
FF:FFFFH
USER ROM /
Emulation ROM
External Bus*4
DE:0000H
External Bus
External Bus
Boot-ROM
Boot-ROM
10:0000H
0F:E000H
Reserved
0E:0000H
Reserved
External RAM
02:0000H
Internal RAM
bank 1
RAMEND1*2
RAMSTART12
01:0000H
ROM/RAM MIRROR
Reserved
Internal RAM
bank 1
Reserved
RAM availability depending on the device
ROM/RAM MIRROR
00:8000H
Internal RAM
Internal RAM
RAMSTART0
bank 0
RAMSTART0*
00:0C00H
*2
bank 0
Reserved
External Bus end
address*2
External Bus
External Bus
Peripherals
Peripherals
GPR*1
GPR*1
DMA
DMA
External Bus
External Bus
Peripheral
Peripheral
00:0380H
00:0180H
00:0100H
00:00F0H
00:0000H
*1: Unused GPR banks can be used as RAM area
*2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page.
*3: For EVA device, RAMSTART0 depends on the configuration of the emulated device.
*4: For details about USER ROM area, see the 9.“User ROM Memory Map For Flash Devices” on the following
pages.
The External Bus area and DMA area are only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
Document Number: 002-04586 Rev. *A
Page 19 of 122
MB96330 Series
8. RAMSTART/END and External Bus End Addresses
Devices
Bank 0 RAM Bank 1 RAM External Bus end
size
size
address
RAMSTART0
RAMSTART1
RAMEND1
MB96F336
24KByte
-
00:11FFH
00:2240H
-
-
MB96F338, MB96338
28KByte
4kB
00:11FFH
00:1240H
01:8000H
01:8FFFH
Document Number: 002-04586 Rev. *A
Page 20 of 122
MB96330 Series
9. User ROM Memory Map For Flash Devices
Alternative mode
CPU address
Flash memory
mode address
FF:FFFFH
FF:0000H
FE:FFFFH
FE:0000H
FD:FFFFH
FD:0000H
FC:FFFFH
FC:0000H
FB:FFFFH
FB:0000H
FA:FFFFH
FA:0000H
F9:FFFFH
F9:0000H
F8:FFFFH
F8:0000H
F7:FFFFH
F7:0000H
F6:FFFFH
F6:0000H
F5:FFFFH
F5:0000H
F4:FFFFH
F4:0000H
F3:FFFFH
F3:0000H
F2:FFFFH
F2:0000H
F1:FFFFH
F1:0000H
F0:FFFFH
F0:0000H
E0:FFFFH
3F:FFFFH
3F:0000H
3E:FFFFH
3E:0000H
3D:FFFFH
3D:0000H
3C:FFFFH
3C:0000H
3B:FFFFH
3B:0000H
3A:FFFFH
3A:0000H
39:FFFFH
39:0000H
38:FFFFH
38:0000H
37:FFFFH
37:0000H
36:FFFFH
36:0000H
35:FFFFH
35:0000H
34:FFFFH
34:0000H
33:FFFFH
33:0000H
32:FFFFH
32:0000H
31:FFFFH
31:0000H
30:FFFFH
30:0000H
E0:0000H
DF:FFFFH
DF:8000H
DF:7FFFH
DF:6000H
DF:5FFFH
DF:4000H
DF:3FFFH
DF:2000H
DF:1FFFH
DF:0000H
DE:FFFFH
DE:0000H
1F:7FFFH
1F:6000H
1F:5FFFH
1F:4000H
1F:3FFFH
1F:2000H
1F:1FFFH
1F:0000H
MB96F336U
MB96F338Y
MB96F338R
MB96F338U
Flash size
288kByte
Flash size
544kByte
S39 - 64K
S39 - 64K
S38 - 64K
S38 - 64K
S37 - 64K
S37 - 64K
S36 - 64K
S36 - 64K
S35 - 64K
Flash A
S34 - 64K
S33 - 64K
S32 - 64K
External bus
External bus
Reserved
Reserved
SA3 - 8K
SA3 - 8K
SA2 - 8K
SA2 - 8K
SA1 - 8K
SA1 - 8K
SA0 - 8K *1
SA0 - 8K *1
Reserved
Reserved
Flash A
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
Document Number: 002-04586 Rev. *A
Page 21 of 122
MB96330 Series
10. Serial Programming Communication Interface
USART pins for Flash serial programming (MD[2:0] = 010)
MB96F33x
Pin number
USART Number
Normal function
LQFP-144
85
86
SIN0
USART0
SOT0
87
SCK0
88
SIN1
89
USART1
SOT1
90
SCK1
26
SIN2
27
28
USART2
SOT2
SCK2
Note: If a Flash programmer and its software needs to use a handshaking pin, Cypress suggests to the tool vendor to support at least
port P00_1 on pin 110.
If handshaking is used by the tool but P00_1 is not available in customer’s application, Cypress suggests to the customer to
check the tool manual or to contact the tool vendor for alternative handshaking pins.
Document Number: 002-04586 Rev. *A
Page 22 of 122
MB96330 Series
11. I/O Map
I/O map MB96(F)33x (1 of 40)
Abbreviation
8-bit access
Abbreviation
16-bit access
Address
Register
000000H
I/O Port P00 - Port Data Register
PDR00
R/W
000001H
I/O Port P01 - Port Data Register
PDR01
R/W
000002H
I/O Port P02 - Port Data Register
PDR02
R/W
000003H
I/O Port P03 - Port Data Register
PDR03
R/W
000004H
I/O Port P04 - Port Data Register
PDR04
R/W
000005H
I/O Port P05 - Port Data Register
PDR05
R/W
000006H
I/O Port P06 - Port Data Register
PDR06
R/W
000007H
I/O Port P07 - Port Data Register
PDR07
R/W
000008H
I/O Port P08 - Port Data Register
PDR08
R/W
000009H
I/O Port P09 - Port Data Register
PDR09
R/W
00000AH
I/O Port P10 - Port Data Register
PDR10
R/W
00000BH
I/O Port P11 - Port Data Register
PDR11
R/W
00000CH
I/O Port P12 - Port Data Register
PDR12
R/W
00000DH
I/O Port P13 - Port Data Register
PDR13
R/W
00000EH
I/O Port P14 - Port Data Register
PDR14
R/W
00000FH
I/O Port P15 - Port Data Register
PDR15
R/W
000010H
Reserved
000011H
I/O Port P17 - Port Data Register
000012H000017H
Reserved
000018H
ADC0 - Control Status register Low
ADCSL
000019H
ADC0 - Control Status register High
ADCSH
00001AH
ADC0 - Data Register Low
ADCRL
00001BH
ADC0 - Data Register High
ADCRH
00001CH
ADC0 - Setting Register
00001DH
ADC0 - Setting Register
00001EH
ADC0 - Extended Configuration Register
00001FH
Reserved
000020H
FRT0 - Data register of free-running timer
000021H
FRT0 - Data register of free-running timer
Document Number: 002-04586 Rev. *A
Access
PDR17
R/W
ADCS
R/W
R/W
ADCR
R
R
ADSR
R/W
R/W
ADECR
R/W
TCDT0
R/W
R/W
Page 23 of 122
MB96330 Series
I/O map MB96(F)33x (2 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
TCCS0
R/W
000022H
FRT0 - Control status register of free-running timer Low
TCCSL0
000023H
FRT0 - Control status register of free-running timer High
TCCSH0
000024H
FRT1 - Data register of free-running timer
000025H
FRT1 - Data register of free-running timer
000026H
FRT1 - Control status register of free-running timer Low
TCCSL1
000027H
FRT1 - Control status register of free-running timer High
TCCSH1
R/W
000028H
OCU0 - Output Compare Control Status
OCS0
R/W
000029H
OCU1 - Output Compare Control Status
OCS1
R/W
00002AH
OCU0 - Compare Register
00002BH
OCU0 - Compare Register
00002CH
OCU1 - Compare Register
00002DH
OCU1 - Compare Register
00002EH
OCU2 - Output Compare Control Status
OCS2
R/W
00002FH
OCU3 - Output Compare Control Status
OCS3
R/W
000030H
OCU2 - Compare Register
000031H
OCU2 - Compare Register
000032H
OCU3 - Compare Register
000033H
OCU3 - Compare Register
000034H
OCU4 - Output Compare Control Status
OCS4
R/W
000035H
OCU5 - Output Compare Control Status
OCS5
R/W
000036H
OCU4 - Compare Register
000037H
OCU4 - Compare Register
000038H
OCU5 - Compare Register
000039H
OCU5 - Compare Register
00003AH
OCU6 - Output Compare Control Status
OCS6
R/W
00003BH
OCU7 - Output Compare Control Status
OCS7
R/W
00003CH
OCU6 - Compare Register
00003DH
OCU6 - Compare Register
00003EH
OCU7 - Compare Register
00003FH
OCU7 - Compare Register
Document Number: 002-04586 Rev. *A
R/W
TCDT1
R/W
R/W
TCCS1
OCCP0
R/W
R/W
R/W
OCCP1
R/W
R/W
OCCP2
R/W
R/W
OCCP3
R/W
R/W
OCCP4
R/W
R/W
OCCP5
R/W
R/W
OCCP6
R/W
R/W
OCCP7
R/W
R/W
Page 24 of 122
MB96330 Series
I/O map MB96(F)33x (3 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000040H
ICU0/ICU1 - Control Status Register
ICS01
R/W
000041H
ICU0/ICU1 - Edge register
ICE01
R/W
000042H
ICU0 - Capture Register Low
IPCPL0
000043H
ICU0 - Capture Register High
IPCPH0
000044H
ICU1 - Capture Register Low
IPCPL1
000045H
ICU1 - Capture Register High
IPCPH1
R
000046H
ICU2/ICU3 - Control Status Register
ICS23
R/W
000047H
ICU2/ICU3 - Edge register
ICE23
R/W
000048H
ICU2 - Capture Register Low
IPCPL2
000049H
ICU2 - Capture Register High
IPCPH2
00004AH
ICU3 - Capture Register Low
IPCPL3
00004BH
ICU3 - Capture Register High
IPCPH3
R
00004CH
ICU4/ICU5 - Control Status Register
ICS45
R/W
00004DH
ICU4/ICU5 - Edge register
ICE45
R/W
00004EH
ICU4 - Capture Register Low
IPCPL4
00004FH
ICU4 - Capture Register High
IPCPH4
000050H
ICU5 - Capture Register Low
IPCPL5
000051H
ICU5 - Capture Register High
IPCPH5
R
000052H
ICU6/ICU7 - Control Status Register
ICS67
R/W
000053H
ICU6/ICU7 - Edge register
ICE67
R/W
000054H
ICU6 - Capture Register Low
IPCPL6
000055H
ICU6 - Capture Register High
IPCPH6
000056H
ICU7 - Capture Register Low
IPCPL7
000057H
ICU7 - Capture Register High
IPCPH7
R
000058H
EXTINT0 - External Interrupt Enable Register
ENIR0
R/W
000059H
EXTINT0 - External Interrupt Interrupt request Register
EIRR0
R/W
00005AH
EXTINT0 - External Interrupt Level Select Low
ELVRL0
00005BH
EXTINT0 - External Interrupt Level Select High
ELVRH0
R/W
00005CH
EXTINT1 - External Interrupt Enable Register
ENIR1
R/W
00005DH
EXTINT1 - External Interrupt Interrupt request Register
EIRR1
R/W
Document Number: 002-04586 Rev. *A
IPCP0
R
R
IPCP1
IPCP2
R
R
R
IPCP3
IPCP4
R
R
R
IPCP5
IPCP6
R
R
R
IPCP7
ELVR0
R
R/W
Page 25 of 122
MB96330 Series
I/O map MB96(F)33x (4 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
ELVR1
R/W
00005EH
EXTINT1 - External Interrupt Level Select Low
ELVRL1
00005FH
EXTINT1 - External Interrupt Level Select High
ELVRH1
000060H
RLT0 - Timer Control Status Register Low
TMCSRL0
000061H
RLT0 - Timer Control Status Register High
TMCSRH0
000062H
RLT0 - Reload Register - for writing
TMRLR0
W
000062H
RLT0 - Reload Register - for reading
TMR0
R
000063H
RLT0 - Reload Register - for writing
W
000063H
RLT0 - Reload Register - for reading
R
000064H
RLT1 - Timer Control Status Register Low
TMCSRL1
000065H
RLT1 - Timer Control Status Register High
TMCSRH1
000066H
RLT1 - Reload Register - for writing
TMRLR1
W
000066H
RLT1 - Reload Register - for reading
TMR1
R
000067H
RLT1 - Reload Register - for writing
W
000067H
RLT1 - Reload Register - for reading
R
000068H
RLT2 - Timer Control Status Register Low
TMCSRL2
000069H
RLT2 - Timer Control Status Register High
TMCSRH2
00006AH
RLT2 - Reload Register - for writing
TMRLR2
W
00006AH
RLT2 - Reload Register - for reading
TMR2
R
00006BH
RLT2 - Reload Register - for writing
W
00006BH
RLT2 - Reload Register - for reading
R
00006CH
RLT3 - Timer Control Status Register Low
TMCSRL3
00006DH
RLT3 - Timer Control Status Register High
TMCSRH3
00006EH
RLT3 - Reload Register - for writing
TMRLR3
W
00006EH
RLT3 - Reload Register - for reading
TMR3
R
00006FH
RLT3 - Reload Register - for writing
W
00006FH
RLT3 - Reload Register - for reading
R
000070H
RLT6 - Timer Control Status Register Low (dedic. RLT for
PPG)
TMCSRL6
000071H
RLT6 - Timer Control Status Register High (dedic. RLT for
PPG)
TMCSRH6
000072H
RLT6 - Reload Register (dedic. RLT for PPG) - for writing
Document Number: 002-04586 Rev. *A
R/W
TMCSR0
R/W
R/W
TMCSR1
R/W
R/W
TMCSR2
R/W
R/W
TMCSR3
R/W
R/W
TMCSR6
R/W
R/W
TMRLR6
W
Page 26 of 122
MB96330 Series
I/O map MB96(F)33x (5 of 40)
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
TMR6
R
Address
Register
000072H
RLT6 - Reload Register (dedic. RLT for PPG) - for reading
000073H
RLT6 - Reload Register (dedic. RLT for PPG) - for writing
W
000073H
RLT6 - Reload Register (dedic. RLT for PPG) - for reading
R
000074H
PPG3-PPG0 - General Control register 1 Low
GCN1L0
000075H
PPG3-PPG0 - General Control register 1 High
GCN1H0
000076H
PPG3-PPG0 - General Control register 2 Low
GCN2L0
000077H
PPG3-PPG0 - General Control register 2 High
GCN2H0
000078H
PPG0 - Timer register
000079H
PPG0 - Timer register
00007AH
PPG0 - Period setting register
00007BH
PPG0 - Period setting register
00007CH
PPG0 - Duty cycle register
00007DH
PPG0 - Duty cycle register
00007EH
PPG0 - Control status register Low
PCNL0
00007FH
PPG0 - Control status register High
PCNH0
000080H
PPG1 - Timer register
000081H
PPG1 - Timer register
000082H
PPG1 - Period setting register
000083H
PPG1 - Period setting register
000084H
PPG1 - Duty cycle register
000085H
PPG1 - Duty cycle register
000086H
PPG1 - Control status register Low
PCNL1
000087H
PPG1 - Control status register High
PCNH1
000088H
PPG2 - Timer register
000089H
PPG2 - Timer register
00008AH
PPG2 - Period setting register
00008BH
PPG2 - Period setting register
00008CH
PPG2 - Duty cycle register
00008DH
PPG2 - Duty cycle register
00008EH
PPG2 - Control status register Low
Document Number: 002-04586 Rev. *A
GCN10
R/W
R/W
GCN20
R/W
R/W
PTMR0
R
R
PCSR0
W
W
PDUT0
W
W
PCN0
R/W
R/W
PTMR1
R
R
PCSR1
W
W
PDUT1
W
W
PCN1
R/W
R/W
PTMR2
R
R
PCSR2
W
W
PDUT2
W
W
PCNL2
PCN2
R/W
Page 27 of 122
MB96330 Series
I/O map MB96(F)33x (6 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
00008FH
PPG2 - Control status register High
000090H
PPG3 - Timer register
000091H
PPG3 - Timer register
000092H
PPG3 - Period setting register
000093H
PPG3 - Period setting register
000094H
PPG3 - Duty cycle register
000095H
PPG3 - Duty cycle register
000096H
PPG3 - Control status register Low
PCNL3
000097H
PPG3 - Control status register High
PCNH3
000098H
PPG7-PPG4 - General Control register 1 Low
GCN1L1
000099H
PPG7-PPG4 - General Control register 1 High
GCN1H1
00009AH
PPG7-PPG4 - General Control register 2 Low
GCN2L1
00009BH
PPG7-PPG4 - General Control register 2 High
GCN2H1
00009CH
PPG4 - Timer register
00009DH
PPG4 - Timer register
00009EH
PPG4 - Period setting register
00009FH
PPG4 - Period setting register
0000A0H
PPG4 - Duty cycle register
0000A1H
PPG4 - Duty cycle register
0000A2H
PPG4 - Control status register Low
PCNL4
0000A3H
PPG4 - Control status register High
PCNH4
0000A4H
PPG5 - Timer register
0000A5H
PPG5 - Timer register
0000A6H
PPG5 - Period setting register
0000A7H
PPG5 - Period setting register
0000A8H
PPG5 - Duty cycle register
0000A9H
PPG5 - Duty cycle register
0000AAH
PPG5 - Control status register Low
PCNL5
0000ABH
PPG5 - Control status register High
PCNH5
R/W
0000ACH
I2C0 - Bus Status Register
IBSR0
R
Document Number: 002-04586 Rev. *A
PCNH2
Access
R/W
PTMR3
R
R
PCSR3
W
W
PDUT3
W
W
PCN3
R/W
R/W
GCN11
R/W
R/W
GCN21
R/W
R/W
PTMR4
R
R
PCSR4
W
W
PDUT4
W
W
PCN4
R/W
R/W
PTMR5
R
R
PCSR5
W
W
PDUT5
W
W
PCN5
R/W
Page 28 of 122
MB96330 Series
I/O map MB96(F)33x (7 of 40)
Address
Register
Abbreviation
8-bit access
0000ADH
I2C0 - Bus Control Register
IBCR0
0000AEH
I2C0 - Ten bit Slave address Register Low
ITBAL0
2
Abbreviation
16-bit access
Access
R/W
ITBA0
R/W
0000AFH
I C0 - Ten bit Slave address Register High
ITBAH0
0000B0H
I2C0 - Ten bit Address mask Register Low
ITMKL0
0000B1H
I2C0 - Ten bit Address mask Register High
ITMKH0
R/W
0000B2H
I2C0 - Seven bit Slave address Register
ISBA0
R/W
0000B3H
I2C0
ISMK0
R/W
0000B4H
I2C0 - Data Register
IDAR0
R/W
0000B5H
I2C0 - Clock Control Register
ICCR0
R/W
0000B6H
I2C1 - Bus Status Register
IBSR1
R
0000B7H
I2C1
IBCR1
R/W
0000B8H
I2C1 - Ten bit Slave address Register Low
ITBAL1
0000B9H
I2C1 - Ten bit Slave address Register High
ITBAH1
0000BAH
I2C1 - Ten bit Address mask Register Low
ITMKL1
0000BBH
I2C1
ITMKH1
R/W
0000BCH
I2C1 - Seven bit Slave address Register
ISBA1
R/W
0000BDH
I2C1 - Seven bit Address mask Register
ISMK1
R/W
0000BEH
I2C1 - Data Register
IDAR1
R/W
0000BFH
I2C1
ICCR1
R/W
0000C0H
USART0 - Serial Mode Register
SMR0
R/W
0000C1H
USART0 - Serial Control Register
SCR0
R/W
0000C2H
USART0 - TX Register
TDR0
W
0000C2H
USART0 - RX Register
RDR0
R
0000C3H
USART0 - Serial Status
SSR0
R/W
0000C4H
USART0 - Control/Com. Register
ECCR0
R/W
0000C5H
USART0 - Ext. Status Register
ESCR0
R/W
0000C6H
USART0 - Baud Rate Generator Register Low
BGRL0
0000C7H
USART0 - Baud Rate Generator Register High
BGRH0
R/W
0000C8H
USART0 - Extended Serial Interrupt Register
ESIR0
R/W
0000C9H
Reserved
- Seven bit Address mask Register
- Bus Control Register
- Ten bit Address mask Register High
- Clock Control Register
Document Number: 002-04586 Rev. *A
R/W
ITMK0
ITBA1
R/W
R/W
R/W
ITMK1
BGR0
R/W
R/W
-
Page 29 of 122
MB96330 Series
I/O map MB96(F)33x (8 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0000CAH
USART1 - Serial Mode Register
SMR1
R/W
0000CBH
USART1 - Serial Control Register
SCR1
R/W
0000CCH
USART1 - TX Register
TDR1
W
0000CCH
USART1 - RX Register
RDR1
R
0000CDH
USART1 - Serial Status
SSR1
R/W
0000CEH
USART1 - Control/Com. Register
ECCR1
R/W
0000CFH
USART1 - Ext. Status Register
ESCR1
R/W
0000D0H
USART1 - Baud Rate Generator Register Low
BGRL1
0000D1H
USART1 - Baud Rate Generator Register High
BGRH1
R/W
0000D2H
USART1 - Extended Serial Interrupt Register
ESIR1
R/W
0000D3H
Reserved
0000D4H
USART2 - Serial Mode Register
SMR2
R/W
0000D5H
USART2 - Serial Control Register
SCR2
R/W
0000D6H
USART2 - TX Register
TDR2
W
0000D6H
USART2 - RX Register
RDR2
R
0000D7H
USART2 - Serial Status
SSR2
R/W
0000D8H
USART2 - Control/Com. Register
ECCR2
R/W
0000D9H
USART2 - Ext. Status Register
ESCR2
R/W
0000DAH
USART2 - Baud Rate Generator Register Low
BGRL2
0000DBH
USART2 - Baud Rate Generator Register High
BGRH2
R/W
0000DCH
USART2 - Extended Serial Interrupt Register
ESIR2
R/W
0000DDH
Reserved
0000DEH
USART3 - Serial Mode Register
SMR3
R/W
0000DFH
USART3 - Serial Control Register
SCR3
R/W
0000E0H
USART3 - TX Register
TDR3
W
0000E0H
USART3 - RX Register
RDR3
R
0000E1H
USART3 - Serial Status
SSR3
R/W
0000E2H
USART3 - Control/Com. Register
ECCR3
R/W
0000E3H
USART3 - Ext. Status Register
ESCR3
R/W
0000E4H
USART3 - Baud Rate Generator Register Low
BGRL3
Document Number: 002-04586 Rev. *A
BGR1
R/W
-
BGR2
R/W
-
BGR3
R/W
Page 30 of 122
MB96330 Series
I/O map MB96(F)33x (9 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0000E5H
USART3 - Baud Rate Generator Register High
BGRH3
R/W
0000E6H
USART3 - Extended Serial Interrupt Register
ESIR3
R/W
0000E7H0000EFH
Reserved
0000F0H-000
0FFH
External Bus area
EXTBUS0
R/W
000100H
DMA0 - Buffer address pointer low byte
BAPL0
R/W
000101H
DMA0 - Buffer address pointer middle byte
BAPM0
R/W
000102H
DMA0 - Buffer address pointer high byte
BAPH0
R/W
000103H
DMA0 - DMA control register
DMACS0
R/W
000104H
DMA0 - I/O register address pointer low byte
IOAL0
000105H
DMA0 - I/O register address pointer high byte
IOAH0
000106H
DMA0 - Data counter low byte
DCTL0
000107H
DMA0 - Data counter high byte
DCTH0
R/W
000108H
DMA1 - Buffer address pointer low byte
BAPL1
R/W
000109H
DMA1 - Buffer address pointer middle byte
BAPM1
R/W
00010AH
DMA1 - Buffer address pointer high byte
BAPH1
R/W
00010BH
DMA1 - DMA control register
DMACS1
R/W
00010CH
DMA1 - I/O register address pointer low byte
IOAL1
00010DH
DMA1 - I/O register address pointer high byte
IOAH1
00010EH
DMA1 - Data counter low byte
DCTL1
00010FH
DMA1 - Data counter high byte
DCTH1
R/W
000110H
DMA2 - Buffer address pointer low byte
BAPL2
R/W
000111H
DMA2 - Buffer address pointer middle byte
BAPM2
R/W
000112H
DMA2 - Buffer address pointer high byte
BAPH2
R/W
000113H
DMA2 - DMA control register
DMACS2
R/W
000114H
DMA2 - I/O register address pointer low byte
IOAL2
000115H
DMA2 - I/O register address pointer high byte
IOAH2
000116H
DMA2 - Data counter low byte
DCTL2
000117H
DMA2 - Data counter high byte
DCTH2
R/W
000118H
DMA3 - Buffer address pointer low byte
BAPL3
R/W
Document Number: 002-04586 Rev. *A
IOA0
R/W
R/W
DCT0
IOA1
R/W
R/W
R/W
DCT1
IOA2
R/W
R/W
R/W
DCT2
R/W
Page 31 of 122
MB96330 Series
I/O map MB96(F)33x (10 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000119H
DMA3 - Buffer address pointer middle byte
BAPM3
R/W
00011AH
DMA3 - Buffer address pointer high byte
BAPH3
R/W
00011BH
DMA3 - DMA control register
DMACS3
R/W
00011CH
DMA3 - I/O register address pointer low byte
IOAL3
00011DH
DMA3 - I/O register address pointer high byte
IOAH3
00011EH
DMA3 - Data counter low byte
DCTL3
00011FH
DMA3 - Data counter high byte
DCTH3
R/W
000120H
DMA4 - Buffer address pointer low byte
BAPL4
R/W
000121H
DMA4 - Buffer address pointer middle byte
BAPM4
R/W
000122H
DMA4 - Buffer address pointer high byte
BAPH4
R/W
000123H
DMA4 - DMA control register
DMACS4
R/W
000124H
DMA4 - I/O register address pointer low byte
IOAL4
000125H
DMA4 - I/O register address pointer high byte
IOAH4
000126H
DMA4 - Data counter low byte
DCTL4
000127H
DMA4 - Data counter high byte
DCTH4
R/W
000128H
DMA5 - Buffer address pointer low byte
BAPL5
R/W
000129H
DMA5 - Buffer address pointer middle byte
BAPM5
R/W
00012AH
DMA5 - Buffer address pointer high byte
BAPH5
R/W
00012BH
DMA5 - DMA control register
DMACS5
R/W
00012CH
DMA5 - I/O register address pointer low byte
IOAL5
00012DH
DMA5 - I/O register address pointer high byte
IOAH5
00012EH
DMA5 - Data counter low byte
DCTL5
00012FH
DMA5 - Data counter high byte
DCTH5
R/W
000130H
DMA6 - Buffer address pointer low byte
BAPL6
R/W
000131H
DMA6 - Buffer address pointer middle byte
BAPM6
R/W
000132H
DMA6 - Buffer address pointer high byte
BAPH6
R/W
000133H
DMA6 - DMA control register
DMACS6
R/W
000134H
DMA6 - I/O register address pointer low byte
IOAL6
000135H
DMA6 - I/O register address pointer high byte
IOAH6
000136H
DMA6 - Data counter low byte
DCTL6
Document Number: 002-04586 Rev. *A
IOA3
R/W
R/W
DCT3
IOA4
R/W
R/W
R/W
DCT4
IOA5
R/W
R/W
R/W
DCT5
IOA6
R/W
R/W
R/W
DCT6
R/W
Page 32 of 122
MB96330 Series
I/O map MB96(F)33x (11 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000137H
DMA6 - Data counter high byte
DCTH6
R/W
000138H
DMA7 - Buffer address pointer low byte
BAPL7
R/W
000139H
DMA7 - Buffer address pointer middle byte
BAPM7
R/W
00013AH
DMA7 - Buffer address pointer high byte
BAPH7
R/W
00013BH
DMA7 - DMA control register
DMACS7
R/W
00013CH
DMA7 - I/O register address pointer low byte
IOAL7
00013DH
DMA7 - I/O register address pointer high byte
IOAH7
00013EH
DMA7 - Data counter low byte
DCTL7
00013FH
DMA7 - Data counter high byte
DCTH7
R/W
000140H
DMA8 - Buffer address pointer low byte
BAPL8
R/W
000141H
DMA8 - Buffer address pointer middle byte
BAPM8
R/W
000142H
DMA8 - Buffer address pointer high byte
BAPH8
R/W
000143H
DMA8 - DMA control register
DMACS8
R/W
000144H
DMA8 - I/O register address pointer low byte
IOAL8
000145H
DMA8 - I/O register address pointer high byte
IOAH8
000146H
DMA8 - Data counter low byte
DCTL8
000147H
DMA8 - Data counter high byte
DCTH8
R/W
000148H
DMA9 - Buffer address pointer low byte
BAPL9
R/W
000149H
DMA9 - Buffer address pointer middle byte
BAPM9
R/W
00014AH
DMA9 - Buffer address pointer high byte
BAPH9
R/W
00014BH
DMA9 - DMA control register
DMACS9
R/W
00014CH
DMA9 - I/O register address pointer low byte
IOAL9
00014DH
DMA9 - I/O register address pointer high byte
IOAH9
00014EH
DMA9 - Data counter low byte
DCTL9
00014FH
DMA9 - Data counter high byte
DCTH9
000150H00017FH
Reserved
000180H00037FH
CPU - General Purpose registers (RAM access)
000380H
000381H
IOA7
R/W
R/W
DCT7
IOA8
R/W
R/W
R/W
DCT8
IOA9
R/W
R/W
R/W
DCT9
R/W
R/W
-
GPR_RAM
R/W
DMA0 - Interrupt select
DISEL0
R/W
DMA1 - Interrupt select
DISEL1
R/W
Document Number: 002-04586 Rev. *A
Page 33 of 122
MB96330 Series
I/O map MB96(F)33x (12 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000382H
DMA2 - Interrupt select
DISEL2
R/W
000383H
DMA3 - Interrupt select
DISEL3
R/W
000384H
DMA4 - Interrupt select
DISEL4
R/W
000385H
DMA5 - Interrupt select
DISEL5
R/W
000386H
DMA6 - Interrupt select
DISEL6
R/W
000387H
DMA7 - Interrupt select
DISEL7
R/W
000388H
DMA8 - Interrupt select
DISEL8
R/W
000389H
DMA9 - Interrupt select
DISEL9
R/W
00038AH00038FH
Reserved
000390H
DMA - Status register low byte
DSRL
000391H
DMA - Status register high byte
DSRH
000392H
DMA - Stop status register low byte
DSSRL
000393H
DMA - Stop status register high byte
DSSRH
000394H
DMA - Enable register low byte
DERL
000395H
DMA - Enable register high byte
DERH
000396H00039FH
Reserved
0003A0H
Interrupt level register
ILR
0003A1H
Interrupt index register
IDX
0003A2H
Interrupt vector table base register Low
TBRL
0003A3H
Interrupt vector table base register High
TBRH
R/W
0003A4H
Delayed Interrupt register
DIRR
R/W
0003A5H
Non Maskable Interrupt register
NMI
R/W
0003A6H0003ABH
Reserved
0003ACH
EDSU communication interrupt selection Low
EDSU2L
0003ADH
EDSU communication interrupt selection High
EDSU2H
R/W
0003AEH
ROM mirror control register
ROMM
R/W
0003AFH
EDSU configuration register
EDSU
R/W
0003B0H
Memory patch control/status register ch 0/1
0003B1H
Memory patch control/status register ch 0/1
Document Number: 002-04586 Rev. *A
DSR
R/W
R/W
DSSR
R/W
R/W
DER
R/W
R/W
-
ICR
R/W
R/W
TBR
R/W
EDSU2
PFCS0
R/W
R/W
R/W
Page 34 of 122
MB96330 Series
I/O map MB96(F)33x (13 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
PFCS1
R/W
0003B2H
Memory patch control/status register ch 2/3
0003B3H
Memory patch control/status register ch 2/3
0003B4H
Memory patch control/status register ch 4/5
0003B5H
Memory patch control/status register ch 4/5
0003B6H
Memory patch control/status register ch 6/7
0003B7H
Memory patch control/status register ch 6/7
0003B8H
Memory Patch function - Patch address 0 low
PFAL0
R/W
0003B9H
Memory Patch function - Patch address 0 middle
PFAM0
R/W
0003BAH
Memory Patch function - Patch address 0 high
PFAH0
R/W
0003BBH
Memory Patch function - Patch address 1 low
PFAL1
R/W
0003BCH
Memory Patch function - Patch address 1 middle
PFAM1
R/W
0003BDH
Memory Patch function - Patch address 1 high
PFAH1
R/W
0003BEH
Memory Patch function - Patch address 2 low
PFAL2
R/W
0003BFH
Memory Patch function - Patch address 2 middle
PFAM2
R/W
0003C0H
Memory Patch function - Patch address 2 high
PFAH2
R/W
0003C1H
Memory Patch function - Patch address 3 low
PFAL3
R/W
0003C2H
Memory Patch function - Patch address 3 middle
PFAM3
R/W
0003C3H
Memory Patch function - Patch address 3 high
PFAH3
R/W
0003C4H
Memory Patch function - Patch address 4 low
PFAL4
R/W
0003C5H
Memory Patch function - Patch address 4 middle
PFAM4
R/W
0003C6H
Memory Patch function - Patch address 4 high
PFAH4
R/W
0003C7H
Memory Patch function - Patch address 5 low
PFAL5
R/W
0003C8H
Memory Patch function - Patch address 5 middle
PFAM5
R/W
0003C9H
Memory Patch function - Patch address 5 high
PFAH5
R/W
0003CAH
Memory Patch function - Patch address 6 low
PFAL6
R/W
0003CBH
Memory Patch function - Patch address 6 middle
PFAM6
R/W
0003CCH
Memory Patch function - Patch address 6 high
PFAH6
R/W
0003CDH
Memory Patch function - Patch address 7 low
PFAL7
R/W
0003CEH
Memory Patch function - Patch address 7 middle
PFAM7
R/W
0003CFH
Memory Patch function - Patch address 7 high
PFAH7
R/W
Document Number: 002-04586 Rev. *A
R/W
PFCS2
R/W
R/W
PFCS3
R/W
R/W
Page 35 of 122
MB96330 Series
I/O map MB96(F)33x (14 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
PFD0
R/W
0003D0H
Memory Patch function - Patch data 0 Low
PFDL0
0003D1H
Memory Patch function - Patch data 0 High
PFDH0
0003D2H
Memory Patch function - Patch data 1 Low
PFDL1
0003D3H
Memory Patch function - Patch data 1 High
PFDH1
0003D4H
Memory Patch function - Patch data 2 Low
PFDL2
0003D5H
Memory Patch function - Patch data 2 High
PFDH2
0003D6H
Memory Patch function - Patch data 3 Low
PFDL3
0003D7H
Memory Patch function - Patch data 3 High
PFDH3
0003D8H
Memory Patch function - Patch data 4 Low
PFDL4
0003D9H
Memory Patch function - Patch data 4 High
PFDH4
0003DAH
Memory Patch function - Patch data 5 Low
PFDL5
0003DBH
Memory Patch function - Patch data 5 High
PFDH5
0003DCH
Memory Patch function - Patch data 6 Low
PFDL6
0003DDH
Memory Patch function - Patch data 6 High
PFDH6
0003DEH
Memory Patch function - Patch data 7 Low
PFDL7
0003DFH
Memory Patch function - Patch data 7 High
PFDH7
0003E0H0003F0H
Reserved
0003F1H
Memory Control Status Register A
MCSRA
0003F2H
Memory Timing Configuration Register A Low
MTCRAL
0003F3H
Memory Timing Configuration Register A High
MTCRAH
0003F4H0003F8H
Reserved
0003F9H
Flash Memory Write Control register 1
FMWC1
R/W
0003FAH
Flash Memory Write Control register 2
FMWC2
R/W
0003FBH
Flash Memory Write Control register 3
FMWC3
R/W
0003FCH
Flash Memory Write Control register 4
FMWC4
R/W
0003FDH
Flash Memory Write Control register 5
FMWC5
R/W
0003FEH0003FFH
Reserved
000400H
Standby Mode control register
SMCR
R/W
000401H
Clock select register
CKSR
R/W
Document Number: 002-04586 Rev. *A
R/W
PFD1
R/W
R/W
PFD2
R/W
R/W
PFD3
R/W
R/W
PFD4
R/W
R/W
PFD5
R/W
R/W
PFD6
R/W
R/W
PFD7
R/W
R/W
R/W
MTCRA
R/W
R/W
-
-
Page 36 of 122
MB96330 Series
I/O map MB96(F)33x (15 of 40)
Abbreviation
8-bit access
Abbreviation
16-bit access
Address
Register
000402H
Clock Stabilization select register
CKSSR
R/W
000403H
Clock monitor register
CKMR
R
000404H
Clock Frequency control register Low
CKFCRL
000405H
Clock Frequency control register High
CKFCRH
000406H
PLL Control register Low
PLLCRL
000407H
PLL Control register High
PLLCRH
R/W
000408H
RC clock timer control register
RCTCR
R/W
000409H
Main clock timer control register
MCTCR
R/W
00040AH
Sub clock timer control register
SCTCR
R/W
00040BH
Reset cause and clock status register with clear function
RCCSRC
R
00040CH
Reset configuration register
RCR
R/W
00040DH
Reset cause and clock status register
RCCSR
R
00040EH
Watch dog timer configuration register
WDTC
R/W
00040FH
Watch dog timer clear pattern register
WDTCP
W
000410H000414H
Reserved
000415H
Clock output activation register
000416H
CKFCR
Access
R/W
R/W
PLLCR
R/W
COAR
R/W
Clock output configuration register 0
COCR0
R/W
000417H
Clock output configuration register 1
COCR1
R/W
000418H
Clock Modulator control register
CMCR
R/W
000419H
Reserved
00041AH
Clock Modulator Parameter register Low
CMPRL
00041BH
Clock Modulator Parameter register High
CMPRH
00041CH00042BH
Reserved
00042CH
Voltage Regulator Control register
VRCR
R/W
00042DH
Clock Input and LVD Control Register
CILCR
R/W
00042EH00042FH
Reserved
000430H
I/O Port P00 - Data Direction Register
DDR00
R/W
000431H
I/O Port P01 - Data Direction Register
DDR01
R/W
000432H
I/O Port P02 - Data Direction Register
DDR02
R/W
Document Number: 002-04586 Rev. *A
CMPR
R/W
R/W
-
-
Page 37 of 122
MB96330 Series
I/O map MB96(F)33x (16 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000433H
I/O Port P03 - Data Direction Register
DDR03
R/W
000434H
I/O Port P04 - Data Direction Register
DDR04
R/W
000435H
I/O Port P05 - Data Direction Register
DDR05
R/W
000436H
I/O Port P06 - Data Direction Register
DDR06
R/W
000437H
I/O Port P07 - Data Direction Register
DDR07
R/W
000438H
I/O Port P08 - Data Direction Register
DDR08
R/W
000439H
I/O Port P09 - Data Direction Register
DDR09
R/W
00043AH
I/O Port P10 - Data Direction Register
DDR10
R/W
00043BH
I/O Port P11 - Data Direction Register
DDR11
R/W
00043CH
I/O Port P12 - Data Direction Register
DDR12
R/W
00043DH
I/O Port P13 - Data Direction Register
DDR13
R/W
00043EH
I/O Port P14 - Data Direction Register
DDR14
R/W
00043FH
I/O Port P15 - Data Direction Register
DDR15
R/W
000440H
Reserved
000441H
I/O Port P17 - Data Direction Register
000442H000443H
Reserved
000444H
I/O Port P00 - Port Input Enable Register
PIER00
R/W
000445H
I/O Port P01 - Port Input Enable Register
PIER01
R/W
000446H
I/O Port P02 - Port Input Enable Register
PIER02
R/W
000447H
I/O Port P03 - Port Input Enable Register
PIER03
R/W
000448H
I/O Port P04 - Port Input Enable Register
PIER04
R/W
000449H
I/O Port P05 - Port Input Enable Register
PIER05
R/W
00044AH
I/O Port P06 - Port Input Enable Register
PIER06
R/W
00044BH
I/O Port P07 - Port Input Enable Register
PIER07
R/W
00044CH
I/O Port P08 - Port Input Enable Register
PIER08
R/W
00044DH
I/O Port P09 - Port Input Enable Register
PIER09
R/W
00044EH
I/O Port P10 - Port Input Enable Register
PIER10
R/W
00044FH
I/O Port P11 - Port Input Enable Register
PIER11
R/W
000450H
I/O Port P12 - Port Input Enable Register
PIER12
R/W
000451H
I/O Port P13 - Port Input Enable Register
PIER13
R/W
Document Number: 002-04586 Rev. *A
DDR17
R/W
-
Page 38 of 122
MB96330 Series
I/O map MB96(F)33x (17 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000452H
I/O Port P14 - Port Input Enable Register
PIER14
R/W
000453H
I/O Port P15 - Port Input Enable Register
PIER15
R/W
000454H
Reserved
000455H
I/O Port P17 - Port Input Enable Register
000456H000457H
Reserved
000458H
I/O Port P00 - Port Input Level Register
PILR00
R/W
000459H
I/O Port P01 - Port Input Level Register
PILR01
R/W
00045AH
I/O Port P02 - Port Input Level Register
PILR02
R/W
00045BH
I/O Port P03 - Port Input Level Register
PILR03
R/W
00045CH
I/O Port P04 - Port Input Level Register
PILR04
R/W
00045DH
I/O Port P05 - Port Input Level Register
PILR05
R/W
00045EH
I/O Port P06 - Port Input Level Register
PILR06
R/W
00045FH
I/O Port P07 - Port Input Level Register
PILR07
R/W
000460H
I/O Port P08 - Port Input Level Register
PILR08
R/W
000461H
I/O Port P09 - Port Input Level Register
PILR09
R/W
000462H
I/O Port P10 - Port Input Level Register
PILR10
R/W
000463H
I/O Port P11 - Port Input Level Register
PILR11
R/W
000464H
I/O Port P12 - Port Input Level Register
PILR12
R/W
000465H
I/O Port P13 - Port Input Level Register
PILR13
R/W
000466H
I/O Port P14 - Port Input Level Register
PILR14
R/W
000467H
I/O Port P15 - Port Input Level Register
PILR15
R/W
000468H
Reserved
000469H
I/O Port P17 - Port Input Level Register
00046AH00046BH
Reserved
00046CH
I/O Port P00 - Extended Port Input Level Register
EPILR00
R/W
00046DH
I/O Port P01 - Extended Port Input Level Register
EPILR01
R/W
00046EH
I/O Port P02 - Extended Port Input Level Register
EPILR02
R/W
00046FH
I/O Port P03 - Extended Port Input Level Register
EPILR03
R/W
000470H
I/O Port P04 - Extended Port Input Level Register
EPILR04
R/W
Document Number: 002-04586 Rev. *A
PIER17
R/W
-
PILR17
R/W
-
Page 39 of 122
MB96330 Series
I/O map MB96(F)33x (18 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000471H
I/O Port P05 - Extended Port Input Level Register
EPILR05
R/W
000472H
I/O Port P06 - Extended Port Input Level Register
EPILR06
R/W
000473H
I/O Port P07 - Extended Port Input Level Register
EPILR07
R/W
000474H
I/O Port P08 - Extended Port Input Level Register
EPILR08
R/W
000475H
I/O Port P09 - Extended Port Input Level Register
EPILR09
R/W
000476H
I/O Port P10 - Extended Port Input Level Register
EPILR10
R/W
000477H
I/O Port P11 - Extended Port Input Level Register
EPILR11
R/W
000478H
I/O Port P12 - Extended Port Input Level Register
EPILR12
R/W
000479H
I/O Port P13 - Extended Port Input Level Register
EPILR13
R/W
00047AH
I/O Port P14 - Extended Port Input Level Register
EPILR14
R/W
00047BH
I/O Port P15 - Extended Port Input Level Register
EPILR15
R/W
00047CH
Reserved
00047DH
I/O Port P17 - Extended Port Input Level Register
00047EH00047FH
Reserved
000480H
I/O Port P00 - Port Output Drive Register
PODR00
R/W
000481H
I/O Port P01 - Port Output Drive Register
PODR01
R/W
000482H
I/O Port P02 - Port Output Drive Register
PODR02
R/W
000483H
I/O Port P03 - Port Output Drive Register
PODR03
R/W
000484H
I/O Port P04 - Port Output Drive Register
PODR04
R/W
000485H
I/O Port P05 - Port Output Drive Register
PODR05
R/W
000486H
I/O Port P06 - Port Output Drive Register
PODR06
R/W
000487H
I/O Port P07 - Port Output Drive Register
PODR07
R/W
000488H
I/O Port P08 - Port Output Drive Register
PODR08
R/W
000489H
I/O Port P09 - Port Output Drive Register
PODR09
R/W
00048AH
I/O Port P10 - Port Output Drive Register
PODR10
R/W
00048BH
I/O Port P11 - Port Output Drive Register
PODR11
R/W
00048CH
I/O Port P12 - Port Output Drive Register
PODR12
R/W
00048DH
I/O Port P13 - Port Output Drive Register
PODR13
R/W
00048EH
I/O Port P14 - Port Output Drive Register
PODR14
R/W
00048FH
I/O Port P15 - Port Output Drive Register
PODR15
R/W
Document Number: 002-04586 Rev. *A
EPILR17
R/W
-
Page 40 of 122
MB96330 Series
I/O map MB96(F)33x (19 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000490H
Reserved
000491H
I/O Port P17 - Port Output Drive Register
000492H00049BH
Reserved
00049CH
I/O Port P08 - Port High Drive Register
PHDR08
R/W
00049DH
I/O Port P09 - Port High Drive Register
PHDR09
R/W
00049EH
I/O Port P10 - Port High Drive Register
PHDR10
R/W
00049FH0004A7H
Reserved
0004A8H
I/O Port P00 - Pull-Up resistor Control Register
PUCR00
R/W
0004A9H
I/O Port P01 - Pull-Up resistor Control Register
PUCR01
R/W
0004AAH
I/O Port P02 - Pull-Up resistor Control Register
PUCR02
R/W
0004ABH
I/O Port P03 - Pull-Up resistor Control Register
PUCR03
R/W
0004ACH
I/O Port P04 - Pull-Up resistor Control Register
PUCR04
R/W
0004ADH
I/O Port P05 - Pull-Up resistor Control Register
PUCR05
R/W
0004AEH
I/O Port P06 - Pull-Up resistor Control Register
PUCR06
R/W
0004AFH
I/O Port P07 - Pull-Up resistor Control Register
PUCR07
R/W
0004B0H
I/O Port P08 - Pull-Up resistor Control Register
PUCR08
R/W
0004B1H
I/O Port P09 - Pull-Up resistor Control Register
PUCR09
R/W
0004B2H
I/O Port P10 - Pull-Up resistor Control Register
PUCR10
R/W
0004B3H
I/O Port P11 - Pull-Up resistor Control Register
PUCR11
R/W
0004B4H
I/O Port P12 - Pull-Up resistor Control Register
PUCR12
R/W
0004B5H
I/O Port P13 - Pull-Up resistor Control Register
PUCR13
R/W
0004B6H
I/O Port P14 - Pull-Up resistor Control Register
PUCR14
R/W
0004B7H
I/O Port P15 - Pull-Up resistor Control Register
PUCR15
R/W
0004B8H
Reserved
0004B9H
I/O Port P17 - Pull-Up resistor Control Register
0004BAH0004BBH
Reserved
0004BCH
I/O Port P00 - External Pin State Register
EPSR00
R
0004BDH
I/O Port P01 - External Pin State Register
EPSR01
R
0004BEH
I/O Port P02 - External Pin State Register
EPSR02
R
Document Number: 002-04586 Rev. *A
PODR17
R/W
-
-
PUCR17
R/W
-
Page 41 of 122
MB96330 Series
I/O map MB96(F)33x (20 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0004BFH
I/O Port P03 - External Pin State Register
EPSR03
R
0004C0H
I/O Port P04 - External Pin State Register
EPSR04
R
0004C1H
I/O Port P05 - External Pin State Register
EPSR05
R
0004C2H
I/O Port P06 - External Pin State Register
EPSR06
R
0004C3H
I/O Port P07 - External Pin State Register
EPSR07
R
0004C4H
I/O Port P08 - External Pin State Register
EPSR08
R
0004C5H
I/O Port P09 - External Pin State Register
EPSR09
R
0004C6H
I/O Port P10 - External Pin State Register
EPSR10
R
0004C7H
I/O Port P11 - External Pin State Register
EPSR11
R
0004C8H
I/O Port P12 - External Pin State Register
EPSR12
R
0004C9H
I/O Port P13 - External Pin State Register
EPSR13
R
0004CAH
I/O Port P14 - External Pin State Register
EPSR14
R
0004CBH
I/O Port P15 - External Pin State Register
EPSR15
R
0004CCH
Reserved
0004CDH
I/O Port P17 - External Pin State Register
0004CEH0004CFH
Reserved
0004D0H
ADC analog input enable register 0
ADER0
R/W
0004D1H
ADC analog input enable register 1
ADER1
R/W
0004D2H
ADC analog input enable register 2
ADER2
R/W
0004D3H
ADC analog input enable register 3
ADER3
R/W
0004D4H
ADC analog input enable register 4
ADER4
R/W
0004D5H
Reserved
0004D6H
Peripheral Resource Relocation Register 0
PRRR0
R/W
0004D7H
Peripheral Resource Relocation Register 1
PRRR1
R/W
0004D8H
Peripheral Resource Relocation Register 2
PRRR2
R/W
0004D9H
Peripheral Resource Relocation Register 3
PRRR3
R/W
0004DAH
Peripheral Resource Relocation Register 4
PRRR4
R/W
0004DBH
Peripheral Resource Relocation Register 5
PRRR5
R/W
0004DCH
Peripheral Resource Relocation Register 6
PRRR6
R/W
0004DDH
Peripheral Resource Relocation Register 7
PRRR7
R/W
Document Number: 002-04586 Rev. *A
EPSR17
R
-
-
Page 42 of 122
MB96330 Series
I/O map MB96(F)33x (21 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0004DEH
Peripheral Resource Relocation Register 8
PRRR8
R/W
0004DFH
Peripheral Resource Relocation Register 9
PRRR9
R/W
0004E0H
RTC - Sub Second Register L
WTBRL0
0004E1H
RTC - Sub Second Register M
WTBRH0
R/W
0004E2H
RTC - Sub-Second Register H
WTBR1
R/W
0004E3H
RTC - Second Register
WTSR
R/W
0004E4H
RTC - Minutes
WTMR
R/W
0004E5H
RTC - Hour
WTHR
R/W
0004E6H
RTC - Timer Control Extended Register
WTCER
R/W
0004E7H
RTC - Clock select register
WTCKSR
R/W
0004E8H
RTC - Timer Control Register Low
WTCRL
0004E9H
RTC - Timer Control Register High
WTCRH
R/W
0004EAH
CAL - Calibration unit Control register
CUCR
R/W
0004EBH
Reserved
0004ECH
CAL - Duration Timer Data Register Low
CUTDL
0004EDH
CAL - Duration Timer Data Register High
CUTDH
0004EEH
CAL - Calibration Timer Register 2 Low
CUTR2L
0004EFH
CAL - Calibration Timer Register 2 High
CUTR2H
0004F0H
CAL - Calibration Timer Register 1 Low
CUTR1L
0004F1H
CAL - Calibration Timer Register 1 High
CUTR1H
0004F2H0004F9H
Reserved
0004FAH
RLT - Timer input select (for Cascading)
0004FBH0004FFH
Reserved
000500H
FRT2 - Data register of free-running timer
000501H
FRT2 - Data register of free-running timer
000502H
FRT2 - Control status register of free-running timer Low
TCCSL2
000503H
FRT2 - Control status register of free-running timer High
TCCSH2
000504H
FRT3 - Data register of free-running timer
000505H
FRT3 - Data register of free-running timer
Document Number: 002-04586 Rev. *A
WTBR0
WTCR
R/W
R/W
CUTD
R/W
R/W
CUTR2
R
R
CUTR1
R
R
-
TMISR
R/W
TCDT2
R/W
R/W
TCCS2
R/W
R/W
TCDT3
R/W
R/W
Page 43 of 122
MB96330 Series
I/O map MB96(F)33x (22 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
TCCS3
R/W
000506H
FRT3 - Control status register of free-running timer Low
TCCSL3
000507H
FRT3 - Control status register of free-running timer High
TCCSH3
R/W
000508H
OCU8 - Output Compare Control Status
OCS8
R/W
000509H
OCU9 - Output Compare Control Status
OCS9
R/W
00050AH
OCU8 - Compare Register
00050BH
OCU8 - Compare Register
00050CH
OCU9 - Compare Register
00050DH
OCU9 - Compare Register
00050EH
OCU10 - Output Compare Control Status
OCS10
R/W
00050FH
OCU11 - Output Compare Control Status
OCS11
R/W
000510H
OCU10 - Compare Register
000511H
OCU10 - Compare Register
000512H
OCU11 - Compare Register
000513H
OCU11 - Compare Register
000514H
ICU8/ICU9 - Control Status Register
ICS89
R/W
000515H
ICU8/ICU9 - Edge Register
ICE89
R/W
000516H
ICU8 - Capture Register Low
IPCPL8
000517H
ICU8 - Capture Register High
IPCPH8
000518H
ICU9 - Capture Register Low
IPCPL9
000519H
ICU9 - Capture Register High
IPCPH9
00051AH000529H
Reserved
00052AH
USART5 - Serial Mode Register
SMR5
R/W
00052BH
USART5 - Serial Control Register
SCR5
R/W
00052CH
USART5 - RX Register
TDR5
W
00052CH
USART5 - TX Register
RDR5
R
00052DH
USART5 - Serial Status
SSR5
R/W
00052EH
USART5 - Control/Com. Register
ECCR5
R/W
00052FH
USART5 - Ext. Status Register
ESCR5
R/W
000530H
USART5 - Baud Rate Generator Register Low
BGRL5
000531H
USART5 - Baud Rate Generator Register High
BGRH5
Document Number: 002-04586 Rev. *A
OCCP8
R/W
R/W
OCCP9
R/W
R/W
OCCP10
R/W
R/W
OCCP11
R/W
R/W
IPCP8
R
R
IPCP9
R
R
-
BGR5
R/W
R/W
Page 44 of 122
MB96330 Series
I/O map MB96(F)33x (23 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
000532H
USART5 - Extended Serial Interrupt Register
000533H00053DH
Reserved
00053EH
USART7 - Serial Mode Register
SMR7
R/W
00053FH
USART7 - Serial Control Register
SCR7
R/W
000540H
USART7 - Serial TX Register
TDR7
W
000540H
USART7 - Serial RX Register
RDR7
R
000541H
USART7 - Serial Status Register
SSR7
R/W
000542H
USART7 - Ext. Control/Com. Register
ECCR7
R/W
000543H
USART7 - Ext. Status Com. Register
ESCR7
R/W
000544H
USART7 - Baud Rate Generator Register Low
BGRL7
000545H
USART7 - Baud Rate Generator Register High
BGRH7
R/W
000546H
USART7 - Extended Serial Interrupt Register
ESIR7
R/W
000547H
Reserved
000548H
USART8 - Serial Mode Register
SMR8
R/W
000549H
USART8 - Serial Control Register
SCR8
R/W
00054AH
USART8 - Serial TX Register
TDR8
W
00054AH
USART8 - Serial RX Register
RDR8
R
00054BH
USART8 - Serial Status Register
SSR8
R/W
00054CH
USART8 - Ext. Control/Com. Register
ECCR8
R/W
00054DH
USART8 - Ext. Status Com. Register
ESCR8
R/W
00054EH
USART8 - Baud Rate Generator Register Low
BGRL8
00054FH
USART8 - Baud Rate Generator Register High
BGRH8
R/W
000550H
USART8 - Extended Serial Interrupt Register
ESIR8
R/W
000551H
Reserved
000552H
USART9 - Serial Mode Register
SMR9
R/W
000553H
USART9 - Serial Control Register
SCR9
R/W
000554H
USART9 - Serial TX Register
TDR9
W
000554H
USART9 - Serial RX Register
RDR9
R
000555H
USART9 - Serial Status Register
SSR9
R/W
000556H
USART9 - Ext. Control/Com. Register
ECCR9
R/W
Document Number: 002-04586 Rev. *A
ESIR5
Access
R/W
-
BGR7
R/W
-
BGR8
R/W
-
Page 45 of 122
MB96330 Series
I/O map MB96(F)33x (24 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000557H
USART9 - Ext. Status Com. Register
ESCR9
000558H
USART9 - Baud Rate Generator Register Low
BGRL9
000559H
USART9 - Baud Rate Generator Register High
BGRH9
R/W
00055AH
USART9 - Extended Serial Interrupt Register
ESIR9
R/W
00055BH00055FH
Reserved
000560H
ALARM0 - Control Status Register
000561H
ALARM0 - Extended Control Status Register
000562H
ALARM1 - Control Status Register
000563H
ALARM1 - Extended Control Status Register
000564H
PPG6 - Timer register
000565H
PPG6 - Timer register
000566H
PPG6 - Period setting register
000567H
PPG6 - Period setting register
000568H
PPG6 - Duty cycle register
000569H
PPG6 - Duty cycle register
00056AH
PPG6 - Control status register Low
PCNL6
00056BH
PPG6 - Control status register High
PCNH6
00056CH
PPG7 - Timer register
00056DH
PPG7 - Timer register
00056EH
PPG7 - Period setting register
00056FH
PPG7 - Period setting register
000570H
PPG7 - Duty cycle register
000571H
PPG7 - Duty cycle register
000572H
PPG7 - Control status register Low
PCNL7
000573H
PPG7 - Control status register High
PCNH7
000574H
PPG11-PPG8 - General Control register 1 Low
GCN1L2
000575H
PPG11-PPG8 - General Control register 1 High
GCN1H2
000576H
PPG11-PPG8 - General Control register 2 Low
GCN2L2
000577H
PPG11-PPG8 - General Control register 2 High
GCN2H2
000578H
PPG8 - Timer register
Document Number: 002-04586 Rev. *A
R/W
BGR9
R/W
ACSR0
R/W
AECSR0
R/W
ACSR1
R/W
AECSR1
R/W
PTMR6
R
R
PCSR6
W
W
PDUT6
W
W
PCN6
R/W
R/W
PTMR7
R
R
PCSR7
W
W
PDUT7
W
W
PCN7
R/W
R/W
GCN12
R/W
R/W
GCN22
R/W
R/W
PTMR8
R
Page 46 of 122
MB96330 Series
I/O map MB96(F)33x (25 of 40)
Address
Register
Abbreviation
8-bit access
000579H
PPG8 - Timer register
00057AH
PPG8 - Period setting register
00057BH
PPG8 - Period setting register
00057CH
PPG8 - Duty cycle register
00057DH
PPG8 - Duty cycle register
00057EH
PPG8 - Control status register Low
PCNL8
00057FH
PPG8 - Control status register High
PCNH8
000580H
PPG9 - Timer register
000581H
PPG9 - Timer register
000582H
PPG9 - Period setting register
000583H
PPG9 - Period setting register
000584H
PPG9 - Duty cycle register
000585H
PPG9 - Duty cycle register
000586H
PPG9 - Control status register Low
PCNL9
000587H
PPG9 - Control status register High
PCNH9
000588H
PPG10 - Timer register
000589H
PPG10 - Timer register
00058AH
PPG10 - Period setting register
00058BH
PPG10 - Period setting register
00058CH
PPG10 - Duty cycle register
00058DH
PPG10 - Duty cycle register
00058EH
PPG10 - Control status register Low
PCNL10
00058FH
PPG10 - Control status register High
PCNH10
000590H
PPG11 - Timer register
000591H
PPG11 - Timer register
000592H
PPG11 - Period setting register
000593H
PPG11 - Period setting register
000594H
PPG11 - Duty cycle register
000595H
PPG11 - Duty cycle register
000596H
PPG11 - Control status register Low
Document Number: 002-04586 Rev. *A
Abbreviation
16-bit access
Access
R
PCSR8
W
W
PDUT8
W
W
PCN8
R/W
R/W
PTMR9
R
R
PCSR9
W
W
PDUT9
W
W
PCN9
R/W
R/W
PTMR10
R
R
PCSR10
W
W
PDUT10
W
W
PCN10
R/W
R/W
PTMR11
R
R
PCSR11
W
W
PDUT11
W
W
PCNL11
PCN11
R/W
Page 47 of 122
MB96330 Series
I/O map MB96(F)33x (26 of 40)
Address
Register
Abbreviation
8-bit access
000597H
PPG11 - Control status register High
PCNH11
000598H
PPG15-PPG12 - General Control register 1 Low
GCN1L3
000599H
PPG15-PPG12 - General Control register 1 High
GCN1H3
00059AH
PPG15-PPG12 - General Control register 2 Low
GCN2L3
00059BH
PPG15-PPG12 - General Control register 2 High
GCN2H3
00059CH
PPG12 - Timer register
00059DH
PPG12 - Timer register
00059EH
PPG12 - Period setting register
00059FH
PPG12 - Period setting register
0005A0H
PPG12 - Duty cycle register
0005A1H
PPG12 - Duty cycle register
0005A2H
PPG12 - Control status register Low
PCNL12
0005A3H
PPG12 - Control status register High
PCNH12
0005A4H
PPG13 - Timer register
0005A5H
PPG13 - Timer register
0005A6H
PPG13 - Period setting register
0005A7H
PPG13 - Period setting register
0005A8H
PPG13 - Duty cycle register
0005A9H
PPG13 - Duty cycle register
0005AAH
PPG13 - Control status register Low
PCNL13
0005ABH
PPG13 - Control status register High
PCNH13
0005ACH
PPG14 - Timer register
0005ADH
PPG14 - Timer register
0005AEH
PPG14 - Period setting register
0005AFH
PPG14 - Period setting register
0005B0H
PPG14 - Duty cycle register
0005B1H
PPG14 - Duty cycle register
0005B2H
PPG14 - Control status register Low
PCNL14
0005B3H
PPG14 - Control status register High
PCNH14
0005B4H
PPG15 - Timer register
Document Number: 002-04586 Rev. *A
Abbreviation
16-bit access
Access
R/W
GCN13
R/W
R/W
GCN23
R/W
R/W
PTMR12
R
R
PCSR12
W
W
PDUT12
W
W
PCN12
R/W
R/W
PTMR13
R
R
PCSR13
W
W
PDUT13
W
W
PCN13
R/W
R/W
PTMR14
R
R
PCSR14
W
W
PDUT14
W
W
PCN14
R/W
R/W
PTMR15
R
Page 48 of 122
MB96330 Series
I/O map MB96(F)33x (27 of 40)
Address
Register
Abbreviation
8-bit access
0005B5H
PPG15 - Timer register
0005B6H
PPG15 - Period setting register
0005B7H
PPG15 - Period setting register
0005B8H
PPG15 - Duty cycle register
0005B9H
PPG15 - Duty cycle register
0005BAH
PPG15 - Control status register Low
PCNL15
0005BBH
PPG15 - Control status register High
PCNH15
0005BCH
PPG19-PPG16 - General Control register 1 Low
GCN1L4
0005BDH
PPG19-PPG16 - General Control register 1 High
GCN1H4
0005BEH
PPG19-PPG16 - General Control register 2 Low
GCN2L4
0005BFH
PPG19-PPG16 - General Control register 2 High
GCN2H4
0005C0H
PPG16 - Timer register
0005C1H
PPG16 - Timer register
0005C2H
PPG16 - Period setting register
0005C3H
PPG16 - Period setting register
0005C4H
PPG16 - Duty cycle register
0005C5H
PPG16 - Duty cycle register
0005C6H
PPG16 - Control status register Low
PCNL16
0005C7H
PPG16 - Control status register High
PCNH16
0005C8H
PPG17 - Timer register
0005C9H
PPG17 - Timer register
0005CAH
PPG17 - Period setting register
0005CBH
PPG17 - Period setting register
0005CCH
PPG17 - Duty cycle register
0005CDH
PPG17 - Duty cycle register
0005CEH
PPG17 - Control status register Low
PCNL17
0005CFH
PPG17 - Control status register High
PCNH17
0005D0H
PPG18 - Timer register
0005D1H
PPG18 - Timer register
0005D2H
PPG18 - Period setting register
Document Number: 002-04586 Rev. *A
Abbreviation
16-bit access
Access
R
PCSR15
W
W
PDUT15
W
W
PCN15
R/W
R/W
GCN14
R/W
R/W
GCN24
R/W
R/W
PTMR16
R
R
PCSR16
W
W
PDUT16
W
W
PCN16
R/W
R/W
PTMR17
R
R
PCSR17
W
W
PDUT17
W
W
PCN17
R/W
R/W
PTMR18
R
R
PCSR18
W
Page 49 of 122
MB96330 Series
I/O map MB96(F)33x (28 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0005D3H
PPG18 - Period setting register
0005D4H
PPG18 - Duty cycle register
0005D5H
PPG18 - Duty cycle register
0005D6H
PPG18 - Control status register Low
PCNL18
0005D7H
PPG18 - Control status register High
PCNH18
0005D8H
PPG19 - Timer register
0005D9H
PPG19 - Timer register
0005DAH
PPG19 - Period setting register
0005DBH
PPG19 - Period setting register
0005DCH
PPG19 - Duty cycle register
0005DDH
PPG19 - Duty cycle register
0005DEH
PPG19 - Control status register Low
PCNL19
0005DFH
PPG19 - Control status register High
PCNH19
0005E0H00065FH
Reserved
000660H
Peripheral Resource Relocation Register 10
PRRR10
R/W
000661H
Peripheral Resource Relocation Register 11
PRRR11
R/W
000662H
Peripheral Resource Relocation Register 12
PRRR12
R/W
000663H
Peripheral Resource Relocation Register 13
PRRR13
W
000664H00069FH
Reserved
0006A0H
USB - Host Control register Low
HCNTL0
0006A1H
USB - Host Control register High
HCNTH0
R/W
0006A2H
USB - Host Interrupt Register
HIRQ0
R/W
0006A3H
USB - Host Error Status Register
HERR0
R/W
0006A4H
USB - Host State Status Register
HSTATE0
R/W
0006A5H
USB - Host SOF Int. Frame Compare Register
HFCOMP0
R/W
0006A6H
USB - Host Retry Timer Setting Register Low
HRTIMERL0
R/W
0006A7H
USB - Host Retry Timer Setting Register Middle
HRTIMERM0
R/W
0006A8H
USB - Host Retry Timer Setting Register High
HRTIMERH0
R/W
0006A9H
USB - Host Address Register
HADR0
R/W
Document Number: 002-04586 Rev. *A
W
PDUT18
W
W
PCN18
R/W
R/W
PTMR19
R
R
PCSR19
W
W
PDUT19
W
W
PCN19
R/W
R/W
-
HCNT0
R/W
Page 50 of 122
MB96330 Series
I/O map MB96(F)33x (29 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
HEOF0
R/W
0006AAH
USB - Host EOF Setting Register Low
HEOFL0
0006ABH
USB - Host EOF Setting Register High
HEOFH0
0006ACH
USB - Host Frame Register Low
HFRAMEL0
0006ADH
USB - Host Frame Register High
HFRAMEH0
R/W
0006AEH
USB - Host Token End Point Register
HTOKEN0
R/W
0006AFH
Reserved
0006B0H
USB - UDC Control Register
0006B1H
Reserved
0006B2H
USB - EP0 Control Register Low
EP0CL0
0006B3H
USB - EP0 Control Register High
EP0CH0
0006B4H
USB - EP1 Control Register Low
EP1CL0
0006B5H
USB - EP1 Control Register High - non public
EP1CH0
0006B6H
USB - EP2 Control Register Low
EP2CL0
0006B7H
USB - EP2 Control Register High
EP2CH0
0006B8H
USB - EP3 Control Register Low
EP3CL0
0006B9H
USB - EP3 Control Register High
EP3CH0
0006BAH
USB - EP4 Control Register Low
EP4CL0
0006BBH
USB - EP4 Control Register High
EP4CH0
0006BCH
USB - EP5 Control Register Low
EP5CL0
0006BDH
USB - EP5 Control Register High
EP5CH0
0006BEH
USB - Timer Stamp Register Low
TMSPL0
0006BFH
USB - Timer Stamp Register High
TMSPH0
R/W
0006C0H
USB - UDC Status Register
UDCS0
R/W
0006C1H
USB - UDC Interrupt Enable Register
UDCIE0
R/W
0006C2H
USB - EP0I Status Register Low
EP0ISL0
0006C3H
USB - EP0I Status Register High
EP0ISH0
0006C4H
USB - EP0O Status Register Low
EP0OSL0
0006C5H
USB - EP0O Status Register High
EP0OSH0
0006C6H
USB - EP1 Status Register Low
EP1SL0
0006C7H
USB - EP1 Status Register High
EP1SH0
Document Number: 002-04586 Rev. *A
R/W
HFRAME0
R/W
UDCC0
R/W
EP0C0
R/W
R/W
EP1C0
R/W
R/W
EP2C0
R/W
R/W
EP3C0
R/W
R/W
EP4C0
R/W
R/W
EP5C0
R/W
R/W
TMSP0
EP0IS0
R/W
W
R/W
EP0OS0
R/W
R/W
EP1S0
R/W
R/W
Page 51 of 122
MB96330 Series
I/O map MB96(F)33x (30 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
EP2S0
R/W
0006C8H
USB - EP2 Status Register Low
EP2SL0
0006C9H
USB - EP2 Status Register High
EP2SH0
0006CAH
USB - EP3 Status Register Low
EP3SL0
0006CBH
USB - EP3 Status Register High
EP3SH0
0006CCH
USB - EP4 Status Register Low
EP4SL0
0006CDH
USB - EP4 Status Register High
EP4SH0
0006CEH
USB - EP5 Status Register Low
EP5SL0
0006CFH
USB - EP5 Status Register High
EP5SH0
0006D0H
USB - EP0 Data register Low
EP0DTL0
0006D1H
USB - EP0 Data register High
EP0DTH0
0006D2H
USB - EP1 Data register Low
EP1DTL0
0006D3H
USB - EP1 Data register High
EP1DTH0
0006D4H
USB - EP2 Data register Low
EP2DTL0
0006D5H
USB - EP2 Data register High
EP2DTH0
0006D6H
USB - EP3 Data register Low
EP3DTL0
0006D7H
USB - EP3 Data register High
EP3DTH0
0006D8H
USB - EP4 Data register Low
EP4DTL0
0006D9H
USB - EP4 Data register High
EP4DTH0
0006DAH
USB - EP5 Data register Low
EP5DTL0
0006DBH
USB - EP5 Data register High
EP5DTH0
0006DCH0006DFH
Reserved
0006E0H
External Bus - Area configuration register 0 Low
EACL0
0006E1H
External Bus - Area configuration register 0 High
EACH0
0006E2H
External Bus - Area configuration register 1 Low
EACL1
0006E3H
External Bus - Area configuration register 1 High
EACH1
0006E4H
External Bus - Area configuration register 2 Low
EACL2
0006E5H
External Bus - Area configuration register 2 High
EACH2
0006E6H
External Bus - Area configuration register 3 Low
EACL3
0006E7H
External Bus - Area configuration register 3 High
EACH3
0006E8H
External Bus - Area configuration register 4 Low
EACL4
Document Number: 002-04586 Rev. *A
R/W
EP3S0
R/W
R/W
EP4S0
R/W
R/W
EP5S0
R/W
R/W
EP0DT0
R/W
R/W
EP1DT0
R/W
R/W
EP2DT0
R/W
R/W
EP3DT0
R/W
R/W
EP4DT0
R/W
R/W
EP5DT0
R/W
R/W
-
EAC0
R/W
R/W
EAC1
R/W
R/W
EAC2
R/W
R/W
EAC3
R/W
R/W
EAC4
R/W
Page 52 of 122
MB96330 Series
I/O map MB96(F)33x (31 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0006E9H
External Bus - Area configuration register 4 High
EACH4
0006EAH
External Bus - Area configuration register 5 Low
EACL5
0006EBH
External Bus - Area configuration register 5 High
EACH5
R/W
0006ECH
External Bus - Area select register 2
EAS2
R/W
0006EDH
External Bus - Area select register 3
EAS3
R/W
0006EEH
External Bus - Area select register 4
EAS4
R/W
0006EFH
External Bus - Area select register 5
EAS5
R/W
0006F0H
External Bus - Mode register
EBM
R/W
0006F1H
External Bus - Clock and Function register
EBCF
R/W
0006F2H
External Bus - Address output enable register 0
EBAE0
R/W
0006F3H
External Bus - Address output enable register 1
EBAE1
R/W
0006F4H
External Bus - Address output enable register 2
EBAE2
R/W
0006F5H
External Bus - Control signal register
EBCS
R/W
0006F6H0006FFH
Reserved
000700H
CAN0 - Control register Low
CTRLRL0
000701H
CAN0 - Control register High (reserved)
CTRLRH0
000702H
CAN0 - Status register Low
STATRL0
000703H
CAN0 - Status register High (reserved)
STATRH0
000704H
CAN0 - Error Counter Low (Transmit)
ERRCNTL0
000705H
CAN0 - Error Counter High (Receive)
ERRCNTH0
000706H
CAN0 - Bit Timing Register Low
BTRL0
000707H
CAN0 - Bit Timing Register High
BTRH0
000708H
CAN0 - Interrupt Register Low
INTRL0
000709H
CAN0 - Interrupt Register High
INTRH0
00070AH
CAN0 - Test Register Low
TESTRL0
00070BH
CAN0 - Test Register High (reserved)
TESTRH0
00070CH
CAN0 - BRP Extension register Low
BRPERL0
00070DH
CAN0 - BRP Extension register High (reserved)
BRPERH0
00070EH00070FH
Reserved
Document Number: 002-04586 Rev. *A
R/W
EAC5
R/W
CTRLR0
R/W
R
STATR0
R/W
R
ERRCNT0
R
R
BTR0
R/W
R/W
INTR0
R
R
TESTR0
R/W
R
BRPER0
R/W
R
-
Page 53 of 122
MB96330 Series
I/O map MB96(F)33x (32 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
IF1CREQ0
R/W
000710H
CAN0 - IF1 Command request register Low
IF1CREQL0
000711H
CAN0 - IF1 Command request register High
IF1CREQH0
000712H
CAN0 - IF1 Command Mask register Low
IF1CMSKL0
000713H
CAN0 - IF1 Command Mask register High (reserved)
IF1CMSKH0
000714H
CAN0 - IF1 Mask 1 Register Low
IF1MSK1L0
000715H
CAN0 - IF1 Mask 1 Register High
IF1MSK1H0
000716H
CAN0 - IF1 Mask 2 Register Low
IF1MSK2L0
000717H
CAN0 - IF1 Mask 2 Register High
IF1MSK2H0
000718H
CAN0 - IF1 Arbitration 1 Register Low
IF1ARB1L0
000719H
CAN0 - IF1 Arbitration 1 Register High
IF1ARB1H0
00071AH
CAN0 - IF1 Arbitration 2 Register Low
IF1ARB2L0
00071BH
CAN0 - IF1 Arbitration 2 Register High
IF1ARB2H0
00071CH
CAN0 - IF1 Message Control Register Low
IF1MCTRL0
00071DH
CAN0 - IF1 Message Control Register High
IF1MCTRH0
00071EH
CAN0 - IF1 Data A1 Low
IF1DTA1L0
00071FH
CAN0 - IF1 Data A1 High
IF1DTA1H0
000720H
CAN0 - IF1 Data A2 Low
IF1DTA2L0
000721H
CAN0 - IF1 Data A2 High
IF1DTA2H0
000722H
CAN0 - IF1 Data B1 Low
IF1DTB1L0
000723H
CAN0 - IF1 Data B1 High
IF1DTB1H0
000724H
CAN0 - IF1 Data B2 Low
IF1DTB2L0
000725H
CAN0 - IF1 Data B2 High
IF1DTB2H0
000726H00073FH
Reserved
000740H
CAN0 - IF2 Command request register Low
IF2CREQL0
000741H
CAN0 - IF2 Command request register High
IF2CREQH0
000742H
CAN0 - IF2 Command Mask register Low
IF2CMSKL0
000743H
CAN0 - IF2 Command Mask register High (reserved)
IF2CMSKH0
000744H
CAN0 - IF2 Mask 1 Register Low
IF2MSK1L0
000745H
CAN0 - IF2 Mask 1 Register High
IF2MSK1H0
000746H
CAN0 - IF2 Mask 2 Register Low
IF2MSK2L0
Document Number: 002-04586 Rev. *A
R/W
IF1CMSK0
R/W
R
IF1MSK10
R/W
R/W
IF1MSK20
R/W
R/W
IF1ARB10
R/W
R/W
IF1ARB20
R/W
R/W
IF1MCTR0
R/W
R/W
IF1DTA10
R/W
R/W
IF1DTA20
R/W
R/W
IF1DTB10
R/W
R/W
IF1DTB20
R/W
R/W
-
IF2CREQ0
R/W
R/W
IF2CMSK0
R/W
R
IF2MSK10
R/W
R/W
IF2MSK20
R/W
Page 54 of 122
MB96330 Series
I/O map MB96(F)33x (33 of 40)
Abbreviation
8-bit access
Address
Register
000747H
CAN0 - IF2 Mask 2 Register High
IF2MSK2H0
000748H
CAN0 - IF2 Arbitration 1 Register Low
IF2ARB1L0
000749H
CAN0 - IF2 Arbitration 1 Register High
IF2ARB1H0
00074AH
CAN0 - IF2 Arbitration 2 Register Low
IF2ARB2L0
00074BH
CAN0 - IF2 Arbitration 2 Register High
IF2ARB2H0
00074CH
CAN0 - IF2 Message Control Register Low
IF2MCTRL0
00074DH
CAN0 - IF2 Message Control Register High
IF2MCTRH0
00074EH
CAN0 - IF2 Data A1 Low
IF2DTA1L0
00074FH
CAN0 - IF2 Data A1 High
IF2DTA1H0
000750H
CAN0 - IF2 Data A2 Low
IF2DTA2L0
000751H
CAN0 - IF2 Data A2 High
IF2DTA2H0
000752H
CAN0 - IF2 Data B1 Low
IF2DTB1L0
000753H
CAN0 - IF2 Data B1 High
IF2DTB1H0
000754H
CAN0 - IF2 Data B2 Low
IF2DTB2L0
000755H
CAN0 - IF2 Data B2 High
IF2DTB2H0
000756H00077FH
Reserved
000780H
CAN0 - Transmission Request 1 Register Low
TREQR1L0
000781H
CAN0 - Transmission Request 1 Register High
TREQR1H0
000782H
CAN0 - Transmission Request 2 Register Low
TREQR2L0
000783H
CAN0 - Transmission Request 2 Register High
TREQR2H0
000784H00078FH
Reserved
000790H
CAN0 - New Data 1 Register Low
NEWDT1L0
000791H
CAN0 - New Data 1 Register High
NEWDT1H0
000792H
CAN0 - New Data 2 Register Low
NEWDT2L0
000793H
CAN0 - New Data 2 Register High
NEWDT2H0
000794H00079FH
Reserved
0007A0H
CAN0 - Interrupt Pending 1 Register Low
INTPND1L0
0007A1H
CAN0 - Interrupt Pending 1 Register High
INTPND1H0
0007A2H
CAN0 - Interrupt Pending 2 Register Low
INTPND2L0
Document Number: 002-04586 Rev. *A
Abbreviation
16-bit access
Access
R/W
IF2ARB10
R/W
R/W
IF2ARB20
R/W
R/W
IF2MCTR0
R/W
R/W
IF2DTA10
R/W
R/W
IF2DTA20
R/W
R/W
IF2DTB10
R/W
R/W
IF2DTB20
R/W
R/W
-
TREQR10
R
R
TREQR20
R
R
-
NEWDT10
R
R
NEWDT20
R
R
-
INTPND10
R
R
INTPND20
R
Page 55 of 122
MB96330 Series
I/O map MB96(F)33x (34 of 40)
Address
Register
Abbreviation
8-bit access
0007A3H
CAN0 - Interrupt Pending 2 Register High
0007A4H0007AFH
Reserved
0007B0H
CAN0 - Message Valid 1 Register Low
MSGVAL1L0
0007B1H
CAN0 - Message Valid 1 Register High
MSGVAL1H0
0007B2H
CAN0 - Message Valid 2 Register Low
MSGVAL2L0
0007B3H
CAN0 - Message Valid 2 Register High
MSGVAL2H0
0007B4H0007CDH
Reserved
0007CEH
CAN0 - Output enable register
0007CFH0007FFH
Reserved
000800H
CAN1 - Control register Low
CTRLRL1
000801H
CAN1 - Control register High (reserved)
CTRLRH1
000802H
CAN1 - Status register Low
STATRL1
000803H
CAN1 - Status register High (reserved)
STATRH1
000804H
CAN1 - Error Counter Low (Transmit)
ERRCNTL1
000805H
CAN1 - Error Counter High (Receive)
ERRCNTH1
000806H
CAN1 - Bit Timing Register Low
BTRL1
000807H
CAN1 - Bit Timing Register High
BTRH1
000808H
CAN1 - Interrupt Register Low
INTRL1
000809H
CAN1 - Interrupt Register High
INTRH1
00080AH
CAN1 - Test Register Low
TESTRL1
00080BH
CAN1 - Test Register High (reserved)
TESTRH1
00080CH
CAN1 - BRP Extension register Low
BRPERL1
00080DH
CAN1 - BRP Extension register High (reserved)
BRPERH1
00080EH00080FH
Reserved
000810H
CAN1 - IF1 Command request register Low
IF1CREQL1
000811H
CAN1 - IF1 Command request register High
IF1CREQH1
000812H
CAN1 - IF1 Command Mask register Low
IF1CMSKL1
000813H
CAN1 - IF1 Command Mask register High (reserved)
IF1CMSKH1
Document Number: 002-04586 Rev. *A
Abbreviation
16-bit access
INTPND2H0
Access
R
-
MSGVAL10
R
R
MSGVAL20
R
R
-
COER0
R/W
CTRLR1
R/W
R
STATR1
R/W
R
ERRCNT1
R
R
BTR1
R/W
R/W
INTR1
R
R
TESTR1
R/W
R
BRPER1
R/W
R
-
IF1CREQ1
R/W
R/W
IF1CMSK1
R/W
R
Page 56 of 122
MB96330 Series
I/O map MB96(F)33x (35 of 40)
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
CAN1 - IF1 Mask 1 Register Low
IF1MSK1L1
IF1MSK11
R/W
000815H
CAN1 - IF1 Mask 1 Register High
IF1MSK1H1
000816H
CAN1 - IF1 Mask 2 Register Low
IF1MSK2L1
000817H
CAN1 - IF1 Mask 2 Register High
IF1MSK2H1
000818H
CAN1 - IF1 Arbitration 1 Register Low
IF1ARB1L1
000819H
CAN1 - IF1 Arbitration 1 Register High
IF1ARB1H1
00081AH
CAN1 - IF1 Arbitration 2 Register Low
IF1ARB2L1
00081BH
CAN1 - IF1 Arbitration 2 Register High
IF1ARB2H1
00081CH
CAN1 - IF1 Message Control Register Low
IF1MCTRL1
00081DH
CAN1 - IF1 Message Control Register High
IF1MCTRH1
00081EH
CAN1 - IF1 Data A1 Low
IF1DTA1L1
00081FH
CAN1 - IF1 Data A1 High
IF1DTA1H1
000820H
CAN1 - IF1 Data A2 Low
IF1DTA2L1
000821H
CAN1 - IF1 Data A2 High
IF1DTA2H1
000822H
CAN1 - IF1 Data B1 Low
IF1DTB1L1
000823H
CAN1 - IF1 Data B1 High
IF1DTB1H1
000824H
CAN1 - IF1 Data B2 Low
IF1DTB2L1
000825H
CAN1 - IF1 Data B2 High
IF1DTB2H1
000826H00083FH
Reserved
000840H
CAN1 - IF2 Command request register Low
IF2CREQL1
000841H
CAN1 - IF2 Command request register High
IF2CREQH1
000842H
CAN1 - IF2 Command Mask register Low
IF2CMSKL1
000843H
CAN1 - IF2 Command Mask register High (reserved)
IF2CMSKH1
000844H
CAN1 - IF2 Mask 1 Register Low
IF2MSK1L1
000845H
CAN1 - IF2 Mask 1 Register High
IF2MSK1H1
000846H
CAN1 - IF2 Mask 2 Register Low
IF2MSK2L1
000847H
CAN1 - IF2 Mask 2 Register High
IF2MSK2H1
000848H
CAN1 - IF2 Arbitration 1 Register Low
IF2ARB1L1
000849H
CAN1 - IF2 Arbitration 1 Register High
IF2ARB1H1
00084AH
CAN1 - IF2 Arbitration 2 Register Low
IF2ARB2L1
Address
Register
000814H
Document Number: 002-04586 Rev. *A
R/W
IF1MSK21
R/W
R/W
IF1ARB11
R/W
R/W
IF1ARB21
R/W
R/W
IF1MCTR1
R/W
R/W
IF1DTA11
R/W
R/W
IF1DTA21
R/W
R/W
IF1DTB11
R/W
R/W
IF1DTB21
R/W
R/W
-
IF2CREQ1
R/W
R/W
IF2CMSK1
R/W
R
IF2MSK11
R/W
R/W
IF2MSK21
R/W
R/W
IF2ARB11
R/W
R/W
IF2ARB21
R/W
Page 57 of 122
MB96330 Series
I/O map MB96(F)33x (36 of 40)
Address
Register
Abbreviation
8-bit access
00084BH
CAN1 - IF2 Arbitration 2 Register High
IF2ARB2H1
00084CH
CAN1 - IF2 Message Control Register Low
IF2MCTRL1
00084DH
CAN1 - IF2 Message Control Register High
IF2MCTRH1
00084EH
CAN1 - IF2 Data A1 Low
IF2DTA1L1
00084FH
CAN1 - IF2 Data A1 High
IF2DTA1H1
000850H
CAN1 - IF2 Data A2 Low
IF2DTA2L1
000851H
CAN1 - IF2 Data A2 High
IF2DTA2H1
000852H
CAN1 - IF2 Data B1 Low
IF2DTB1L1
000853H
CAN1 - IF2 Data B1 High
IF2DTB1H1
000854H
CAN1 - IF2 Data B2 Low
IF2DTB2L1
000855H
CAN1 - IF2 Data B2 High
IF2DTB2H1
000856H00087FH
Reserved
000880H
CAN1 - Transmission Request 1 Register Low
TREQR1L1
000881H
CAN1 - Transmission Request 1 Register High
TREQR1H1
000882H
CAN1 - Transmission Request 2 Register Low
TREQR2L1
000883H
CAN1 - Transmission Request 2 Register High
TREQR2H1
000884H00088FH
Reserved
000890H
CAN1 - New Data 1 Register Low
NEWDT1L1
000891H
CAN1 - New Data 1 Register High
NEWDT1H1
000892H
CAN1 - New Data 2 Register Low
NEWDT2L1
000893H
CAN1 - New Data 2 Register High
NEWDT2H1
000894H00089FH
Reserved
0008A0H
CAN1 - Interrupt Pending 1 Register Low
INTPND1L1
0008A1H
CAN1 - Interrupt Pending 1 Register High
INTPND1H1
0008A2H
CAN1 - Interrupt Pending 2 Register Low
INTPND2L1
0008A3H
CAN1 - Interrupt Pending 2 Register High
INTPND2H1
0008A4H0008AFH
Reserved
0008B0H
CAN1 - Message Valid 1 Register Low
Document Number: 002-04586 Rev. *A
Abbreviation
16-bit access
Access
R/W
IF2MCTR1
R/W
R/W
IF2DTA11
R/W
R/W
IF2DTA21
R/W
R/W
IF2DTB11
R/W
R/W
IF2DTB21
R/W
R/W
-
TREQR11
R
R
TREQR21
R
R
-
NEWDT11
R
R
NEWDT21
R
R
-
INTPND11
R
R
INTPND21
R
R
-
MSGVAL1L1
MSGVAL11
R
Page 58 of 122
MB96330 Series
I/O map MB96(F)33x (37 of 40)
Address
Register
Abbreviation
8-bit access
0008B1H
CAN1 - Message Valid 1 Register High
MSGVAL1H1
0008B2H
CAN1 - Message Valid 2 Register Low
MSGVAL2L1
0008B3H
CAN1 - Message Valid 2 Register High
MSGVAL2H1
0008B4H0008CDH
Reserved
0008CEH
CAN1 - Output enable register
0008CFH0008FFH
Reserved
000900H
CAN2 - Control register Low
CTRLRL2
000901H
CAN2 - Control register High (reserved)
CTRLRH2
000902H
CAN2 - Status register Low
STATRL2
000903H
CAN2 - Status register High (reserved)
STATRH2
000904H
CAN2 - Error Counter Low (Transmit)
ERRCNTL2
000905H
CAN2 - Error Counter High (Receive)
ERRCNTH2
000906H
CAN2 - Bit Timing Register Low
BTRL2
000907H
CAN2 - Bit Timing Register High
BTRH2
000908H
CAN2 - Interrupt Register Low
INTRL2
000909H
CAN2 - Interrupt Register High
INTRH2
00090AH
CAN2 - Test Register Low
TESTRL2
00090BH
CAN2 - Test Register High (reserved)
TESTRH2
00090CH
CAN2 - BRP Extension register Low
BRPERL2
00090DH
CAN2 - BRP Extension register High (reserved)
BRPERH2
00090EH00090FH
Reserved
000910H
CAN2 - IF1 Command request register Low
IF1CREQL2
000911H
CAN2 - IF1 Command request register High
IF1CREQH2
000912H
CAN2 - IF1 Command Mask register Low
IF1CMSKL2
000913H
CAN2 - IF1 Command Mask register High (reserved)
IF1CMSKH2
000914H
CAN2 - IF1 Mask 1 Register Low
IF1MSK1L2
000915H
CAN2 - IF1 Mask 1 Register High
IF1MSK1H2
000916H
CAN2 - IF1 Mask 2 Register Low
IF1MSK2L2
000917H
CAN2 - IF1 Mask 2 Register High
IF1MSK2H2
Document Number: 002-04586 Rev. *A
Abbreviation
16-bit access
Access
R
MSGVAL21
R
R
-
COER1
R/W
CTRLR2
R/W
R
STATR2
R/W
R
ERRCNT2
R
R
BTR2
R/W
R/W
INTR2
R
R
TESTR2
R/W
R
BRPER2
R/W
R
-
IF1CREQ2
R/W
R/W
IF1CMSK2
R/W
R
IF1MSK12
R/W
R/W
IF1MSK22
R/W
R/W
Page 59 of 122
MB96330 Series
I/O map MB96(F)33x (38 of 40)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
IF1ARB12
R/W
000918H
CAN2 - IF1 Arbitration 1 Register Low
IF1ARB1L2
000919H
CAN2 - IF1 Arbitration 1 Register High
IF1ARB1H2
00091AH
CAN2 - IF1 Arbitration 2 Register Low
IF1ARB2L2
00091BH
CAN2 - IF1 Arbitration 2 Register High
IF1ARB2H2
00091CH
CAN2 - IF1 Message Control Register Low
IF1MCTRL2
00091DH
CAN2 - IF1 Message Control Register High
IF1MCTRH2
00091EH
CAN2 - IF1 Data A1 Low
IF1DTA1L2
00091FH
CAN2 - IF1 Data A1 High
IF1DTA1H2
000920H
CAN2 - IF1 Data A2 Low
IF1DTA2L2
000921H
CAN2 - IF1 Data A2 High
IF1DTA2H2
000922H
CAN2 - IF1 Data B1 Low
IF1DTB1L2
000923H
CAN2 - IF1 Data B1 High
IF1DTB1H2
000924H
CAN2 - IF1 Data B2 Low
IF1DTB2L2
000925H
CAN2 - IF1 Data B2 High
IF1DTB2H2
000926H00093FH
Reserved
000940H
CAN2 - IF2 Command request register Low
IF2CREQL2
000941H
CAN2 - IF2 Command request register High
IF2CREQH2
000942H
CAN2 - IF2 Command Mask register Low
IF2CMSKL2
000943H
CAN2 - IF2 Command Mask register High (reserved)
IF2CMSKH2
000944H
CAN2 - IF2 Mask 1 Register Low
IF2MSK1L2
000945H
CAN2 - IF2 Mask 1 Register High
IF2MSK1H2
000946H
CAN2 - IF2 Mask 2 Register Low
IF2MSK2L2
000947H
CAN2 - IF2 Mask 2 Register High
IF2MSK2H2
000948H
CAN2 - IF2 Arbitration 1 Register Low
IF2ARB1L2
000949H
CAN2 - IF2 Arbitration 1 Register High
IF2ARB1H2
00094AH
CAN2 - IF2 Arbitration 2 Register Low
IF2ARB2L2
00094BH
CAN2 - IF2 Arbitration 2 Register High
IF2ARB2H2
00094CH
CAN2 - IF2 Message Control Register Low
IF2MCTRL2
00094DH
CAN2 - IF2 Message Control Register High
IF2MCTRH2
00094EH
CAN2 - IF2 Data A1 Low
IF2DTA1L2
Document Number: 002-04586 Rev. *A
R/W
IF1ARB22
R/W
R/W
IF1MCTR2
R/W
R/W
IF1DTA12
R/W
R/W
IF1DTA22
R/W
R/W
IF1DTB12
R/W
R/W
IF1DTB22
R/W
R/W
-
IF2CREQ2
R/W
R/W
IF2CMSK2
R/W
R
IF2MSK12
R/W
R/W
IF2MSK22
R/W
R/W
IF2ARB12
R/W
R/W
IF2ARB22
R/W
R/W
IF2MCTR2
R/W
R/W
IF2DTA12
R/W
Page 60 of 122
MB96330 Series
I/O map MB96(F)33x (39 of 40)
Address
Register
Abbreviation
8-bit access
00094FH
CAN2 - IF2 Data A1 High
IF2DTA1H2
000950H
CAN2 - IF2 Data A2 Low
IF2DTA2L2
000951H
CAN2 - IF2 Data A2 High
IF2DTA2H2
000952H
CAN2 - IF2 Data B1 Low
IF2DTB1L2
000953H
CAN2 - IF2 Data B1 High
IF2DTB1H2
000954H
CAN2 - IF2 Data B2 Low
IF2DTB2L2
000955H
CAN2 - IF2 Data B2 High
IF2DTB2H2
000956H00097FH
Reserved
000980H
CAN2 - Transmission Request 1 Register Low
TREQR1L2
000981H
CAN2 - Transmission Request 1 Register High
TREQR1H2
000982H
CAN2 - Transmission Request 2 Register Low
TREQR2L2
000983H
CAN2 - Transmission Request 2 Register High
TREQR2H2
000984H00098FH
Reserved
000990H
CAN2 - New Data 1 Register Low
NEWDT1L2
000991H
CAN2 - New Data 1 Register High
NEWDT1H2
000992H
CAN2 - New Data 2 Register Low
NEWDT2L2
000993H
CAN2 - New Data 2 Register High
NEWDT2H2
000994H00099FH
Reserved
0009A0H
CAN2 - Interrupt Pending 1 Register Low
INTPND1L2
0009A1H
CAN2 - Interrupt Pending 1 Register High
INTPND1H2
0009A2H
CAN2 - Interrupt Pending 2 Register Low
INTPND2L2
0009A3H
CAN2 - Interrupt Pending 2 Register High
INTPND2H2
0009A4H0009AFH
Reserved
0009B0H
CAN2 - Message Valid 1 Register Low
MSGVAL1L2
0009B1H
CAN2 - Message Valid 1 Register High
MSGVAL1H2
0009B2H
CAN2 - Message Valid 2 Register Low
MSGVAL2L2
0009B3H
CAN2 - Message Valid 2 Register High
MSGVAL2H2
Document Number: 002-04586 Rev. *A
Abbreviation
16-bit access
Access
R/W
IF2DTA22
R/W
R/W
IF2DTB12
R/W
R/W
IF2DTB22
R/W
R/W
-
TREQR12
R
R
TREQR22
R
R
-
NEWDT12
R
R
NEWDT22
R
R
-
INTPND12
R
R
INTPND22
R
R
-
MSGVAL12
R
R
MSGVAL22
R
R
Page 61 of 122
MB96330 Series
I/O map MB96(F)33x (40 of 40)
Address
Register
0009B4H0009CDH
Reserved
0009CEH
CAN2 - Output enable register
0009CFH000BFFH
Reserved
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
-
COER2
R/W
-
Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results
in reading ‘X’.
Registers of resources which are described in this table, but which are not supported by the device, should also be handled
as “Reserved”.
Document Number: 002-04586 Rev. *A
Page 62 of 122
MB96330 Series
12. Interrupt Vector Table
Interrupt vector table MB96(F)33x (1 of 5)
Vector
number
Offset in
vector
table
Vector name
Cleared
by DMA
Index in
ICR to
program
0
3FCH
CALLV0
No
-
1
3F8H
CALLV1
No
-
2
3F4H
CALLV2
No
-
3
3F0H
CALLV3
No
-
4
3ECH
CALLV4
No
-
5
3E8H
CALLV5
No
-
6
3E4H
CALLV6
No
-
7
3E0H
CALLV7
No
-
8
3DCH
RESET
No
-
9
3D8H
INT9
No
-
10
3D4H
EXCEPTION
No
-
11
3D0H
NMI
No
-
12
3CCH
DLY
No
12
Delayed Interrupt
13
3C8H
RC_TIMER
No
13
RC Timer
14
3C4H
MC_TIMER
No
14
Main Clock Timer
15
3C0H
SC_TIMER
No
15
Sub Clock Timer
16
3BCH
PLL_UNLOCK
No
16
Reserved
17
3B8H
EXTINT0
Yes
17
External Interrupt 0
18
3B4H
EXTINT1
Yes
18
External Interrupt 1
19
3B0H
EXTINT2
Yes
19
External Interrupt 2
20
3ACH
EXTINT3
Yes
20
External Interrupt 3
21
3A8H
EXTINT4
Yes
21
External Interrupt 4
22
3A4H
EXTINT5
Yes
22
External Interrupt 5
23
3A0H
EXTINT6
Yes
23
External Interrupt 6
24
39CH
EXTINT7
Yes
24
External Interrupt 7
25
398H
EXTINT8
Yes
25
External Interrupt 8
26
394H
EXTINT9
Yes
26
External Interrupt 9
Document Number: 002-04586 Rev. *A
Description
Non-Maskable Interrupt
Page 63 of 122
MB96330 Series
Interrupt vector table MB96(F)33x (2 of 5)
Vector
number
Offset in
vector
table
Vector name
Cleared
by DMA
Index in
ICR to
program
27
390H
EXTINT10
Yes
27
External Interrupt 10
28
38CH
EXTINT11
Yes
28
External Interrupt 11
29
388H
EXTINT12
Yes
29
External Interrupt 12
30
384H
EXTINT13
Yes
30
External Interrupt 13
31
380H
EXTINT14
Yes
31
External Interrupt 14
32
37CH
EXTINT15
Yes
32
External Interrupt 15
33
378H
CAN0
No
33
CAN Controller 0
34
374H
CAN1
No
34
CAN Controller 1
35
370H
CAN2
No
35
CAN Controller 2
36
36CH
PPG0
Yes
36
Programmable Pulse Generator 0
37
368H
PPG1
Yes
37
Programmable Pulse Generator 1
38
364H
PPG2
Yes
38
Programmable Pulse Generator 2
39
360H
PPG3
Yes
39
Programmable Pulse Generator 3
40
35CH
PPG4
Yes
40
Programmable Pulse Generator 4
41
358H
PPG5
Yes
41
Programmable Pulse Generator 5
42
354H
PPG6
Yes
42
Programmable Pulse Generator 6
43
350H
PPG7
Yes
43
Programmable Pulse Generator 7
44
34CH
PPG8
Yes
44
Programmable Pulse Generator 8
45
348H
PPG9
Yes
45
Programmable Pulse Generator 9
46
344H
PPG10
Yes
46
Programmable Pulse Generator 10
47
340H
PPG11
Yes
47
Programmable Pulse Generator 11
48
33CH
PPG12
Yes
48
Programmable Pulse Generator 12
49
338H
PPG13
Yes
49
Programmable Pulse Generator 13
50
334H
PPG14
Yes
50
Programmable Pulse Generator 14
51
330H
PPG15
Yes
51
Programmable Pulse Generator 15
52
32CH
PPG16
Yes
52
Programmable Pulse Generator 16
53
328H
PPG17
Yes
53
Programmable Pulse Generator 17
Document Number: 002-04586 Rev. *A
Description
Page 64 of 122
MB96330 Series
Interrupt vector table MB96(F)33x (3 of 5)
Vector
number
Offset in
vector
table
Vector name
Cleared
by DMA
Index in
ICR to
program
54
324H
PPG18
Yes
54
Programmable Pulse Generator 18
55
320H
PPG19
Yes
55
Programmable Pulse Generator 19
56
31CH
RLT0
Yes
56
Reload Timer 0
57
318H
RLT1
Yes
57
Reload Timer 1
58
314H
RLT2
Yes
58
Reload Timer 2
59
310H
RLT3
Yes
59
Reload Timer 3
60
30CH
PPGRLT
Yes
60
Reload Timer 6 - dedicated for PPG
61
308H
ICU0
Yes
61
Input Capture Unit 0
62
304H
ICU1
Yes
62
Input Capture Unit 1
63
300H
ICU2
Yes
63
Input Capture Unit 2
64
2FCH
ICU3
Yes
64
Input Capture Unit 3
65
2F8H
ICU4
Yes
65
Input Capture Unit 4
66
2F4H
ICU5
Yes
66
Input Capture Unit 5
67
2F0H
ICU6
Yes
67
Input Capture Unit 6
68
2ECH
ICU7
Yes
68
Input Capture Unit 7
69
2E8H
ICU8
Yes
69
Input Capture Unit 8
70
2E4H
ICU9
Yes
70
Input Capture Unit 9
71
2E0H
OCU0
Yes
71
Output Compare Unit 0
72
2DCH
OCU1
Yes
72
Output Compare Unit 1
73
2D8H
OCU2
Yes
73
Output Compare Unit 2
74
2D4H
OCU3
Yes
74
Output Compare Unit 3
75
2D0H
OCU4
Yes
75
Output Compare Unit 4
76
2CCH
OCU5
Yes
76
Output Compare Unit 5
77
2C8H
OCU6
Yes
77
Output Compare Unit 6
78
2C4H
OCU7
Yes
78
Output Compare Unit 7
79
2C0H
OCU8
Yes
79
Output Compare Unit 8
80
2BCH
OCU9
Yes
80
Output Compare Unit 9
Document Number: 002-04586 Rev. *A
Description
Page 65 of 122
MB96330 Series
Interrupt vector table MB96(F)33x (4 of 5)
Vector
number
Offset in
vector
table
Vector name
Cleared
by DMA
Index in
ICR to
program
81
2B8H
OCU10
Yes
81
Output Compare Unit 10
82
2B4H
OCU11
Yes
82
Output Compare Unit 11
83
2B0H
FRT0
Yes
83
Free Running Timer 0
84
2ACH
FRT1
Yes
84
Free Running Timer 1
85
2A8H
FRT2
Yes
85
Free Running Timer 2
86
2A4H
FRT3
Yes
86
Free Running Timer 3
87
2A0H
RTC0
No
87
Real Timer Clock
88
29CH
CAL0
No
88
Clock Calibration Unit
89
298H
IIC0
Yes
89
I2C interface
90
294H
IIC1
Yes
90
I2C interface
91
290H
ADC0
Yes
91
A/D Converter
92
28CH
ALARM0
No
92
Alarm Comparator 0
93
288H
ALARM1
No
93
Alarm Comparator 1
94
284H
LINR0
Yes
94
LIN USART 0 RX
95
280H
LINT0
Yes
95
LIN USART 0 TX
96
27CH
LINR1
Yes
96
LIN USART 1 RX
97
278H
LINT1
Yes
97
LIN USART 1 TX
98
274H
LINR2
Yes
98
LIN USART 2 RX
99
270H
LINT2
Yes
99
LIN USART 2 TX
100
26CH
LINR3
Yes
100
LIN USART 3 RX
101
268H
LINT3
Yes
101
LIN USART 3 TX
102
264H
LINR5
Yes
102
LIN USART 5 RX
103
260H
LINT5
Yes
103
LIN USART 5 TX
104
25CH
LINR7
Yes
104
LIN USART 7 RX
105
258H
LINT7
Yes
105
LIN USART 7 TX
106
254H
LINR8
Yes
106
LIN USART 8 RX
107
250H
LINT8
Yes
107
LIN USART 8 TX
Document Number: 002-04586 Rev. *A
Description
Page 66 of 122
MB96330 Series
Interrupt vector table MB96(F)33x (5 of 5)
Vector
number
Offset in
vector
table
Vector name
Cleared
by DMA
Index in
ICR to
program
108
24CH
LINR9
Yes
108
LIN USART 9 RX
109
248H
LINT9
Yes
109
LIN USART 9 TX
110
244H
FLASH_A
No
110
Main Flash memory interrupt (only Flash
devices)
111
240H
reserved
-
-
112
23CH
USB_EP0IN0
Yes
112
USB End point 0 IN
113
238H
USB_EP0OUT0
Yes
113
USB End point 0 OUT
114
234H
USB_EP10
Yes
114
USB End point 1
115
230H
USB_EP20
Yes
115
USB End point 2
116
22CH
USB_EP30
Yes
116
USB End point 3
117
228H
USB_EP40
Yes
117
USB End point 4
118
224H
USB_EP50
Yes
118
USB End point 5
119
220H
USB_F10
No
119
USB function Flags 1 (SUSP SOF BRST
WKUP CONF)
120
21CH
USB_F20
No
120
USB function Flags 2 (SPK)
121
218H
USB_H10
No
121
USB MiniHost 1 (DIRQ CNNIRQ URIRQ
RWKIRQ)
122
214H
USB_H20
No
122
USB MiniHost 2 (SOFIRQ CMPIRQ)
Document Number: 002-04586 Rev. *A
Description
reserved
Page 67 of 122
MB96330 Series
13. Handling Devices
Special care is required for the following when handling the device:
•
•
•
•
•
•
•
•
•
•
•
Latch-up prevention
Unused pins handling
External clock usage
Unused sub clock signal
Notes on PLL clock mode operation
Power supply pins (VCC/VSS)
Crystal oscillator circuit
Turn on sequence of power supply to A/D converter and analog inputs
Pin handling when not using the A/D converter
Notes on energization
Stabilization of power supply voltage
13.1 Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply
voltage.
13.2 Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device.
They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 k.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or
external pull-up/pull-down resistor as described above.
13.3 External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for
detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows:
1. Single phase external clock
• When using a single phase external clock, X0 pin must be driven and X1 pin left open.
X0
X1
Document Number: 002-04586 Rev. *A
Page 68 of 122
MB96330 Series
2. Opposite phase external clock
• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to
the X0 (X0A) pins.
X0
X1
13.4 Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin
must be left open.
13.5 Notes on PLL clock mode operation
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts
to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed.
13.6 Power supply pins (VCC/VSS)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or
VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range.
VCC and VSS must be connected to the device from the power supply with lowest possible impedance.
As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 F between VCC and VSS as close
as possible to VCC and VSS pins.
13.7 Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest
possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost
effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area
for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially
when using low-Q resonators at higher frequencies.
13.8 Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power
supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage
must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable).
13.9 Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
13.10 Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than
50s from 0.2 V to 2.7 V.
Document Number: 002-04586 Rev. *A
Page 69 of 122
MB96330 Series
13.11 Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may
occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be
stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10%
of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous fluctuation for
power supply switching.
13.12 Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error
occurs.
Document Number: 002-04586 Rev. *A
Page 70 of 122
MB96330 Series
14. Electrical Characteristics
14.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS - 0.3
VSS + 6.0
V
AVCC
VSS - 0.3
VSS + 6.0
V
VCC = AVCC *1
VCC3
VSS - 0.3
VSS + 4.0
V
USB device only
AVRH,
AVRL
VSS - 0.3
VSS + 6.0
V
AVCC AVRH, AVCC AVRL, AVRH
AVRL, AVRL AVSS
VI
VSS - 0.3
VSS + 6.0
V
VI VCC + 0.3V *2
VIUSB
VSS - 0.5
VSS + 4.0
V
VIUSB VCC3 + 0.5
(USB pins UDP, UDM)
VO
VSS - 0.3
VSS + 6.0
V
VO VCC + 0.3V *2
USB output voltage
VOUSB
VSS - 0.5
VSS + 4.0
V
VOUSB VCC3 + 0.5
(USB pins UDP, UDM)
Maximum Clamp Current
ICLAMP
-4.0
+4.0
mA
Applicable to general purpose
I/O pins *3
|ICLAMP|
-
40
mA
Applicable to general purpose
I/O pins *3
IOL1
-
15
mA
Normal outputs with driving strength
set to 5mA
IOLUSB
-
36
mA
USB pins UDP, UDM
IOLAV1
-
5
mA
Normal outputs with driving strength
set to 5mA
IOLAVUSB
-
15
mA
USB pins UDP, UDM
IOL1
-
100
mA
Normal outputs
IOLAV1
-
50
mA
Normal outputs
IOH1
-
-15
mA
Normal outputs with driving strength
set to 5mA
IOHUSB
-
-36
mA
USB pins UDP, UDM
IOHAV1
-
-5
mA
Normal outputs with driving strength
set to 5mA
IOHAVUSB
-
-15
mA
USB pins UDP, UDM
IOH1
-
-100
mA
Normal outputs
IOHAV1
-
-50
mA
Normal outputs
Power supply voltage
USB power supply voltage
AD Converter voltage references
Input voltage
USB Input voltage
Output voltage
Total Maximum Clamp Current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
“L” level average overall output current
”H” level maximum output current
”H” level average output current
”H” level maximum overall output current
”H” level average overall output current
Document Number: 002-04586 Rev. *A
Page 71 of 122
MB96330 Series
Parameter
Permitted Power dissipation (Flash devices) *4
Operating ambient temperature
Symbol
PD
TA
TSTG
Storage temperature
Rating
Unit
Remarks
Min
Max
-
370*5
mW TA=105oC
-
740*5
mW TA=85oC
-
460*5
mW
TA=125oC, no Flash program/erase,
MB96(F)338Y/R only *6
-
550*5
mW
TA=120oC, no Flash program/erase,
MB96(F)338Y/R only *6
0
+70
-40
+105
-40
+125
-55
+150
MB96V300B
oC
MB96(F)33x
MB96(F)338Y/R*6
oC
*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog
inputs does not exceed AVCC neither when the power is switched on.
*2: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current
to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output
voltages of standard ports depend on VCC.
*3:  Applicable to all general purpose I/O pins (Pnn_m)
 Use within recommended operating conditions.
 Use at DC voltage (current)
 The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller.
 The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller
pin does not exceed rated values, either instantaneously or for prolonged periods.
 Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
 Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided
from the pins, so that incomplete operation may result.
 Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage
may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode).
 Sample recommended circuits:
Protective Diode
VCC
Limiting
resistance
P-ch
+B input (0V to 16V)
N-ch
R
Document Number: 002-04586 Rev. *A
Page 72 of 122
MB96330 Series
*4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance
of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO =  (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VCC * (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation
mode and clock frequency and the usage of functions like Flash programming or the clock modulator.
IA is the analog current consumption into AVCC.
*5: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
*6: Please contact Cypress for reliability limitations when using under these conditions.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04586 Rev. *A
Page 73 of 122
MB96330 Series
14.2 Recommended Operating Conditions
Parameter
Symbol
Value
Min
Typ
Max
Unit
Remarks
Power supply voltage
VCC
3.0
-
5.5
V
USB power supply voltage
VCC3
3.0
3.3
3.6
V
USB device only
CS
4.7
-
10
F
Use a low inductance capacitor (for
example X7R ceramic capacitor)
Smoothing capacitor at C pin
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their Cypress representatives
beforehand.
Document Number: 002-04586 Rev. *A
Page 74 of 122
MB96330 Series
14.3 DC characteristics
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VCC3 = 3.0V to 3.6V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
Condition
Port inputs
Max
0.8
VCC
-
VCC +
0.3
V
0.7
VCC
-
VCC +
0.3
V
VCC 4.5V
0.74
VCC
-
VCC +
0.3
V
VCC < 4.5V
AUTOMOTIVE
Hysteresis input
selected
0.8
VCC
-
VCC +
0.3
V
TTL input selected
2.0
-
VCC +
0.3
V
2.0
-
VCC3 +
0.3
V
CMOS Hysteresis
0.7/0.3 input
selected
VIHUSB
UDP, UDM
VIHX0F
X0
External clock in
“Fast Clock Input
mode”
0.8
VCC
-
VCC +
0.3
V
VIHX0S
X0,X1,
X0A,X1A
External clock in
“oscillation mode”
2.5
-
VCC +
0.3
V
VIHR
RSTX
-
0.8
VCC
-
VCC +
0.3
V
VIHM
MD2-MD0
-
VCC 0.3
-
VCC +
0.3
V
Document Number: 002-04586 Rev. *A
Remarks
Typ
Pnn_m
Input H voltage
Unit
Min
CMOS Hysteresis
0.8/0.2 input
selected
VIH
Value
-
USB pins
CMOS Hysteresis input
Page 75 of 122
MB96330 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VCC3 = 3.0V to 3.6V, VSS = AVSS = 0V)
Parameter
Symbol
VIL
Pin
Port inputs
Pnn_m
Condition
Unit
Min
Typ
Max
CMOS Hysteresis
0.8/0.2 input
selected
VSS 0.3
-
0.2
VCC
V
CMOS Hysteresis
0.7/0.3 input
selected
VSS 0.3
-
0.3
VCC
V
VSS 0.3
-
0.5
VCC
V
VSS 0.3
-
0.46
VCC
VSS 0.3
-
0.8
V
VSS 0.3
-
0.8
V
AUTOMOTIVE
Hysteresis input
selected
TTL input selected
Input L voltage
Value
Remarks
VCC 4.5V
VCC < 4.5V
VILUSB
UDP, UDM
VILX0F
X0
External clock in
“Fast Clock Input
mode”
VSS 0.3
-
0.2 VCC
V
VILX0S
X0,X1,
X0A,X1A
External clock in
“oscillation mode”
VSS 0.3
-
0.4
V
VILR
RSTX
-
VSS 0.3
-
0.2 VCC
V
VILM
MD2-MD0
-
VSS 0.3
-
VSS +
0.3
V
VCC 0.5
-
-
V
Driving strength set to
2mA
VCC 0.5
-
-
V
Driving strength set to
5mA
VCC 0.5
-
-
V
VCC3 0.4
-
-
V
-
USB pins
CMOS Hysteresis input
4.5V VCC  5.5V
VOH2
Normal outputs
IOH = -2mA
3.0V VCC  4.5V
IOH = -1.6mA
4.5V VCC  5.5V
VOH5
Normal outputs
IOH = -5mA
3.0V VCC  4.5V
IOH = -3mA
4.5V VCC  5.5V
Output H voltage
VOH3
3mA outputs
IOH = -3mA
3.0V VCC  4.5V
IOH = -2mA
VOHUSB
UDP, UDM
Document Number: 002-04586 Rev. *A
3.0V VCC3  3.6V
IOH = -20mA
USB pins
Page 76 of 122
MB96330 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VCC3 = 3.0V to 3.6V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
Condition
Value
Unit
Remarks
Min
Typ
Max
-
-
0.4
V
Driving strength set to
2mA
-
-
0.4
V
Driving strength set to
5mA
-
-
0.4
V
-
-
0.4
V
USB pins
AVSS, AVRL < VI <
AVCC, AVRH
-1
-
+1
A
Single port pin
VSS < VI < VCC3
-5
-
+5
A
USB pins
VCC  3.3V  10
40
100
160
k
VCC  5.0V  10
25
50
100
k
4.5V VCC  5.5V
VOL2
Normal
outputs
IOL = +2mA
3.0V VCC  4.5V
IOL = +1.6mA
4.5V VCC  5.5V
VOL5
Normal
outputs
VOL3
3mA outputs
VOLUSB
UDP, UDM
IIL
Pnn_m
(except USB
pins)
USB input leak current
Pull-up resistance
3.0V VCC  4.5V
IOL = +3mA
Output L voltage
Input leak current
IOL = +5mA
UDP, UDM
RUP
Pnn_m,
RSTX
Document Number: 002-04586 Rev. *A
3.0V VCC  5.5V
IOL = +3mA
3.0V VCC3  3.6V
IOL = +20mA
VSS < VI < VCC
Page 77 of 122
MB96330 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
PLL Run mode with
CLKS1/2 = 48MHz, CLKB =
CLKP1/2 = 24MHz,
CLKP3 = 48MHz
ICCPLL
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1/3 = 48MHz,
CLKP2 = 24MHz
PLL Run mode with
CLKS1/2 = 96MHz,
CLKB = CLKP1/3 = 48MHz,
CLKP2 = 24MHz
ICCMAIN
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2/3 = 4MHz
Power supply
current in Run
modes*
ICCRCH
Value
Condition (at TA)
Symbol
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2/3 = 2MHz
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2/3 = 100kHz,
SMCR:LPMS = 0
+25°C
Typ
Max
39
47
Unit
mA
+125°C
40
50
+25°C
45
57
46
60
+25°C
56
68
57
71
+25°C
5
6
5.6
9
+25°C
2.9
4
3.5
6.5
+25°C
0.4
0.6
CLKPLL, CLKSC and CLKRC
stopped
1 Flash/ROM wait state
mA
+125°C
CLKRC and CLKSC stopped.
Core voltage at 1.9V
1 Flash/ROM wait state
mA
+125°C
CLKRC and CLKSC stopped.
Core voltage at 1.9V
2 Flash/ROM wait states
mA
+125°C
CLKRC and CLKSC stopped.
Core voltage at 1.9V
0 Flash/ROM wait states
mA
+125°C
Remarks
CLKMC, CLKPLL and CLKSC
stopped
1 Flash/ROM wait state
mA
CLKMC, CLKPLL and CLKSC
stopped. Voltage regulator in
high power mode
+125°C
0.9
3.5
1 Flash/ROM wait state
+25°C
0.15
0.25
CLKMC, CLKPLL and CLKSC
stopped. Voltage regulator in
low power mode, no Flash
programming/erasing allowed.
ICCRCL
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2/3 = 100kHz,
SMCR:LPMS = 1
ICCSUB
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2/3 = 32kHz
Document Number: 002-04586 Rev. *A
mA
+125°C
0.65
3.2
1 Flash/ROM wait state
+25°C
0.1
0.2
CLKMC, CLKPLL and CLKRC
stopped, no Flash
programming/erasing allowed.
mA
+125°C
0.6
3
1 Flash/ROM wait state
Page 78 of 122
MB96330 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
PLL Sleep mode with
CLKS1/2 = 48MHz,
CLKP1/2 = 24MHz
CLKP3 = 48MHz
ICCSPLL
PLL Sleep mode with
CLKS1/2 = CLKP1/3 =
48MHz,
CLKP2 = 24MHz
PLL Sleep mode with
CLKS1/2 = 96MHz,
CLKP1/3 = 48MHz,
CLKP2 = 24MHz
ICCSMAIN
Main Sleep mode with
CLKS1/2 = CLKP1/2/3 =
4MHz
Power supply
current in Sleep
modes*
ICCSRCH
Value
Condition (at TA)
Symbol
RC Sleep mode with
CLKS1/2 = CLKP1/2/3 =
2MHz
RC Sleep mode with
CLKS1/2 = CLKP1/2/3 =
100kHz,
SMCR:LPMSS = 0
+25°C
Typ
Max
12.5
15
+125°C
13.3
17.5
+25°C
17
20
+125°C
17.8
22.5
+25°C
19
22
+125°C
19.8
24.5
+25°C
1.9
2.3
+125°C
2.4
5
+25°C
0.9
1.4
+125°C
1.5
4.1
+25°C
0.3
0.5
+125°C
0.8
3.4
+25°C
0.06
0.15
Unit
Remarks
mA
CLKRC and CLKSC stopped.
Core voltage at 1.9V
mA
CLKRC and CLKSC stopped.
Core voltage at 1.9V
mA
CLKRC and CLKSC stopped.
Core voltage at 1.9V
mA
CLKPLL, CLKSC and CLKRC
stopped
mA
CLKMC, CLKPLL and CLKSC
stopped
mA
CLKMC, CLKPLL and CLKSC
stopped. Voltage regulator in
high power mode
mA
CLKMC, CLKPLL and CLKSC
stopped. Voltage regulator in
low power mode
mA
CLKMC, CLKPLL and CLKRC
stopped
ICCSRCL
RC Sleep mode with
CLKS1/2 = CLKP1/2/3 =
100kHz,
SMCR:LPMSS = 1
ICCSSUB
Sub Sleep mode with
CLKS1/2 = CLKP1/2/3 =
32kHz
Document Number: 002-04586 Rev. *A
+125°C
0.56
3
+25°C
0.04
0.12
+125°C
0.54
2.9
Page 79 of 122
MB96330 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
ICCTPLL
Value
Condition (at TA)
Symbol
PLL Timer mode with
CLKMC = 4MHz,
CLKPLL = 48MHz
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 0
+25°C
Typ
Max
1.6
2
+125°C
2.1
4.8
+25°C
0.35
0.5
+125°C
0.85
3.3
+25°C
0.1
0.15
Unit
Remarks
mA
CLKRC and CLKSC stopped.
Core voltage at 1.9V
mA
CLKPLL, CLKRC and CLKSC
stopped. Voltage regulator in
high power mode
mA
CLKPLL, CLKRC and CLKSC
stopped. Voltage regulator in
low power mode
mA
CLKMC, CLKPLL and CLKSC
stopped. Voltage regulator in
high power mode
mA
CLKMC, CLKPLL and CLKSC
stopped. Voltage regulator in
low power mode
mA
CLKMC, CLKPLL and CLKSC
stopped. Voltage regulator in
high power mode
mA
CLKMC, CLKPLL and CLKSC
stopped. Voltage regulator in
low power mode
mA
CLKMC, CLKPLL and CLKRC
stopped
ICCTMAIN
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 1
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
Power supply
current in
Timer modes*
+125°C
0.6
2.9
+25°C
0.35
0.5
+125°C
0.85
3.3
+25°C
0.1
0.15
ICCTRCH
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 1
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 0
+125°C
0.6
2.9
+25°C
0.3
0.45
+125°C
0.8
3.2
+25°C
0.05
0.1
ICCTRCL
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 1
ICCTSUB
+125°C
0.55
2.8
+25°C
0.03
0.1
Sub Timer mode with
CLKSC = 32kHz
+125°C
Document Number: 002-04586 Rev. *A
0.53
2.8
Page 80 of 122
MB96330 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Value
Condition (at TA)
Symbol
+25°C
Typ
Max
0.02
0.08
VRCR:LPMB[2:0] = 110B
Stop Mode
+125°C
0.52
2.8
+25°C
0.015
0.06
Remarks
mA
Core voltage at 1.8V
mA
Core voltage at 1.2V
A
This current must be added to
all Power supply currents
above
ICCH
VRCR:LPMB[2:0] = 000B
Power supply
current for active
Low Voltage
detector
ICCLVD
Clock modulator
current
ICCCLOMO
Flash
Write/Erase current
Input capacitance
Unit
+125°C
0.4
2.3
+25°C
90
140
Low voltage detector enabled (RCR:LVDE = 1)
+125°C
100
150
Clock modulator enabled
(CMCR:PDX = 1)
-
3
4.5
mA
Must be added to all current
above
ICCFLASH
Current for one Flash module
-
15
40
mA
Must be added to all current
above
CIN
-
-
5
15
pF
Other than C, AVCC, AVSS,
AVRH, AVRL, VCC, VSS
*: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock
connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for
further details about voltage regulator control.
Document Number: 002-04586 Rev. *A
Page 81 of 122
MB96330 Series
14.4 AC Characteristics
Source Clock timing
Parameter
Clock frequency
Clock frequency
Clock frequency
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Symbol
fC
Pin
X0, X1
fFCI
fCL
Value
X0A
Remarks
Typ
Max
3
-
16
MHz When using a crystal oscillator, PLL off
0
-
16
using an opposite phase external clock,
MHz When
PLL off
3.5
-
16
using a crystal oscillator or opposite
MHz When
phase external clock, PLL on
0
-
56
using a single phase external clock in
MHz When
“Fast Clock Input mode”, PLL off
3.5
-
56
using a single phase external clock in
MHz When
“Fast Clock Input mode”. PLL on
32
32.768
100
kHz
When using an oscillation circuit
0
-
100
kHz
When using an opposite phase external clock
0
-
50
kHz
When using a single phase external clock
50
100
200
kHz
When using slow frequency of RC oscillator
1
2
4
X0
X0A, X1A
Unit
Min
fCR
-
PLL Clock
frequency
fCLKVCO
-
64
-
200
PLL Phase Jitter
TPSKEW
-
-
-
5
ns
For CLKMC (PLL input clock) MHz
Input clock pulse
width
PWH, PWL
X0,X1
8
-
-
ns
Duty ratio is about 30% to 70%
Input clock pulse
width
PWHL, PWLL
X0A,X1A
5
-
-
s
Clock frequency
MHz When using fast frequency of RC oscillator
VCO output frequency of PLL
MHz Permitted
(CLKVCO)
tCYL
VIH
X0
VIL
PWH
PWL
tCYLL
VIH
X0A
VIL
PWHL
Document Number: 002-04586 Rev. *A
PWLL
Page 82 of 122
MB96330 Series
Internal Clock timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Core Voltage Settings
Parameter
Internal System clock
frequency (CLKS1 and
CLKS2)
Internal CPU clock frequency
(CLKB), internal peripheral
clock frequency (CLKP1)
Symbol
fCLKS1, fCLKS2
fCLKB, fCLKP1
1.8V
1.9V
Unit
Remarks
Min
Max
Min
Max
0
92
0
96
MHz
Others than below
0
90
0
96
MHz
MB96F33x
0
52
0
56
MHz
Others than below
0
43.5
0
48
MHz
MB96F33x
Internal peripheral clock
frequency (CLKP2)
fCLKP2
0
28
0
32
MHz
Internal peripheral clock
frequency (Clock CLKP3)
fCLKP3
0
43.5
0
48
MHz
WARNING:
MB96F33x
For USB usage, it is important to change the voltage regulator setting to output 1.9V. Please refer to the chapter
Standby Mode and Voltage Regulator control circuit of the hardware manual to perform such setting.
Document Number: 002-04586 Rev. *A
Page 83 of 122
MB96330 Series
External Reset timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
tRSTL
RSTX
Reset input time
Value
Min
Typ
Max
500
-
-
Unit
Remarks
ns
tRSTL
RSTX
0.2 VCC
Document Number: 002-04586 Rev. *A
0.2 VCC
Page 84 of 122
MB96330 Series
Power On Reset timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Power on rise time
Power off time
Symbol
Pin
tR
tOFF
Value
Unit
Min
Typ
Max
Vcc
0.05
-
30
ms
Vcc
1
-
-
ms
Remarks
tR
2.7V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below.
VCC
3V
Document Number: 002-04586 Rev. *A
Rising edge of 50 mV/ms
maximum is allowed
Page 85 of 122
MB96330 Series
External Input timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
Value
Condition
INTn(_R)
NMI(_R)
Input pulse
width
tINH
tINL
Min
Max
200
—
Unit
ns
Used Pin input function
External Interrupt
NMI
Pnn_m
General Purpose IO
TINn(_R)
Reload Timer
—
TTGn(_R)
2*tCLKP1 + 200
(tCLKP1=1/fCLKP1)
ADTG(_R)
PPG Trigger input
—
ns
AD Converter Trigger
FRCKn(_R)
Free Running Timer
external clock
INn(_R)
Input Capture
Note : Relocated Resource Inputs have same characteristics
External Pin input
VIH
VIH
tINH
Document Number: 002-04586 Rev. *A
VIL
VIL
tINL
Page 86 of 122
MB96330 Series
External Bus timing
Note:
The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described
in the different tables must then be increased by 10ns.
Basic Timing
Parameter
(TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Symbol
Pin
Condition
Min
Max
25
—
tCYC/2-5
tCYC/2+5
tCLCH
tCYC/2-5
tCYC/2+5
tCHCBH
-20
20
-20
20
-20
20
tCLCBL
-20
20
tCHLH
-10
10
-10
10
-10
10
-10
10
-15
15
-15
15
-15
15
-15
15
-15
15
-15
15
-10
10
-10
10
-10
10
-10
10
tCYC
ECLK
ECLK →
UBX/ LBX / CSn time
ECLK → ALE time
tCHCL
tCHCBL
tCLCBH
tCHLL
tCLLH
ECLK
CSn, UBX,
LBX, ECLK
ALE, ECLK
—
—
—
tCLLL
ECLK →address valid time
(non-multiplexed)
tCHAV
tCLAV
tCHAV
ECLK →address valid time
(multiplexed)
tCLAV
tCLADV
tCHADV
A[23:0], ECLK
EBM:NMS=1
A[23:16], ECLK
EBM:NMS=0
AD[15:0],
ECLK
EBM:NMS=0
tCHRWH
ECLK → RDX /WRX time
Value
tCHRWL
tCLRWH
tCLRWL
Document Number: 002-04586 Rev. *A
RDX, WRX,
WRLX,WRHX,
ECLK
—
Unit
Remarks
ns
ns
ns
ns
ns
ns
ns
Page 87 of 122
MB96330 Series
(TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Condition
Min
Max
30
—
tCYC/2-8
tCYC/2+8
tCLCH
tCYC/2-8
tCYC/2+8
tCHCBH
-25
25
-25
25
-25
25
tCLCBL
-25
25
tCHLH
-15
15
-15
15
-15
15
-15
15
-20
20
-20
20
-20
20
-20
20
-20
20
-20
20
-15
15
-15
15
-15
15
-15
15
tCYC
ECLK
ECLK →
UBX/ LBX / CSn time
ECLK → ALE time
tCHCL
tCHCBL
tCLCBH
tCHLL
tCLLH
ECLK
CSn, UBX, LBX,
ECLK
ALE, ECLK
—
—
—
tCLLL
ECLK →address valid time
(non-multiplexed)
tCHAV
tCLAV
tCHAV
ECLK →address valid time
(multiplexed)
tCLAV
tCLADV
tCHADV
A[23:0], ECLK
EBM:NMS=1
A[23:16], ECLK
EBM:NMS=0
AD[15:0], ECLK
EBM:NMS=0
tCHRWH
ECLK → RDX /WRX time
Value
tCHRWL
tCLRWH
tCLRWL
Document Number: 002-04586 Rev. *A
RDX, WRX,
WRLX, WRHX,
ECLK
—
Unit
Remarks
ns
ns
ns
ns
ns
ns
ns
Page 88 of 122
MB96330 Series
tCYC
tCHCL
ECLK
tCLCH
0.8*Vcc
0.2*Vcc
tCLAV
tCHAV
A[23:0]
tCHCBL
tCLCBH
tCLCBL
tCHCBH
tCHRWL
tCLRWH
tCLRWL
tCHRWH
CSn
LBX
UBX
RDX
WRX (WRLX, WRHX)
tCLLH
tCHLL
tCHLH
tCLLL
ALE
tCHADV
tCLADV
AD[15:0]
Address
Refer to the Hardware Manual for detailed Timing Charts
Document Number: 002-04586 Rev. *A
Page 89 of 122
MB96330 Series
Bus Timing (Read)
Parameter
(TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Symbol
Pin
Conditions
Min
Max
tCYC/2  5
—
tCYC  5
—
EACL:STS=0 and
EACL:ACE=1
3tCYC/2  5
—
EACL:STS=0 and
EACL:ACE=0
tCYC  15
—
EACL:STS=1 and
EACL:ACE=0
3tCYC/2  15
—
EACL:STS=0 and
EACL:ACE=1
2tCYC  15
—
EACL:STS=1 and
EACL:ACE=1
5tCYC/2  15
—
EACL:STS=0 and
EACL:ACE=0
tCYC/2  15
—
EACL:STS=1 and
EACL:ACE=0
tCYC  15
—
EACL:STS=0 and
EACL:ACE=1
3tCYC/2  15
—
EACL:STS=1 and
EACL:ACE=1
2tCYC  15
—
EACL:STS=0
tCYC/2  15
—
EACL:STS=1
-15
—
EBM:NMS= 1
tCYC/2  15
—
EACL:ACE=0
EBM:NMS=0
3tCYC/2  15
—
EACL:ACE=1
EBM:NMS=0
5tCYC/2  15
—
EACL:ACE=0
EBM:NMS=0
tCYC  15
—
EACL:ACE=1
EBM:NMS=0
2tCYC  15
—
EBM:NMS= 1
—
2tCYC  55
EACL:STS=0 and
EACL:ACE=0
ALE pulse width
(multiplexed)
tLHLL
tAVLL
ALE
ALE, A[23:16],
Valid address
 ALE  time
(multiplexed)
tADVLL ALE,AD[15:0]
ALE 
 Address valid time
(multiplexed)
tLLAX
Valid address
 RDX  time
(non-multiplexed)
tAVRL RDX, A[23:0]
tAVRL
ALE, AD[15:0]
RDX, A[23:16]
Valid address
 RDX  time
(multiplexed)
tADVRL RDX, AD[15:0]
Valid address
 Valid data input
(non-multiplexed)
tAVDV
Document Number: 002-04586 Rev. *A
A[23:0],
AD[15:0]
Value
EACL:STS=1
Unit
Remarks
ns
ns
EBM:NMS
=0
ns
ns
ns
ns
ns
ns
w/o cycle
extension
Page 90 of 122
MB96330 Series
(TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
tAVDV
Pin
A[23:16],
AD[15:0]
Valid address
 Valid data input
(multiplexed)
tADVDV
AD[15:0]
Conditions
Value
Min
Max
EACL:ACE=0
EBM:NMS=0
—
3tCYC  55
EACL:ACE=1
EBM:NMS=0
—
4tCYC  55
EACL:ACE=0
EBM:NMS=0
—
5tCYC/2  55
EACL:ACE=1
EBM:NMS=0
—
7tCYC/2  55
Unit
Remarks
ns
w/o cycle
extension
ns
w/o cycle
extension
RDX pulse width
tRLRH RDX
—
3 tCYC/2  5
—
ns
w/o cycle
extension
RDX   Valid data input
tRLDV RDX, AD[15:0]
—
—
3 tCYC/2  50
ns
w/o cycle
extension
RDX   Data hold time
tRHDX RDX, AD[15:0]
—
0
—
ns
—
0
—
ns
EACL:STS=1 and
EACL:ACE=1
3tCYC/2  10
—
other ECL:STS,
EACL:ACE setting
tCYC/2  10
—
tCYC  15
—
tCYC/2  15
—
tCYC/2  10
—
EACL:STS=0
tCYC/2  10
—
EACL:STS=1
 10
—
—
tCYC  50
Address valid  Data hold time tAXDX A[23:0], AD[15:0]
RDX   ALE  time
Valid address
 ECLK  time
tRHLH RDX, ALE
tAVCH A[23:0], ECLK
tADVCH
AD[15:0], ECLK
RDX   ECLK  time
tRLCH RDX, ECLK
ALE   RDX  time
tLLRL
ECLK  Valid data input
tCHDV AD[15:0], ECLK
Document Number: 002-04586 Rev. *A
ALE, RDX
—
—
—
ns
ns
ns
ns
ns
Page 91 of 122
MB96330 Series
(TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Conditions
Min
Max
tCYC/2  8
—
tCYC  8
—
EACL:STS=0 and
EACL:ACE=1
3tCYC/2  8
—
EACL:STS=0 and
EACL:ACE=0
tCYC  20
—
EACL:STS=1 and
EACL:ACE=0
3tCYC/2  20
—
EACL:STS=0 and
EACL:ACE=1
2tCYC  20
—
EACL:STS=1 and
EACL:ACE=1
5tCYC/2  20
—
EACL:STS=0 and
EACL:ACE=0
tCYC/2  20
—
EACL:STS=1 and
EACL:ACE=0
tCYC  20
—
EACL:STS=0 and
EACL:ACE=1
3tCYC/2  20
—
EACL:STS=1 and
EACL:ACE=1
2tCYC  20
—
EACL:STS=0
tCYC/2  20
—
EACL:STS=1
-20
—
EBM:NMS= 1
tCYC/2  20
—
EACL:ACE=0
EBM:NMS=0
3tCYC/2  20
—
EACL:ACE=1
EBM:NMS=0
5tCYC/2  20
—
EACL:ACE=0
EBM:NMS=0
tCYC  20
—
EACL:ACE=1
EBM:NMS=0
2tCYC  20
—
EBM:NMS= 1
—
2tCYC  60
EACL:STS=0 and
EACL:ACE=0
ALE pulse width
(multiplexed)
tLHLL
tAVLL
ALE
ALE, A[23:16],
Valid address
 ALE  time
(multiplexed)
tADVLL ALE, AD[15:0]
ALE 
 Address valid time
(multiplexed)
tLLAX
Valid address
 RDX  time
(non-multiplexed)
tAVRL RDX, A[23:0]
tAVRL
ALE, AD[15:0]
RDX, A[23:16]
Valid address
 RDX  time
(multiplexed)
tADVRL RDX, AD[15:0]
Valid address
 Valid data input
(non-multiplexed)
tAVDV
Document Number: 002-04586 Rev. *A
A[23:0],
AD[15:0]
Value
EACL:STS=1
Unit
Remarks
ns
ns
EBM:NMS
=0
ns
ns
ns
ns
ns
ns
w/o cycle
extension
Page 92 of 122
MB96330 Series
(TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
tAVDV
Pin
A[23:16],
AD[15:0]
Valid address
 Valid data input
(multiplexed)
tADVDV
AD[15:0]
Conditions
Value
Min
Max
EACL:ACE=0
EBM:NMS=0
—
3tCYC  60
EACL:ACE=1
EBM:NMS=0
—
4tCYC  60
EACL:ACE=0
EBM:NMS=0
—
5tCYC/2  60
EACL:ACE=1
EBM:NMS=0
—
7tCYC/2  60
Unit
Remarks
ns
w/o cycle
extension
ns
w/o cycle
extension
RDX pulse width
tRLRH RDX
—
3tCYC/2  8
—
ns
w/o cycle
extension
RDX   Valid data input
tRLDV RDX, AD[15:0]
—
—
3tCYC/2  55
ns
w/o cycle
extension
RDX   Data hold time
tRHDX RDX, AD[15:0]
—
0
—
ns
—
0
—
ns
EACL:STS=1 and
EACL:ACE=1
3tCYC/2  15
—
other ECL:STS,
EACL:ACE setting
tCYC/2  15
—
tCYC  20
—
tCYC/2  20
—
tCYC/2  15
—
EACL:STS=0
tCYC/2  15
—
EACL:STS=1
 15
—
—
tCYC  55
Address valid  Data hold time tAXDX A[23:0]
RDX   ALE  time
Valid address
 ECLK  time
tRHLH RDX, ALE
tAVCH A[23:0], ECLK
tADVCH
AD[15:0], ECLK
RDX   ECLK  time
tRLCH RDX, ECLK
ALE   RDX  time
tLLRL
ECLK  Valid data input
tCHDV AD[15:0], ECLK
Document Number: 002-04586 Rev. *A
ALE, RDX
—
—
—
ns
ns
ns
ns
ns
Page 93 of 122
MB96330 Series
tAVCH
tRLCH
tADVCH
ECLK
.
tCHDV
0.8*Vcc
tAVLL
tLLAX
tADVLL
ALE
tRHLH
0.2*VCC
tLHLL
tAVRL
tRLRH
tADVRL
RDX
tLLRL
A[23:0]
tRLDV
tAVDV
tAXDX
tRHDX
tADVDV
AD[15:0]
Address
VIH
VIL
Read data
VIH
VIL
Refer to the Hardware Manual for detailed Timing Charts
Document Number: 002-04586 Rev. *A
Page 94 of 122
MB96330 Series
Bus Timing (Write)
Parameter
Valid address
 WRX  time
(non-multiplexed)
(TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Symbol
tAVWL
tAVWL
Pin
WRX, WRLX,
WRHX,
A[23:0]
WRX, WRLX,
WRHX, A[23:16]
Valid address
 WRX  time
(multiplexed)
tADVWL
WRX, WRLX,
WRHX, AD[15:0]
Condition
Value
Min
Max
EACL:STS=0
EBM:NMS=1
tCYC/2  15
—
EACL:STS=1
EBM:NMS=1
tCYC  15
—
EACL:ACE=0
EBM:NMS=0
3tCYC/2  15
—
EACL:ACE=1
EBM:NMS=0
5tCYC/2  15
—
EACL:ACE=0
EBM:NMS=0
tCYC  15
—
EACL:ACE=1
EBM:NMS=0
2tCYC  15
—
Unit
Remarks
ns
ns
ns
WRX pulse width
tWLWH
WRX, WRXL,
WRHX
—
tCYC  5
—
ns
w/o cycle
extension
Valid data output
 WRX  time
tDVWH
WRX, WRLX,
WRHX, AD[15:0]
—
tCYC  20
—
ns
w/o cycle
extension
WRX 
 Data hold time
tWHDX
WRX, WRLX,
WRHX, AD[15:0]
—
tCYC/2  15
—
ns
WRX 
 Address valid time
(non-multiplexed)
EACL:STS=1
EBM:NMS=1
EACL:STS=0
EBM:NMS=1
 15
—
ns
tWHAX
WRX, WRLX,
WRHX, A[23:0]
tCYC/2  15
—
ns
WRX 
 Address valid time
(multiplexed)
tWHAX
WRX, WRLX,
WRHX, A[23:16]
EBM:NMS=0
tCYC/2  15
—
ns
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE
and
EACL:STS setting
2tCYC  10
—
tCYC  10
—
—
tCYC/2  10
—
EACL:STS=0
EBM:NMS=1
—
tCYC/2  15
EACL:STS=1
EBM:NMS=1
—
tCYC  15
EACL:ACE=0
EBM:NMS=0
—
3tCYC/2  15
EACL:ACE=1
EBM:NMS=0
—
5tCYC/2  15
WRX   ALE  time
(multiplexed)
tWHLH
WRX, WRLX,
WRHX, ALE
WRX   ECLK  time
tWLCH
WRX, WRLX,
WRHX, ECLK
tCSLWL
WRX, WRLX,
WRHX, CSn
CSn  WRX time
(non-multiplexed)
CSn  WRX time
(multiplexed)
tCSLWL
WRX, WRLX,
WRHX, CSn
Document Number: 002-04586 Rev. *A
ns
EBM:NMS=0
ns
ns
ns
Page 95 of 122
MB96330 Series
(TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
WRX  CSn time
(non-multiplexed)
WRX  CSn time
(multiplexed)
Symbol
Pin
Condition
Value
Min
Max
Unit
EACL:STS=1
EBM:NMS=1
EACL:STS=0
EBM:NMS=1
 15
—
ns
tWHCSH
WRX, WRLX,
WRHX, CSn
tCYC/2  15
—
ns
tWHCSH
WRX, WRLX,
WRHX, CSn
EBM:NMS=0
tCYC/2  15
—
ns
Remarks
(TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Valid address
 WRX  time
(non-multiplexed)
Symbol
tAVWL
tAVWL
Pin
WRX, WRLX,
WRHX,
A[23:0]
WRX, WRLX,
WRHX, A[23:16]
Valid address
 WRX  time
(multiplexed)
tADVWL
WRX, WRLX,
WRHX, AD[15:0]
Condition
Value
Min
Max
EACL:STS=0
EBM:NMS=1
tCYC/2  20
—
EACL:STS=1
EBM:NMS=1
tCYC  20
—
EACL:ACE=0
EBM:NMS=0
3tCYC/2  20
—
EACL:ACE=1
EBM:NMS=0
5tCYC/2  20
—
EACL:ACE=0
EBM:NMS=0
tCYC  20
—
EACL:ACE=1
EBM:NMS=0
2tCYC  20
—
Unit
Remarks
ns
ns
ns
WRX pulse width
tWLWH
WRX, WRXL,
WRHX
—
tCYC  8
—
ns
w/o cycle
extension
Valid data output
 WRX  time
tDVWH
WRX, WRLX,
WRHX, AD[15:0]
—
tCYC  25
—
ns
w/o cycle
extension
WRX 
 Data hold time
tWHDX
WRX, WRLX,
WRHX, AD[15:0]
—
tCYC/2  20
—
ns
WRX 
 Address valid time
(non-multiplexed)
EACL:STS=1
EBM:NMS=1
EACL:STS=0
EBM:NMS=1
 20
—
ns
tWHAX
WRX, WRLX,
WRHX, A[23:0]
tCYC/2  20
—
ns
WRX 
 Address valid time
(multiplexed)
tWHAX
WRX, WRLX,
WRHX, A[23:16]
EBM:NMS=0
tCYC/2  20
—
ns
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE
and
EACL:STS setting
2tCYC  15
—
tCYC  15
—
—
tCYC/2  15
—
WRX   ALE  time
(multiplexed)
tWHLH
WRX, WRLX,
WRHX, ALE
WRX   ECLK  time
tWLCH
WRX, WRLX,
WRHX, ECLK
Document Number: 002-04586 Rev. *A
ns
EBM:NMS=0
ns
Page 96 of 122
MB96330 Series
(TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
CSn  WRX time
(non-multiplexed)
CSn  WRX time
(multiplexed)
WRX  CSn time
(non-multiplexed)
WRX  CSn time
(multiplexed)
Symbol
tCSLWL
tCSLWL
Pin
Value
Condition
WRX, WRLX,
WRHX, CSn
WRX, WRLX,
WRHX, CSn
Min
Max
EACL:STS=0
EBM:NMS=1
—
tCYC/2  20
EACL:STS=1
EBM:NMS=1
—
tCYC  20
EACL:ACE=0
EBM:NMS=0
—
3tCYC/2  20
EACL:ACE=1
EBM:NMS=0
—
5tCYC/2  20
Unit
Remarks
ns
ns
EACL:STS=1
EBM:NMS=1
EACL:STS=0
EBM:NMS=1
 20
—
ns
tWHCSH
WRX, WRLX,
WRHX, CSn
tCYC/2  20
—
ns
tWHCSH
WRX, WRLX,
WRHX, CSn
EBM:NMS=0
tCYC/2  20
—
ns
tWLCH
0.8*VCC
ECLK
tWHLH
ALE
tAVWL
tADVWL
WRX (WRLX, WRHX)
tWLWH
0.2*VCC
tCSLWL
tWHCSH
CSn
tWHAX
A[23:0]
tDVWH
AD[15:0]
Address
tWHDX
Write data
Refer to the Hardware Manual for detailed Timing Charts
Document Number: 002-04586 Rev. *A
Page 97 of 122
MB96330 Series
.
Ready Input Timing
Parameter
(TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Symbol
Pin
RDY setup time
tRYHS
RDY
RDY hold time
tRYHH
RDY
Test
Condition
Rated Value
Units
Min
Max
35
—
ns
0
—
ns
—
Remarks
(TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
RDY setup time
tRYHS
RDY
RDY hold time
tRYHH
RDY
Test
Condition
Rated Value
Units
Min
Max
45
—
ns
0
—
ns
—
Remarks
Note : If the RDY setup time is insufficient, use the auto-ready function.
ECLK
0.8*VCC
tRYHS
RDY
When WAIT is not used.
RDY
When WAIT is used.
VIH
tRYHH
VIH
VIL
Refer to the Hardware Manual for detailed Timing Charts
Document Number: 002-04586 Rev. *A
Page 98 of 122
MB96330 Series
Hold Timing
(TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Pin floating  HAKX  time
tXHAL
HAKX
HAKX  time  Pin valid time
tHAHV
HAKX
Value
Condition
—
Units
Min
Max
tCYC  20
tCYC + 20
ns
tCYC  20
tCYC + 20
ns
Remarks
(TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Pin floating  HAKX  time
tXHAL
HAKX
HAKX  time  Pin valid time
tHAHV
HAKX
Value
Condition
Min
—
Units
tCYC  25 tCYC + 25
ns
tCYC  25 tCYC + 25
ns
Remarks
0.8*VCC
HAKX
0.2*VCC
tHAHV
tXHAL
Each pin
Max
0.8*VCC
High-Z
0.2*VCC
Refer to the Hardware Manual for detailed Timing Charts
Document Number: 002-04586 Rev. *A
Page 99 of 122
MB96330 Series
USART timing
WARNING:
The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing
described in the different tables must then be increased by 10ns.
(TA = -40°C to 125°C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Condition
VCC = AVCC= 4.5V
to 5.5V
VCC = AVCC= 3.0V to
4.5V
Min
Max
Min
Max
Unit
Serial clock cycle time
tSCYCI
SCKn
4 tCLKP1
—
4 tCLKP1
—
ns
SCK ↓ → SOT delay time
tSLOVI
SCKn,
SOTn
-20
20
-30
30
ns
SOT → SCK ↑ delay time
tOVSHI
SCKn,
SOTn
N*tCLKP1
- 20 *1
—
N*tCLKP1 30 *1
—
ns
Valid SIN → SCK ↑
tIVSHI
SCKn,
SINn
tCLKP1 +
45
—
tCLKP1 +
55
—
ns
SCK ↑ → Valid SIN hold
time
tSHIXI
SCKn,
SINn
0
—
0
—
ns
Serial clock “L” pulse width
tSLSHE
SCKn
tCLKP1 +
10
—
tCLKP1 +
10
—
ns
Serial clock “H” pulse width
tSHSLE
SCKn
tCLKP1 +
10
—
tCLKP1 +
10
—
ns
SCK ↓ → SOT delay time
tSLOVE
SCKn,
SOTn
—
2 tCLKP1
+ 45
—
2 tCLKP1
+ 55
ns
Valid SIN → SCK ↑
tIVSHE
SCKn,
SINn
tCLKP1/2
+ 10
—
tCLKP1/2 +
10
—
ns
SCK ↑ → Valid SIN hold
time
tSHIXE
SCKn,
SINn
tCLKP1 +
10
—
tCLKP1 +
10
—
ns
SCK fall time
tFE
SCKn
—
20
—
20
ns
SCK rise time
tRE
SCKn
—
20
—
20
ns
Internal Shift
Clock Mode
External Shift
Clock Mode
Notes: • AC characteristic in CLK synchronized mode.
• CL is the load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters.
These parameters are shown in “MB96300 Super series Hardware Manual”
• tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns
*1: Parameter N depends on tSCYCI and can be calculated as follows:
• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1
Examples:
tSCYCI
N
4*tCLKP1
2
5*tCLKP1, 6*tCLKP1
3
7*tCLKP1, 8*tCLKP1
4
...
...
Document Number: 002-04586 Rev. *A
Page 100 of 122
MB96330 Series
tSCYCI
SCK for
ESCR:SCES = 0
0.8*VCC
0.2*VCC
0.2*VCC
SCK for
ESCR:SCES = 1
0.8*VCC
0.8*VCC
0.2*VCC
tOVSHI
tSLOVI
0.8*VCC
SOT
0.2*VCC
tSHIXI
tIVSHI
SIN
VIH
VIH
VIL
VIL
Internal Shift Clock Mode
tSHSLE
tSLSHE
SCK for
ESCR:SCES = 0
VIH
SCK for
ESCR:SCES = 1
VIL
VIH
VIH
VIL
tFE
SOT
VIL
tSLOVE
VIH
VIL
VIL
tRE
0.8*VCC
0.2*VCC
tIVSHE
SIN
VIH
tSHIXE
VIH
VIH
VIL
VIL
External Shift Clock Mode
Document Number: 002-04586 Rev. *A
Page 101 of 122
MB96330 Series
I2C Timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V,VSS = AVSS =0V)
Parameter
Symbol
Condition
Standard-mode
Fast-mode*4
Unit
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
tHDSTA
4.0
—
0.6
—
s
“L” width of the SCL clock
tLOW
4.7
—
1.3
—
s
“H” width of the SCL clock
tHIGH
4.0
—
0.6
—
s
4.7
—
0.6
—
s
0
3.45*2
0
0.9*3
s
SCL clock frequency
Hold time (repeated) START condition
SDA↓→SCL↓
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
Data hold time
SCL↓→SDA↓↑
tHDDAT
Data set-up time
SDA↓↑→SCL↑
tSUDAT
250
—
100
—
ns
Set-up time for STOP condition
SCL↑→SDA↑
tSUSTO
4.0
—
0.6
—
s
tBUS
4.7
—
1.3
—
s
Bus free time between a STOP and START condition
R  1.7 k,
C  50 pF*1
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
SDA
tSUDAT
tLOW
tBUS
tHDSTA
SCL
tHDSTA
tHDDAT
Document Number: 002-04586 Rev. *A
tHIGH
tSUSTA
tSUSTO
Page 102 of 122
MB96330 Series
14.5 USB Characteristics
(TA = -40°C to 105°C, VCC = AVCC= 3.0V to 5.5V,VSS = AVSS = 0V, VCC3 = 3.0V to 3.6V, USB pins UDP and UDM)
Parameter
Input
characteristics
Symbol
Conditions
Input High level voltage
VIH
Input Low level voltage
Remarks
Max
—
2.0
VCC  0.3
V
*1
VIL
—
VSS  0.3
0.8
V
*1
Differential input sensitivity
VDI
—
0.2
—
V
*2
Differential common
mode input voltage
VCM
—
0.8
2.5
V
*2
VOH
External
pull-down
resistance 
15 k
2.8
3.6
V
*3
VOL
External
pull-up
resistance 
1.5 k
0.0
0.3
V
*3
Output Low level voltage
Input
capacitance
Unit
Min
Output High level voltage
Output
characteristics
Value
VCRS
—
1.3
2.0
V
*4
Rise time
tFR
—
4
20
nS
*5
Fall time
tFF
—
4
20
nS
*5
Rise/fall time matching
tRFM
—
90
111.11

*5
Output impedance
ZDRV
—
28
44

Including
Rs  27 
CEDGE
—
—
75
pF
*6
RS
—
25
30

Recommended
value:27 
Crossover voltage
Transceiver edge rate
control capacitance
Series resistance
*1 : The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max)  0.8 [V],
VIH (Min)  2.0 [V] (TTL input standard).
There are some hystereses to lower noise sensitivity.
(Continued)
Document Number: 002-04586 Rev. *A
Page 103 of 122
MB96330 Series
(Continued)
*2 : Use differential-Receiver to receive USB differential data signal.
Differential-Receiver has 200 [mV] of differential input sensitivity when the differential data input is within 0.8 [V] to 2.5 [V] to the
local ground reference level.
Above voltage range is the common mode input voltage range.
Minimum differential input sensitivity [V]
1.0 [V]
0.2 [V]
0.8 [V]
2.5 [V]
Common mode input voltage [V]
*3 : The output drive capability of the driver is below 0.3 [V] at Low-State (VOL) (to 3.6 [V] and 1.5 k load), and 2.8 [V] or above (to
the VSS and 1.5 k load).
*4 : The cross voltage of the external differential output signal (D  /D  ) of USB I/O buffer is within 1.3 [V] to 2.0 [V].
D+
Max 2.0 [V]
VCRS standard range
Min 1.3 [V]
D-
*5 : Regarding tFR ,tFF, tRFM
They indicate rise time (Trise) and fall time (Tfall) of the differential data signal.
They are defined by the time between 10 to 90 of the output signal voltage.
For full-speed buffer, tFR/tFF ratio is regulated as within 10 to minimize RFI emission.
Rise time
UDP
UDM
VCRS
90%
Fall time
90%
10%
10%
tFR
tFF
(Continued)
Document Number: 002-04586 Rev. *A
Page 104 of 122
MB96330 Series
(Continued)
*6 : The place to connect transceiver edge rate control capacitance CEDGE
For this USB I/O, it is recommended to use CEDGE control capacitor.
For USB Max standard as 75 pF, please control the edge characteristic of output waveform by connecting 30 to
50 [pF] (recommended value : 47 [pF] =: 50[pF]) to D  and D  lines when implementing on the board.
RS = 27 Ω
+D
CEDGE
3-State
RS = 27 Ω
-D
CEDGE
Driver output impedance 3  to 19 
Rs serial resistance value 25  to 30 
Please apply 27  of serial resistance value as a recommended value.
Document Number: 002-04586 Rev. *A
Page 105 of 122
MB96330 Series
14.6 Analog Digital Converter
(TA = -40 °C to +125 °C, 3.0 V AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
Resolution
-
Total error
Value
Unit
Remarks
Min
Typ
Max
-
-
-
10
bit
-
-
-3
-
+3
LSB
Nonlinearity error
-
-
-2.5
-
+2.5
LSB
Differential nonlinearity error
-
-
-1.9
-
+1.9
LSB
VOT
ANn
AVRL - 1.5
LSB
AVRL+
0.5 LSB
AVRL +
2.5 LSB
V
VFST
ANn
AVRH 3.5 LSB
AVRH 1.5 LSB
AVRH +
0.5 LSB
V
Compare time
-
-
1.0
-
16,500
s
4.5V VCC  5.5V
2.0
-
-
s
3.0V VCC  4.5V
Sampling time
-
-
0.5
-
-
s
4.5V VCC  5.5V
1.2
-
-
s
3.0V VCC  4.5V
IAIN
ANn
-3
-
+3
A
AVSS, AVRL < VI <
AVCC, AVRH
-1
-
+1
A
TA  25 °C,
AVSS, AVRL < VI <
AVCC, AVRH
-3
-
+3
A
TA  125 °C,
AVSS, AVRL < VI <
AVCC, AVRH
Zero reading voltage
Full scale reading
voltage
Analog port input current
Analog port input current
Analog input voltage range
Reference voltage range
Power supply current
Reference voltage current
Offset between input
channels
IAIN
ANn
VAIN
ANn
AVRL
-
AVRH
V
AVRH
AVRH
0.75 AVcc
-
AVcc
V
AVRL
AVRL
AVSS
-
0.25 AVCC
V
IA
AVcc
-
2.5
5
mA
A/D Converter active
IAH
AVcc
-
-
5
A
A/D Converter not
operated
IR
AVRH/AVRL
-
0.7
1
mA
A/D Converter active
IRH
AVRH/AVRL
-
-
5
A
A/D Converter not
operated
-
ANn
-
-
4
LSB
Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.
Document Number: 002-04586 Rev. *A
Page 106 of 122
MB96330 Series
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition
error and nonlinearity error.
Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” <--> “00 0000 0001”) and full-scale transition
line (“11 1111 1110” <--> “11 1111 1111”) and actual conversion characteristics.
Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Zero reading voltage: Input voltage which results in the minimum conversion value.
Full scale reading voltage: Input voltage which results in the maximum conversion value.
Total error
3FF
3FE
1.5 LSB
Actual conversion
characteristics
Digital output
3FD
{1 LSB × (N − 1) + 0.5 LSB}
004
VNT
(Actually-measured value)
003
Actual conversion
characteristics
Ideal characteristics
002
001
0.5 LSB
AVRL
AVRH
Analog input
VNT  {1 LSB × (N  1)  0.5 LSB}
1 LSB
Total error of digital output “N” 
1 LSB  (Ideal value)
AVRH  AVRL
1024
[LSB]
[V]
N: A/D converter digital output value
VOT (Ideal value)  AVRL  0.5 LSB [V]
VFST (Ideal value)  AVRH  1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N  1) to N.
Document Number: 002-04586 Rev. *A
Page 107 of 122
MB96330 Series
Nonlinearity error
Differential nonlinearity error
Ideal
characteristics
3FF
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
Digital output
3FD
N+1
VFST (actual
measurement
value)
VNT (actual
measurement value)
004
Actual conversion
characteristics
003
Digital output
3FE
Actual conversion
characteristics
N
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
N−1
002
Ideal characteristics
Actual conversion
characteristics
N−2
001
VOT (actual measurement value)
AVRL
AVRH
AVRL
AVRH
Analog input
Analog input
VNT  {1 LSB × (N  1)  VOT}
1 LSB
Nonlinearity error of digital output N 
Differential nonlinearity error of digital output N 
V (N+1) T  VNT
1 LSB 
1 LSB
VFST  VOT
1022
[LSB]
1 LSB [LSB]
[V]
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
Notes on A/D Converter Section
• About the external impedance of the analog input and the sampling time of the A/D converter (with sample and hold circuit):
If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold
capacitor is insufficient, adversely affecting A/D conversion precision.
analog input circuit model:
R
Comparator
Analog input
C
Sampling switch
Reference value:
• C = 8.5 pF (Max)
Document Number: 002-04586 Rev. *A
Page 108 of 122
MB96330 Series
To satisfy the A/D conversion precision standard, the relationship between the external impedance and minimum sampling time must
be considered and then either the resistor value and operating frequency must be adjusted or the external impedance must be
decreased so that the sampling time (Tsamp) is longer than the minimum value. Usually, this value is set to 7where= RC. If the
external input resistance (Rext) connected to the analog input is included, the sampling time is expressed as follows:
Tsamp [min] = 7 × (Rext + 2.6k) × C for 4.5 AVcc 5.5
Tsamp [min] = 7 × (Rext + 12.1k) × C for 3.0 AVcc 4.5
If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin.
About the error
The accuracy gets worse as |AVRH - AVRL| becomes smaller.
Document Number: 002-04586 Rev. *A
Page 109 of 122
MB96330 Series
14.7 Alarm Comparator
(TA = -40 °C to +125 °C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
IA5ALMF
Power supply current
IA5ALMS
AVCC
IA5ALMH
Value
Unit
Remarks
Min
Typ
Max
-
25
45
A
Alarm comparator
enabled in fast mode
(one channel)
-
7
13
A
Alarm comparator
enabled in slow mode
(one channel)
-
-
5
A
Alarm comparator
disabled
-1
-
+1
A
TA = 25 °C
-3
-
+3
A
TA = 125 °C
ALARM pin input current
IALIN
ALARM pin input voltage
range
VALIN
0
-
AVCC
V
External low threshold
high->low transition
VEVTL(H->L)
0.36 * AVCC
-0.25
0.36 * AVCC
-0.1
-
V
External low threshold
low->high transition
VEVTL(L->H)
-
0.36 * AVCC
+0.1
0.36 * AVCC
+0.25
V
External high threshold
high->low transition
VEVTH(H->L)
0.78 * AVCC
-0.25
0.78 * AVCC
-0.1
-
V
External high threshold
low->high transition
VEVTH(L->H)
0.78 * AVCC
+0.1
0.78 * AVCC
+0.25
V
Internal low threshold
high->low transition
VIVTL(H->L)
0.9
1.1
-
V
Internal low threshold
low->high transition
VIVTL(L->H)
-
1.3
1.55
V
Internal high threshold
high->low transition
VIVTH(H->L)
2.2
2.4
-
V
Internal high threshold
low->high transition
VIVTH(L->H)
-
2.6
2.85
V
VHYS
50
-
300
mV
tCOMPF
-
0.1
1
s
CMD = 1 (fast)
tCOMPS
-
1
10
s
CMD = 0 (slow)
tCMD
-
100
500
s
Threshold levels
specified above are not
guaranteed within this
time
Switching hysteresis
Comparison time
Slow/Fast mode transition
time
ALARM0,
ALARM1
INTREF = 0
INTREF = 1
Document Number: 002-04586 Rev. *A
Page 110 of 122
MB96330 Series
Comparator
Output
H
L
VxVTx(H->L)
VHYS
VALIN
VxVTx(L->H)
Document Number: 002-04586 Rev. *A
Page 111 of 122
MB96330 Series
14.8 Low Voltage Detector characteristics
(TA = -40 °C to +125 °C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V)
Parameter
Symbol
Value
Unit
Remarks
Min
Max
TLVDSTAB
60
75
s
Level 0
VDL0
2.7
2.9
V
CILCR:LVL[3:0]=”0000”
Level 1
VDL1
2.9
3.1
V
CILCR:LVL[3:0]=”0001”
Level 2
VDL2
3.1
3.3
V
CILCR:LVL[3:0]=”0010”
Level 3
VDL3
3.5
3.75
V
CILCR:LVL[3:0]=”0011”
Level 4
VDL4
3.6
3.85
V
CILCR:LVL[3:0]=”0100”
Level 5
VDL5
3.7
3.95
V
CILCR:LVL[3:0]=”0101”
Level 6
VDL6
3.8
4.05
V
CILCR:LVL[3:0]=”0110”
Level 7
VDL7
3.9
4.15
V
CILCR:LVL[3:0]=”0111”
Level 8
VDL8
4.0
4.25
V
CILCR:LVL[3:0]=”1000”
Level 9
VDL9
4.1
4.35
V
CILCR:LVL[3:0]=”1001”
Level 10
VDL10
not used
Level 11
VDL11
not used
Level 12
VDL12
not used
Level 13
VDL13
not used
Level 14
VDL14
not used
Level 15
VDL15
not used
Stabilization time
CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.
Levels 10 to 15 are not used in this device.
V
dV
For correct detection, the slope of the voltage level must satisfy dt ≤ 0.004 μs .
Faster variations are regarded as noise and may not be detected.
The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of Vcc = 2.7V. The electrical
characteristics however are only valid in the specified range (usually down to 3.0V).
Document Number: 002-04586 Rev. *A
Page 112 of 122
MB96330 Series
Low Voltage Detector Operation
In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup
behavior, please refer to the corresponding hardware manual chapter.
Voltage [V]
VCC
VDLx, Max
VDLx, Min
dV
dt
Time [s]
Normal Operation
Document Number: 002-04586 Rev. *A
Low Voltage Reset Assertion
Power Reset Extension Time
Page 113 of 122
MB96330 Series
14.9 FLASH memory program/erase characteristics
(TA = -40°C to 105°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Value
Unit
Remarks
3.6
s
Without erasure pre-programming
time
n*0.9
n*3.6
s
Without erasure pre-programming
time (n is the number of Flash sector
of the device)
-
23
370
us
Without overhead time for submitting
write command
10 000
-
-
cycle
20
-
-
year
Min
Typ
Max
Sector erase time
-
0.9
Chip erase time
-
Word (16-bit width) programming time
Program/Erase cycle
Flash data retention time
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high
temperature measurements into normalized value at 85oC)
Document Number: 002-04586 Rev. *A
Page 114 of 122
MB96330 Series
15. Example Characteristics
To be prepared
Document Number: 002-04586 Rev. *A
Page 115 of 122
MB96330 Series
16. Package Dimension MB96(F)33x LQFP 144P
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
0.50 mm
Package width ×
package length
20.0 × 20.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
1.20g
Code
(Reference)
P-LFQFP144-20×20-0.50
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00±0.20(.866±.008)SQ
* 20.00±0.10(.787±.004)SQ
108
Lead pitch
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0˚~8˚
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
Document Number: 002-04586 Rev. *A
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
©2003-2008
FUJITSU MICROELECTRONICS LIMITED F144019S-c-4-7
C
2003 FUJITSU LIMITED F144019S-c-4-6
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mounting height)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Page 116 of 122
MB96330 Series
17. Ordering Information
Flash/ROM
Part number
MB96F336USA PMC-GSE2 *1
MB96F336UWA
PMC-GSE2 *1
Flash A (288KB)
MB96F338YSA PMC-GSE2 *1
MB96F338RSA PMC-GSE2
MB96F338YWA PMC-GSE2
MB96F338USA
MB96F338UWA
PMC-GSE2 *1
MB96V300BRB-ES
(for evaluation)
Yes
Flash A (544KB)
Yes
MB96F338RWA PMC-GSE2 *1
PMC-GSE2 *1
No
No
*1
*1
Subclock
Flash A (544KB)
Emulated by ext.
RAM
No
Yes
Yes
Persistent
Low Voltage
Reset
Package
Remarks
No
144 pin Plastic LQFP
(FPT-144P-M08)
with USB
Yes
No
Yes
144 pin Plastic LQFP
(FPT-144P-M08)
No
No
144 pin Plastic LQFP
(FPT-144P-M08)
No
416 pin Plastic BGA
(BGA-416P-M02)
with USB
*1: These devices are under development and specification is preliminary. These products under development may change its
specification without notice.
Document Number: 002-04586 Rev. *A
Page 117 of 122
MB96330 Series
18. Revision History
Revision
Date
Modification
Prelim 0.1
2007-05-23
Creation
Prelim 0.2
2007-08-14
- information about MB96F338U (with USB function) is added
- DMA 8ch --> 16ch
- ADC reference switch is removed
Prelim 0.3
2007-09-11
- Circuit Type of Device with “U“ suffix is added
- Circuit Type diagram: TTL input cell type was changed from NOR to NAND
- IO Map, IRQ table are updated
- Parallel Programing Flash Memory Control Signals is updated
- DC/AC spec of USB I/O is added
Prelim 0.4
2007-09-24
- Block diagram for MB96F338U was corrected: USB PB1 -> PB3
- IRQ table was modified: Vector number 111 was inserted (reserved)
- Pin assignment was corrected: not used resource name was removed
Prelim 0.5
2007-11-02
- Internal Max Freq 56MHz --> 48MHz
- DMA 12ch --> 10ch
- FPT-144P-M12 package was removed
2007-12-20
Update of the block diagram to include USB block.
Update DC characteristics to include all USB pins characteristics.
IOMAP regenerated.
Memory maps and Flash configuration reworked.
Typos corrected across the document.
Renaming of the Flash banks.
2008-02-07
• Features:
- Removed ADC reference switch
- changed USB description
• Lineup:
- option description added
- Part number names corrected
- Flash B removed
- RLT6 added
• Block diagrams:
- Flash B removed
- OUT5_R -> OUT6_R
- TX2_R, RX2_R added
- SIN2_R, SOT2_R, SCK2_R and SOT9 added
- not existing TTGx, TTGx_R and PPGx_R pins deleted
- RLT6 added
• Pin function description: relocated clock output and CAN pins added
• I/O circuit types updated
• Memory maps replaced by new standard maps
• Parallel Flash programming pinning removed
• IOMAP regenerated (naming style changed, all reserved registers added)
• DC current limits updated with new setting and corrected frequencies
• External bus timings: missing conditions added and readability improved
• Alarm comparator spec updated (transition voltages defined)
• Ordering information updated
• Typos and formatting corrected
Prelim 1
Prelim 2
Document Number: 002-04586 Rev. *A
Page 118 of 120
MB96330 Series
Revision
Prelim 3
Date
2008-11-24
Modification
• Format adjusted to official Fujitsu Microelectronics datasheet standard (mainly style changes
and official notes and disclaimer added)
• Note about devices under development modified
• I/O map: Note added about reserved addresses
• Serial programming interface: Note about handshaking pins improved
• specified AD converter channel offset to 4LSB
• package code of MB96V300 corrected in ordering information
• Added voltage condition to pull-up resistance spec
• ROM devices removed from lineup, memory map and ordering information
• Ordering information: column “Flash/ROM added”
• Official package dimension drawing with additional notes added
• Empty pages removed
• adjusted Run and Sleep mode specifications according to evaluation results
• Absolute maximum ratings: VIUSB and VOUSB corrected, permitted power dissipation spec
added
• DC characteristics: Output H/L voltage for USB pins: specified for load of 20mA
• USB characteristics: updated according to MB91660 series
• Alarm comparator: Power supply current max values increased, comparison time reduced,
mode transition time newly added
• Handling devices: Notes added about Serial communication and about using ceramic resonators.
• Feature list and AC Characteristics: 16MHz maximum frequency is valid for crystal oscillators.
For resonators, maximum frequency depends on Q-factor
• AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz
• New family member MB96F336U added
• VOL3 spec improved: spec valid for 3mA load for full Vcc range
Document Number: 002-04586 Rev. *A
Page 119 of 120
MB96330 Series
19. Major Changes
Spansion Publication Number: DS07-13805-1E
Page
108
Section
Electrical Characteristics
5. Analog Digital Converter
Change Results
Changed the item for “Zero reading voltage” and “Full scale reading
voltage”.
NOTE: Please see “Document History” about later revised information.
Document Number: 002-04586 Rev. *A
Page 120 of 120
MB96330 Series
Document History
Document Title: MB96330 Series F2MC-16FX 16-bit Proprietary Microcontroller
Document Number: 002-04586
Revision
ECN
Orig. of
Change
Submission
Date
**

AKIH
05/23/2007
Migrated to Cypress and assigned document number 002-04586.
No change to document contents or format.
*A
5245336
AKIH
05/13/2016
Updated to Cypress template
Document Number: 002-04586 Rev. *A
Description of Change
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MB96330 Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2007-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 002-04586 Rev. *A
Revised May 13, 2016
Page 122 of 122