Elpida MC-4516DA727XFB-A75 16 m-word by 72-bit synchronous dynamic ram module registered type Datasheet

DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4516DA727
16 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
EO
Description
The MC-4516DA727 is a 16,777,216 words by 72 bits synchronous dynamic RAM module on which 9 pieces of
128M SDRAM: µPD45128841 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
L
Features
• 16,777,216 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK.
Part number
/CAS latency
MC-4516DA727PFA-A75
MC-4516DA727XFA-A75
MC-4516DA727XFB-A75
Access time from CLK
u
od
Pr
MC-4516DA727EFA-A75
Clock frequency
(MAX.)
(MAX.)
CL = 3
133 MHz
5.4 ns
CL = 2
100 MHz
6.0 ns
CL = 3
133 MHz
5.4 ns
CL = 2
100 MHz
6.0 ns
CL = 3
133 MHz
5.4 ns
CL = 2
100 MHz
6.0 ns
CL = 3
133 MHz
5.4 ns
CL = 2
100 MHz
6.0 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length
(1, 2, 4, 8 and Full Page)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ±10 % of series resistor
ct
• Programmable wrap sequence (Sequential / Interleave)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0075N20 (Ver.2.0)
Date Published September 2001 (K)
Printed in Japan
This product became EOL in September, 2002.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-4516DA727
• Single 3.3 V ±0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Registered type
• Serial PD
EO
Ordering Information
Part number
MC-4516DA727EFA-A75
Clock frequency
Package
MHz (MAX.)
133 MHz
MC-4516DA727PFA-A75
168-pin Dual In-line Memory Module
9 pieces of µPD45128841G5 (Rev. E)
(Socket Type)
(10.16mm (400) TSOP (II))
Edge connector: Gold plated
9 pieces of µPD45128841G5 (Rev. P)
38.1 mm height
(10.16mm (400) TSOP (II))
9 pieces of µPD45128841G5 (Rev. P)
MC-4516DA727XFA-A75
L
MC-4516DA727XFB-A75
Mounted devices
(10.16mm (400) TSOP (II))
30.35 mm height
9 pieces of µPD45128841G5 (Rev. X)
(10.16mm (400) TSOP (II))
ct
u
od
Pr
2
Data Sheet E0075N20
MC-4516DA727
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
85
86
87
88
89
90
91
92
93
94
EO
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
CB4
CB5
VSS
NC
NC
Vcc
/CAS
DQMB4
DQMB5
NC
/RAS
VSS
A1
A3
A5
A7
A9
BA0 (A13)
A11
Vcc
VSS
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
1
2
3
4
5
6
7
8
9
10
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
CB0
CB1
VSS
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
VSS
A0
A2
A4
A6
A8
A10
BA1(A12)
Vcc
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
L
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
VSS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
: Address Inputs
[Row: A0 - A11, Column: A0 - A9]
u
od
Pr
CLK1
NC
VSS
CKE0
NC
DQMB6
DQMB7
NC
Vcc
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
VSS
CLK3
NC
SA0
SA1
SA2
Vcc
Vcc
CLK0
VSS
NC
/CS2
DQMB2
DQMB3
NC
Vcc
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
* WP
SDA
SCL
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Data Sheet E0075N20
BA0 (A13), BA1 (A12) : SDRAM Bank Select
DQ0-DQ63, CB0-CB7 : Data Inputs/Outputs
CLK0 - CLK3
: Clock Input
CKE0
: Clock Enable Input
WP*
: Write Protect
/CS0, /CS2
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQMB0 - DQMB7
: DQ Mask Enable
SA0 - SA2
: Address Input for EEPROM
SDA
: Serial Data I/O for PD
SCL
: Clock Input for PD
VCC
: Power Supply
VSS
: Ground
REGE
: Register / Buffer Enable
NC
ct
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
A0 - A11
: No Connection
* : 81 pin of MC-4516DA727XFB is NC pin.
3
MC-4516DA727
Block Diagram
/RCS0
RDQMB4
RDQMB0
30 pF
10 Ω
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 7 DQM
DQ 6
DQ 5
DQ 4
D0
DQ 3
DQ 2
DQ 1
DQ 0
/CS
DQ 7 DQM
/CS
RDQMB1
10 Ω
30 pF
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQ 0 DQM
DQ 1
DQ 2
DQ 3
D5
DQ 4
DQ 5
DQ 6
DQ 7
/CS
RDQMB5
10 Ω
15 pF
EO
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
15 pF
10 Ω
30 pF
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
/CS
DQ 0DQM
DQ 1
DQ 2
DQ 3
D6
DQ 4
DQ 5
DQ 6
DQ 7
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
D1
D0 - D8,
Register1, Register2, PLL
VCC
C
D0 - D8,
Register1, Register2, PLL
V SS
SERIAL PD
10 Ω
DQ 2 DQM
DQ 0
DQ 7
DQ 5
D2
DQ 3
DQ 1
DQ 6
DQ 4
/CS
DQ 7 DQM
/CS
SDA
SCL
A1
A0
WP
A2
47 kΩ
SA0 SA1 SA2
L
CB 0
CB 1
CB 2
CB 3
CB 4
CB 5
CB 6
CB 7
MC-4516DA727XFB
have no this circuit.
/RCS2
RDQMB2
10 Ω
30 pF
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
D3
10 Ω
/CS
DQ 0 DQM
DQ 1
DQ 2
DQ 3
D7
DQ 4
DQ 5
DQ 6
DQ 7
10 Ω
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
A0 - A9
12 pF
10 Ω
CLK0
CLK : D0,D1,D5
/RAS
/WE
Register1
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
A0 - A9 : D0 - D8
PLL
DQ 0 DQM
DQ 1
DQ 2
DQ 3
D8
DQ 4
DQ 5
DQ 6
DQ 7
/CS
A10, A11, BA0, BA1
/RRAS
/RAS : D0 - D8
CKE0
/RCAS
/CAS : D0 - D8
DQMB2, 3, 6, 7
/RWE
/WE : D0 - D8
CLK : D4,D7,D8
CLK : Register 1,
Register 2
RA10, RA11,
RBA0, RBA1
A10, A11,
BA0, BA1 : D0 - D8
RCKE0
CKE : D0 - D8
RDQMB2, 3, 6, 7
Register2
/CS2
/RCS2
15 pF
/RCS0
/CS0
VCC
/CS
RDQMB0, 1, 4, 5
DQMB0, 1, 4, 5
REGE
CLK : D2,D3,D6
10 Ω
30 pF
DQ 7 DQM
DQ 6
DQ 5
DQ 4
D4
DQ 3
DQ 2
DQ 1
DQ 0
RA0 - RA9
/CAS
/LE
15 pF
/LE
2. D0 - D8: µPD45128841 (4M words × 8 bits × 4 banks)
3. REGE ≤ VIL: Buffer mode
REGE ≥ VIH: Register mode
Data Sheet E0075N20
ct
Remarks 1. The value of all resistors of DQs is 10 Ω.
4
CLK1 - CLK3
RDQMB7
30 pF
10 kΩ
10 Ω
30 pF
u
od
Pr
RDQMB3
RDQMB6
MC-4516DA727
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VCC
–0.5 to +4.6
V
Voltage on input pin relative to GND
VT
–0.5 to +4.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
10
W
Operating ambient temperature
TA
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Voltage on power supply pin relative to GND
EO
Caution
Condition
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
L
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Supply voltage
Low level input voltage
Operating ambient temperature
VCC
MIN.
TYP.
MAX.
Unit
3.0
3.3
3.6
V
u
od
Pr
High level input voltage
Condition
VIH
2.0
VCC + 0.3
V
VIL
–0.3
+ 0.8
V
TA
0
70
°C
MAX.
Unit
pF
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Data input/output capacitance
Symbol
Test condition
MIN.
TYP.
CI1
A0 - A11, BA0 (A13), BA1 (A12), /RAS,
/CAS, /WE
4
10
CI2
CLK0
15
25
CI3
CKE0
4
10
CI4
/CS0, /CS2
4
10
CI5
DQMB0 - DQMB7
3
10
CI/O
DQ0 - DQ63, CB0 - CB7
5
13
pF
ct
Data Sheet E0075N20
5
MC-4516DA727
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Precharge standby current in
power down mode
Precharge standby current in
Symbol
ICC1
ICC2P
ICC2PS
ICC2N
non power down mode
EO
Active standby current in
power down mode
Active standby current in
MIN.
MAX.
Unit Notes
mA
Burst length = 1
/CAS latency = 2
-A75
1,300
tRC ≥ tRC (MIN.), IO = 0 mA
/CAS latency = 3
-A75
1,345
CKE ≤ VIL (MAX.), tCK = 15 ns
259
CKE ≤ VIL (MAX.), tCK = ∞
89
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
430
ICC2NS
ICC3P
ICC3PS
ICC3N
CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.
152
CKE ≤ VIL (MAX.), tCK = 15 ns
295
CKE ≤ VIL (MAX.), tCK = ∞
116
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
520
1
mA
mA
mA
mA
Input signals are changed one time during 30 ns.
ICC3NS
ICC4
CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.
tCK ≥ tCK (MIN.), IO = 0 mA
L
(Burst mode)
CBR (Auto) Refresh current
Grade
Input signals are changed one time during 30 ns.
non power down mode
Operating current
Test condition
ICC5
tRC ≥ tRC (MIN.)
260
/CAS latency = 2
-A75
1,480
/CAS latency = 3
-A75
1,795
/CAS latency = 2
-A75
2,470
/CAS latency = 3
-A75
2,560
Self refresh current
ICC6
CKE ≤ 0.2 V
Input leakage current
II (L)
VI = 0 to 3.6 V, All other pins not under test = 0 V
Output leakage current
IO (L)
High level output voltage
Low level output voltage
mA
2
mA
3
mA
–10
+10
µA
DOUT is disabled, VO = 0 to 3.6 V
–1.5
+1.5
µA
VOH
IO = –4.0 mA
2.4
VOL
IO = +4.0 mA
u
od
Pr
268
0.4
V
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
ct
6
Data Sheet E0075N20
MC-4516DA727
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Output timing measurement reference level
Value
Unit
2.4 / 0.4
V
1.4
V
1
ns
1.4
V
CLK
tCL
2.4 V
1.4 V
0.4 V
tSETUP tHOLD
2.4 V
1.4 V
L
EO
tCK
tCH
Input
0.4 V
tAC
tOH
ct
u
od
Pr
Output
Data Sheet E0075N20
7
MC-4516DA727
Synchronous Characteristics
Parameter
Symbol
-A75
Unit
MIN.
MAX.
tCK3
7.5
(133 MHz)
10
Note
Clock cycle time
/CAS latency = 3
/CAS latency = 2
tCK2
(100 MHz)
ns
Access time from CLK
/CAS latency = 3
tAC3
5.4
ns
1
/CAS latency = 2
tAC2
6.0
ns
1
50
133
MHz
45
55
Input clock frequency
EO
Input CLK duty cycle
ns
%
Data-out hold time
tOH
2.7
ns
Data-out low-impedance time
tLZ
0
ns
/CAS latency = 3
tHZ3
3.0
5.4
/CAS latency = 2
6.0
Data-out high-impedance time
1
ns
3.0
tDS
1.5
ns
Data-in hold time
tDH
0.8
ns
Address setup time
tAS
1.5
ns
Address hold time
tAH
0.8
ns
CKE setup time
tCKS
1.5
ns
CKE hold time
tCKH
0.8
ns
CKE setup time (Power down exit)
tCKSP
1.5
ns
Command (/CS0, /CS2, /RAS, /CAS, /WE,
tCMS
1.5
ns
L
tHZ2
Data-in setup time
ns
DQMB0 - DQMB7) setup time
u
od
Pr
tCMH
Command (/CS0, /CS2, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
Note 1. Output load
0.8
ns
Z = 50 Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
ct
8
Data Sheet E0075N20
MC-4516DA727
Asynchronous Characteristics
Parameter
Symbol
-A75
MIN.
Unit
MAX.
tRC
67.5
ns
REF to REF/ACT command period (refresh)
tRC1
67.5
ns
ACT to PRE command period
tRAS
45
PRE to ACT command period
tRP
20
ns
Delay time ACT to READ/WRITE command
tRCD
20
ns
ACT(one) to ACT(another) command period
tRRD
15
ns
Data-in to PRE command period
tDPL
8
ns
ns
EO
ACT to REF/ACT command period (operation)
120,000
ns
Data-in to ACT(REF) command
/CAS latency = 3
tDAL3
1CLK+22.5
period (Auto precharge)
/CAS latency = 2
tDAL2
1CLK+20
ns
tRSC
2
CLK
tT
0.5
Mode register set cycle time
Transition time
Refresh time (4,096 refresh cycles)
tREF
Note
30
ns
64
ms
1
Note1. This device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125 MHz operation.
L
ct
u
od
Pr
Data Sheet E0075N20
9
MC-4516DA727
Serial PD
(1/2)
Byte No.
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
0
Defines the number of bytes written into
serial PD memory
80H
1
0
0
0
0
0
0
0
128 bytes
1
Total number of bytes of serial PD memory
08H
0
0
0
0
1
0
0
0
256 bytes
2
Fundamental memory type
04H
0
0
0
0
0
1
0
0
SDRAM
3
Number of rows
0CH
0
0
0
0
1
1
0
0
12 rows
4
Number of columns
0AH
0
0
0
0
1
0
1
0
10 columns
5
Number of banks
01H
0
0
0
0
0
0
0
1
1 bank
EO
6
Data width
48H
0
1
0
0
1
0
0
0
72 bits
7
Data width (continued)
00H
0
0
0
0
0
0
0
0
0
8
Voltage interface
01H
0
0
0
0
0
0
0
1
LVTTL
CL = 3 Cycle time
-A75
75H
0
1
1
1
0
1
0
1
7.5 ns
CL = 3 Access time
-A75
54H
0
1
0
1
0
1
0
0
5.4 ns
11
DIMM configuration type
02H
0
0
0
0
0
0
1
0
ECC
12
Refresh rate/type
80H
1
0
0
0
0
0
0
0
Normal
13
SDRAM width
08H
0
0
0
0
1
0
0
0
x8
14
Error checking SDRAM width
08H
0
0
0
0
1
0
0
0
x8
15
Minimum clock delay
01H
0
0
0
0
0
0
0
1
1 clock
16
Burst length supported
8FH
1
0
0
0
1
1
1
1
1, 2, 4, 8, F
17
Number of banks on each SDRAM
04H
0
0
0
0
0
1
0
0
4 banks
18
/CAS latency supported
06H
0
0
0
0
0
1
1
0
2, 3
19
/CS latency supported
01H
0
0
0
0
0
0
0
1
0
20
/WE latency supported
01H
0
0
0
0
0
0
0
1
0
21
SDRAM module attributes
1FH
0
0
0
1
1
1
1
1
Registered
L
9
10
u
od
Pr
22
SDRAM device attributes : General
0EH
0
0
0
0
1
1
1
0
23
CL = 2 Cycle time
-A75
0AH
0
0
0
0
1
0
1
0
10 ns
24
CL = 2 Access time
-A75
60H
0
1
1
0
0
0
0
0
6 ns
25-26
27
tRP(MIN.)
28
tRRD(MIN.)
29
tRCD(MIN.)
30
tRAS(MIN.)
31
Module bank density
00H
0
0
0
0
0
0
0
0
-A75
14H
0
0
0
1
0
1
0
0
20 ns
-A75
0FH
0
0
0
0
1
1
1
1
15 ns
-A75
14H
0
0
0
1
0
1
0
0
20 ns
-A75
2DH
0
0
1
0
1
1
0
1
45 ns
20H
0
0
1
0
0
0
0
0
128M bytes
ct
10
Data Sheet E0075N20
MC-4516DA727
(2/2)
Byte No.
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
32
Command and address signal input
setup time
15H
0
0
0
1
0
1
0
1
1.5 ns
33
Command and address signal input hold
time
08H
0
0
0
0
1
0
0
0
0.8 ns
34
Data signal input setup time
15H
0
0
0
1
0
1
0
1
1.5 ns
35
Data signal input hold time
08H
0
0
0
0
1
0
0
0
0.8 ns
00H
0
0
0
0
0
0
0
0
02H
0
0
0
0
0
0
1
0
3AH
0
0
1
1
1
0
1
0
64H
0
1
1
0
0
1
0
0
85H
1
0
0
0
0
1
0
1
36-61
SPD revision
63
Checksum for bytes 0 - 62
EO
62
64-71
72
73-90
91
-A75
JEDEC 2
Manufacture’s JEDEC ID code
Manufacturing location
Manufacture’s P/N
Revision Code
Manufacturing date
95-98
Assembly serial number
99-125
Mfg specific
L
93-94
126
Intel specification frequency
127
Intel specification /CAS
-A75
100 MHz
latency support
u
od
Pr
Timing Chart
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).
ct
Data Sheet E0075N20
11
MC-4516DA727
Package Drawing
MC-4516DA727EFA, MC-4516DA727PFA, MC-4516DA727XFA
Front side
Unit: mm
(DATUM -A-)
4.00 max
3.0 min
4.00 min
3.00
EO
Component area
(Front)
1
8.89
11.43
24.495
84
B
C
A
1.27 ± 0.1
54.61
36.83
42.18
133.35 ± 0.13
L
Back side
85
u
od
Pr
38.1 ± 0.13
17.78
168
4.0 ± 0.10
2 – φ 3.00
Component area
(Back)
R2.0
(DATUM -A-)
1.00 ± 0.05
Detail B
R FULL
Detail C
(DATUM -A-)
1.00
2.0
R FULL
6.35
3.125
6.35
3.125
1.27(T.P.)
0.20 ± 0.15
2.54 ± 0.10
Detail A
4.175
2.0
Note: Tolerance on all dimensions ± 0.15 unless otherwise specified.
ct
12
Data Sheet E0075N20
MC-4516DA727
MC-4516DA727XFB
Unit: mm
Front side
(DATUM -A-)
4.00 max
Component area
(Front)
3.00
EO
4.00 min
3.0 min
1
8.89
11.43
24.495
84
B
C
A
1.27 ± 0.1
54.61
36.83
42.18
133.35 ± 0.13
L
Back side
85
R2.0
u
od
Pr
Component area
(Back)
30.35 ± 0.13
17.78
168
4.0 ± 0.10
2 – φ 3.00
(DATUM -A-)
1.00 ± 0.05
Detail B
R FULL
Detail C
(DATUM -A-)
1.00
2.0
R FULL
6.35
3.125
6.35
3.125
1.27(T.P.)
0.20 ± 0.15
2.54 ± 0.10
Detail A
4.175
2.0
Note: Tolerance on all dimensions ± 0.15 unless otherwise specified.
ct
Data Sheet E0075N20
13
MC-4516DA727
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0107
EO
1
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
2
L
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
3
u
od
Pr
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
ct
14
Data Sheet E0075N20
MC-4516DA727
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
EO
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
L
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
u
od
Pr
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
ct
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