Elpida MC-4532CD646PF-A80 32m-word by 64-bit synchronous dynamic ram module unbuffered type Datasheet

DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532CD646
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
EO
Description
The MC-4532CD646EF, MC-4532CD646PF and MC-4532CD646XF are 33,554,432 words by 64 bits synchronous
dynamic RAM module on which 16 pieces of 128M SDRAM: µPD45128841 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
L
Features
• 33,554,432 words by 64 bits organization
• Clock frequency and access time from CLK
Part number
MC-4532CD646EF-A10
MC-4532CD646PF-A80
Clock frequency
Access time from CLK
(MAX.)
(MAX.)
Pr
MC-4532CD646EF-A80
/CAS latency
CL = 3
125 MHz
6 ns
CL = 2
100 MHz
6 ns
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
CL = 3
125 MHz
6 ns
CL = 2
100 MHz
CL = 3
MC-4532CD646XF-A80
CL = 3
MC-4532CD646XF-A10
CL = 3
CL = 2
CL = 2
CL = 2
6 ns
od
MC-4532CD646PF-A10
100 MHz
6 ns
77 MHz
7 ns
125 MHz
6 ns
100 MHz
6 ns
100 MHz
6 ns
77 MHz
7 ns
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• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and full page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ±10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0055N10 (1st edition)
(Previous No. M13681EJ5V0DS00)
Date Published January 2001 CP (K)
Printed in Japan
This product became EOL in March, 2004.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-4532CD646
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
Ordering Information
EO
Part number
Clock frequency
Package
Mounted devices
MHz (MAX.)
MC-4532CD646EF-A80
125 MHz
168-pin Dual In-line Memory Module
16 pieces of µPD45128841G5 (Rev. E)
MC-4532CD646EF-A10
100 MHz
(Socket Type)
(10.16 mm (400) TSOP (II))
MC-4532CD646PF-A80
125 MHz
Edge connector : Gold plated
16 pieces of µPD45128841G5 (Rev. P)
MC-4532CD646PF-A10
100 MHz
34.93 mm height
(10.16 mm (400) TSOP (II))
MC-4532CD646XF-A80
125 MHz
16 pieces of µPD45128841G5 (Rev. X)
MC-4532CD646XF-A10
100 MHz
(10.16 mm (400) TSOP (II))
L
od
Pr
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2
Data Sheet E0055N10
MC-4532CD646
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
1
2
3
4
5
6
7
8
9
10
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ40
DQ8
VSS
VSS
DQ41
DQ9
DQ42
DQ10
DQ43
DQ11
DQ44
DQ12
DQ45
DQ13
Vcc
Vcc
DQ46
DQ14
DQ47
DQ15
NC
NC
NC
NC
VSS
VSS
NC
NC
NC
NC
Vcc
Vcc
/WE
/CAS
DQMB0
DQMB4
DQMB1
DQMB5
/CS0
/CS1
NC
/RAS
VSS
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
BA0 (A13)
BA1 (A12)
A11
Vcc
Vcc
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
VSS
CKE0
/CS3
DQMB6
DQMB7
NC
Vcc
NC
NC
NC
NC
VSS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
VSS
CLK3
NC
SA0
SA1
SA2
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
L
A0 - A11
Data Sheet E0055N10
: Address Inputs
[Row: A0 - A11, Column: A0 - A9]
od
Pr
Vcc
CLK0
VSS
NC
/CS2
DQMB2
DQMB3
NC
Vcc
NC
NC
NC
NC
VSS
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
WP
SDA
SCL
Vcc
BA0 (A13), BA1 (A12)
: SDRAM Bank Select
DQ0 - DQ63
: Data Inputs/Outputs
CLK0 - CLK3
: Clock Input
CKE0, CKE1
: Clock Enable Input
/CS0 - /CS3
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
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VSS
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
EO
85
86
87
88
89
90
91
92
93
94
DQMB0 - DQMB7 : DQ Mask Enable
SA0 - SA2
: Address Input for EEPROM
SDA
: Serial Data I/O for PD
SCL
: Clock Input for PD
VCC
: Power Supply
VSS
: Ground
WP
: Write Protect
NC
: No Connection
3
MC-4532CD646
Block Diagram
/WE
/CS0
/CS1
/CS2
DQMB0
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
D0
DQ 3
DQ 2
DQ 1
DQ 0
/WE
DQ 0 DQM /CS
DQ 1
DQ 2
DQ 3
D8
DQ 4
DQ 5
DQ 6
DQ 7
/WE
DQ 7 DQM
/WE
DQ 0 DQM
/CS
/WE
EO
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
/CS
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D1
D9
/WE
/CS
/WE
DQ 3 DQM /CS
DQ 0
DQ 1
DQ 2
D12
DQ 4
DQ 5
DQ 6
DQ 7
/WE
DQ 0 DQM /CS
DQ 1
DQ 2
DQ 3
D10
DQ 4
DQ 5
DQ 6
DQ 7
/WE
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQ 4 DQM /CS
DQ 7
DQ 6
DQ 5
D3
DQ 3
DQ 2
DQ 1
DQ 0
/WE
DQ 3 DQM /CS
DQ 0
DQ 1
DQ 2
D11
DQ 4
DQ 5
DQ 6
DQ 7
/WE
DQ 2 DQM
/WE
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQ 7DQM /CS
DQ 6
DQ 5
DQ 4
D6
DQ 3
DQ 2
DQ 1
DQ 0
/WE
DQ 0 DQM /CS
DQ 1
DQ 2
DQ 3
D14
DQ 4
DQ 5
DQ 6
DQ 7
/WE
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
D7
DQ 3
DQ 2
DQ 1
DQ 0
/WE
DQ 0 DQM /CS
DQ 1
DQ 2
DQ 3
D15
DQ 4
DQ 5
DQ 6
DQ 7
/WE
DQMB7
DQ 5 DQM
D5
DQ 0
DQ 1
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
SDA
A1
A2
D13
CLK0
SCL
A0
/CS
WP
47 kΩ
CLK: D8, D9, D12, D13 CLK3
A0 - A11
A0 - A11: D0 - D15
A13, A12: D0 - D15
/RAS
10 kΩ
/RAS: D0 - D15
CKE1
/CAS
/CAS: D0 - D15
CKE0
CKE: D0 - D7
D0 - D15
Remarks 1. The value of all resistors is 10 Ω except CKE1 and W P.
2. D0 - D15: µPD45128841 (4M words × 8 bits × 4 banks)
4
Data Sheet E0055N10
CLK: D10, D11, D14, D15
3.3 pF
D0 - D15
C
CLK: D2, D3, D6, D7
3.3 pF
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CLK1
3.3 pF
BA0, BA1
CLK2
CLK: D0, D1, D4, D5
3.3 pF
SA0 SA1 SA2
VCC
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
od
DQ 7
DQ 6
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
SERIAL PD
V SS
/WE
Pr
DQ 4 DQM /CS
DQ 7
DQ 6
DQ 5
D4
DQ 3
DQ 2
DQ 1
DQ 0
DQMB5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
D2
DQ 3
DQ 2
DQ 1
DQ 0
DQMB6
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DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQMB3
DQMB1
DQMB4
/CS3
DQMB2
CKE: D8-D15
MC-4532CD646
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Symbol
Rating
Unit
Voltage on power supply pin relative to GND
VCC
–0.5 to +4.6
V
Voltage on input pin relative to GND
VT
–0.5 to +4.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
16
W
Operating ambient temperature
TA
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
EO
Parameter
Caution
Condition
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
L
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Supply voltage
Symbol
Condition
Pr
Parameter
VCC
High level input voltage
Low level input voltage
Operating ambient temperature
Unit
3.0
3.3
3.6
V
2.0
VCC + 0.3
V
VIL
−0.3
+0.8
V
TA
0
70
°C
MAX.
Unit
pF
Symbol
Test condition
MIN.
TYP.
CI1
A0 - A11, BA0 (A13), BA1 (A12),
/RAS, /CAS, /WE
56
94
CI2
CLK0 - CLK3
20
40
CI3
CKE0, CKE1
28
52
CI4
/CS0 - /CS3
CI5
DQMB0 - DQMB7
CI/O
DQ0 - DQ63
Data Sheet E0055N10
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Data input/output capacitance
MAX.
od
Input capacitance
TYP.
VIH
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
MIN.
15
29
5
17
7
19
pF
5
MC-4532CD646
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Operating current
Symbol
ICC1
Grade MIN. MAX.
Test condition
/CAS latency = 2
Burst length = 1
tRC ≥ tRC(MIN.), IO =
0 mA
/CAS latency = 3
Precharge standby current in
EO
power down mode
Precharge standby current in
non power down mode
Active standby current in
power down mode
Active standby current in
ICC2P
-A80
1,040
-A10
1,040
-A80
1,040
-A10
1,040
CKE ≤ VIL(MAX.), tCK = 15 ns
16
ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
ICC2N
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
320
CKE ≤ VIL(MAX.), tCK = 15 ns
80
400
ICC4
(Burst mode)
mA
mA
tCK ≥ tCK(MIN.)
320
/CAS latency = 2
-A80
-A10
1,000
/CAS latency = 3
-A80
1,400
-A10
1,240
/CAS latency = 2
-A80
2,080
-A10
2,080
/CAS latency = 3
-A80
2,080
-A10
2,080
IO = 0 mA
Pr
CBR (Auto) refresh current
mA
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
Operating current
mA
64
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
L
non power down mode
1
96
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
ICC3N
mA
16
ICC2NS CKE ≥ VIH(MIN.), tCK = ∞
Input signals are stable.
ICC3P
Unit Notes
ICC5
tRC ≥ tRC(MIN.)
ICC6
CKE ≤ 0.2 V
Input leakage current
II(L)
VI = 0 to 3.6 V, All other pins not under test = 0 V
Input leakage current (CKE1)
od
Self refresh current
1,200
– 16
mA
2
mA
3
32
mA
+ 16
µA
– 500 +500
Output leakage current
IO(L)
DOUT is disabled, VO = 0 to 3.6 V
–3
High level output voltage
VOH
IO = – 4.0 mA
2.4
Low level output voltage
VOL
IO = + 4.0 mA
+3
µA
V
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
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addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
6
Data Sheet E0055N10
MC-4532CD646
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Input timing measurement reference level
Value
Unit
2.4 / 0.4
V
1.4
V
1
ns
1.4
V
Transition time (Input rise and fall time)
tCK
tCH
CLK
tCL
2.4 V
1.4 V
0.4 V
tSETUP tHOLD
2.4 V
1.4 V
L
EO
Output timing measurement reference level
Input
0.4 V
tAC
tOH
Pr
Output
od
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Data Sheet E0055N10
7
MC-4532CD646
Synchronous Characteristics
Parameter
Symbol
Clock cycle time
Access time from CLK
-A80
Unit
-A 10
MIN.
MAX.
MIN.
MAX.
/CAS latency = 3
tCK3
8
(125 MHz)
10
(100 MHz)
ns
/CAS latency = 2
tCK2
10
(100 MHz)
13
(77 MHz)
ns
/CAS latency = 3
tAC3
6
ns
1
/CAS latency = 2
tAC2
7
ns
1
6
6
tCH
3
3
ns
CLK low level width
tCL
3
3
ns
Data-out hold time
tOH
3
3
ns
EO
CLK high level width
Data-out low-impedance time
0
tHZ3
3
6
3
6
ns
/CAS latency = 2
tHZ2
3
6
3
7
ns
Data-in setup time
tDS
2
Data-in hold time
tDH
0
Address setup time
tAS
Address hold time
ns
1
1
ns
2
2
ns
tAH
1
1
ns
CKE setup time
tCKS
2
2
ns
CKE hold time
tCKH
1
1
ns
CKE setup time (Power down exit)
tCKSP
2
2
ns
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
tCMS
2
2
ns
tCMH
1
1
ns
L
2
Pr
DQMB0 - DQMB7) setup time
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
Note 1. Output load
1
ns
tLZ
/CAS latency = 3
Data-out high-impedance time
Note
od
Z = 50 Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
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8
Data Sheet E0055N10
MC-4532CD646
Asynchronous Characteristics
Parameter
Symbol
-A80
MIN.
-A10
MAX.
MIN.
Unit
MAX.
ACT to REF/ACT command period (Operation)
tRC
70
70
ns
REF to REF/ACT command period (Refresh)
tRC1
70
78
ns
ACT to PRE command period
tRAS
48
120,000
50
120,000
ns
tRP
20
20
ns
Delay time ACT to READ/WRITE command
tRCD
20
20
ns
ACT(one) to ACT(another) command period
tRRD
16
20
ns
Data-in to PRE command period
tDPL
8
10
ns
Data-in to ACT(REF) command period /CAS latency = 3
tDAL3
1CLK+20
1CLK+20
ns
(Auto precharge)
tDAL2
1CLK+20
1CLK+20
ns
tRSC
2
2
CLK
tT
0.5
EO
PRE to ACT command period
/CAS latency = 2
Mode register set cycle time
Transition time
Refresh time (4,096 refresh cycles)
tREF
30
1
64
Note
30
ns
64
ms
L
od
Pr
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Data Sheet E0055N10
9
MC-4532CD646
Serial PD
(1/2)
Byte No.
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Defines the number of bytes written into
serial PD memory
80H
1
0
0
0
0
0
0
0
1
Total number of bytes of serial PD memory
08H
0
0
0
0
1
0
0
0
256 bytes
2
Fundamental memory type
04H
0
0
0
0
0
1
0
0
SDRAM
3
Number of rows
0CH
0
0
0
0
1
1
0
0
12 rows
4
Number of columns
0AH
0
0
0
0
1
0
1
0
10 columns
EO
Number of banks
02H
0
0
0
0
0
0
1
0
2 banks
6
Data width
40H
0
1
0
0
0
0
0
0
64 bits
7
Data width (continued)
00H
0
0
0
0
0
0
0
0
0
8
Voltage interface
01H
0
0
0
0
0
0
0
1
LVTTL
9
CL = 3 Cycle time
-A80
80H
1
0
0
0
0
0
0
0
8 ns
-A10
A0H
1
0
1
0
0
0
0
0
10 ns
10
CL = 3 Access time
-A80
60H
0
1
1
0
0
0
0
0
6 ns
-A10
60H
0
1
1
0
0
0
0
0
6 ns
11
DIMM configuration type
00H
0
0
0
0
0
0
0
0
None
Refresh rate/type
80H
1
0
0
0
0
0
0
0
Normal
13
SDRAM width
08H
0
0
0
0
1
0
0
0
×8
14
Error checking SDRAM width
00H
0
0
0
0
0
0
0
0
None
15
Minimum clock delay
01H
0
0
0
0
0
0
0
1
1 clock
16
Burst length supported
8FH
1
0
0
0
1
1
1
1
1, 2, 4, 8, F
17
Number of banks on each SDRAM
04H
0
0
0
0
0
1
0
0
4 banks
18
/CAS latency supported
06H
0
0
0
0
0
1
1
0
2, 3
19
/CS latency supported
01H
0
0
0
0
0
0
0
1
0
20
/WE latency supported
01H
0
0
0
0
0
0
0
1
0
21
SDRAM module attributes
00H
0
0
0
0
0
0
0
0
22
SDRAM device attributes : General
0EH
0
0
0
0
1
1
1
0
23
CL = 2 Cycle time
-A80
A0H
1
0
1
0
0
0
0
0
10 ns
-A10
D0H
1
1
0
1
0
0
0
0
13 ns
-A80
60H
0
1
1
0
0
0
0
0
6 ns
-A10
70H
0
1
1
1
0
0
0
0
7 ns
00H
0
0
0
0
0
0
0
0
14H
0
0
0
1
0
1
0
0
CL = 2 Access time
25-26
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12
Pr
L
5
24
27
tRP(MIN.)
-A80
-A10
14H
0
0
0
1
0
1
0
0
20 ns
28
tRRD(MIN.)
-A80
10H
0
0
0
1
0
0
0
0
16 ns
-A10
14H
0
0
0
1
0
1
0
0
20 ns
29
tRCD(MIN.)
-A80
14H
0
0
0
1
0
1
0
0
20 ns
-A10
14H
0
0
0
1
0
1
0
0
20 ns
30
tRAS(MIN.)
-A80
30H
0
0
1
1
0
0
0
0
48 ns
-A10
32H
0
0
1
1
0
0
1
0
50 ns
31
Module bank density
20H
0
0
1
0
0
0
0
0
128M bytes
Data Sheet E0055N10
20 ns
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Notes
128 bytes
MC-4532CD646
(2/2)
Byte No.
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
32
Command and address signal input setup
time
20H
0
0
1
0
0
0
0
0
2 ns
Notes
33
Command and address signal input
10H
0
0
0
1
0
0
0
0
1 ns
hold time
Data signal input setup time
20H
0
0
1
0
0
0
0
0
2 ns
35
Data signal input hold time
10H
0
0
0
1
0
0
0
0
1 ns
00H
0
0
0
0
0
0
0
0
EO
34
36-61
SPD revision
63
Checksum for bytes 0 - 62
64-71
72
12H
0
0
0
1
0
0
1
0
-A80
F1H
1
1
1
1
0
0
0
1
-A10
57H
0
1
0
1
0
1
1
1
64H
0
1
1
0
0
1
0
0
-A80
FFH
1
1
1
1
1
1
1
1
Pr
62
1
1
1
0
1
1.2
Manufacture’s JEDEC ID code
Manufacturing location
Manufacture’s P/N
91-92
Revision code
93-94
Manufacturing date
95-98
Assembly serial number
L
73-90
99-125 Mfg specific
126
Intel specification frequency
127
Intel specification /CAS
latency support
Timing Chart
-A10
FDH
1
1
1
100 MHz
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).
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Data Sheet E0055N10
11
MC-4532CD646
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
Z1
Z2
Y1
Y2
R2
N
F2
EO
F1
Q
R1
L
A
B
H
J
I
S
(OPTIONAL HOLES)
K
C
B
G
U1
U2
T
E
D
L
A1 (AREA A)
M2 (AREA A)
Pr
M1 (AREA B)
M
detail of A part
V
D2
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W
detail of B part
P
X
D1
MILLIMETERS
133.35
133.35±0.13
11.43
36.83
6.35
2.0
3.125
54.61
2.44
3.18
6.35
1.27 (T.P.)
8.89
24.495
42.18
17.78
34.93±0.13
15.15
19.78
4.0 MAX.
1.0
R2.0
4.0±0.10
9.53
φ 3.0
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ITEM
A
A1
B
C
D
D1
D2
E
F1
F2
G
H
I
J
K
L
M
M1
M2
N
P
Q
R1
R2
S
T
U1
U2
V
W
X
Y1
1.27±0.1
4.0 MIN.
4.0 MIN.
0.2±0.15
1.0±0.05
2.54±0.10
3.0 MIN.
Y2
Z1
Z2
2.26
3.0 MIN.
2.26
M168S-50A78
12
Data Sheet E0055N10
MC-4532CD646
[ MEMO ]
L
EO
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Data Sheet E0055N10
13
MC-4532CD646
[ MEMO ]
L
EO
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14
Data Sheet E0055N10
MC-4532CD646
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
EO
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
L
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
Pr
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
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Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
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Data Sheet E0055N10
15
MC-4532CD646
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
EO
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
L
• The information in this document is current as of September, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or
data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all
products and/or types are available in every country. Please check with an Elpida Memory, Inc. for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document.
• Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of Elpida semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of Elpida or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• Elpida semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in
Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in
applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine
Elpida's willingness to support a given application.
(Note)
(1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned
subsidiaries.
(2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or
for Elpida (as defined above).
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