Elpida MC-458CA721XSA 8m-word by 72-bit synchronous dynamic ram module (so dimm) Datasheet

DATA SHEET
MOS INTEGRATED CIRCUIT
MC-458CA721ESA,458CA721PSA,458CA721XSA
8M-WORD BY 72-BIT
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
EO
Description
The MC-458CA721ESA, MC-458CA721PSA and 458CA721XSA are 8,388,608 words by 72 bits synchronous
dynamic RAM module (Small Outline DIMM) on which 5 pieces of 128M SDRAM: µPD45128163 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
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Features
• 8,388,608 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency (MAX.)
Access time from CLK (MAX.)
CL = 3
125 MHz
6 ns
MC-458CA721ESA-A80
MC-458CA721PSA-A80
MC-458CA721PSA-A10
MC-458CA721XSA-A80
MC-458CA721XSA-A10
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MC-458CA721ESA-A10
CL = 2
100 MHz
6 ns
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
CL = 3
125 MHz
6 ns
CL = 2
100 MHz
6 ns
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
CL = 3
125 MHz
6 ns
CL = 2
100 MHz
6 ns
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0, BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single 3.3 V ± 0.3 V power supply
ct
• Programmable wrap sequence (Sequential / Interleave)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0067N10 (1st edition)
(Previous No. M14494EJ3V0DS00)
Date Published January 2001 CP (K)
Printed in Japan
This product became EOL in September, 2002.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)
• Unbuffered type
• Serial PD
Ordering Information
EO
Part number
Clock frequency
Package
Mounted devices
MHz (MAX.)
MC-458CA721ESA-A80
125 MHz
144-pin Small Outline DIMM
5 piece of µPD45128163G5 (Rev. E)
MC-458CA721ESA-A10
100 MHz
(Socket Type)
(10.16mm (400) TSOP (II))
MC-458CA721PSA-A80
125 MHz
Edge connector: Gold plated
5 piece of µPD45128163G5 (Rev. P)
MC-458CA721PSA-A10
100 MHz
31.75 mm height
(10.16mm (400) TSOP (II))
MC-458CA721XSA-A80
125 MHz
5 piece of µPD45128163G5 (Rev. X)
MC-458CA721XSA-A10
100 MHz
(10.16mm (400) TSOP (II))
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2
Data Sheet E0067N10
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Pin Configuration
144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
Vss
DQ 32
DQ 33
DQ 34
DQ 35
Vcc
DQ 36
DQ 37
DQ 38
DQ 39
Vss
DQMB4
DQMB5
Vcc
A3
A4
A5
Vss
DQ 40
DQ 41
DQ 42
DQ 43
Vcc
DQ 44
DQ 45
DQ 46
DQ 47
Vss
CB 4
CB 5
Vss
DQ 0
DQ 1
DQ 2
DQ 3
VCC
DQ 4
DQ 5
DQ 6
DQ 7
Vss
DQMB0
DQMB1
VCC
A0
A1
A2
Vss
DQ 8
DQ 9
DQ 10
DQ 11
VCC
DQ 12
DQ 13
DQ 14
DQ 15
Vss
CB 0
CB 1
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EO
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
CLK0
CKE0
Vcc
Vcc
/RAS
/CAS
/WE
NC
/CS0
NC
NC
NC
NC
CLK1
Vss
Vss
CB 2
CB 6
CB 3
CB 7
VCC
Vcc
DQ 16
DQ 48
DQ 17
DQ 49
DQ 18
DQ 50
DQ 19
DQ 51
Vss
Vss
DQ 20
DQ 52
DQ 21
DQ 53
DQ 22
DQ 54
DQ 23
DQ 55
Vcc
Vcc
A6
A7
A8
BA0 (A13)
Vss
Vss
A9
BA1 (A12)
A10
A11
Vcc
Vcc
DQMB2
DQMB6
DQMB3
DQMB7
Vss
Vss
DQ 24
DQ 56
DQ 25
DQ 57
DQ 26
DQ 58
DQ 27
DQ 59
VCC
Vcc
DQ 28
DQ 60
DQ 29
DQ 61
DQ 30
DQ 62
DQ 31
DQ 63
Vss
Vss
SDA
SCL
VCC
Vcc
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
/xxx indicates active low signal.
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Data Sheet E0067N10
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A8]
BA0(A13), BA1(A12) : SDRAM Bank Select
DQ0 - DQ63
: Data Inputs/Outputs
CB0 - CB7
: Data Inputs/Outputs
CLK0, CLK1
: Clock Input
CKE0
: Clock Enable Input
/CS0
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQMB0 - DQMB7
: DQ Mask Enable
SDA
: Serial Data I/O for PD
SCL
: Clock Input for PD
VCC
: Power Supply
VSS
: Ground
NC
: No Connection
ct
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
3
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Block Diagram
/WE
/CS0
LDQM
/CS
/WE
/CS
LDQM
DQ 0
DQMB4
DQ 32
DQ 0
DQ 1
DQ 1
DQ 33
DQ 1
DQ 2
DQ 2
DQ 34
DQ 2
DQ 3
DQ 3
DQ 35
DQ 3
DQ 4
DQ 4
DQ 36
DQ 4
DQ 5
DQ 5
DQ 37
DQ 5
DQ 6
DQ 6
DQ 38
DQ 6
EO
DQMB0
DQ 0
DQ 7
DQ 39
DQ 7
UDQM
DQ 7
DQMB1
D0
UDQM
DQ 8
DQ 8
DQMB5
DQ 40
DQ 9
DQ 9
DQ 41
DQ 9
DQ 10
DQ 10
DQ 42
DQ 10
DQ 11
DQ 11
DQ 43
DQ 11
DQ 12
DQ 12
DQ 44
DQ 12
DQ 13
DQ 13
DQ 45
DQ 13
DQ 14
DQ 14
DQ 46
DQ 14
DQ 15
DQ 15
DQ 47
DQ 15
LDQM
/CS
/WE
DQ 0
CB 1
DQ 1
DQ 49
DQ 1
CB 2
DQ 2
DQ 50
DQ 2
CB 3
DQ 3
DQ 51
DQ 3
CB 4
DQ 4
DQ 52
DQ 4
CB 5
DQ 5
DQ 53
DQ 5
CB 6
DQ 6
DQ 54
DQ 6
CB 7
DQ 7
DQ 55
DQ 7
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DQMB6
DQ 48
/WE
D4
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UDQM
UDQM
DQ 8
DQMB7
DQ 56
DQ 8
DQ 9
DQ 57
DQ 9
DQ 10
DQ 58
DQ 10
DQ 11
DQ 59
DQ 11
DQ 12
DQ 60
DQ 12
DQ 13
DQ 61
DQ 13
DQ 14
DQ 62
DQ 14
DQ 15
DQ 63
DQ 15
LDQM
DQMB2
DQ 16
DQ 0
DQ 17
DQ 1
DQ 18
DQ 2
DQ 19
DQ 3
DQ 20
DQ 4
DQ 21
DQ 5
DQ 22
DQ 6
DQ 23
DQ 7
/CS
/WE
SERIAL PD
VCC
SCL
SDA
A0
A1
A2
D0 - D4
C
VSS
D0 - D4
D2
UDQM
DQ 8
DQ 25
DQ 9
DQ 26
DQ 10
BA0
A13 : D0 - D4
DQ 27
DQ 11
BA1
A12 : D0 - D4
DQ 28
DQ 12
/RAS
/RAS : D0 - D4
DQ 29
DQ 13
DQ 30
DQ 14
/CAS
/CAS : D0 - D4
DQ 31
DQ 15
CKE0
CKE : D0 - D4
A0 - A11
2. The value of all resistors is 10 Ω.
Data Sheet E0067N10
A0 - A11 : D0 - D4
CLK : D0 - D4
CLK0
10 Ω
CLK1
10 pF
ct
DQ 24
Remarks 1. D0 – D4: µPD45128163 (2M words x 16 bits x 4 banks)
4
/CS
LDQM
DQ 0
DQMB3
D3
DQ 8
CB 0
D1
/WE
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VCC
–0.5 to +4.6
V
Voltage on input pin relative to GND
VT
–0.5 to +4.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
5
W
Operating ambient temperature
TA
0 to 70
°C
Storage temperature
Tstg
–55 to +125
°C
Voltage on power supply pin relative to GND
EO
Caution
Condition
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
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conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
High level input voltage
Low level input voltage
Operating ambient temperature
Condition
MIN.
TYP.
MAX.
Unit
VCC
3.0
3.3
3.6
V
VIH
2.0
VCC + 0.3
V
VIL
–0.3
+0.8
V
TA
0
70
°C
MAX.
Unit
pF
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Supply voltage
Symbol
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Data input/output capacitance
Symbol
Test condition
MIN.
TYP.
CI1
A0 - A11, BA0(A13), BA1(A12),
/RAS, /CAS, /WE
17
34
CI2
CLK0
23
37
CI3
CKE0
18
30
CI4
/CS0
18
30
CI5
DQMB0 - DQMB7
5
16.5
CI/O
DQ0 - DQ63, CB0 - CB7
5
13
pF
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Data Sheet E0067N10
5
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
ICC1
Test condition
Burst length = 1, tRC ≥ tRC(MIN.)
MIN.
/CAS latency = 2
-A80
MAX.
Unit Notes
550
mA
1
-A10
/CAS latency = 3
-A80
550
-A10
Precharge standby current in
power down mode
EO
Precharge standby current in
ICC2P
ICC2PS
ICC2N
power down mode
Active standby current in
5
CKE ≤ VIL(MAX.), tCK = ∞
5
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
ICC2NS
ICC3P
ICC3PS
ICC3N
CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
40
CKE ≤ VIL(MAX.), tCK = 15 ns
25
CKE ≤ VIL(MAX.), tCK = ∞
20
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
150
CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
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ICC3NS
ICC4
tCK ≥ tCK(MIN.), IO = 0 mA
/CAS latency = 2
(Burst mode)
mA
mA
/CAS latency = 3
100
-A80
725
-A10
550
-A80
875
-A10
700
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CBR (Auto) refresh current
mA
Input signals are changed one time during 30 ns.
non power down mode
Operating current
100
mA
Input signals are changed one time during 30 ns.
non power down mode
Active standby current in
CKE ≤ VIL(MAX.), tCK = 15 ns
ICC5
tRC ≥ tRC(MIN.)
/CAS latency = 2
-A80
1,150
mA
2
mA
3
-A10
/CAS latency = 3
-A80
1,150
-A10
Self refresh current
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
ICC6
CKE ≤ 0.2 V
II(L)
VI = 0 to 3.6 V, All other pins not under test = 0 V
IO(L)
10
mA
–5
+5
µA
DOUT is disabled, VO = 0 to 3.6 V
–1.5
+1.5
µA
VOH
IO = – 4.0 mA
2.4
VOL
IO = + 4.0 mA
0.4
V
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK(MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
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Data Sheet E0067N10
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Output timing measurement reference level
Value
Unit
2.4 / 0.4
V
1.4
V
1
ns
1.4
V
CLK
tCL
2.4 V
1.4 V
0.4 V
tSETUP tHOLD
Input
2.4 V
1.4 V
L
EO
tCK
tCH
0.4 V
tAC
tOH
Output
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Data Sheet E0067N10
7
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Synchronous Characteristics
Parameter
Symbol
Clock cycle time
Access time from CLK
-A80
-A10
Unit
MIN.
MAX.
MIN.
MAX.
/CAS latency = 3
tCK3
8
(125 MHz)
10
(100 MHz)
ns
/CAS latency = 2
tCK2
10
(100 MHz)
13
(77 MHz)
ns
/CAS latency = 3
tAC3
6
6
ns
1
/CAS latency = 2
tAC2
6
7
ns
1
CLK high level width
3
3
ns
CLK low level width
tCL
3
3
ns
Data-out hold time
tOH
3
3
ns
Data-out low-impedance time
tLZ
0
0
ns
/CAS latency = 3
tHZ3
3
6
3
6
ns
/CAS latency = 2
tHZ2
3
6
3
7
ns
Data-in setup time
tDS
2
2
ns
Data-in hold time
tDH
1
1
ns
Address setup time
tAS
2
2
ns
Address hold time
tAH
1
1
ns
CKE setup time
tCKS
2
2
ns
CKE hold time
tCKH
1
1
ns
CKE setup time (Power down exit)
tCKSP
2
2
ns
Command (/CS0, /RAS, /CAS, /WE,
tCMS
2
2
ns
tCMH
1
1
ns
EO
tCH
Data-out high-impedance time
L
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
Note 1. Output load
1
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DQMB0 - DQMB7) setup time
Note
Z = 50 Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
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Data Sheet E0067N10
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Asynchronous Characteristics
Parameter
Symbol
-A80
MIN.
-A10
MAX.
MIN.
Unit
MAX.
tRC
70
70
ns
REF to REF/ACT command period (Refresh)
tRC1
70
70
ns
ACT to PRE command period
tRAS
48
PRE to ACT command period
tRP
20
20
ns
Delay time ACT to READ/WRITE command
tRCD
20
20
ns
ACT(one) to ACT(another) command period
tRRD
16
20
ns
Data-in to PRE command period
tDPL
8
10
ns
Data-in to ACT(REF) command /CAS latency = 3
tDAL3
1CLK+20
1CLK+20
ns
period (Auto precharge)
tDAL2
1CLK+20
1CLK+20
ns
tRSC
2
2
CLK
tT
0.5
EO
ACT to REF/ACT command period (Operation)
/CAS latency = 2
Mode register set cycle time
Transition time
Refresh time (4,096 refresh cycles)
tREF
120,000
30
64
50
1
Note
120,000
ns
30
ns
64
ms
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Data Sheet E0067N10
9
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Serial PD
(1/2)
Byte No.
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Defines the number of bytes written into
serial PD memory
80H
1
0
0
0
0
0
0
0
128 bytes
1
Total number of bytes of serial PD memory
08H
0
0
0
0
1
0
0
0
256 bytes
2
Fundamental memory type
04H
0
0
0
0
0
1
0
0
SDRAM
3
Number of rows
0CH
0
0
0
0
1
1
0
0
12 rows
4
Number of columns
09H
0
0
0
0
1
0
0
1
9 columns
5
Number of banks
01H
0
0
0
0
0
0
0
1
1 bank
EO
6
Data width
48H
0
1
0
0
1
0
0
0
72 bits
7
Data width (continued)
00H
0
0
0
0
0
0
0
0
0
8
Voltage interface
9
CL = 3 Cycle time
10
CL = 3 Access time
01H
0
0
0
0
0
0
0
1
LVTTL
-A80
80H
1
0
0
0
0
0
0
0
8 ns
-A10
A0H
1
0
1
0
0
0
0
0
10 ns
60H
0
1
1
0
0
0
0
0
6 ns
60H
0
1
1
0
0
0
0
0
6 ns
DIMM configuration type
02H
0
0
0
0
0
0
1
0
ECC
12
Refresh rate/type
80H
1
0
0
0
0
0
0
0
Normal
13
SDRAM width
10H
0
0
0
1
0
0
0
0
×16
14
Error checking SDRAM width
10H
0
0
0
1
0
0
0
0
×16
15
Minimum clock delay
01H
0
0
0
0
0
0
0
1
1 clock
16
Burst length supported
8FH
1
0
0
0
1
1
1
1
1, 2, 4, 8, F
17
Number of banks on each SDRAM
04H
0
0
0
0
0
1
0
0
4 banks
18
/CAS latency supported
06H
0
0
0
0
0
1
1
0
2, 3
19
/CS latency supported
01H
0
0
0
0
0
0
0
1
0
20
/WE latency supported
01H
0
0
0
0
0
0
0
1
0
21
SDRAM module attributes
00H
0
0
0
0
0
0
0
0
L
-A80
-A10
11
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22
SDRAM device attributes : General
0EH
0
0
0
0
1
1
1
0
23
CL = 2 Cycle time
-A80
A0H
1
0
1
0
0
0
0
0
10 ns
-A10
D0H
1
1
0
1
0
0
0
0
13 ns
24
CL = 2 Access time
25-26
27
tRP(MIN.)
28
tRRD(MIN.)
29
tRCD(MIN.)
tRAS(MIN.)
31
Module bank density
60H
0
1
1
0
0
0
0
0
6 ns
70H
0
1
1
1
0
0
0
0
7 ns
00H
0
0
0
0
0
0
0
0
-A80
14H
0
0
0
1
0
1
0
0
20 ns
-A10
14H
0
0
0
1
0
1
0
0
20 ns
-A80
10H
0
0
0
1
0
0
0
0
16 ns
-A10
14H
0
0
0
1
0
1
0
0
20 ns
-A80
14H
0
0
0
1
0
1
0
0
20 ns
-A10
14H
0
0
0
1
0
1
0
0
20 ns
-A80
30H
0
0
1
1
0
0
32H
0
0
1
1
0
0
10H
0
0
0
1
0
0
Data Sheet E0067N10
ct
30
-A80
-A10
-A10
10
Notes
0
0
48 ns
1
0
50 ns
0
0
64M bytes
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
(2/2)
Byte No.
32
33
34
Function Described
63
72
Bit 3
Bit 2
Bit 1
Bit 0
Notes
0
0
1
0
0
0
0
0
2 ns
signal setup time
-A10
20H
0
0
1
0
0
0
0
0
2 ns
Command and address
-A80
10H
0
0
0
1
0
0
0
0
1 ns
signal hold time
-A10
10H
0
0
0
1
0
0
0
0
1 ns
Data signal input setup time
-A80
20H
0
0
1
0
0
0
0
0
2 ns
-A10
20H
0
0
1
0
0
0
0
0
2 ns
-A80
10H
0
0
0
1
0
0
0
0
1 ns
-A10
10H
0
0
0
1
0
0
0
0
1 ns
00H
0
0
0
0
0
0
0
0
-A80
12H
0
0
0
1
0
0
1
0
1.2 A
-A10
12H
0
0
0
1
0
0
1
0
1.2 A
Checksum
-A80
01H
0
0
0
0
0
0
0
1
for bytes 0 - 62
-A10
67H
0
1
1
0
0
1
1
1
Data signal input hold time
SPD revision
Manufacture’s JEDEC ID code
Manufacturing location
91-92
Revision code
93-94
Manufacturing date
95-98
Assembly serial number
99-125
Mfg specific
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Manufacture’s P/N
127
Bit 4
20H
73-90
126
Bit 5
L
64-71
Bit 6
-A80
36-61
62
Bit 7
Command and address
EO
35
Hex
Intel specification frequency
-A80
64H
0
1
1
0
0
1
0
0
100 MHz
-A10
64H
0
1
1
0
0
1
0
0
100 MHz
Intel specification /CAS
-A80
87H
1
0
0
0
0
1
1
1
latency support
-A10
85H
1
0
0
0
0
1
0
1
Timing Chart
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).
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Data Sheet E0067N10
11
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Package Drawing
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
M1 (AREA B)
Y
N
Z
EO
R
M2 (AREA A)
Q
M
L
U1
U2
T
(OPTIONAL HOLES)
C
L
I
S
A
H
B
E
D
A1 (AREA A)
F
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ITEM
detail of A part
W
D2
D1
X
V
MILLIMETERS
A
67.6
A1
67.6±0.15
B
23.2
C
29.0
D
4.6
D1
1.5±0.10
D2
4.0
E
F
32.8
3.7
H
0.8 (T.P.)
I
L
3.3
20.0
M
M1
31.75±0.15
9.75
M2
22.0
N
3.8 MAX.
Q
R2.0
4.00±0.10
S
φ 1.8
T
U1
1.0±0.1
3.2 MIN.
U2
4.0 MIN.
V
W
0.25 MAX.
0.6±0.05
X
Y
2.55 MIN.
2.0 MIN.
Z
2.0 MIN.
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R
M144S-80A13
12
Data Sheet E0067N10
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
[MEMO]
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EO
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Data Sheet E0067N10
13
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
[MEMO]
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14
Data Sheet E0067N10
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
EO
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
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causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
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3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
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Data Sheet E0067N10
15
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
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When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
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• The information in this document is current as of September, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or
data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all
products and/or types are available in every country. Please check with an Elpida Memory, Inc. for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document.
• Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of Elpida semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of Elpida or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• Elpida semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in
Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in
applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine
Elpida's willingness to support a given application.
(Note)
(1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned
subsidiaries.
(2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or
for Elpida (as defined above).
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M8E 00. 4