ON MC100LVE210FN 3.3v ecl dual 1:4, 1:5 differential fanout buffer Datasheet

MC100LVE210
3.3VECL Dual 1:4, 1:5
Differential Fanout Buffer
Description
The MC100LVE210 is a low voltage, low skew dual differential ECL
fanout buffer designed with clock distribution in mind. The device features
two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device
features fully differential clock paths to minimize both device and system
skew. The dual buffer allows for the fanout of two signals through a single
chip, thus reducing the skew between the two fundamental signals from a
part−to−part skew down to an output−to−output skew. This capability
reduces the skew by a factor of 4 as compared to using two LVE111’s to
accomplish the same task.
To ensure that the tight skew specification is met it is necessary that both
sides of the differential output are identically terminated, even if only one
side is being used. In most applications all nine differential pairs will be
used and therefore terminated. In the case where fewer than nine pairs are
used it is necessary to terminate at least the output pairs adjacent to the
output pair being used in order to maintain minimum skew. Failure to
follow this guideline will result in small degradations of propagation delay
(on the order of 10−20 ps) of the outputs being used, while not catastrophic
to most designs this will result in an increase in skew. Note that the
package corners isolate outputs from one another such that the guideline
expressed above holds only for outputs on the same side of the package.
The MC100LVE210, as with most ECL devices, can be operated from a
positive VCC supply in PECL mode. This allows the LVE210 to be used
for high performance clock distribution in +3.3 V systems. Designers can
take advantage of the LVE210’s performance to distribute low skew clocks
across the backplane or the board. In a PECL environment series or
Thevenin line terminations are typically used as they require no additional
power supplies, if parallel termination is desired a terminating voltage of
VCC − 2.0 V will need to be provided. For more information on using
PECL, designers should refer to Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, VBB should be left open.
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MARKING
DIAGRAM*
1 28
MC100LVE210G
AWLYYWW
PLCC−28
FN SUFFIX
CASE 776
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Features
•
•
•
•
•
•
•
•
200 ps Part−to−Part Skew
50 ps Typical Output−to−Output Skew
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 7
1
Publication Order Number:
MC100LVE210/D
MC100LVE210
Qa0 Qa0 Qa1 VCCO Qa1 Qa2 Qa2
25
VEE
VBB
CLKa
VCC
24
23
22
21
20
Qa0
19
26
18
27
28
Pinout: 28−Lead PLCC
(Top View)
1
Qa0
Qa3
17
Qa3
16
Qb0
15
VCCO
2
14
Qb0
CLKb
3
13
Qb1
CLKb
4
12
Qb1
6
7
8
9
10
Qa1
CLKa
Qa1
Qa2
CLKa
5
CLKa
Qa2
Qa3
Qa3
Qb0
Qb0
11
CLKb
Qb1
CLKb
Qb1
Qb2
Qb4 Qb4 Qb3 VCCO Qb3 Qb2 Qb2
Qb2
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Qb3
Qb3
Figure 1. Pinout Assignment
Qb4
Qb4
Table 1. PIN DESCRIPTION
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
Pin
VBB
Function
CLKa, CLKa
ECL Differential Input Pairs
CLKb, CLKb
ECL Differential Input Pairs
Qa0:3, Qa0:3
ECL Differential Outputs
Qb0:3, Qb0:3
ECL Differential Outputs
VBB
Reference Voltage Output
VCC, VCCO
Positive Supply
VEE
Negative Supply
Figure 2. Logic Diagram
Table 2. ATTRIBUTES
Characteristic
Value
Internal Input Pulldown Resistor
50 kW
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
PLCC−28
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 2 kV
> 200 V
Pb Pkg
Pb−Free Pkg
Level 1
Level 3
UL 94 V−0 @ 0.125 in
179
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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2
MC100LVE210
Table 3. MAXIMUM RATINGS
Rating
Unit
VCC
Symbol
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
VEE = 0 V
VI v VCC
6 to 0
V
NECL Mode Input Voltage
VCC = 0 V
VI w VEE
−6 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26 ± 5%
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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MC100LVE210
Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 2)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
55
85°C
Max
Min
Typ
55
Max
Unit
65
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 3)
2215
2295
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 3)
1470
1605
1745
1490
1595
1680
1490
1595
1680
mV
VIH
Input HIGH Voltage (Single−Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1490
1825
1490
1825
1490
1825
mV
VBB
Output Voltage Reference
1.92
2.04
1.92
2.04
1.92
2.04
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 7)
1.8
2.9
1.8
2.9
1.8
2.9
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
150
0.5
mA
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
3. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device
still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than
or equal to VPP(min).
Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 5)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
55
85°C
Max
Min
Typ
55
Max
Unit
65
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 6)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1475
−1810
−1475
−1810
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 7)
−1.5
−0.4
−1.5
−0.4
−1.5
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
150
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device
still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than
or equal to VPP(min).
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MC100LVE210
Table 6. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 8)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
700
Typ
85°C
Max
Min
700
Typ
Max
700
Unit
fmax
Maximum Toggle Frequency
GHz
tPLH
tPHL
Propagation Delay to Output
IN (Differential) (Note 9)
IN (Single−Ended) (Note 10)
tskew
Within−Device Skew (Note 11)
Qa to Qb
Qa to Qa, Qb to Qb
Part−to−Part Skew (Diff)
50
50
tJITTER
Cycle−to−Cycle Jitter
<1
VPP
Input Swing (Note 12)
500
1000
500
1000
500
1000
mV
tr/tf
Output Rise/Fall Time (20%−80%)
200
600
200
600
200
600
ps
ps
475
400
875
850
500
450
75
75
200
900
900
50
30
500
450
75
50
200
900
900
50
30
<1
75
50
200
<1
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. VEE can vary ±0.3 V.
9. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
10. The single−ended propagation delay is defined as the delay from the 50% point of the input signal to the crossing point of the differential output
signals.
11. The within−device skew is defined as the worst case difference between any two similar delay paths within a single device.
12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the LVE210 as a differential input as low as 50 mV will still produce full ECL levels at the output.
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MC100LVE210
Zo = 50 W
Q
D
Receiver
Device
Driver
Device
Zo = 50 W
Q
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC100LVE210FN
PLCC−28
37 Units / Rail
MC100LVE210FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100LVE210FNR2
PLCC−28
500 Tape & Reel
MC100LVE210FNR2G
PLCC−28
(Pb−Free)
500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC100LVE210
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PACKAGE
CASE 776−02
ISSUE E
0.007 (0.180)
B
Y BRK
−N−
T L−M
M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
0.010 (0.250)
G1
V
1
T L−M
S
N
S
S
VIEW D−D
A
0.007 (0.180)
R
0.007 (0.180)
Z
C
M
M
T L−M
T L−M
S
S
N
S
N
S
0.007 (0.180)
H
J
0.010 (0.250)
S
0.004 (0.100)
−T− SEATING
T L−M
S
N
S
N
S
K
PLANE
F
VIEW S
G1
T L−M
K1
E
G
M
S
VIEW S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
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MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC100LVE210
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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