ON MC10EPT20D Lvttl/lvcmos to differential lvpecl translator Datasheet

MC10EPT20
LVTTL/LVCMOS to
Differential LVPECL Translator
The MC10EPT20 is a LVTTL/LVCMOS to differential LVPECL
translator. Because LVPECL (Positive ECL) levels are used only
+3.3V and ground are required. The small outline 8–lead SOIC
package and the single gate of the EPT20 makes it ideal for those
applications where space, performance, and low power are at a
premium.
•
•
•
•
•
•
•
•
•
•
•
390ps Typical Propagation Delay
High Bandwidth to 1.0 GHz Typical
Differential LVPECL Outputs
Small Outline SOIC Package
PNP LVTTL Inputs for Minimal Loading
VCC Range of 3.0V to 3.6V
ESD Protection: >1.5KV HBM, >200V MM
Q Output will default HIGH with inputs open
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 150 devices
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1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
HPT20
ALYW
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
1
*For additional information, see Application Note
AND8002/D
NC
Q
Q
1
8
LVTTL
2
3
7
VCC
D
6
NC
5
GND
PIN DESCRIPTION
PIN
FUNCTION
Q, Q
Differential LVPECL Outputs
D
LVTTL Input
VCC
Positive Supply
GND
Ground
LVPECL
NC
4
ORDERING INFORMATION
Device
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
 Semiconductor Components Industries, LLC, 1999
September, 1999 – Rev. 1.0
1
Package
Shipping
MC10EPT20D
SOIC
98 Units/Rail
MC10EPT20DR2
SOIC
2500 Tape & Reel
Publication Order Number:
MC10EPT20/D
MC10EPT20
MAXIMUM RATINGS*
Value
Unit
VCC
Symbol
Power Supply
Parameter
6.0 to 0
VDC
VI
Input Voltage (VI not more positive than VCC)
6.0 to 0
VDC
Iout
Output Current
50
100
mA
TA
Operating Temperature Range
–40 to +85
°C
Tstg
Storage Temperature
–65 to +150
°C
θJA
Thermal Resistance (Junction–to–Ambient)
190
130
°C/W
θJC
Thermal Resistance (Junction–to–Case)
41 to 44 ± 5%
°C/W
Tsol
Solder Temperature (<2 to 3 Seconds: 245°C desired)
265
°C
Continuous
Surge
Still Air
500lfpm
* Maximum Ratings are those values beyond which damage to the device may occur.
LVTTL INPUT DC CHARACTERISTICS (VCC = 3.3V ±0.3V; GND = 0V; TA = –40°C to +85°C)
Symbol
Characteristic
Min
Typ
Max
Unit
20
µA
IIH
Input HIGH Current (Vin = 2.7V)
IIHH
Input HIGH Current MAX (Vin = 6.0V)
100
µA
IIL
Input LOW Current (Vin = 0.5V)
–0.6
mA
VIK
Input Clamp Voltage (Iin = –18mA)
–1.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.0
V
0.8
V
LVPECL OUTPUT DC CHARACTERISTICS (VCC = 3.3V ± 0.3V; GND = 0V) (Note 3.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
15
23
31
15
23
31
15
23
31
mA
ICC
Power Supply Current HIGH
(Note 1.)
VOH
Output HIGH Voltage
(Note 3.)
2165
2310
2415
2230
2355
2480
2290
2375
2540
mV
VOL
Output LOW Voltage
(Note 3.)
1365
1550
1615
1430
1570
1680
1490
1580
1740
mV
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
1. VCC = 3.3V, GND = 0V, all other pins floating.
2. All loading with 50 ohms to VCC–2.0 volts.
3. Output parameters vary 1:1 with VCC.
AC CHARACTERISTICS (VCC = 3.3V ± 0.3V; GND = 0V)
–40°C
Symbol
Characteristic
fmax
Maximum Toggle
Frequency (Note 4.)
tPLH,
tPHL
Propagation Delay to
Output Differential
tJITTER
Cycle–to–Cycle Jitter
Min
Typ
25°C
Max
Min
1000
Typ
85°C
Max
Min
1000
Typ
Max
1000
Unit
MHz
ps
150
350
600
150
TBD
370
600
150
TBD
tr
Output Rise/Fall Times
tf
(20% – 80%)
Q, Q
50
100
180
60
120
4. Fmax guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only.
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380
600
TBD
ps
ps
200
70
140
220
MC10EPT20
PACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–06
ISSUE T
D
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
5
0.25
H
E
M
B
M
1
4
h
B
e
X 45 _
q
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
M
C B
S
A
S
DIM
A
A1
B
C
D
E
e
H
h
L
q
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MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
MC10EPT20
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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4
MC10EPT20/D
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