MOTOROLA MC13110AFB Universal cordless telephone subsystem ic Datasheet

Order this document by MC13110A/D
The MC13110A/B and MC13111A/B integrates several of the functions
required for a cordless telephone into a single integrated circuit. This
significantly reduces component count, board space requirements, external
adjustments, and lowers overall costs. It is designed for use in both the
handset and the base.
• MC13110A and MC13111A: Fully Programmable in all Power Modes
•
•
•
•
•
•
•
•
MC13110B and MC13111B: MPU Clk Out and Second Local Oscillator
are “Always On”. There is No Inactive Mode
Dual Conversion FM Receiver
– Complete Dual Conversion Receiver – Antenna Input to Audio Out
80 MHz Maximum Carrier Frequency
– RSSI Output
– Carrier Detect Output with Programmable Threshold
– Comparator for Data Recovery
– Operates with Either a Quad Coil or Ceramic Discriminator
Compander
– Expander Includes Mute, Digital Volume Control, Speaker Driver,
Programmable Low Pass Filter, and Gain Block
– Compressor Includes Mute, Programmable Low Pass Filter, Limiter,
and Gain Block
MC13110A/B only: Frequency Inversion Scrambler
– Function Controlled via MPU Interface
– Programmable Carrier Modulation Frequency
Dual Universal Programmable PLL
– Supports New 25 Channel U.S. Standard with No External Switches
– Universal Design for Domestic and Foreign Cordless Telephone
Standards
– Digitally Controlled Via a Serial Interface Port
– Receive Side Includes 1st LO VCO, Phase Detector, and 14–Bit
Programmable Counter and 2nd LO with 12–Bit Counter
– Transmit Section Contains Phase Detector and 14–Bit Counter
– MPU Clock Outputs Eliminates Need for MPU Crystal
Low Battery Detect
– Provides Two Levels of Monitoring with Separate Outputs
– Separate, Adjustable Trip Points
2.7 to 5.5 V Operation (15 µA Current Consumption in Inactive Mode)
AN1575: Refer to this Application Note for a List of the “Worldwide
Cordless Telephone Frequencies
UNIVERSAL
NARROWBAND FM RECEIVER
INTEGRATED CIRCUIT
52
1
FB SUFFIX
PLASTIC PACKAGE
CASE 848B
(QFP–52)
48 1
FTA SUFFIX
PLASTIC PACKAGE
CASE 932
(LQFP–48)
ORDERING INFORMATION
Device
Tested Operating
Temperature Range
Package
MC13110AFB
QFP–52
MC13110AFTA
LQFP–48
MC13110BFB
QFP–52
MC13110BFTA
LQFP–48
MC13111AFB
TA = – 40° to +85°C
QFP–52
MC13111AFTA
LQFP–48
MC13111BFB
QFP–52
MC13111BFTA
LQFP–48
Simplified Block Diagram
Rx In
2nd
Mixer
1st
Mixer
1st LO
= MC13110A/B Only
2nd LO
Detector
RSSI
Rx PD In
NOTE:
Limiting IF
Amplifier
Rx PD Out
Rx Phase
Detector
Tx PD Out
Tx Phase
Detector
2nd LO
Scrambler
MPU Clock Out
RSSI
Carrier Detect Out
Data Out
µP Serial
Interface
Low Battery
Detect
Expander
Low Battery
Indicator
Rx Out
SPI
Scrambler
Tx Out
Compressor
Tx In
This device contains 8262 active transistors.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
MOTOROLA ANALOG IC DEVICE DATA
 Motorola, Inc. 1997
Rev 0
1
MC13110A/B MC13111A/B
PIN CONNECTIONS
1st Mix
Rx Gain
Adjust
Rx
Mute
2nd LO
Speaker
Mute
6 b Prog
SC Clk Ctr
23 VCC Audio
22 DA In
SC Filter
Clock
÷2
Tx
Mute
ALC
Mic Amp
Data
Amp
µP Serial
Interface
Clk 11
Data 9
TxVCO 8
15 DA Out
14 BD1 Out
Carrier
Detect
Prog
Clk Ctr
Gnd PLL 7
Tx PD 6
PLL Vref 5
Tx Phase
Detect
Rx PD 4
Vag 3
LO2 Out 2
Rx Phase
Detect
16 BD2 Out
Low Battery
Detect
Ref1
14 b Prog
Tx Ctr
VB 52
LO2 In 1
Ref2
Reg 2.5 V
2nd LO
10.240
18 C Cap
17 Tx Out
VB
Vref
÷25
÷4
÷1
12 b Prog
Ref Ctr
Ref1 51
19 C In
LPF
Bypass
14 b Prog
Rx Ctr
2nd LO
20 Amp Out
Tx Gain
Adjust
4.129 kHz
Limiter
Compressor
C Cap
1st LO
21 Tx In
Scrambler
Modulating Clock
LPF
Scr Out 49
27 Q Coil
Bypass
÷40
E In 48
28 Lim Out
29 VCC RF
24 Rx Audio In
E Out 46
Ref 2 50
30 Lim C2
31 Lim C1
32 Lim In
4.129 kHz
Expander
Vol
Control
Ecap 47
AALPF
CD Out 13
Speaker
Amp
LPF
EN 10
SA In 45
25 Det Out
LPF
Gnd Audio 43
26 RSSI
RSSI
Scrambler
1st LO
VcapCtrl 42
SA Out 44
Detector
2nd LO
1st LO
VCO
LO1Out 41
IF Amp/
Limiter
2nd Mix
Clk Out 12
LO1In 40
33 SGnd RF
34 Mix2 In
35 Mix2 Out
36 Gnd RF
39 Mix1 In1
38 Mix1 In2
37 Mix1 Out
QFP–52
NOTE:
1st Mix
Rx Gain
Adjust
Rx
Mute
2nd LO
SA Out 41
6 b Prog
SC Clk Ctr
LPF
22 Rx Audio In
Bypass
21 VCC Audio
14 b Prog
Rx Ctr
1st LO
16 C Cap
VCC Audio
14 b Prog
Tx Ctr
µP Serial
Interface
14 BD Out
Programmable
Low Battery
Detect
Tx Phase
Detect
Data
Amp
EN 9
Data 8
13 DA Out
Carrier
Detect
Prog
Clk Ctr
TxVCO 7
Gnd PLL 6
Vag 2
LO2Out 1
17 C In
LPF
Reg 2.5 V
Rx Phase
Detect
18 Amp Out
Tx Gain
Adjust
15 Tx Out
VB
Vref
Tx PD 5
12 b Prog
Ref Ctr
19 Tx In
Bypass
÷25
÷4
÷1
PLL Vref 4
2nd LO
2nd LO
10.240
2
Limiter
Compressor
C Cap
Rx PD 3
LO2In 48
4.129 kHz
LPF
Scr Out 46
VB 47
Tx
Mute
Mic Amp
Scrambler
Modulating Clock
÷40
ALC
20 DA In
SC Filter
Clock
÷2
E Out 43
E In 45
25 Lim Out
4.129 kHz
Expander
Vol
Control
AALPF
CD Out 12
Speaker
Amp
Speaker
Mute
SA In 42
26 VCC RF
23 Det Out
LPF
Gnd Audio 40
Ecap 44
27 Lim C2
28 Lim C1
29 Lim In
30 RSSI
Scrambler
1st LO
VcapCtrl 39
24 Q Coil
RSSI
Clk Out 11
LO1Out 38
Detector
2nd LO
1st LO
VCO
= MC13110A/B Only
IF Amp/
Limiter
2nd Mix
Clk 10
LO1In 37
31 Mix2 In
32 Mix2 Out
33 Gnd RF
36 Mix1 In1
35 Mix1 In2
34 Mix1 Out
LQFP–48
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
MAXIMUM RATINGS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Symbol
Value
Unit
Power Supply Voltage
Characteristic
VCC
– 0.5 to +6.0
Vdc
Junction Temperature
TJ
– 65 to +150
°C
Maximum Power Dissipation, TA = 25°C
PD
70
mW
NOTES: 1. Devices should not be operated at these limits. The “Recommended Operating Conditions”
provide for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Supply Voltage
Min
Typ
Max
Unit
VCC
2.7
3.6
5.5
Vdc
Operating Ambient Temperature
TA
–40
–
85
°C
Input Voltage Low (Data, Clk, EN)
VIL
–
–
0.3
V
Input Voltage High (Data, Clk, EN)
VIH
PLL Vref –
0.3
–
–
V
Bandgap Reference Voltage
VB
–
1.5
–
V
NOTE:
3. All limits are not necessarily functional concurrently.
DC ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, TA = 25°C, unless otherwise specified, IP3 = 0;
Test Circuit Figure 1.)
Characteristic
Static Current
Active Mode
Receive Mode
Standby Mode
Inactive Mode [Note 4]
Symbol
Min
Typ
Max
Unit
5.5
3.1
–
–
8.5
4.1
465
15
10.5
5.3
560
30
mA
mA
µA
µA
–
1.4
1.8
mA
1
ACT ICC
Rx ICC
STD ICC
INACT ICC
Current Increase When IP3 = 1
(Active and Receive Modes)
NOTE:
Figure
IIP3
1
4. MC13110B/MC13111B versions have no inactive mode.
MOTOROLA ANALOG IC DEVICE DATA
3
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Figure
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
–
–
2.2
–100
–
–
Single–Ended, Matched Input, Generator
Referred
–
–
0.4
–115
–
–
Differential, Matched Input, Generator Referred
–
–
0.4
–115
–
–
Unit
FM RECEIVER (fRF = 46.77 MHz [USA Ch 21], fdev = ± 3.0 kHz, fmod = 1.0 kHz, Vcap ctrl = 1.2 V)
Input Sensitivity (for 12 dB SINAD at Det Out
Using C–Message Weighting Filter)
50 Ω Termination, Generator Referred
68, 69
Mix1
In1/In2
Det Out
VSIN
µVrms
dBm
First and Second Mixer Voltage Gain Total
(Vin = 1.0 mVrms, with CF1 and CF2 Load)
1
Mix1
In1 or In2
Mix2 Out
MXgainT
24
29
–
dB
Isolation of First Mixer Output and Second Mixer
Input (Vin = 1.0 mVrms, with CFI Removed)
–
Mix1
In1 or In2
Mix2 In
Mix–Iso
–
60
–
dB
Total Harmonic Distortion (Vin = 3.16 mVrms)
1
Mix1
In1 or In2
Det Out
THD
–
1.4
2.0
%
Recovered Audio (Vin = 3.16 mVrms)
1
Mix1
In1 or In2
Det Out
AFO
80
112
150
mVrms
AM Rejection Ratio (Vin = 3.16 mVrms, 30% AM,
@ 1.0 kHz)
1
Mix1
In1 or In2
Det Out
AMR
30
48
–
dB
Signal to Noise Ratio (Vin = 3.16 mVrms,
No Modulation)
–
Mix1
In1 or In2
Det Out
SNR
–
48
–
dB
RPS1
CPS1
–
–
1.6
3.7
–
–
RPD1
CPD1
–
–
1.6
1.8
–
–
FIRST MIXER (No Modulation, fin = USA Ch21, 46.77 MHz, 50 Ω Termination at Inputs)
Input Impedance
Single–Ended
Differential
Output Impedance
Voltage Conversion Gain
(Vin = 1.0 mVrms, with CF1 Filter as Load)
1.0 dB Voltage Compression Level (Input Referred)
IP3 Bit Set to 0
IP3 Bit Set to 1
Third Order Intercept (Input Referred) [Note 5]
IP3 Bit Set to 0
IP3 Bit Set to 1
–3.0 dB IF Bandwidth
NOTE:
4
–
16
16
Mix1
In1 or In2
Mix1
In1/In2
kΩ
pF
14
–
Mix1 Out
RP1 Out
CP1 Out
–
–
300
3.7
–
–
Ω
pF
17, 18
Mix1
In1 or In2
Mix1 Out
MXgain1
–
12
–
dB
Mix1
In1 or In2
Mix1 Out
VO Mix1
1 dB
–
–
20
–21
–
–
–
–
56
–12
–
–
–
–
64
–11
–
–
–
–
178
–2.0
–
–
–
13
–
19, 21
20, 21
19, 21
Mix1
In1 or In2
Mix1 Out
TOImix1
20, 21
22
Mix1 In1
or In2
Mix1 Out
Mix1 BW
mVrms
dBm
mVrms
dBm
MHz
5. Third order intercept calculated for input levels 10 dB below 1.0 dB compression point.
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Figure
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
SECOND MIXER (No Modulation, fin = 10.7 MHz, 50 Ω Termination at Inputs)
Input Impedance
24
Mix2 In
Mix2 In
RP2 In
CP2 In
–
–
2.8
3.6
–
–
kΩ
pF
Output Impedance
24
–
Mix2 Out
RP2 Out
CP2 Out
–
–
1.5
6.1
–
–
kΩ
pF
26, 27
Mix2 In
Mix2 Out
MXgain2
–
20
–
dB
Mix2 In
Mix2 Out
VO
Mix2
1 dB
–
–
32
–17
–
–
–
–
45
–14
–
–
28, 30
–
–
136
–4.3
–
–
29, 30
–
–
158
–3.0
–
–
Voltage Conversion Gain
(Vin = 1.0 mVrms, with CF2 Filter as Load)
1.0 dB Voltage Compression Level (Input Referred)
IP3 Bit Set 0
IP3 Bit Set 1
Third Order Intercept (Input Referred) [Note 6]
IP3 Bit Set 0
IP3 Bit Set 1
–3.0 dB IF Bandwidth
28, 30
29, 30
Mix2 In
31
Mix2 In
Mix2 Out
TOImix2
mVrms
dBm
mVrms
dBm
Mix2 Out
Mix2 BW
–
2.5
–
MHz
LIMITER/DEMODULATOR (fin = 455 kHz, fdev = ±3.0 kHz, fmod = 1.0 kHz)
Input Impedance
49
Lim In
Lim In
RPLim
CPLim
–
–
1.5
16
–
–
kΩ
pF
Detector Output Impedance
–
–
Det Out
RO
–
1.1
–
kΩ
IF – 3.0 dB Limiting Sensitivity
1
Lim In
Det Out
IF Sens
–
71
100
µVrms
Demodulator Bandwidth
–
Lim In
Det Out
BW
–
20
–
kHz
RSSI Output Dynamic Range
56
Mix1 In
RSSI
RSSI
–
80
–
dB
DC Voltage Range
56
Mix1 In
RSSI
DC RSSI
–
0.2 to
1.5
–
Vdc
Carrier Detect Threshold
CD Threshold Adjust = (10100)
(Threshold Relative to Mix1 In Level)
57
Mix1 In
CD Out
VT
–
15
–
µVrms
Hysteresis, CD = (10100)
(Threshold Relative to Mix1 In Level)
57
Mix1 In
CD Out
Hys
–
2.0
–
dB
Output High Voltage
CD = (00000), RSSI = 0.2 V
1
RSSI
CD Out
VOH
VCC –
0.1
3.6
–
V
Output Low Voltage
CD = (11111), RSSI = 0.9 V
1
RSSI
CD Out
VOL
–
0.02
0.4
V
Carrier Detect Threshold Adjustment Range
(Programmable through MPU Interface)
126
–
–
VT
Range
–
–20 to
11
–
dB
Carrier Detect Threshold – Number of
Programmable Levels
126
–
–
VTn
–
32
–
–
ā
RSSI/CARRIER DETECT (No Modulation)
NOTE:
6. Third order intercept calculated for input levels 10 dB below 1.0 dB compression point.
MOTOROLA ANALOG IC DEVICE DATA
5
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Figure
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
–4.0
0
4.0
dB
Rx AUDIO PATH (fin = 1.0 kHz, Active Mode, scrambler bypassed)
Absolute Gain (Vin = – 20 dBV)
1, 72
Rx Audio In
SA Out
G
Gain Tracking
(Referenced to E Out for Vin = –20 dBV)
Vin = – 30 dBV
Vin = – 40 dBV
1, 76
E In
E Out
Gt
Total Harmonic Distortion (Vin = – 20 dBV)
1, 76
Rx Audio In
SA Out
Maximum Input Voltage (VCC = 2.7 V)
76
Rx Audio In
Maximum Output Voltage (Increase input voltage
until output voltage THD = 5.0%, then measure
output voltage)
1
Input
p Impedance
p
dB
–21
–42
–20
–40
–19
–38
THD
–
0.7
1.0
%
–
–
–
–11.5
–
dBV
E In
E Out
VOmax
–2.0
0
–
dBV
–
Rx Audio In
E In
I
–
Zin
–
–
600
75
7.5
–
–
kΩ
Attack Time
Ecap = 0.5 µF, Rfilt = 40 k (See Appendix B)
–
E In
E Out
ta
–
3.0
–
ms
Release Time
Ecap = 0.5 µF, Rfilt = 40 k (See Appendix B)
–
E In
E Out
tr
–
13.5
–
ms
Compressor to Expander Crosstalk
Vin = –10 dBV, V(E In) = AC Gnd
1
C In
E Out
CT
–
–90
–70
dB
Rx Muting (∆ Gain)
Vin = –20 dBV, Rx Gain Adj = (01111)
1
Rx Audio In
E Out
Me
–
–84
–60
dB
Rx High Frequency Corner
Rx Path, V Rx Audio In = –20 dBV
1
Rx Audio In
Scr Out
Rx fch
3.779
3.879
3.979
kHz
Low Pass Filter Passband Ripple (Vin = –20 dBV)
1, 73
Rx Audio In
Scr Out
Ripple
–
0.4
0.6
dB
Rx Gain Adjust Range (Programmable through
MPU Interface)
125
Rx Audio In
Scr Out
Rx
Range
–
–9.0 to
10
–
dB
Rx Gain Adjust Steps – Number of
Programmable Levels
125
Rx Audio In
Scr Out
Rx n
–
20
–
dB
Audio Path Noise, C–Message Weighting
(Input AC–Grounded)
70
Rx Audio In
Scr Out
E Out
SA Out
EN
–
–
–85
<–95
<–95
–
–
dBV
Volume Control Adjust Range
123
E In
E Out
VcnRange
–
–14 to
16
–
dB
Volume Control – Number of Programmable
Levels
123
E In
E Out
Vcn
–
16
–
–
Maximum Output Swing
RL = No Load, Vin = 3.4 Vpp
RL = 130 Ω, Vin = 2.8 Vpp
RL = 620 Ω, Vin = 4.0 Vpp
1, 79
SA In
SA Out
VOmax
2.8
2.0
–
3.2
2.6
3.4
–
–
–
Speaker Amp Muting
Vin = –20 dBV, RL = 130 Ω
1
–
–92
–60
SPEAKER AMP/SP MUTE (Active Mode)
6
SA In
SA Out
Msp
Vpp
dB
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Figure
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
Hysteresis
1
DA In
DA Out
Hys
30
42
50
mV
Threshold Voltage
–
DA In
DA Out
VT
–
VCC –
0.7
–
V
Input Impedance
1
–
DA In
ZI
200
250
280
kΩ
Output Impedance
–
–
DA Out
ZO
–
100
–
kΩ
Output High Voltage
Vin = VCC – 1.0 V, IOH = 0 mA
1
DA In
DA Out
VOH
VCC –
0.1
3.6
–
V
Output Low Voltage
Vin = VCC – 0.4 V, IOL = 0 mA
1
DA In
DA Out
VOL
–
0.1
0.4
V
Maximum Frequency
–
DA In
DA Out
Fmax
–
10
–
kHz
Characteristic
DATA AMP COMPARATOR
MIC AMP (fin = 1.0 kHz, External resistors set to gain of 1, Active Mode)
Open Loop Gain
–
Tx In
Amp Out
AVOL
–
100,000
–
V/V
Gain Bandwidth
–
Tx In
Amp Out
GBW
–
100
–
kHz
Maximum Output Swing (RL = 10 kΩ)
–
Tx In
Amp Out
VOmax
–
3.2
–
Vpp
Tx AUDIO PATH (fin = 1.0 kHz, Tx Gain Adj = (01111); ALC, Limiter, and Mutes Disabled; Active Mode, scrambler bypassed)
Absolute Gain (Vin = –10 dBV)
1, 83
Tx In
Tx Out
G
–4.0
0
4.0
Gain Tracking
(Referenced to Tx Out for Vin = –10 dBV)
Vin = – 30 dBV
Vin = – 40 dBV
1, 87
Tx In
Tx Out
Total Harmonic Distortion (Vin = – 10 dBV)
1, 87
Tx In
Tx Out
Maximum Output Voltage (Increase input voltage
until output voltage THD = 5.0%, then measure
output voltage. Tx Gain Adjust = 8 dB)
1
Tx In
Input Impedance
–
Attack Time (Ccap = 0.5 µF, Rfilt = 40 k (See
Appendix B))
Gt
dB
dB
–11
–17
–10
–15
–9.0
–13
THD
–
0.8
1.8
%
Tx Out
VOmax
–2.0
0
–
dBV
–
C In
Zin
–
10
–
kΩ
–
C In
Tx Out
ta
–
3.0
–
ms
Release Time (Ccap = 0.5 µF, Rfilt = 40 k (See
Appendix B))
–
C In
Tx Out
tr
–
13.5
–
ms
Expander to Compressor Crosstalk (Vin = –20 dBV,
Speaker Amp No Load, V(C In) = AC Gnd)
1
E In
Tx Out
CT
–
–60
–40
dB
Tx Muting (Vin – 10 dBV)
1
Tx In
Tx Out
Mc
–
–88
–60
dB
1, 87,
90
Tx In
Tx Out
ALCout
–15
–13
–13
–11
–8.0
–6.0
ALC Slope (ALC enabled)
Vin = –10 dBv
Vin = –2.5 dBv
1
Tx In
Tx Out
Slope
p
0.1
0.25
0.4
dB/dB
ALC Input Dynamic Range
–
C In
Tx Out
DR
–
–16 to
–2.5
–
dBV
Limiter Output Level (Vin = – 2.5 dBV,
Limiter enabled)
1
Tx In
Tx Out
Vlim
–10
–8.0
–
dBV
Tx High Frequency Corner [Note 7]
(VTx In = –10 dBV, Mic Amp = Unity Gain)
1
Tx In
Tx Out
Tx fc
3.6
3.7
3.8
kHz
ALC Output Level (ALC enabled)
Vin = –10 dBV
Vin = –2.5 dBV
NOTE:
dBV
7. The filter specification is based on a 10.24 MHz 2nd LO, and a switched–capacitor (SC) filter counter divider ratio of 31. If other 2nd LO frequencies
and/or SC filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting SC filter clock frequency.
MOTOROLA ANALOG IC DEVICE DATA
7
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Figure
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
Tx AUDIO PATH (fin = 1.0 kHz, Tx Gain Adj = (01111); ALC, Limiter, and Mutes Disabled; Active Mode, scrambler bypassed)
Low Pass Filter Passband Ripple (Vin = –10 dBV)
1, 84
Tx In
Tx Out
Ripple
–
0.7
1.2
dB
Maximum Compressor Gain (Vin = –70 dBV)
–
C In
Tx Out
AVmax
–
23
–
dB
Tx Gain Adjust Range (Programmable through
MPU Interface)
125
C In
Tx Out
Tx Range
–
–9.0 to
10
–
dB
Tx Gain Adjust Steps – Number of Programmable
Levels
125
C In
Tx Out
Tx n
–
20
–
–
Rx AND Tx SCRAMBLER (2nd LO = 10.24 MHz, Tx Gain Adj = (01111), Rx Gain Adj = (01111), Volume Control = (0 dB Default Levels),
SCF Clock Divider = 31. Total is divide by 62 for SCF clock frequency of 165.16 kHz)
Rx High Frequency Corner (Note 8)
Rx Path, f = 479 Hz, V Rx Audio In = –20 dBV
–
Rx Audio In
Scr Out
Rx fch
3.55
3.65
3.75
kHz
Tx High Frequency Corner (Note 8)
Tx Path, f = 300 Hz, V Tx In = –10 dBV,
Mic Amp = Unity Gain
–
Tx In
Tx Out
Tx fch
3.829
3.879
3.929
kHz
–
–
Rx Audio In
Tx In
E Out
Tx Out
–4.0
–4.0
0.4
–1.0
4.0
4.0
–
C In
E Out
Ripple
–
1.9
2.5
dB
fmod
4.119
4.129
4.139
kHz
–
–
Rx Audio In
C In
E Out
Tx Out
–
C In
E Out
GD
–
1.0
–
–
C In
E Out
GD
–
4.0
–
Carrier Breakthrough
Rx + Tx Path – 1.0 µF from Tx Out to
Rx Audio In
–
C In
E Out
CBT
–
–60
–
dB
Baseband Breakthrough
Rx + Tx Path – 1.0 µF from Tx Out to
Rx Audio In,
fin = 1.0 kHz, fmeas = 3.192 kHz
–
C In
E Out
BBT
–
–50
–
dB
1, 131
Ref1
Ref2
BD1 Out
BD2 Out
VTi
1.38
1.48
1.58
V
Average Threshold
Voltage After Electronic Adjustment
(Vref_Adj = (adjusted value))
1
Ref1
Ref2
BD1 Out
BD2 Out
VTf
1.475
1.5
1.525
V
Hysteresis
–
Ref1
Ref2
BD1 Out
BD2 Out
Hys
–
4.0
–
mV
Input Current (Vin = 1.0 and 2.0 V)
1
–
Ref1
Ref2
Iin
–50
–
50
nA
Output High Voltage (Vin = 2.0 V)
1
Ref1
Ref2
BD1 Out
BD2 Out
VOH
VCC –
0.1
3.6
–
V
Absolute Gain
Rx: Vin = –20 dBV
Tx: Vin = –10 dBV, Limiter disabled
Pass Band Ripple
Rx + Tx Path – 1.0 µF from Tx Out to
Rx Audio In, fin = low corner frequency to
high corner frequency
Scrambler Modulation Frequency
Rx: 100 mV (–20 dBV)
Tx: 316 mV (–10 dBV)
Group Delay
Rx + Tx Path – 1.0 µF from Tx Out to
Rx Audio In,, fin = 1.0 kHz
fin = low corner frequency to high corner
frequency
AV
dB
ms
LOW BATTERY DETECT
Average Threshold
Voltage Before Electronic Adjustment
(Vref_Adj = (0111))
NOTE:
8
8. The filter specification is based on a 10.24 MHz 2nd LO, and a switch–capacitor (SC) filter counter divider ratio of 31. If other 2nd LO frequencies
and/or SC filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting SC filter clock frequency.
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Input
Pin
Measure
Pin
1
Ref1
Ref2
BD1 Out
BD2 Out
1, 128
VCC Audio
BD2 Out
Figure
Symbol
Min
Typ
Max
Unit
VOL
–
0.2
0.4
V
IBS7
IBS6
IBS5
IBS4
IBS3
IBS2
IBS1
3.381
3.298
3.217
3.134
2.970
2.886
2.802
3.455
3.370
3.287
3.202
3.034
2.948
2.862
3.529
3.442
3.357
3.270
3.098
3.010
2.922
LOW BATTERY DETECT
Output Low Voltage (Vin = 1.0 V)
BATTERY DETECT INTERNAL THRESHOLD
After Electronic Adjustment of VB Voltage
BD Select = (111)
BD Select = (110)
BD Select = (101)
BD Select = (100)
BD Select = (011)
BD Select = (010)
BD Select = (001)
V
PLL PHASE DETECTOR
Output Source Current
(VPD = Gnd + 0.5 V to PLL Vref – 0.5 V)
–
–
Rx PD
Tx PD
IOH
–
1.0
–
mA
Output Sink Current
(VPD = Gnd + 0.5 V to PLL Vref – 0.5 V)
–
–
Rx PD
Tx PD
IOL
–
1.0
–
mA
Maximum 2nd LO Frequency
(No Crystal)
–
LO2 In
–
f2ext
–
12
–
MHz
Maximum 2nd LO Frequency
(With Crystal)
–
–
LO2 In
LO2 Out
f2ext
–
12
–
MHz
Maximum Tx VCO (Input Frequency),
Vin = 200 mVpp
–
–
Tx VCO
ftxmax
–
80
–
MHz
Regulated Output Level (IL = 0 mA, after Vref
Adjustment)
1
–
PLL Vref
VO
2.4
2.5
2.6
V
Line Regulation (IL = 0 mA, VCC = 3.0 to 5.5 V)
1
VCC Audio
PLL Vref
VRegLine
–
11.8
40
mV
Load Regulation (IL = 1.0 mA)
1
VCC Audio
PLL Vref
VReg
Load
–20
–1.4
–
mV
Input Current Low (Vin = 0.3 V, Standby Mode)
1
–
Data,
Clk, EN
IIL
–5.0
0.4
–
µA
Input Current High (Vin = 3.3 V, Standby Mode)
1
–
Data,
Clk, EN
IIH
–
1.6
5.0
µA
Hysteresis Voltage
–
–
Data,
Clk, EN
Vhys
–
1.0
–
V
Maximum Clock Frequency
–
Data,
EN, Clk
–
–
–
2.0
–
MHz
Input Capacitance
–
Data,
Clk, EN
–
Cin
–
8.0
–
pF
EN to Clk Setup Time
106
–
EN, Clk
tsuEC
–
200
–
ns
Data to Clk Setup Time
105
–
Data, Clk
tsuDC
–
100
–
ns
Hold Time
105
–
Data, Clk
th
–
90
–
ns
Recovery Time
106
–
EN, Clk
trec
–
90
–
ns
–
–
EN, Clk
tw
–
100
–
ns
108
–
–
tpuMPU
–
100
–
µs
PLL LOOP CHARACTERISTICS
PLL VOLTAGE REGULATOR
MICROPROCESSOR SERIAL INTERFACE
Input Pulse Width
MPU Interface Power–Up Delay (90% of PLL Vref
to Data,Clk, EN)
MOTOROLA ANALOG IC DEVICE DATA
9
4700
0.1
32.4 k
1.0 k
0.1
0.1
3.01 k
1.0 µF
VCCA
5.0 – 50
10.240 MHz
0.1
0.1
0.047
49.9 k
49.9 k
1.0 k
0.1
1.5 k
Vref2
Vref1
Scr Out
E In
Rx Loop Filter
22.1 k
7.5 k
1.0 µF
E Out
SA In
SA Out
110
0.1
10 µF
MC13110A/B
MC13111A/B
IC
C Cap
Tx Out
Scr Out
C In
Amp Out
Tx In
DA In
VCC Audio
Rx Audio In
Det Out
RSSI
E In
E Cap
E Out
SA In
SA Out
Gnd Audio
V Cap Ctrl
LO1 Out
Mix 1 In2
LO2 Out
8.2
0.1
1
10 µ F
2
3
0.1
4
5
6
8
Tx VCO
0.01
7
9
BD 1 Out
DA Out
Ref1
VB
BD 2 Out
Ref2
MPU Clock Output
10 11 12 13
10
14
15
16
17
18
19
20
21
22
24
23
25
26
0.1
VCC
100 k
0.1
L2
0.01
22.1 k
NOTE: This schematic is only a partial representation of the actual production test circuit.
52
51
50
49
48
47
0.1 46
45
44
43
42
41
Gnd RF
Rx PD
LO1
In
Mix 1Out
Vag
40
PLL Vref
10 µ F
Mix2 Out
39 38 37 36 35 34 33 32 31 30 29 28 27
Mix2 In
Tx PD
33
0.1
Lim C1
Data
Mix 1
In1
LO2 In
L3
332
SGnd RF
Gnd PLL
0.01
CF2
455 kHz
Lim C2
EN
49.9
To VCC
Lim In
Tx VCO
Lim Out
Clk Out
RF In
CF1
10.7 MHz
VCC RF
Clk
Q
Coil
10
CD
Out
0.01
Figure 1. Production Test Circuit (52 Pin QFP)
0.1
100 k
VCC
0.1
Mic Amp Out
49.9 k
0.1
Carrier
Detect Out
Tx In
DA In
Rx Audio In
7.5 k
Tx Out
1.0µF
C In
Legend:
If ≥1, then capacitor value = pF
If <1, then capacitor value = µ F
49.9 k
V
100 k CC
VCCA
0.1
10 µF
1000
BD2 Out
Data Out
BD1 Out
Det Out
VCC Audio
0.1
15 k
MC13110A/B MC13111A/B
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
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PIN FUNCTION DESCRIPTION
Pin
LQFP–48
QFP–52
Symbol/
Type
48
1
1
2
LO2 In
LO2 Out
E i l
Equivalent
IInternall Ci
Circuit
i (52 Pi
Pin QFP)
These pins form the PLL reference oscillator when
connected to an external parallel–resonant crystal
(10.24 MHz typical). The reference oscillator is
also the second Local Oscillator (LO2) for the RF
receiver. “LO2 In” may also serve as an input for
an externally generated reference signal which is
typically ac–coupled.
PLL
Vref
100
1
PLL
Vref
PLL
Vref
LO2
In
100
2
LO2
Out
2
3
Vag
VCC
Audio
D
Description
i i
When the IC is set to the inactive mode, LO2 In is
internally pulled low to disable the oscillator. The
input capacitance to ground at each pin (LO2 In/
LO2 Out) is 3.0 pF.
Vag is the internal reference voltage for the
switched capacitor filter section. This pin must be
decoupled with a 0.1 µF capacitor.
PLL
Vref
3
Vag
30 k
3
4
Rx PD
(Output)
PLL
Vref
PLL
Vref
4 6
4,
15
5
6
Tx PD
(Output)
4
5
PLL Vref
Rx PD,
Tx PD
PLL Vref is a PLL voltage regulator output pin. An
internal voltage regulator provides a stable power
supply voltage for the Rx and Tx PLL’s and can
also be used as a regulated supply voltage for
other IC’s. It can source up to 1.0 mA externally.
Proper supply filtering is a must on this pin. PLL
Vref is pulled up to VCC audio for the standby and
inactive modes (Note 1).
VCC
Audio
5
PLL Vref
This pin is a tri–state voltage output of the Rx and
Tx Phase Detector. It is either “high”, “low”, or “high
impedance,” depending on the phase difference of
the phase detector input signals. During lock, very
narrow pulses with a frequency equal to the
reference frequency are present. This pin drives
the external Rx and Tx PLL loop filters. Rx and Tx
PD outputs can sink or source 1.0 mA.
132 k
6
7
Gnd PLL
Ground pin for digital PLL section of IC.
7
8
Tx VCO
(Input)
Tx VCO is the transmit divide counter input which
is driven by an ac–coupled external transmit loop
VCO. The minimum signal level is 200 mVpp @
60.0 MHz. This pin also functions as the test mode
input for the counter tests.
PLL
Vref
8
PLL
Vref
1.0 k
TX VCO
MOTOROLA ANALOG IC DEVICE DATA
11
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
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MC13110A/B MC13111A/B
PIN FUNCTION DESCRIPTION (continued)
Pin
LQFP–48
QFP–52
8
9
10
9
10
11
Symbol/
Type
Equivalent Internal Circuit (52 Pin QFP)
Data
EN
Clk
(Input)
VCC
Audio
240
9, 10, 11
Data, EN, Clk
11
12
PLL
Vref
1.0 µA
Clk Out
(Output)
VCC
Audio
VCC
Audio
12
1.0 k
Clk Out
Description
Microprocessor serial interface input pins are for
programming various counters and control
functions. The switching thresholds are referenced
to PLL Vref and Gnd PLL. The inputs operate up to
VCC. These pins have 1.0 µA internal pull–down
currents.
The microprocessor clock output is derived from
the 2nd LO crystal oscillator and a programmable
divider with divide ratios of 2 to 312.5. It can be
used to drive a microprocessor and thereby
reduce the number of crystals required in the
system design. The driver has an internal resistor
in series with the output which can be combined
with an external capacitor to form a low pass filter
to reduce radiated noise on the PCB. This output
also functions as the output for the counter test
modes.
1) For the MC13110A/B and MC13111A/B the Clk
Out can be disabled via the MPU interface.
2) For the MC13110B and MC13111B this output is
always active (on) (Note 2).
12
13
CD Out
(I/O)
Dual function pin;
VCC
Audio
PLL
Vref
240
13
1) Carrier detect output (open collector with
external 100 kΩ pull–up resistor.
Hardware
Interrupt
CD Out
2) Hardware interrupt input which can be used to
“wake–up” from the Inactive Mode.
CD
Comparator
–
14
BD1 Out
14
16
BD2 Out
(Output)
13
15
DA Out
(Output)
Low battery detect output #1 is an open collector
with external pull–up resistor.
VCC
Audio
14 16
14,
BD1 Out
BD2 Out
VCC
Audio
Low battery detect output #2 is an open collector
with external pull–up resistor.
Data amplifier output (open collector with internal
100 kΩ pull–up resistor).
VCC
Audio
100 k
15
DA Out
15
17
Tx Out
(Output)
VCC
Audio
17
Tx Out is the Tx path audio output. Internally this
pin has a low–pass filter circuitry with –3 dB
bandwidth of 4.0 kHz. Tx gain and mute are
programmable through the MPU interface. This pin
is sensitive to load capacitance.
Tx Out
VB
12
MOTOROLA ANALOG IC DEVICE DATA
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ÁÁÁÁ
ÁÁÁÁÁ
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MC13110A/B MC13111A/B
PIN FUNCTION DESCRIPTION (continued)
Pin
LQFP–48
QFP–52
Symbol/
Type
16
18
C Cap
Equivalent Internal Circuit (52 Pin QFP)
C Cap is the compressor rectifier filter capacitor
pin. It is recommended that an external filter
capacitor to VCC audio be used. A practical
capacitor range is 0.1 to 1.0 µF. 0.47 µF is the
recommended value.
VCC
Audio
VCC
Audio
Description
40 k
18
C Cap
17
19
C In
(Input)
C In is the compressor input. This pin is internally
biased and has an input impedance of 12.5 k. C In
must be ac–coupled.
VCC
Audio
12.5 k
19
C In
VB
18
20
Amp Out
(Output)
19
21
Tx In
(Input)
Microphone amplifier output. The gain is set with
external resistors. The feedback resistor should be
less than 200 kΩ.
VCC
Audio
VCC
Audio
21
20
Tx In
Amp Out
VB
20
22
VCC
Audio
DA In
(Input)
Tx In is the Tx path input to the microphone
amplifier (Mic Amp). An external resistor is
connected to this pin to set the Mic Amp gain and
input impedance. Tx In must be ac–coupled, too.
The data amplifier input (DA In) resistance is
250 kΩ and must be ac–coupled. Hysteresis is
internally provided.
VCC
Audio
250 k
250 k
22
DA In
21
23
VCC Audio
22
24
Rx Audio In
(Input)
VCC audio is the supply for the audio section. It is
necessary to adequately filter this pin.
The Rx audio input resistance is 600 kΩ and must
be ac–coupled.
VCC
Audio
600 k
24
Rx Audio In
VB
23
25
Det Out
(Output)
VCC
RF
240
30 µA
MOTOROLA ANALOG IC DEVICE DATA
Det Out is the audio output from the FM detector.
This pin is dc–coupled from the FM detector and
has an output impedance of 1100 Ω.
VCC
Audio
25
Det Out
13
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ÁÁÁÁÁÁÁÁÁÁÁÁÁ
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MC13110A/B MC13111A/B
PIN FUNCTION DESCRIPTION (continued)
Pin
LQFP–48
QFP–52
Symbol/
Type
30
26
RSSI
Equivalent Internal Circuit (52 Pin QFP)
RSSI is the receive signal strength indicator. This
pin must be filtered through a capacitor to ground.
The capacitance value range should be 0.01 to
0.1 µF. This is also the input to the Carrier Detect
comparator. An external R to ground shifts the
RSSI voltage.
VCC
RF
VCC
RF
Description
VCC
Audio
26
RSSI
186 k
24
27
Q Coil
VCC
RF
A quad coil or ceramic discriminator connects this
pin as part of the FM demodulator circuit.
DC–couple this pin to VCC RF through the quad
coil or the external resistor.
VCC
RF
27
Q Coil
26
29
VCC RF
VCC supply for RF receiver section (1st LO, mixer,
limiter, demodulator). Proper supply filtering is
needed on this pin too.
25
28
Lim Out
A quad coil or ceramic discriminator are connected
to these pins as part of the FM demodulator circuit.
A coupling capacitor connects this pin to the quad
coil or ceramic discriminator as part of the FM
demodulator circuit. This pin can drive coupling
capacitors up to 47 pF with no deterioration in
performance.
VCC VCC VCC
RF RF RF
53.5 k
VCC
RF
31
27
28
30
31
Lim C2
Lim C1
28
Lim C1
32
Lim Out
Lim In
1.5 k
30
52 k
Lim C2
IF amplifier/limiter capacitor pins. These
decoupling capacitors should be 0.1 µF. They
determine the IF limiter gain and low frequency
bandwidth.
29
32
Lim In
(Input)
Signal input for IF amplifier/limiter. Signals should
be ac–coupled to this pin. The input impedance is
1.5 kΩ at 455 kHz.
–
33
SGnd RF
This pin is not connected internally but should be
grounded to reduce potential coupling between
pins.
31
34
Mix2 In
(Input)
VCC
RF
3.0 k
34
VCC
RF
Mix2 In is the second mixer input. Signals are to be
ac–coupled to this pin, which is biased internally to
VCC RF. The input impedance is
2.8 kΩ at 455 kHz. The input impedance can be
reduced by connecting an external resistor to
VCC RF.
Mix2 In
14
MOTOROLA ANALOG IC DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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MC13110A/B MC13111A/B
PIN FUNCTION DESCRIPTION (continued)
Pin
LQFP–48
QFP–52
32
35
Symbol/
Type
Equivalent Internal Circuit (52 Pin QFP)
Mix2 Out
(Output)
VCC
RF
Description
Mix2 Out is the second mixer output. The second
mixer has a 3 dB bandwidth of 2.5 MHz and an
output impedance of 1.5 kΩ. The output current
drive is 50 µA.
VCC
RF
1.2 k
35
Mix2 Out
33
36
Gnd RF
34
37
Mix1 Out
(Output)
Ground pin for RF section of the IC.
VCC
RF
The first mixer has a 3 dB IF bandwidth of 13 MHz
and an output impedance of 300 Ω. The output
current drive is 300 µA and can be programmed
for 1.0 mA.
VCC
RF
200
37
Mix1 Out
35
38
Mix1 In2
(Input)
20 k
VCC
RF
950
36
37
38
39
40
41
Mix1 In1
(Input)
VCC
RF
950
38, 39
Mix1 In2,
Mix1 In1
LO1 In
LO1 Out
Tank Elements, an internal varactor and capacitor
matrix for 1st LO multivibrator oscillator are
connected to these pins. The oscillator is useable
up to 80 MHz.
40
41
LO1
Out
39
42
Signals should be ac–coupled to this pin, which is
biased internally to VCC – 1.6 V. The single–ended
and differential input impedance are about 1.6 and
1.8 kΩ at 46 MHz, respectively.
Vref
LO1
In
Vcap Ctrl
VCC
RF
55 k
42
Vcap Ctrl is the 1st LO varactor control pin. The
voltage at this pin is referenced to Gnd Audio and
varies the capacitance between LO1 In and
LO2 Out. An increase in voltage will decrease
capacitance.
Vcap
Ctrl
40
43
Gnd Audio
41
44
SA Out
(Output)
Ground for audio section of the IC.
VCC
Audio
VCC
Audio
45
44
42
45
SA In
(Input)
SA In
I
SA Out
VB
MOTOROLA ANALOG IC DEVICE DATA
The speaker amplifier gain is set with an external
feedback resistor. It should be less than 200 kΩ.
The speaker amplifier can be muted through the
MPU interface.
An external resistor is connected to the speaker
amplifier input (SA In). This will set the gain and
input impedance and must be ac–coupled.
15
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MC13110A/B MC13111A/B
PIN FUNCTION DESCRIPTION (continued)
Pin
LQFP–48
QFP–52
43
46
Symbol/
Type
Equivalent Internal Circuit (52 Pin QFP)
E Out
(Output)
Description
The output level of the expander output is
determined by the volume control. Volume control
is programmable through the MPU interface.
VCC
Audio
46
E Out
VB
44
47
E Cap
VCC
Audio
E Cap is the expander rectifier filter capacitor pin.
Connect an external filter capacitor between VCC
audio and E Cap. The recommended capacitance
range is 0.1 to 1.0 µF. 0.47 µF is the suggested
value.
VCC
Audio
40 k
47
E Cap
45
48
VCC
Audio
E In
(Input)
The expander input pin is internally biased and has
input impedance of 30 kΩ.
30 k
48
E In
VB
46
49
Scr Out
(Output)
Scr Out is the Rx audio output. An internal low
pass filter has a –3 dB bandwidth of 4.0 kHz.
VCC
Audio
49
Scr Out
VB
–
50
Ref2
–
51
Ref1
47
52
VB
VCC
Audio
Reference voltage input for Low Battery Detect #2.
50, 51
Ref2, Ref1
Reference voltage input for Low Battery Detect #1.
VCC
Audio
VCC
Audio
240
52
VB
NOTE:
16
VB is the internal half supply analog ground
reference. This pin must be filtered with a
capacitor to ground. A typical capacitor range of
0.5 to 10 µF is desired to reduce crosstalk and
noise. It is important to keep this capacitor value
equal to the PLL Vref capacitor due to logic timing
(Note 9).
9. A capacitor range of 0.5 to 10 µF is recommended. The capacitor value should be the same used on the VB pin (Pin 52). An additional high
quality parallel capacitor of 0.01 µF is essential to filter out spikes originating from the PLL logic circuitry.
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
DEVICE DESCRIPTION AND APPLICATION INFORMATION
The following text, graphics, tables and schematics are
provided to the user as a source of valuable technical
information about the Universal Cordless Telephone IC. This
information originates from thorough evaluation of the device
performance for the US and French applications. This data
was obtained by using units from typical wafer lots. It is
important to note that the forgoing data and information was
from a limited number of units. By no means is the user to
assume that the data following is a guaranteed parametric.
Only the minimum and maximum limits identified in the
electrical characteristics tables found earlier in this spec are
guaranteed.
General Circuit Description
The MC13110A/B and MC13111A/B are a low power dual
conversion narrowband FM receiver designed for
applications up to 80 MHz carrier frequency. This device is
primarily designated to be used for the 49 MHz cordless
phone (CT–0), but has other applications such as low data
rate narrowband data links and as a backend device for 900
MHz systems where baseband analog processing is
required. This device contains a first and second mixer,
limiter, demodulator, extended range receive signal strength
(RSSI), receive and transmit baseband processing, dual
programmable PLL, low battery detect, and serial interface
for microprocessor control. The FM receiver can also be
used with either a quadrature coil or ceramic resonator.
Refer to the Pin Function Description table for the simplified
internal circuit schematic and description of this device.
DC Current and Battery Detect
Figures 3 through 6 are the current consumption for
Inactive, Standby, Receive, and Active modes versus supply
voltages. Figures 7 and 8 show the typical behavior of current
consumption in relation to temperature. The relationship of
additional current draw due to IP3 bit set to <1> and supply
voltage are shown in Figures 9 and 10.
For the Low Battery Detect, the user has the option to
operate the IC in the programmable or non–programmable
modes. Note that the 48 pin package can only be used in the
programmable mode. Figure 128 describes this operation
(refer to the Serial Interface section under Clock Divider
Register).
In the programmable mode several different internal
threshold levels are available (Figure 2). The bits are set
through the SCF Clock Divider Register as shown in Figures
108 and 126. The reference for the internal divider network is
VCC Audio. The voltages on the internal divider network are
compared to the Internal Reference Voltage, VB, generated
by an internal source. Since the internal comparator used is
non–inverting, a high at VCC Audio will yield a high at the
MOTOROLA ANALOG IC DEVICE DATA
battery detect output, and vice versa for VCC Audio set to a
low level. For the 52 pin package option, the Ref 1 and Ref 2
pins need to be tied to VCC when used in the programmable
mode. It is essential to keep the external reference pins
above Gnd to prevent any possible power–on reset to be
activated.
When considering the non–programmable mode (bits set
to <000>) for the 52 pin package, the Ref 1 and Ref 2 pins
become the comparators reference. An internal switch is
activated when the non–programmable mode is chosen
connecting Ref 1 and Ref 2. Here, two external precision
resistor dividers are used to set independent thresholds for
two battery detect hysteresis comparators. The voltages on
Ref 1 and Ref 2 are again compared to the internally
generated 1.5 V reference voltage (VB).
The Low Battery Detect threshold tolerance can be
improved by adjusting a trim–pot in the external resistor
divider (user designed). The initial tolerance of the internal
reference voltage (VB) is ±6.0%. Alternately, the tolerance of
the internal reference voltage can be improved to ±1.5%
through MPU serial interface programming (refer to the Serial
Interface section, Figure 131). The internal reference can be
measured directly at the “VB” pin. During final test of the
telephone, the VB internal reference voltage is measured.
Then, the internal reference voltage value is adjusted
electronically through the MPU serial interface to achieve the
desired accuracy level. The voltage reference register value
should be stored in ROM during final test so that it can be
reloaded each time the combo IC is powered up. The Low
Battery Detect outputs are open collector. The battery detect
levels will depend on the accuracy of the VB voltage. Figure
12 indicates that the VB voltage is fairly flat over temperature.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 2. Internal Low Battery Detect Levels
(with VB = 1.5 V)
Battery
Detect
Select
Ramping
Up
(V)
Ramping
Down
(V)
Average
(V)
Hysteresis
(mV)
0
–
–
–
–
1
2.867
2.861
2.864
4.0
2
2.953
2.947
2.950
6.0
3
3.039
3.031
3.035
8.0
4
3.207
3.199
3.204
8.0
5
3.291
3.285
3.288
6.0
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
6
3.375
3.367
3.371
8.0
7
3.461
3.453
3.457
8.0
NOTE: 10. Battery Detect Select 0 is the non–programmable operating
mode.
17
MC13110A/B MC13111A/B
DC CURRENT
Figure 4. Current versus Supply
Voltage Standby Mode, MCU
Clock Output – On at 2.048 MHz
Figure 3. Current versus Supply
Voltage Inactive Mode
30
25
20
15
10
5.0
0
2.7
Rx ICC, SUPPLY CURRENT (mA)
STD ICC, SUPPLY CURRENT (mA)
35
3.1
3.5
3.9
4.3
4.7
5.1
5.5
0.8
0.7
0.6
0.5
0.3
0.2
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VCC, SUPPLY VOLTAGE (V)
Figure 5. Current versus Supply
Voltage Receive Mode
Figure 6. Current versus Supply Voltage
Active Mode
8.0
4.9
7.9
4.8
4.7
4.6
MCU Clock Out On
4.5
4.4
4.3
MCU Clock Out Off
4.2
3.1
3.5
3.9
4.3
4.7
5.1
MCU Clock Out On
7.8
7.7
7.6
7.5
MCU Clock Out Off
7.4
7.3
7.2
7.1
7.0
2.7
5.5
3.1
3.5
3.9
4.3
4.7
5.1
VCC, SUPPLY VOLTAGE (V)
VCC, SUPPLY VOLTAGE (V)
Figure 7. Current versus
Temperature Normalized to 25°C
Figure 8. Current versus
Temperature Normalized to 25°C
DELTA CURRENT DRAIN (% FROM 25 C)
15
°
°
10
5.0
Standby
0
–5.0
–10
–40 –30 –20 –10
Inactive
0
10
20 30
40
50
TA, TEMPERATURE (°C)
18
MCU Clock Out Off
0.4
5.0
4.0
2.7
MCU Clock Out On
0.9
VCC, SUPPLY VOLTAGE (V)
4.1
DELTA CURRENT DRAIN (% FROM 25 C)
1.0
0.1
0
2.7
ACT I CC , SUPPLY CURRENT (mA)
I INACT IC, SUPPLY CURRENT (µA)
40
60 70
80
90
6.0
4.0
5.5
Receive
2.0
Active
0
–2.0
–4.0
–6.0
–8.0
–10
–12
–40 –30 –20 –10
0
10
20 30
40
50
60 70
80
90
TA, TEMPERATURE (°C)
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
DC CURRENT
Figure 10. Additional IP3
Supply Current Consumption versus
Temperature Normalized to 25°C
1.50
10
°
1.48
DELTA CURRENT DRAIN (mA)
DELTA CURRENT DRAIN (% FROM 25 C)
Figure 9. Additional Supply Current Consumption
versus Supply Voltage, IP3 = <1>
1.46
ÁÁÁÁÁ
ÁÁÁÁÁ
1.44
1.42
Receive/Active
1.40
1.38
1.36
1.34
1.32
1.30
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
5
ÁÁÁÁ
ÁÁÁÁ
0
Receive/Active
–5
–10
–15
–20
–40 –30 –20 –10
VCC, SUPPLY VOLTAGES (V)
Vs , NORMALIZED VB VOLTAGE (V)
STD I CC , SUPPLY CURRENT (mA)
650
No load
500
450
400
350
300
1.0
40
50
60 70
80
90
1.5075
10 pF load
700
550
20 30
Figure 12. VB Voltage versus Temperature
Normalized to 1.5 V at 25°C
800
600
10
TA, TEMPERATURE (°C)
Figure 11. Current Standby
Mode versus MCU Clock Output
750
0
MCU clock off
10
100
MCU CLK OUT DIVIDE VALUE
MOTOROLA ANALOG IC DEVICE DATA
1000
1.5050
1.5025
1.5000
1.4975
1.4950
1.4925
–20 –10
0
10
20
30
40
50
60
70
80
90
TA, TEMPERATURE (°C)
19
MC13110A/B MC13111A/B
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
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FIRST AND SECOND MIXER
Mixer Description
Figure 14. First Mixer Output Impedance
The 1st and 2nd mixers are similar in design. Both are
double balanced to suppress the LO and the input
frequencies to give only the sum and difference frequencies
at the mixer output. Typically the LO is suppressed better
than –50 dB for the first mixer and better than –40 dB for the
second mixer. The gain of the 1st mixer has a –3.0 dB corner
at approximately 13 MHz and is used at a 10.7 MHz IF. It has
an output impedance of 300 Ω and matches to a typical
10.7 MHz ceramic filter with a source and load impedance of
330 Ω. A series resistor may be used to raise the impedance
for use with crystal filters. They typically have an input
impedance much greater than 330 Ω.
First Mixer
Figures 17 through 20 show the first mixer transfer curves
for the voltage conversion gain, output level, and
intermodulation. Notice that there is approximately 10 dB
linearity improvement when the “IP3 Increase” bit is set to
<1>. The “IP3 Increase” bit is a programmable bit as shown in
the Serial Programmable Interface section under the Rx
Counter Latch Register. The IP3 = <1> option will increase
the supply current demand by 1.3 mA.
Figure 13. First Mixer Input and Output Impedance
Schematic
1st Mixer
Mix1 In
Mix1 Out
RPI
CPI
CPO
RPO
Unit
Output Impedance
B IP3 = <0> (Set Low)
304 Ω // 3.7 pF
B IP3 = <1> (Set High)
300 Ω // 4.0 pF
Figures 13, 14, and 16 represent the input and output
impedance for the first mixer. Notice that the input
single–ended and differential impedances are basically the
same. The output impedance as described in Figure 14 will
be used to match to a ceramic or crystal filter’s input
impedance. A typical ceramic filter input impedance is 330 Ω
while crystal filter input impedance is usually 1500 Ω. Exact
impedance matching to ceramic filters are not critical,
however, more attention needs to be given to the filter
characteristics of a crystal filter. Crystal filters are much
narrower. It is important to accurately match to these filters to
guaranty a reasonable response.
To find the IF bandwidth response of the first mixer refer to
Figure 22. The –3.0 dB bandwidth point is approximately 13
MHz. Figure 15 is a summary of the first mixer feedthrough
parameters.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
Figure 15. First Mixer Feedthrough Parameters
Parameter
(dBm)
1st LO Feedthrough @ Mix1 In1
–70.0
1st LO Feedthrough @ Mix1 Out
–55.5
RF Feedthrough @ Mix1 Out with –30 dBm
–61.0
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ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 16. First Mixer Input Impedance over Input Frequency
US Center Channels
France Center Channels
49 MHz
46 MHz
41 MHz
26 MHz
Single–Ended
1550 Ω // 3.7 pF
1560 Ω // 3.7 pF
1570 Ω // 3.8 pF
1650 Ω // 3.7 pF
Differential
1600 Ω // 1.8 pF
1610 Ω // 1.8 pF
1670 Ω // 1.8 pF
1710 Ω // 1.8 pF
U i
Unit
Note:
20
11. Single–Ended data is from measured results. Differential data is from simulated results.
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
FIRST MIXER
Figure 17. First Mixer Voltage Conversion
Gain, IP3_bit = 0
Figure 18. First Mixer Voltage Conversion
Gain, IP3_bit = 1
14
12
MXgain1, VOLTAGE
CONVERSION GAIN (dB)
MXgain1, VOLTAGE
CONVERSION GAIN (dB)
14
10
8.0
VCC = 3.6 V
IF = 10.695 MHz, 330 Ω
6.0
12
10
VCC = 3.6 V
IF = 10.695 MHz, 330 Ω
8.0
4.0
2.0
–40
–35
–30
–25
–20
–15
6.0
–40
–10
–35
Mix1 In, MIXER INPUT LEVEL (dBm)
Figure 19. First Mixer Output Level and
Intermodulation, IP3_bit = 0
Fundamental Level
–20
3rd Order
Intermodulation
–40
–60
VCC = 3.6 V
IF = 10.695 MHz, 330 Ω
–80
–35
–30
–25
–20
–15
Mix 1 Out, MIXER OUTPUT (dBm)
Mix 1 Out, MIXER OUTPUT (dBm)
–20
–15
–10
0
–20
Fundamental Level
–40
3rd Order
Intermodulation
–60
VCC = 3.6 V
IF = 10.695 MHz, 330 Ω
–80
–100
–40
–10
–35
–30
–25
–20
–15
Mix1 In, MIXER INPUT LEVEL (dBm)
Mix1 In, MIXER INPUT LEVEL (dBm)
Figure 21. First Mixer Compression versus
Supply Voltage
Figure 22. First IF Bandwidth
–10
15
–10
IP3_bit = 1
–12
MXgain1, VOLTAGE
CONVERSION GAIN (dB)
VO 1.0 dB Mix1, 1.0 dB
VOLTAGE COMPRESSION (dBm)
–25
Figure 20. First Mixer Output Level and
Intermodulation, IP3_bit = 1
0
–100
–40
–30
Mix1 In, MIXER INPUT LEVEL (dBm)
–14
IF = 10.695 MHz, 330 Ω
–16
–18
IP3_bit = 0
–20
–22
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
VCC Audio, AUDIO SUPPLY VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
5.1
10
5.0
0
–5.0
VCC = 3.6 V
RL = 330 Ω
LO = 36.075 MHz
–10
5.4
–15
1.0
10
100
f, IF FREQUENCY (MHz)
21
MC13110A/B MC13111A/B
Second Mixer
Figures 26 through 29 represents the second mixer
transfer characteristics for the voltage conversion gain,
output level, and intermodulation. There is a slight
improvement in gain when the “IP3 bit” is set to <1> for the
second mixer. (Note: This is the same programmable bit
discussed earlier in the section.)
Figure 23. Second Mixer Input and Output
Impedance Schematic
The 2nd mixer input impedance is typically 2.8 kΩ. It
requires an external 360 Ω parallel resistor for use with a
standard 330 Ω, 10.7 MHz ceramic filter. The second mixer
output impedance is 1.5 kΩ making it suitable to match
standard 455 kHz ceramic filters.
The IF bandwidth response of the second mixer is shown
in Figure 31. The –3.0 dB corner is 2.5 MHz. The feedthrough
parameters are summarized in Figure 25.
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ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
Figure 25. Second Mixer Feedthrough Parameters
Parameter
2nd Mixer
Mix2 In
Mix2 Out
RPI
CPI
CPO
RPO
(dBm)
2nd LO Feedthrough @ Mix2 Out
–42.9
IF Feedthrough @ Mix2 Out with –30 dBm
–61.7
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ÁÁÁÁÁÁ
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ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Figure 24. Second Mixer Input and Output
Impedances
Unit
Input Impedance
RPI // CPI
Output
Impedance
RPO // CPO
IP3 = <0> (Set Low)
2817 Ω // 3.6 pF
1493 Ω // 6.1 pF
IP3 = <1> (Set High)
2817 Ω // 3.6 pF
1435 Ω // 6.2 pF
22
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
SECOND MIXER
Figure 27. Second Mixer Conversion Gain,
IP3_bit = 1
Figure 26. Second Mixer Conversion Gain,
IP3_bit = 0
22
20
MX gain2, VOLTAGE
CONVERSION GAIN (dB)
MX gain2, VOLTAGE
CONVERSION GAIN (dB)
22
18
16
VCC = 3.6 V
IF = 455 kHz
RL = 1500 Ω
14
12
–40
–35
–30
–25
–20
–15
–35
–30
–25
–20
–15
Figure 28. Second Mixer Output Level and
Intermodulation, IP3_bit = 0
Figure 29. Second Mixer Output Level and
Intermodulation, IP3_bit = 1
–10
10
Fundamental Level
3rd Order
Intermodulation
–50
VCC = 3.6 V
IF = 455 kHz
RL = 1500 Ω
–70
–35
–30
–25
–20
–15
Mix 2 Out, MIXER OUTPUT (dBm)
Mix 2 Out, MIXER OUTPUT (dBm)
16
Mix2 In, MIXER INPUT LEVEL (dBm)
–90
–40
–10
Fundamental Level
3rd Order
Intermodulation
–30
–50
VCC = 3.6 V
IF = 455 kHz
RL = 1500 Ω
–70
–90
–40
–10
–35
–30
–25
–20
–15
Mix2 In, MIXER INPUT LEVEL (dBm)
Mix2 In, MIXER INPUT LEVEL (dBm)
Figure 30. Second Mixer Compression
versus Supply Voltage
Figure 31. Second IF Bandwidth
–10
–10
25
–12
IP3_bit = 1
MX gain2 , VOLTAGE
CONVERSION GAIN (dB)
VO 1.0 dB Mix2, 1.0 dB
VOLTAGE COMPRESSION (dBm)
VCC = 3.6 V
IF = 455 kHz
RL = 1500 Ω
Mix2 In, MIXER INPUT LEVEL (dBm)
–30
–14
IP3_bit = 0
–16
–18
IF = 455 kHz
RL = 1500 Ω
–20
–22
2.7
18
14
–40
–10
10
–10
20
3.0
3.3
3.6
3.9
4.2
4.5
4.8
VCC Audio, AUDIO SUPPLY VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
20
15
10
5.0
5.1
5.4
0
0.1
VCC = 3.6 V
RL = 1500 Ω
1.0
10
f, IF FREQUENCY (MHz)
23
MC13110A/B MC13111A/B
First Local Oscillator
The 1st LO is a multi–vibrator oscillator. The tank circuit is
composed of a parallel external capacitance and inductance,
internal programmable capacitor matrix, and internal
varactor. The local oscillator requires a voltage controlled
input to the internal varactor and an external loop filter driven
by on–board phase–lock control loop (PLL). The 1st LO
internal component values have a tolerance of ±15%. A
typical dc bias level on the LO Input and LO Output is 0.45
Vdc. The temperature coefficient of the varactor is
+0.08%/°C. The curve in Figure 33 is the varactor control
voltage range as it relates to varactor capacitance. It
represents the expected internal capacitance for a given
control voltage (V cap Ctrl) of the MC13110A/B and
MC13111A/B. Figure 32 shows a representative schematic of
the first LO function.
Figure 32. First Local Oscillator Schematic
Vcap Ctrl
Varactor
1st LO
24
Programmable
Internal
Varactor
Capacitor
LO1 In
Cext
LO1 Out
Lext
To select the proper Lext and Cext we can do the following
analysis. From Figure 34 it is observed that an inductor will
have a significant affect on first LO performance, especially
over frequency. The overall minimum Q required for first LO
to function as it relates to the LO frequency is also given in
Figure 34.
Choose an inductor value, say 470 nH. From Figure 34,
the minimum operating Q is approximately 25. From the
following equation:
Q Coil = Rp/X Coil
where: Rp = parallel equivalent impedance (Figure 35).
Cext can be determined as follows:
1
f
LO
2p L extC ext
+
Ǹ
where: Lext = external inductance, Cext = external
capacitance.
Figure 34 clearly indicates that for lower coil values, higher
quality factors (Q) are required for the first LO to function
properly. Also, lower LO frequencies need higher Q’s. In
Figure 35 the internal programmable capacitor selection
relative to the first LO frequency and the parallel impedance
is shown. This information will help the user to decide what
inductor (Lext) to choose for best performance in terms of Q.
Refer to the Auxiliary Register in the Serial Interface
Section for further discussion on LO programmability.
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
FIRST LOCAL OSCILLATOR
Figure 34. First LO Minimum Required Overall
Q Value versus Inductor Value
15
120
14
100
OVERALL MINIMUM Q VALUE
Vcap , CAPACITANCE (pF)
Figure 33. First LO Varicap Capacitance
versus Control Voltage
13
12
11
10
9.0
8.0
7.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
40
50 MHz
20
1000
VcapCtrl, CONTROL VOLTAGE (V)
LO INDUCTOR VALUE (nH)
Figure 35. Representative Parallel Impedance
versus Capacitor Select
Figure 36. Varicap Value at VCV = 1.0 V
Over Temperature
Vcap , CAPACITANCE (pF)
11
RP, REPRESENTATIVE PARALLEL
IMPEDANCE (k Ω)
30 MHz
40 MHz
50 MHz
0
2
1
5
6
7
4
3
8
10.6
10.2
9.8
9.4
9.8
9 10 11 12 13 14 15
0
25
55
70
85
TA, AMBIENT TEMPERATURE (°C)
Figure 37. Control Voltage versus
Channel Number, U.S. Handset Application
Figure 38. Control Voltage versus
Channel Number, U.S. Baseset Application
1.8
1.8
1.7 Cap 11
1.7
1.6
Cap 10
Cap 6
1.5
1.4
1.3
Cap 9
1.2
1.1
1.0
0.9
1
–20
C1–C15, CAPACITANCE SELECT
Vcap Ctrl, CONTROL VOLTAGE (V)
Vcap Ctrl, CONTROL VOLTAGE (V)
40 MHz
60
0
100
5.5
100
10
30 MHz
80
3
5
7
9
11
13
15
17
19
21
23
CH1–CH25, U.S. HANDSET CHANNEL APPLICATION
MOTOROLA ANALOG IC DEVICE DATA
25
1.6
Cap 8
1.5
Cap 3
1.4
1.3
Cap 4
1.2
1.1
1.0
0.9
0.8
1
3
5
7
9
11
13
15
17
19
21
23
25
CH1–CH25, U.S. BASESET CHANNEL APPLICATION
25
MC13110A/B MC13111A/B
Second Local Oscillator
The 2nd LO is a CMOS oscillator. It is used as the PLL
reference oscillator and local oscillator for the second
frequency conversion in the RF receiver. It is designed to
utilize an external parallel resonant crystal. See schematic in
Figure 39.
Figure 39. Second Local Oscillator Schematic
2nd LO
RPI
CPI
CPO
Gm
LO2 In
RPO
LO2 Out
Xtal
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
C1
C2
Figure 40. Second Local Oscillator
Input and Output Impedance
Input Impedance (RPI // CPI)
11.6 kΩ // 2.9 pF
Output Impedance (RPO // CPO)
9.6 kΩ // 2.7 pF
Figure 41 shows a typical gain/phase response of the
second local oscillator. Load capacitance (CL), equivalent
series resistance (ESR), and even supply voltage will have
and affect on the 2nd LO response as shown in Figures 45
and 46. Except for the standby mode open loop gain is fairly
constant as supply voltage increases from 2.5 V. This is due
to the regulated voltage of 2.5 V on PLL Vref. From the graphs
it can seen that optimum performance is achieved when C1
equals C2 (C1/C2 = 1).
Figure 46 represents the ESR versus crystal load
capacitance for the 2nd LO. This relationship was defined by
using a 6.0 dB minimum loop gain margin at 3.6 V. This is
considered the minimum gain margin to guarantee oscillator
start–up.
Oscillator start–up is also significantly affected by the
crystal load capacitance selection. In Figures 42 and 43 the
relationship between crystal load capacitance, supply
voltage, and external load capacitance ratio (C2/C1), can be
seen. The lower the load capacitance the better the
performance.
Given the desired crystal load capacitance, C1 and C2
can be determined from Figure 47. It is also interesting to
point out that current consumption increases when C1 ≠ C2,
as shown in Figure 44.
Be careful not to overdrive the crystal. This could cause a
noise problem. An external series resistor on the crystal
output can be added to reduce the drive level, if necessary.
SECOND LOCAL OSCILLATOR
15
90
10
67.5
5.0
0
10.24 MHz Crystal
CL = 10 pF
RS = 20 Ω
C1 = C2 = 15 pF
Gain
22.5
–5.0
0
–10
–22.5
–45
–15
Phase
–20
–25
10.235
10.24
f, FREQUENCY (MHz)
26
45
–67.5
–90
10.245
Figure 42. Start–Up Time versus Capacitor
Ratio, Inactive to Rx Mode
6.0
10.24 MHz Crystal
CL = 10 pF
RS = 20 Ω
5.0
START–UP TIME (ms)
Vgain2, LO VOLTAGE GAIN (dB)
Figure 41. Second LO Gain/Phase @ –10 dBm
4.0
VCC = 2.3 V
3.0
VCC = 2.7 V
2.0
VCC = 3.6 V
1.0
0
VCC = 5.0 V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
CAPACITOR RATIO (C2:C1)
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Figure 44. Second LO Current Consumption
versus Capacitor Ratio
Figure 43. Start–Up Time versus Capacitor
Ratio, Inactive to Rx Mode
30
10.24 MHz Crystal
CL = 24 pF
RS = 16 Ω
25
800
VCC = 2.3 V
20
I STD, STANDBY CURRENT ( µ A)
LO2, SECOND OSCILLATOR LEVEL (dBm)
START–UP TIME (ms)
SECOND LOCAL OSCILLATOR
VCC = 2.7 V
15
VCC = 3.6 V
10
5.0
0
VCC = 5.0 V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
500
400
11
Standby Current
with Clk_Out Off
300
200
10
10.24 MHz Crystal
CL = 10 pF
RS = 20 Ω
100
0
0
0.5
1.0
Oscillator Level
1.5
2.0
2.5
3.0
3.5
Figure 45. Maximum Open Loop Gain
versus Capacitor Ratio
Figure 46. Maximum Allowable
Equivalent Series Resistance (ESR)
versus Crystal Load Capacitance
ESR, EQUIVALENT RESISTANCE ( Ω )
AVOL, OPEN LOOP GAIN (dB)
12
CAPACITOR RATIO (C2:C1)
VCC = 2.7, 3.6, 5.0 V
12
VCC = 2.3 V
8.0
10.24 MHz Crystal
CL = 10 pF
RS = 20 Ω
Rx Mode
0
600
CAPACITOR RATIO (C2:C1)
16
0
700
4.0
20
4.0
13
Standby Current with Clk_Out
Running at 2.048 MHz
0.5
1.0
1.5
2.0
2.5
3.0
3.5
9.0
4.0
1000
100
10
10
4.0
Curve Valid for fosc in the Range of 10 MHz to 12 MHz
12
14
16
18
20
22
24
26
28
30
32
CRYSTAL LOAD CAPACITANCE (pF)
CAPACITOR RATIO (C2:C1)
Figure 47. Optimum Value for C1 and C2
versus Equivalent Required Parallel
Capacitance of the Crystal
OPTIMUM C1 AND C2 VALUE (pF)
70
60
C1 = C2
50
40
30
20
10
0
0
5.0
10
15
20
25
30
35
REQUIRED PARALLEL CRYSTAL LOAD CAPACITANCE (pF)
MOTOROLA ANALOG IC DEVICE DATA
27
MC13110A/B MC13111A/B
IF Limiter and Demodulator
The limiting IF amplifier typically has about 110 dB of gain;
the frequency response starts rolling off at 1.0 MHz.
Decoupling capacitors should be placed close to Pins 31 and
32 to ensure low noise and stable operation. The IF input
impedance is 1.5 kΩ. This is a suitable match to 455 kHz
ceramic filters.
Figure 48. IF Limiter Schematic
the IF bandpass Q is approximately 23; the loaded Q of the
quadrature tank is chosen slightly lower at 15.
Example:
Let the total external C = 180 pF. (Note: the capacitance is
the typical capacitance for the quad coil.) Since the external
capacitance is much greater than the internal device and
PCB parasitic capacitance, the parasitic capacitance may be
neglected.
Rewrite equation (2) and solve for L:
Limiter Stage
Lim In
Lim Out
RPI
CPI
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Figure 49. Limiter Input Impedance
Unit
Lim In
Input Impedance
(RPI)
Input Impedance
(CPI)
1538 Ω
15.7 pF
Figure 50. Quadrature Detector
Demodulator Schematic
C28
10 p
Lim Out1
Q Coil
Rext
22.1 k
Toko Q Coil
7MCS–8128Z
The quadrature detector is coupled to the IF with an
external capacitor between Pins 27 and 28. Thus, the
recovered signal level output is increased for a given
bandwidth by increasing the capacitor. The external
quadrature component may be either a LCR resonant circuit,
which may be adjustable, or a ceramic resonator which is
usually fixed tuned. (More on ceramic resonators later.)
The bandwidth performance of the detector is controlled
by the loaded Q of the LC tank circuit (Figure 50). The
following equation defines the components which set the
detector circuit’s bandwidth:
(1) RT = Q XL,
where RT is the equivalent shunt resistance across the LC
tank. XL is the reactance of the quadrature inductor at the IF
frequency (XL= 2π f L).
The 455 kHz IF center frequency is calculated by:
L = (0.159)2/(C fc2 )
L = 678 µH ; Thus, a standard value is chosen:
L = 680 µH (surface mount inductor)
The value of the total damping resistor to obtain the
required loaded Q of 15 can be calculated from equation (1):
RT = Q(2π f L)
RT = 15(2π)(0.455)(680) = 29.5 kΩ
The internal resistance, Rint at the quadrature tank Pin 27
is approximately 100 kΩ and is considered in determining the
external resistance, Rext which is calculated from:
Rext = ((RT)(Rint))/(Rint – RT)
Rext = 41.8 kΩ;Thus, choose a standard value:
Rext = 39 kΩ
In Figure 50, the Rext is chosen to be 22.1 kΩ. An
adjustable quadrature coil is selected. This tank circuit
represents one popular network used to match to the
455 kHz carrier frequency. The output of the detector is
represented as a “S–curve” as shown in Figure 52. The goal
is to tune the inductor in the area that is most linear on the
“S–curve” (minimum distortion) to optimize the performance
in terms of dc output level. The slope of the curve can also be
adjusted by choosing higher or lower values of Rext . This will
have an affect on the audio output level and bandwidth. As
Rext is increased the detector output slope will decrease.
The maximum audio output swing and distortion will be
reduced and the bandwidth increased. Of course, just the
opposite is true for smaller Rext.
A ceramic discriminator is recommended for the
quadrature circuit in applications where fixed tuning is
desired. The ceramic discriminator and a 5.6 kΩ resistor are
placed from Pin 27 to VCC . A 22 pF capacitor is placed from
Pin 28 to 27 to properly drive the discriminator. MuRata Erie
has designed a resonator for this part (CDBM455C48 for
USA & A/P regions and CDBM450C48 for Europe). This
resonator has been designed specifically for the
MC13110/111 family. Figure 51 shows the schematic used to
generate the “S–curve” and waveform shown in Figure 54
and 55.
(2) fc = [2π (L Cp)1/2] – 1
where L is the parallel tank inductor. Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a detector at 455
kHz and a specific loaded Q:
The loaded Q of the quadrature detector is chosen
somewhat less than the Q of the IF bandpass for margin. For
an IF frequency of 455 kHz and an IF bandpass of 20 kHz,
28
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
(CDBM455C48 US; CDBM450C48 France)
Figure 51. Ceramic Resonator Demodulator
Schematic with Murata CDBM450C48
C28
390 p
Lim Out1
Q Coil
Rext
2.7 k
Ceramic Resonator
Murata
CDBM450C34
The “S–curve” for the ceramic discriminator shown in
Figure 54 is centered around 450 kHz. It is for the French
application. The same resonator is also used for the US
application and is centered around 455 kHz. Clearly, the
“S–curves” for the resonator and quad coil have very similar
limiter outputs. As discussed previously, the slope of the
“S–curve” centered around the center frequency can be
controlled by the parallel resistor, Rext. Distortion, bandwidth,
and audio output level will be affected.
IF LIMITER AND DEMODULATION
Figure 52. S–Curve of Limiter
Discriminator with Quadrature Coil
Figure 53. Typical Limiter Output
Waveform with Quadrature Coil
800
Toko 7MCS–8128Z
1.8
AC VOLTAGE LEVEL (V)
Det Out, DC VOLTAGE (V)
2.2
1.4
1.0
0.6
0.2
425
435
445
455
465
475
1.0
400
200
0
485
Lim In, INPUT FREQUENCY (kHz)
t, TIME (ms)
Figure 54. S–Curve of Limiter
Discriminator with Ceramic Resonator
Figure 55. Typical Limiter Output
Waveform with Ceramic Resonator
1.7
800
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
440 442
f = 450 kHz
Vpptyp = 370 mV
Murata CDBM450C48
AC VOLTAGE LEVEL (V)
Det Out, DC VOLTAGE (V)
f = 455 kHz
Vpptyp = 344 mV
600
444
446
448
450
452
454
Lim In, INPUT FREQUENCY (kHz)
MOTOROLA ANALOG IC DEVICE DATA
456
458
460
600
1.0
400
200
0
t, TIME (ms)
29
MC13110A/B MC13111A/B
RSSI and Carrier Detect
The Received Signal Strength Indicator (RSSI) indicates
the strength of the IF level. The output is proportional to the
logarithm of the IF input signal magnitude. RSSI dynamic
range is typically 80 dB. A 187 kΩ resistor to ground is
provided internally to the IC. This internal resistor converts
the RSSI current to a voltage level at the “RSSI” pin. To
improve the RSSI accuracy over temperature an internal
compensated reference is used. Figure 56 shows the RSSI
versus RF input. The slope of the curve is 16.5 mV/dB.
The Carrier Detect Output (CD Out) is an open–collector
transistor output. An external pull–up resistor of 100 kΩ will
be required to bias this device. To form a carrier detect filter a
capacitor needs to be connected from the RSSI pin to
ground. The carrier detect threshold is programmable
through the MPU interface (see “Carrier Detect Threshold
Programming” in the serial interface section). The range can
be scaled by connecting additional external resistance from
the RSSI pin to ground in parallel with the capacitor. From
Figure 57, the affect of an external resistor at RSSI on the
carrier detect level can be noticed. Since there is hysteresis
in the carrier detect comparator, one trip level can be found
when the input signal is increased while the another one can
be found when the signal is decreased.
Figure 58 represents the RSSI ripple in relation to the RF
input for different filtering capacitors at RSSI. Clearly, the
higher the capacitor, the less the ripple. However, at low
carrier detect thresholds, the ripple might supersede the
hysteresis of the carrier detect. The carrier detect output may
appear to be unstable. Using a large capacitor will help to
stabilize the RSSI level, but RSSI charge time will be
affected. Figure 59 shows this relationship.
The user must decide on a compromise between the RSSI
ripple and RSSI start–up time. Choose a 0.01 µf capacitor as
a starting point. For low carrier detect threshold settings, a
0.047 µf capacitor is recommended.
RSSI AND CARRIER DETECT
Figure 57. Carrier Detect Threshold versus
External RSSI Resistor
1.6
0
1.4
–10
1.2
–20
MIX1 IN, RF INPUT (dBm)
RSSI OUTPUT (Vdc)
Figure 56. Typical RSSI Voltage
Level versus RF Input
1.0
0.8
0.6
0.4
0.2
–50
Decreasing Signal
–60
Increasing Signal
Mixer 1
Input
–70
Decreasing Signal
–100
–80
–60
–40
–20
–90
100
0
1000
Mix1 In, RF INPUT (dBm)
RRSSI, LOAD RESISTANCE (kΩ)
Figure 58. RSSI Ripple versus RF Input Level for
Different RSSI Capacitors
Figure 59. RSSI Charge Time
versus Capacitor Value
35
10 nF
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
–120
30
RSSI CHARGE TIME (ms)
11
10
RSSI RIPPLE (mVrms)
Increasing Signal
–40
–80
0
–120
22 nF
33 nF
47 nF
100 nF
25
20
15
10
5.0
–110
–100
–90
–80
Mix1 In, RF INPUT (dBm)
30
Limiter Input
–30
–70
–60
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
CRSSI, LOAD CAPACITANCE (µF)
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
RF System Performance
The sensitivity of the IC is typically 0.4 µVrms matched
(single ended or differential) with no preamp. To achieve
suitable system performance, a preamp and passive
duplexer may be used. In production final test, each section
of the IC is separately tested to guarantee its system
performance in the specific application. The preamp and
duplexer (differential, matched input) yields typically
–115 dBm @ 12 dB SINAD sensitivity performance under full
duplex operation. See Figure 45 and 48.
The duplexer is important to achieve full duplex operation
without significant “de–sensing” of the receiver by the
transmitter. The combination of the duplexer and preamp
circuit should attenuate the transmitter power to the receiver
by over 60 dB. This will improve the receiver system noise
figure without giving up too much IMD performance.
The duplexer may be a two piece unit offered by Shimida,
Sansui, or Toko products (designed for 25 channel CT–0
cordless phone). The duplexer frequency response at the
receiver port has a notch at the transmitter frequency band of
about 35 to 40 dB with a 2.0 to 3.0 dB insertion loss at the
receiver frequency band.
The preamp circuit utilizes a tuned transformer at the
output side of the amplifier. This transformer is designed to
bandpass filter at the receiver input frequency while rejecting
the transmitter frequency. The tuned preamp also improves
the noise performance by reducing the bandwidth of the pass
band and by reducing the second stage contribution of the
1st mixer. The preamp is biased such that it yields suitable
noise figure and gain.
The following matching networks have been used to
obtain 12 dB SINAD sensitivity numbers:
Figure 60. Matching Input Networks
The exact impedance looking into the RF In1 pin is
displayed in the following table along with the sensitivity
levels.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Figure 61. 12 dB SINAD Sensitivity Levels, US
Handset Application Channel 21
Sensitivity
(dBm)
Input
Impedance
(dBm)
Differential matched
–115.3
50.2 ± 0.1j
Single–ended match
–114.8
50.2 ± 0.1j
Single–ended 50 Ω
–100.1
50.2 ± 0.1j
The graphs in Figures 64 to 69 are performance results
based on Evaluation Board Schematic (Figure 138). This
evaluation board did not use a duplexer or preamp stage.
Figure 62 is a summary of the RF performance and Figure 63
contains the French RF Performance Summary.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 62. RF Performance Summary
for US Applications
MC13110A/MC13111A (fdev = 3.0 kHz, fmod = 1.0 kHz, 50 Ω)
Parameter
Handset
Baseset
Unit
–100.1
–100.1
dBm
Recovered Audio
132
132
mVrms
SINAD @ –30 dBm
41.8
41.4
dB
Sensitivity at
12 dB SINAD
THD @ –30 dBm
0.8
0.8
%
S/N @ –30 dBm
78.2
78.5
dB
AMRR @ –30 dBm
73.4
72.2
dB
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
RSSI range
Differential Match
360
Mix1 In1
RF In1
39
1:5
Mix1 In2
Single–ended Match
680
Mix1 In1
39
1:5
15
0.01
>80
dB
Figure 63. RF Performance Summary
for US French Applications
MC13110A/MC13111A (fdev = 1.5 kHz, fmod = 1.0 kHz, 50 Ω)
15
RF In1
>80
Mix1 In2
Parameter
Handset
Baseset
Unit
Sensitivity at
12 dB SINAD
–91
–90.8
dBm
Recovered Audio
89.8
90
mVrms
SINAD @ –30 dBm
42.1
44.3
dB
THD @ –30 dBm
0.8
0.8
%
S/N @ –30 dBm
75.7
75.1
dB
AMRR @ –30 dBm
56
84.7
dB
RSSI range
>80
>80
dB
Single–ended 50 Ω
Mix1 In1
RF In1
49.9 Ω
Mix1 In2
0.01
MOTOROLA ANALOG IC DEVICE DATA
31
MC13110A/B MC13111A/B
Figure 65. Typical Performance Parameters
Over U.S. Handset Channel Frequencies
Figure 64. Typical Receiver Performance
Parameters U.S. Handset Application Channel 21
80
1.5
70
1.1
40
0.9
SINAD
30
0.7
131
35
–20
129
1
3
5
9
11
13
15
17
19
21
23
128
25
138
137
75
136
70
135
AMRR
65
134
60
133
55
132
SA Out Level
131
50
SINAD
130
40
129
35
128
25
3
5
7
9
11
13
15
17
19
21
23
SA Out, SPEAKER AMPLIFIER OUTPUT (dBV)
Figure 67. Typical Receiver Performance for
US Handset Application Channel 21
45
–10
S+N+D
–30
–50
N+D
–70
AMR
–90
N
–110
–120
–100
U.S. BASESET CHANNEL NUMBER
–80
–60
–40
–20
0
Mix1 In1, FIRST MIXER INPUT (dBm)
Figure 69. 12 dB SINAD Sensitivity Over
US Baseset Application Channels
Figure 68. 12 dB SINAD Sensitivity Over
US Handset Application Channels
–96
–96
–97
–97
12 dB SINAD (dBm)
12 dB SINAD (dBm)
7
Figure 66. Typical Performance Parameters
Over U.S. Baseset Channel Frequencies
80
–98
–99
–100
–98
–99
–100
–101
–101
–102
130
U.S. HANDSET CHANNEL NUMBER
S/N
1
SINAD
45
Mix1 In, RF INPUT (dBm)
85
SINAD, S/N, AMRR (dB)
132
50
0.1
0
–40
133
SA Out Level
55
40
–60
135
134
60
0.3
–80
AMRR
65
10
–100
137
136
70
0.5
0
–120
S/N
75
20
SA Out, SPEAKER AMPLIFIER OUTPUT (mVrms)
SINAD, S/N (dB)
RSSI
50
RSSI OUTPUT (V)
1.3
SINAD, S/N, AMRR (dB)
S/N
60
138
85
1.7
80
1
5
9
13
17
US CHANNEL NUMBERS
32
21
25
–102
1
5
9
13
17
21
25
US CHANNEL NUMBERS
MOTOROLA ANALOG IC DEVICE DATA
SA Out, SPEAKER AMPLIFIER OUTPUT (mVrms)
RF SYSTEM PERFORMANCE
MC13110A/B MC13111A/B
Receive Audio Path
The Rx Audio signal path begins at “Rx Audio In” and goes
through the IC to “E Out”. The “Rx Audio In”, “Scr Out”, and
“E In” pins are all ac–coupled. This signal path consists of
filters; programmable Rx gain adjust, Rx mute, and volume
control, and finally the expander. The typical maximum
output voltage at “E Out” should be approximately 0 dBV @
THD = 5.0% .
Figures 71 to 73 represent the receive audio path filter
response. The filter response attenuation is very sharp above
3900 Hz, which is the cutoff frequency. Inband (audio),
out–of–band, and ripple characteristics are also shown in
these graphs.
The group delay (Figure 75) has a peak around 6.5 kHz.
This spike is formed by rapid change in the phase at the
frequency. In practice this does not cause a problem since
the signal is attenuated by at least 50 dB.
The output capability at “Scr Out” and “E Out” are shown in
Figures 76, 77, and 78. The results were obtained by
increasing the input level for 2.0% distortion at the outputs.
In Figure 70, noise data for the Rx audio path is shown.
At Scr Out, the noise level clearly rises when the scrambler is
enabled. However, assuming a nominal output level of –20
dBV (100 mVrms) at the 0 dB gain setting, the noise floor is
more than 56 dB below the audio signal. However, the noise
data at E Out and SA Out is much more improved.
Speaker Amp
The Speaker Amp is an inverting rail–to–rail operational
amplifier. The noninverting input is connected to the internal
VB reference. External resistors and capacitors are used to
set the gain and frequency response. The “SA In” input pin
must be ac–coupled. The typical output voltage at “SA Out” is
2.6 Vpp with a 130 Ω load. The speaker amp response is
shown in Figures 79 and 80.
Data Amp Comparator
The data amp comparator is an inverting hysteresis
comparator. Its open collector output has an internal 100 kΩ
pull–up resistor. A band pass filter is connected between the
“Det Out” pin and the “DA In” pin with component values as
shown in the Application Circuit schematic. The “DA In” input
signal needs to be ac–coupled, too.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 70. Rx Path Noise Data
Receive
Scrambler
Receive Gain
(dB)
Volume
(dB)
SCR_Out
(dBV)
E_Out
(dBV)
SA_Out
(dBV)
off/on
muted
muted
< –95
< –95
< –95
off
–9.0
–14
–92
< –95
< –95
off
0
0
–85
< –95
< –95
off
1.0
16
–76
< –95
< –95
on (MC13110A/B)
–9.0
–14
–85
< –95
< –95
on (MC13110A/B)
0
0
–77
< –95
< –95
on (MC13110A/B)
10
16
–66
< –95
< –95
MOTOROLA ANALOG IC DEVICE DATA
33
MC13110A/B MC13111A/B
Rx AUDIO
Figure 72. Rx Audio Inband Frequency Response
10
5.0
–10
–5.0
V gain, VOLTAGE GAIN (dB)
V gain, VOLTAGE GAIN (dB)
Figure 71. Rx Audio Wideband Frequency Response
–30
–50
–70
–110
–90
100
Rx Audio In
to Scr Out
Vin = –20 dBV
1000
–15
–25
–35
–45
10000
100000
Rx Audio In
to Scr Out
Vin = –20 dBV
–55
100
1000000
1000
10000
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 73. Rx Audio Ripple Response
Figure 74. Rx Audio Inband Phase Response
180
0.5
90
0.1
PHASE (°)
–0.1
–0.3
–0.5
100
45
0
–45
–90
Rx Audio In
to Scr Out
Vin = –20 dBV
1000
10000
Rx Audio In
–135 to Scr Out
Vin = –20 dBV
–180
100
1000
f, FREQUENCY (Hz)
Figure 75. Rx Audio Inband Group Delay
Figure 76. Rx Audio Expander Response
E out , OUTPUT VOLTAGE LEVEL (dBV)
GROUP DELAY (ms)
10
Rx Audio In
to Scr Out
Vin = –20 dBV
1.0
0.1
0
100
1000
f, FREQUENCY (Hz)
34
10000
f, FREQUENCY (Hz)
10000
5.0
28
–5.0
24
Expander Transfer
–15
20
–25
16
–35
12
–45
8.0
–55
DISTORTION (%)
V gain, VOLTAGE GAIN (dB)
135
0.3
4.0
Distortion
–65
–40
–35
–30
–25
–20
–15
–10
–5.0
0
0
Ein, INPUT VOLTAGE LEVEL (dBV)
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Rx AUDIO
Figure 77. Rx Audio Maximum Output Voltage
versus Gain Control Setting
Figure 78. Rx Audio Maximum Output Voltage
versus Volume Setting
1.4
–6.0
E out , OUTPUT VOLTAGE LEVEL (dBV)
Scr Out, OUTPUT VOLTAGE LEVEL (dBV)
–4.0
VCC = 3.6 V
THD = 2%
–8.0
–10
–12
–14
–16
–18
–20
–9.0
–7.0
–5.0
–3.0
–1.0
1.0
3.0
5.0
7.0
VCC = 3.6 V
THD = 2%
1.2
1.0
0.8
0.6
0.4
0.2
0
–14
9.0
Rx PROGRAMMABLE GAIN CONTROL SETTING
No Load
620 Ω
1.2
1.0
130 Ω
0.8
0.6
0.4
0.2
0
0
0.4
0.8
1.2
1.6
2.0
2.4
SA In, INPUT VOLTAGE LEVEL (dBV)
MOTOROLA ANALOG IC DEVICE DATA
2.8
–2.0
2.0
6.0
10
14
Figure 80. Rx Audio Speaker Amplifier Distortion
SA Out, OUTPUT VOLTAGE LEVEL(dBV)
SA Out, OUTPUT VOLTAGE LEVEL (dBV)
Figure 79. Rx Audio Speaker Amplifier Drive
1.6
–6.0
Rx PROGRAMMABLE VOLUME LEVEL SETTING
1.8
1.4
–10
3.2
25
130 Ω
20
15
620 Ω
No Load
10
5.0
0
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
SA In, INPUT VOLTAGE LEVEL (dBV)
35
MC13110A/B MC13111A/B
Transmit Audio Path
This portion of the audio path goes from “C In” to “Tx Out”.
The “C In” pin will be ac–coupled. The audio transmit signal
path includes automatic level control (ALC) (also referred to
as the Compressor), Tx mute, limiter, filters, and Tx gain
adjust. The ALC provides “soft” limiting to the output signal
swing as the input voltage slowly increases. With this
technique the gain is slightly lowered to help reduce distortion
of the audio signal. The limiter section provides hard limiting
due to rapidly changing signal levels, or transients. This is
accomplished by clipping the signal peaks. The ALC, Tx
mute, and limiter functions can be enabled or disabled via the
MPU serial interface. The Tx gain adjust can also be remotely
controlled to set different desired signal levels. The typical
maximum output voltage at “Tx Out” should be approximately
0 dBV @ THD = 5.0%.
Figures 82 to 86 represent the transmit audio path filter
response. The filter response attenuation, again, is very
definite above 3800 Hz. This is the filter cutoff frequency.
Inband (audio), wideband, and ripple characteristics are also
shown in these graphs.
The compressor transfer characteristics, shown in
Figure 87, has three different slopes. A typical compressor
slope can be found between –55 and –15 dBV. Here the
slope is 2.0. At an input level above –15 dBV the automatic
level control (ALC) function is activated and prevents hard
clipping of the output. The slope below –55 dBV input level is
one. This is where the compressor curve ends. Above 5.0
dBV the output actually begins to decrease and distort. This
is due to supply voltage limitations.
In Figure 88 the ALC function is off. Here the compressor
curve continues to increase above –15 dBV up to –4.0 dBV.
36
The limiter begins to clip the output signal at this level and
distortion is rapidly rising. Similarly, Figure 68 (ALC and
Limiter Off) shows to compressor transfer curve extending all
the way up to the maximum output. Finally, Figure 90 through
93 show the Tx Out signal versus several combinations of
ALC and Limiter selected.
Figure 81 is the noise data measured for the
MC13110A/13111A. This data is for 0 dB gain setting and –20
dBV (100 mVrms) audio levels.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 81. Tx Path Noise Data
Transmit
Scrambler
Transmit
Gain
(dB)
Amp_Out
(dBV)
Tx_Out
(dBV)
off/on
muted
muted
< –95
off
–9.0
< –95
–83
off
0
< –95
–74
off
10
< –95
–64
on (MC13110A)
–9.0
< –95
–82
on (MC13110A)
0
< –95
–73
on (MC13110A)
10
–< –95
–63
Mic Amp
Like the Speaker Amp the Mic Amp is also an inverting
rail–to–rail operational amplifier. The noninverting input
terminal is connected to the internal VB reference. External
resistors and capacitors are used to set the gain and
frequency response. The “Tx In” input is ac–coupled.
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Tx AUDIO
Figure 83. Tx Audio Inband Frequency Response
5.0
10
0
–10
–5.0
V gain, VOLTAGE GAIN (dB)
–20
–30
–40
–50
–60
–70
–80
C In to Tx Out
–90 Vin = –10 dBV
–100
100
1000
10000
100000
–15
–25
–35
–45
C In to Tx Out
Vin = –10 dBV
–55
100
1000000
1000
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 85. Tx Audio Inband Phase Response
180
0.2
135
0.1
90
0
PHASE (°)
V gain, VOLTAGE GAIN (dB)
Figure 84. Tx Audio Ripple Response
0.3
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
45
0
–45
–90
C In to Tx Out
Vin = –10 dBV
–0.7
100
C In to Tx Out
Vin = –10 dBV
–135
1000
10000
–180
100
1000
f, FREQUENCY (Hz)
Figure 86. Tx Audio Inband Group Delay
0
GROUP DELAY (ms)
–5.0
C In to Tx Out
Vin = –10 dBV
1.0
0.1
0
100
1000
f, FREQUENCY (Hz)
MOTOROLA ANALOG IC DEVICE DATA
10000
f, FREQUENCY (Hz)
Tx Out, OUTPUT VOLTAGE LEVEL (dBV)
10
10000
10000
Figure 87. Tx Audio Compressor Response
4.0
ALC On,
Limiter On or Off
–10
3.0
–15
Compressor
–20
2.0
–25
Distortion
–30
1.0
–35
–40
–60
–50
–40
–30
–20
–10
0
0
10
C In, INPUT VOLTAGE LEVEL (dBV)
37
DISTORTION (%)
V gain, VOLTAGE GAIN (dB)
Figure 82. Tx Audio Wideband Frequency Response
MC13110A/B MC13111A/B
4.0
ALC Off,
Limiter On
–5.0
–5.0
–10
3.0
–15
Compressor Transfer
2.0
–20
–25
1.0
–30
Distortion
–35
–40
–60
0
–50
–40
–30
–20
–10
0
0
10
4.0
ALC Off,
Limiter Off
–10
3.0
–15
Compressor Transfer
–20
2.0
–25
–30
1.0
Distortion
–35
–40
–60
–50
–40
–30
–20
–10
0
C In, INPUT VOLTAGE LEVEL (dBV)
C In, INPUT VOLTAGE LEVEL (dBV)
Figure 90. Tx Audio Maximum Output Voltage
versus Gain Control Setting
Figure 91. Tx Output Audio Response
0
VCC = 3.6 V
0
10
Limiter and ALC Off
A
–4.0
OUTPUT LEVEL (mV)
Tx Out, OUTPUT VOLTAGE LEVEL (dBV)
Figure 89. Tx Audio Compressor Response
DISTORTION (%)
Figure 88. Tx Audio Compressor Response
0
DISTORTION (%)
Tx Out, OUTPUT VOLTAGE LEVEL (dBV)
Tx Out, OUTPUT VOLTAGE LEVEL (dBV)
Tx AUDIO
B
–8.0
C
–12
–16
–20
–9.0
A: ALC Off, Limiter Off
B: ALC Off, Limiter On
C: ALC On, Limiter On or Off
–7.0
–5.0
–3.0
–1.0
1.0
3.0
5.0
7.0
200 mV/Div
500 µs/Div
9.0
Tx PROGRAMMABLE GAIN CONTROL SETTING
t, TIME (µs)
Figure 92. Tx Output Audio Response
Figure 93. Tx Audio Output Response
OUTPUT LEVEL (mV)
Limiter On and ALC On
OUTPUT LEVEL (mV)
Limiter On and ALC Off
200 mV/Div
500 µs/Div
200 mV/Div
500 µs/Div
t, TIME (µs)
38
t, TIME (µs)
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
PLL SYNTHESIZER SECTION
microprocessor. The maximum input and output levels for
these pins is VCC. Figure 94 shows a simplified schematic of
the I/O pins.
PLL Frequency Synthesizer General Description
Figure 95 shows a simplified block diagram of the
programmable universal dual phase locked loop (PLL)
designed into the MC13110A/B and MC13111A/B IC. This
dual PLL is fully programmable through the MCU serial
interface and supports most country channel frequencies
including USA (25 ch), Spain, Australia, Korea, New Zealand,
U.K., Netherlands, France, and China (see channel frequency
tables in AN1575, “Worldwide Cordless Telephone
Frequencies”).
The 2nd local oscillator and reference divider provide the
reference frequency signal for the Rx and Tx PLL loops. The
programmed divider value for the reference divider is
selected based on the crystal frequency and the desired Rx
and Tx reference frequency values. For the U.K., additional
divide by 25 and divide by 4 blocks are provided to allow for
generation of the 1.0 kHz and 6.2 kHz reference frequencies.
The 14–bit Rx counter is programmed for the desired first
local oscillator frequency. The 14–bit T x counter is
programmed for the desired transmit channel frequency. All
counters power–up to a set default state for USA channel #21
using a 10.24 MHz reference frequency crystal (see power–up
default latch register state in the Serial Programmable
Interface section).
To extend the sensitivity of the 1st LO for U.S. 25 channel
operation, internal fixed capacitors can be connected to the
tank circuit through microprocessor programmable control.
When designing the external PLL loop filters, it is
recommended that the Tx and Rx phase detectors be
considered as current drive type outputs. The loop filter
control voltage must be 0.5 V away from either the positive or
negative supply rail.
Figure 94. PLL I/O Pin Simplified Schematics
PLL Vref
(2.5 V)
I/O
VCC Audio
(2.7 to 5.5 V)
VCC Audio
(2.7 to 5.5 V)
PLL Vref
(2.5 V)
In
Out
2.0 µA
LO2 In, LO2 Out,
Rx PD, Tx PD and
Tx VCO Pins
Data, Clk and EN Pins
Clk Out Pin
PLL Loop Control Voltage Range
The control voltage for the Tx and Rx loop filters is set by
the phase detector outputs which drive the external loop
filters. The phase detectors are best considered to have a
current mode type output. The output can have three states;
ground, high impedance, and positive supply, which in this
case is the voltage at “PLL Vref”. When the loop is locked the
phase detector outputs are at high impedance. An exception
of this state is for narrow current pulses, referenced to either
the positive or negative supply rails. If the loop voltages get
within 0.5 V of either rail the linear current output starts to
degrade. The phase detector current source was not
designed to operate at the supply rails. VCO tuning range will
also be limited by this voltage range
The maximum loop control voltage is the “PLL Vref” voltage
which is 2.5 V. If a higher loop control voltage range is
desired, the “PLL Vref” pin can be pulled to a higher voltage.
It can be tied directly to the VCC voltage (with suitable filter
capacitors connected close to each pin). When this is done,
the internal voltage regulator is automatically disabled. This
is commonly used in the telephone base set where an
external 5.0 V regulated voltage is available. It is important to
remember, that if “PLL Vref” is tied to VCC and VCC is not a
regulated voltage, the PLL loop parameters and lock–up time
will vary with supply voltage variation. The phase detector
gain constant, Kpd, will not be affected if the “PLL Vref” is tied
to VCC.
PLL I/O Pin Configurations
The 2nd LO, Rx and Tx PLL’s, and MPU serial interface are
powered by the internal voltage regulator at the “PLL Vref” pin.
The “PLL Vref” pin is the output of a voltage regulator which is
powered from the “VCC Audio” power supply pin. It is regulated
by an internal bandgap voltage reference. Therefore, the
maximum input and output levels for most of the PLL I/O pins
(LO2 In, LO2 Out, Rx PD, Tx PD, Tx VCO) is the regulated
voltage at the “PLL Vref” pin. The ESD protection diodes on
these pins are also connected to “PLL Vref”.
Internal level shift buffers are provided for the pins (Data,
Clk, EN, Clk Out) which connect directly to the
Figure 95. Dual PLL Simplified Block Diagram
Tx VCO
14–b Programmable
Tx Counter
U.K. Base
Tx Ref
LO2 In
1
LO2 Out
2
÷ 25
12–b
Programmable
÷4
Reference
÷1
Counter
U.K. Handset
U.K. Base
Rx Ref
U.K. Handset
14–b Programmable
Rx Counter
1st LO
8
Tx Phase
Detector
(Current
Output)
Tx PD
6
Rx PD
Rx Phase
Detector
(Current
Output)
Programmable
Internal Capacitor
4
Vcap Ctrl
Tx
VCO
LP Loop Filter
LP Loop Filter
42
LO1 In
40
LO1 Out
41
MOTOROLA ANALOG IC DEVICE DATA
39
MC13110A/B MC13111A/B
Loop Filter Characteristics
Lets consider the following discussion on loop filters. The
fundamental loop characteristics, such as capture range,
loop bandwidth, lock–up time, and transient response are
controlled externally by loop filtering.
Figure 96 is the general model for a Phase Lock Loop
(PLL).
second order slope (–40 dB/dec) creating a phase of –180
degrees at the lower and higher frequencies. The filter
characteristic needs to be determined such that it is adding a
pole and a zero around the 0 dB point to guarantee sufficient
phase margin in this design (Qp in Figure 98).
Figure 98. Bode Plot of Gain and
Phase in Open Loop Condition
0
Figure 96. PLL Model
Phase
Detector (Kpd)
Filter
(Kf)
VCO
(Ko)
Open Loop Gain
fo
Divider
(Kn)
Where:
Kpd = Phase Detector Gain Constant
Kf = Loop Filter Transfer Function
Ko = VCO Gain Constant
Kn = Divide Ratio (1/N)
fi = Input frequency
fo = Output frequency
fo/N = Feedback frequency divided by N
From control theory the loop transfer function can be
represented as follows:
A, Open Loop Gain
fi
0
–90
Phase
Qp
wp
A
Figure 97. Loop Filter
with Additional Integrating Element
From
Phase
Detector
To VCO
R2
C1
C2
From Figure 97, capacitor C1 forms an additional
integrator, providing the type 2 response, and filters the
discrete current steps from the phase detector output. The
function of the additional components R2 and C2 is to create
a pole and a zero (together with C1) around the 0 dB point of
the open loop gain. This will create sufficient phase margin
for stable loop operation.
In Figure 98, the open loop gain and the phase is
displayed in the form of a Bode plot. Since there are two
integrating functions in the loop, originating from the loopfilter
and the VCO gain, the open loop gain response follows a
40
) jw(R2C2))
jw 1 ) jw R2C1C2
C1)C2
ǒ ǒ ǒ Ǔ ǓǓ
+
openloop
K
jwK n
A = Kpd Kf Ko Kn Open loop gain
Kpd can be either expressed as being 2.5 V/4.0 π or
1.0 mA/2.0 π for the CT–0 circuits. More details about
performance of different type PLL loops, refer to Motorola
application note AN535.
The loop filter can take the form of a simple low pass filter.
A current output, type 2 filter will be used in this discussion
since it has the advantage of improved step response,
velocity, and acceleration.
The type 2 low pass filter discussed here is represented as
follows:
–180
The open loop gain including the filter response can be
expressed as:
K (1
pd o
(1)
The two time constants creating the pole and the zero in
the Bode plot can now be defined as:
R2C1C2
+ C1
) C2
T1
T2
+ R2C2
ǒ Ǔǒ
By substituting equation (2) into (1), it follows:
A
+
openloop
K
K T1
pd o
w 2C1K nT2
1
1
(2)
Ǔ
) jwT2
) jwT1
(3)
The phase margin (phase + 180) is thus determined by:
Qp
+ arctan(wT2)–arctan(wT1)
(4)
At w=wp, the derivative of the phase margin may be set to
zero in order to assure maximum phase margin occurs at wp
(see also Figure 98). This provides an expression for wp:
dQ p
dw
+0+
T2
–
T1
) (wT2) 1 ) (wT1)
w + wp + 1
ǸT2T1
2
1
2
(5)
(6)
Or rewritten:
T1
+ w 12T2
p
(7)
MOTOROLA ANALOG IC DEVICE DATA
ǒ Ǔ
MC13110A/B MC13111A/B
By substituting into equation (4), solve for T2:
+
Qp
2
) p4
(8)
wp
By choosing a value for wp and Qp, T1 and T2 can be
calculated. The choice of Qp determines the stability of the
loop. In general, choosing a phase margin of 45 degrees is a
good choice to start calculations. Choosing lower phase
margins will provide somewhat faster lock–times, but also
generate higher overshoots on the control line to the VCO.
This will present a less stable system. Larger values of phase
margin provide a more stable system, but also increase
lock–times. The practical range for phase margin is 30
degrees up to 70 degrees.
The selection of wp is strongly related to the desired
lock–time. Since it is quite complicated to accurately
calculate lock time, a good first order approach is:
T_lock
[ w3p
+
ǒ Ǔ
K
K T1
pd o
w 2K nT2
f
(11)
(12)
+ 2p Ǹ1LC
(13)
T
In which L represents the external inductor value and CT
represents the total capacitance (including internal
capacitance) in parallel with the inductor. The VCO gain can
be easily calculated via the internal varicap transfer curve
shown below.
Figure 99. Varicap Capacitance
versus Control Voltage
15
(9)
14
Equation (9) only provides an order of magnitude for lock
time. It does not clearly define what the exact frequency
difference is from the desired frequency and it does not show
the effect of phase margin. It assumes, however, that the
phase detector steps up to the desired control voltage
without hesitation. In practice, such step response approach
is not really valid. The two input frequencies are not locked.
Their phase maybe momentarily zero and force the phase
detector into a high impedance mode. Hence, the lock times
may be found to be somewhat higher.
In general, wp should be chosen far below the reference
frequency in order for the filter to provide sufficient
attenuation at that frequency. In some applications, the
reference frequency might represent the spacing between
channels. Any feedthrough to the VCO that shows up as a
spur might affect adjacent channel rejection. In theory, with
the loop in lock, there is no signal coming from the phase
detector. But in practice leakage currents will be supplied to
both the VCO and the phase detector. The external
capacitors may show some leakage, too. Hence, the lower
wp, the better the reference frequency is filtered, but the
longer it takes for the loop to lock.
As shown in Figure 98, the open loop gain at wp is 1 (or
0 dB), and thus the absolute value of the complex open loop
gain as shown in equation (3) solves C1:
C1
ǒ Ǔ
*1
+ C1 T2
T1
R2 + T2
C2
The VCO gain is dependent on the selection of the
external inductor and the frequency required. The free
running frequency of the VCO is determined by:
Ǹ
ǒ) Ǔ
ǒ) Ǔ
1
1
2
w pT2
2
w pT1
With C1 known, and equation (2) solve C2 and R2:
MOTOROLA ANALOG IC DEVICE DATA
(10)
Vcap , CAPACITANCE (pF)
T2
tan
C2
13
12
11
10
9.0
8.0
7.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
As can be derived from Figure 99, the varicap capacitance
changes 1.3 pF over the voltage range from 1.0 V to 2.0 V:
DCvar + 1.3VpF
(14)
Combining (13) with (14) the VCO gain can be determined
by:
Ko
+ jw1
ȡȧ
ȥȧ Ǹ ǒ
Ȣ
2p
L C
1
T
) DCvar
2
Ǔ
*
2p
Ǹǒ
L C
1
T
) DCvar
2
ȣȧ
ǓȦȧȤ
(15)
Although the basic loopfilter previously described provides
adequate performance for most applications, an extra pole
may be added for additional reference frequency filtering.
Given that the channel spacing in a CT–0 telephone set is
based on the reference frequency, and any feedthrough to
41
MC13110A/B MC13111A/B
the first LO may effect parameters like adjacent channel
rejection and intermodulation. Figure 100 shows a loopfilter
architecture incorporating an additional pole.
Figure 100. Loop Filter
with Additional Integrating Element
From
Phase
Detector
To VCO
R3
R2
C1
C3
C2
For the additional pole formed by R3 and C3 to be efficient,
the cut–off frequency must be much lower than the reference
frequency. However, it must also be higher than wp in order
not to compromise phase margin too much. The following
equations were derived in a similar manner as for the basic
filter previously described.
Similarly, it can be shown:
A
+–
openloop
K
ǒ
K nw 2 (C1
In which:
) C2 )
T1
) (C1C2)T3
+ C1(C1))C2C2))T2
C3 * w 2C1T2T3
T2
+ R2C2
1 ) jwT2
)
Ǔ 1 ) jwT1
K
pd o
(16)
C3) – w 2C1C2C3R2R3
(17)
(18)
T3
+ R3C3
(19)
From T1 it can be derived that:
C2
ǒ
Ǔ
+ (T1 ) T2)C3 * C1 T2T3 )* T3T1 * T1 ) w T1T2T3
Ǹ
2
(20)
In analogy with (10), by forcing the loopgain to 1 (0 dB) at
wp, we obtain:
C1(T1
) T2) ) C2T3 ) C3T2 +
ǒ Ǔ
K
K
pd o
K nw p 2
Solving for C1:
(T2
C1
1
1
* T1)T3C3 * (T3 * T1)T2C3 ) (T3 * T1)
+
(T3
* T1)T2 ) (T3 * T1)T3 *
ǒ
T2
ǒ Ǔ
)ǒ Ǔ
)
2
w pT2
2
w pT1
ǒ Ǔ
K
K T1
pd o
w p 2K n
Ǹ
(21)
ǒ Ǔ
ǒ Ǔ
) wpT2
2
1) w pT1
1
Ǔ
) T3 * T1 ) wp2T1T2T3 T3
2
(22)
By selecting wp via (9), the additional time constant
expressed as T3, can be set to:
T3
42
+ Kw1 p
(23)
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
The K–factor shown determines how far the additional
pole frequency will be separated from wp. Selecting too small
of a K–factor, the equations may provide negative
capacitance or resistor values. Too large of a K–factor may
not provide the maximum attenuation.
By selecting R3 to be 100 kΩ, C3 becomes known and C1
and C2 can be solved from the equations. By using equations
(8) and (7), time constants T2 and T1 can be derived by
selecting a phase margin. Finally, R2 follows from T2 and C2.
The following pages, the loopfilter components are
determined for both handset and baseset the US application
based on the equations described. Choose K to be
approximately five times wp (5.0wp).
In an application, wp is chosen to be 20 times less than the
reference frequency of 5.0 kHz and the phase margin has
been set to 45 degrees. This provides a lock time according
to (9) of about 2.0 ms (order of magnitude). With the adjacent
channels spaced at least 15 kHz away, reference
feedthrough at wp will not be directly disastrous but still, the
additional pole may be added in the loopfilter design for
added safety.
In an application, wp is chosen to be 20 times less than the
reference frequency of 5.0 kHz and the phase margin has
been set to 45 degrees. This provides a lock time according
to (9) of about 2.0 ms (order of magnitude). With the adjacent
channels spaced at least 15 kHz away, reference
feedthrough at wp will not be directly disastrous but still, the
additional pole may be added in the loopfilter design for
added safety.
Figure 101. Open Loop Response Handset US
with Selected Values
Figure 102. Open Loop Response Baseset US
with Selected Values
100 k
From
Phase
Detector
100 k
From
Phase
Detector
To VCO
To VCO
22 k
6800
.068
18 k
1000
8200
80
80
80
60
0
40
Phase
Margin
–40
20
1000
10000
100000
0
1000000
40
60
0
40
Phase
Margin
–40
–80
100
20
1000
10000
f, FREQUENCY (Hz)
100000
f, FREQUENCY (Hz)
Figure 103. Handset US
Figure 104. Baseset US
Conditions
L = 470 uH
RF = 46.77 MHz
VCO center = 36.075 MHz
Fref = 5.0 kHz
Qp = 45 degrees
wp = wref / 20 radians
Conditions
L = 470 uH
RF = 49.83 MHz
VCO center = 39.135 MHz
Fref = 5.0 kHz
Qp = 45 degrees
wp = wref / 20 radians
Results
Equations
Results
Equations
Kpd = 159.2 uA/rad
KVCO = 4.54 Mrad/V
T2 = 1540 µs
T1 = 264 µs
T3 = 91 µs
(14), (15)
(8)
(7)
with K = 7
C1 = 9.1 nF
C2 = 83.5 nF
R2 = 18.4 kΩ
R3 = 100 kΩ
C3 = 909.5 pF
(21)
(20)
(18)
choose:
(19)
Kpd = 159.2 uA/rad
KVCO = 3.56 Mrad/V
T2 = 1540 µs
T1 = 264 µs
T3 = 91 µs
(14), (15)
(8)
(7)
with K = 7
C1 = 7.6 nF
C2 = 70.9 nF
R2 = 21.7 kΩ
R3 = 100 kΩ
C3 = 909.5 pF
(21)
(20)
(18)
choose:
(19)
0
1000000
Select
C1 = 6.8 nF
C2 = 68 nF
R2 = 22 kΩ
R3 = 100 kΩ
C3 = 1 nf
MOTOROLA ANALOG IC DEVICE DATA
Select
C1 = 8.2 nF
C2 = 82 nF
R2 = 18 kΩ
R3 = 100 kΩ
C3 = 1 nf
43
Phase Margin (degrees)
40
Open Loop Gain (dB)
Loop
Gain
Phase Margin (degrees)
Open Loop Gain (dB)
1000
80
Loop
Gain
–80
100
.082
MC13110A/B MC13111A/B
SERIAL PROGRAMMABLE INTERFACE
Microprocessor Serial Interface
The Data, Clock, and Enable (“Data”, “Clk”, and “EN”
respectively) pins provide a MPU serial interface for
programming the reference counters, the transmit and
receive channel divide counters, the switched capacitor filter
clock counter, and various other control functions. The “Data”
and “Clk” pins are used to load data into the MC13111A/B
shift register (Figure 109). Figure 105 shows the timing
required on the “Data” and “Clk” pins. Data is clocked into the
shift register on positive clock transitions.
Figure 105. Data and Clock Timing Requirement
tr
The state of the “EN” pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure 107 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when “EN” is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the “EN” high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first. A minimum of four “Clk” rising edge
transition must occur before a negative “EN” transition will
latch data or an address into a register.
tf
Figure 107. Microprocessor Interface
Programming Mode Diagrams
90%
10%
Data,
Clk, EN
Data
MSB
8–Bit Address
LSB
Latch
50%
EN
Address Register Programming Mode
Data
tsuDC
Data
th
MSB
16–Bit Data
LSB
Latch
EN
50%
Data Register Programming Mode
Clk
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the “EN” pin.
This is done in two steps. First, an 8–bit address is loaded
into the shift register and latched into the 8–bit address latch
register. Then, up to 16–bits of data is loaded into the shift
register and latched into the data latch register. It is specified
by the address that was previously loaded. Figure 106 shows
the timing required on the EN pin. Latching occurs on the
negative EN transition.
The MPU serial interface is fully operational within 100 µs
after the power supply has reached its minimum level during
power–up (see Figure 108). The MPU Interface shift
registers and data latches are operational in all four power
saving modes; Inactive, Standby, Rx, and Active Modes.
Data can be loaded into the shift registers and latched into
the latch registers in any of the operating modes.
Figure 108. Microprocessor Serial
Interface Power–Up Delay
Figure 106. Enable Timing Requirement
50%
Clk
tsuEC
44
50%
Last
Clock
First
Clock
2.7 V
VCC
tpuMPU
trec
50%
EN
Latch
50%
Previous Data Latched
Data,
Clk, EN
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Data Registers
Figure 109 shows the data latch registers and addresses
which are used to select each of each registers. Latch bits to
the left (MSB) are loaded into the shift register first. The LSB
bit must always be the last bit loaded into the shift register.
Bits proceeding the register must be “0’s” as shown.
Rx mode with all mutes active. The reference counter is set to
generate a 5.0 kHz reference frequency from a 10.24 MHz
crystal. The switched capacitor filter clock counter is set
properly for operation with a 10.24 MHz crystal. The Tx and Rx
counter registers are set for USA handset channel frequency,
number 21 (Channel 6 for previous FCC 10 Channel Band).
Figure 110 shows the initial power–up states for all latch
registers.
Power–Up Defaults for Data Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The device is initially placed in the
Figure 109. Microprocessor Interface Data Latch Registers
Latch Address
0
0
MSB
14–b Tx Counter
LSB
1. (00000001)
LSB
2. (00000010)
LSB
3. (00000011)
Rx
Mute
SP
Mute
4. (00000100)
5–b CD Threshold Control
LSB
5. (00000101)
Tx Counter Latch
0
IP3
Increase
MSB
14–b Rx Counter
Rx Counter Latch
0
0
U.K.
HS
Select
U.K.
BS
Select
MSB
12–b Reference Counter
Reference Counter Latch
0
ALC
Disable
MPU
Clk 2
Limiter
Disable
Clk
Disable
MPU
Clk 0
MPU
Clk 1
MSB
4–b Vol Control
LSB
Stdby
Mode
LSB
MSB
Rx
Mode
Tx
Mute
Mode Control Latch
0
5–b Tx Gain Control
MSB
LSB
5–b Rx Gain Control
MSB
Gain Control Latch
0
3–b Low Battery
Detect Threshold Select
MSB
4–b Voltage
Reference Adjust
LSB
Tx Sbl
Bypass
Rx Sbl
Bypass
MSB
6–b Switched
Capacitor Filter
Clock Counter Latch
LSB
6. (00000110)
MSB
6–b Switched
Capacitor Filter
Clock Counter Latch
LSB
6. (00000110)
SCF Clock Dividers Latch (MC13110A/B only)
0
3–b Low Battery
Detect Threshold Select
MSB
4–b Voltage
Reference Adjust
LSB
0
0
SCF Clock Dividers Latch (MC13111A/B only)
0
0
0
0
0
0
0
0
0
3–b Test Mode
4–b 1st LO Capacitor Selection
7. (00000111)
Auxillary Latch
MOTOROLA ANALOG IC DEVICE DATA
45
MC13110A/B MC13111A/B
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Figure 110. Latch Register Power–Up Defaults
MSB
LSB
R i
Register
C
Count
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Tx
9966
–
–
1
0
0
1
1
0
1
1
1
0
1
1
1
0
Rx
7215
–
–
0
1
1
1
0
0
0
0
1
0
1
1
1
1
Ref
2048
–
–
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Mode
N/A
–
0
0
0
0
1
1
0
1
1
1
0
1
1
1
1
Gain
N/A
–
0
1
1
1
1
0
1
1
1
1
1
0
1
0
0
SCF
(MC13110A/B)
31
–
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
SCF
(MC13111A/B)
31
–
0
0
0
0
1
1
1
–
–
0
1
1
1
1
1
Aux
N/A
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
NOTE: 12. Bits 6 and 7 in the SCF latch register are ”Don’t Cares” for the MC13111A/B since this part does not have a scrambler.
Tx and Rx Counter Registers
The 14 bit Tx and Rx counter registers are used to select
the transmit and receive channel frequencies. In the Rx
counter there is an “IP3 Increase” bit that allows the ability to
trade off increased receiver mixer performance versus
reduced power consumption. With “IP3 increase” = <1>,
there is about a 10 dB improvement in 1 dB compression and
3rd order intercept for both the 1st and 2nd mixers. However,
there is also an increase in power supply current of 1.3 mA.
The power–up default for the MC13111A/B is “IP3 Increase”
= <0>. The register bits are shown in Figure 111.
Reference Counter Register
Reference Counter
Figure 113 shows how the reference frequencies for the
Rx and Tx loops are generated. All countries except the U.K.
require that the Tx and Rx reference frequencies be identical.
In this case, set “U.K. Base Select” and “U.K. Handset
Select” bits to “0”. Then the fixed divider is set to “1” and the
Tx and Rx reference frequencies will be equal to the crystal
oscillator frequency divided by the programmable reference
counter value.
The U.K. is a special case which requires a different
reference frequency value for Tx and Rx. For U.K. base
operation, set “U.K. Base Select” to “1”. For U.K. handset
operation, set “U.K. Handset Select” to “1”. The Netherlands
is also a special case. A 2.5 kHz reference frequency is used
for both the Tx and Rx reference and the total divider value
required is 4096. This is larger than the maximum divide
value available from the 12–bit reference divider (4095). In
this case, set “U.K. Base Select” to “1” and set “U.K. Handset
Select” to “1”. This will give a fixed divide by 4 for both the Tx
and Rx reference. Then set the reference divider to 1024 to
get a total divider of 4096.
Figure 111. Rx and Tx Counter Register Latch Bits
0
0
MSB
14–b Tx Counter
LSB
Tx Counter Latch
0
IP3
Increase
MSB
14–b Rx Counter
LSB
Rx Counter Latch
Figure 112. Reference Counter Register
0
46
0
U.K.
Handset
Select
U.K.
Base
Select
MSB
12–b Ref Counter
LSB
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Figure 113. Reference Counter Register Programming Mode
U.K. Base
Tx Reference Frequency
LO2 In
÷ 25
12–b
Programmable
Reference ÷ 4.0
Counter
÷1.0
LO2
LO2 Out
U.K. Handset
U.K. Base
Rx Reference Frequency
U.K. Handset
U.K. Handset
Select
U.K. Base
Select
Tx Divider
Value
Rx Divider
Value
Application
0
0
1
1
0
1
0
1
1
25
4
4
1
4
25
4
All but U.K. and Netherlands
U.K. Base Set
U.K. Hand Set
Netherlands Base and Hand Set
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ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
Figure 114. Reference Frequency and Divider Values
MC13110A/B
MC13111A/B
Crystal
Frequency
Reference
Divider
Value
U.K. Base/
Handset
Divider
Reference
Frequency
SC Filter
Clock
Divider
SC Filter
Clock
Frequency
Scrambler
Modulation
Divider
Scrambler
Modulation
Frequency
10.24 MHz
2048
1
5.0 kHz
31
165.16 kHz
40
4.129 kHz
10.24 MHz
1024
4
5.0 kHz
31
165.16 kHz
40
4.129 kHz
11.15 MHz
2230
1
5.0 kHz
34
163.97 kHz
40
4.099 kHz
12.00 MHz
2400
1
5.0 kHz
36
166.67 kHz
40
4.167 kHz
11.15 MHz
1784
1
6.25 kHz
34
163.97 kHz
40
4.099 kHz
11.15 MHz
446
4
6.25 kHz
34
163.97 kHz
40
4.099 kHz
11.15 MHz
446
25
1.0 kHz
34
163.97 kHz
40
4.099 kHz
Figure 115. Mode Control Register
0
ALC
Disable
MPU
Clk 2
Limiter
Disable
Clk
Disable
MPU
Clk 1
MPU
Clk 0
Reference Frequency Selection
The “LO2 In” and “LO2 Out” pins form a reference oscillator
when connected to an external parallel–resonant crystal. The
reference oscillator is also the second local oscillator for the
RF Receiver. Figure 114 shows the relationship between
different crystal frequencies and reference frequencies for
cordless phone applications in various countries. “LO2 In”
may also serve as an input for an externally generated
reference signal which is ac–coupled. The switched
capacitor filter 6–bit programmable counter must be
programmed for the crystal frequency that is selected since
this clock is derived from the crystal frequency and must be
held constant regardless of the crystal that is selected. The
actual switched capacitor clock divider ratio is twice the
programmed divider ratio due to the a fixed divide by 2.0 after
the programmable counter. The scrambler mixer modulation
frequency is the switched capacitor clock divided by 40 for
the MC13110A/B.
Mode Control Register
The power saving modes; mutes, disables, volume
control, and microprocessor clock output frequency are all
MOTOROLA ANALOG IC DEVICE DATA
4–b Volume
Control
Stdby
Mode
Rx
Mode
Tx
Mute
Rx
Mute
SP
Mute
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set by the Mode Control Register. Operation of the Control
Register is explained in Figures 115 through 119.
Figure 116. Mute and Disable Control Bit Descriptions
ALC Disable
1
0
Automatic Level Control Disabled
Normal Operation
Tx Limiter Disable
1
0
Tx Limiter Disabled
Normal Operation
Clock Disable
(MC13110A/111A)
1
0
MPU Clock Output Disabled
Normal Operation
Clock Disable
(MC13110B/111B)
1
0
Don’t Care
Normal Operation
Tx Mute
1
0
Transmit Channel Muted
Normal Operation
Rx Mute
1
0
Receive Channel Muted
Normal Operation
SP Mute
1
0
Speaker Amp Muted
Normal Operation
47
MC13110A/B MC13111A/B
Power Saving Operating Modes
When the MC13110A/B or MC13111A/B are used in a
handset, it is important to conserve power in order to prolong
battery life. There are five modes of operation for the
MC13110A/MC13111A; Active, Rx, Standby, Interrupt, and
Inactive. The MC13110B/MC13111B has three modes of
operation. They are Active, Rx, and Standby. In the Active
mode, all circuit blocks are powered. In the Rx mode, all
circuitry is powered down except for those circuit sections
needed to receive a transmission from the base. In the
Standby and Interrupt Modes, all circuitry is powered down
except for the circuitry needed to provide the clock output for
the microprocessor. In the Inactive Mode, all circuitry is
powered down except the MPU serial interface. Latch
memory is maintained in all modes. All mode functions are
the same for the MC13110B/MC13111B, except that there is
no Inactive mode. With the B” version the MPU Clock is
always running so that there can never be a register reset if
the memory is disturbed. Figure 118 shows the control
register bit values for selection of each power saving mode
and Figure 118 shows the circuit blocks which are powered in
each of these operating modes.
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Figure 117. Power Saving Mode Selection
Stdby Mode Bit
Rx Mode Bit
“CD Out/
Hardware
Interrupt” Pin
Power
Saving
Mode
MC13110A/MC13111A
0
0
X
Active
0
1
X
Rx
1
0
X
Standby
1
1
1 or High
Impedance
Inactive
1
1
0
Interrupt
MC13110B/MC13111B [Note 14]
0
0
X
Active
0
1
X
Rx
1
X
X
Standby
1
1
0
Interrupt
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Figure 118. Circuit Blocks Powered
During Power Saving Modes
MC13110A/MC13111A
MC13110B/MC13111B
Circuit
Ci
i Blocks
Bl k
Active
Rx
Standby
Inactive
X1, 2
X2
“PLL Vref” Regulated
Voltage
X
X
X1
MPU Serial Interface
X
X
X
2nd LO Oscillator
X
X
X
MPU Clock Output
X
X
X
RF Receiver and 1st LO
VCO
X
X
Rx PLL
X
X
Carrier Detect
X
X
Data Amp
X
X
Low Battery Detect
X
X
Tx PLL
Rx and Tx Audio Paths
X
X
NOTES: 15. In Standby and Inactive Modes, “PLL Vref” remains powered
but is not regulated. It will fluctuate with VCC.
16. There is no Inactive mode for MC13110B/MC13111B.
Power Saving Application – Option 1 (MC13110B and
MC13111B Only)
When the handset is in standby, power can be reduced by
entering a “low power” mode and periodically switching to
“sniff” mode to check for incoming calls. Figure 119. shows
an application where the “Clk Out” pin provides the clock for
the MPU. In this application, the 2nd LO and MPU clock run
continuously. The MPU maintains control at all times and sets
the timing for transitions into the “sniff” mode. Power is saved
in the low power mode by putting the MC13110B/MC13111B
into its “Standby” mode. Only the 2nd LO and MPU clock
divider are active. By programming the MPU clock divider to
a large divide value of 20, 80, or 312.5 this will reduce the
MPU clock frequency and save power in the MPU.
NOTES: 13. “X” is a don’t care
14. MPU Clock Out is ”Always On”
48
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Power Saving Application – Option 2 (MC13110A and
MC13111A Only)
In some handset applications it may be desirable to power
down all circuitry including the microprocessor (MPU). First
put the MC13110A/MC13111A into the Inactive mode. This
turns off the MPU Clock Output (see Figure 120) and
disables the microprocessor. Once a command is given to
switch the IC into an “Inactive” mode, the MPU Clock output
will remain active for a minimum of one reference counter
cycle (about 200 µs) and up to a maximum of two reference
counter cycles (about 400 µs). This is performed in order to
give the MPU adequate time to power down.
An external timing circuit should be used to initiate the
turn–on sequence. The “CD Out” pin has a dual function. In
the Active and Rx modes it performs the carrier detect
function. In the Standby and Inactive modes the carrier
detect circuit is disabled and the “CD Out” pin is in a “High”
state, because of an external pull–up resistor. In the Inactive
mode, the “CD Out” pin is the input for the hardware interrupt
function. When the “CD Out” pin is pulled “low”, by the
external timing circuit, the IC switches from the Inactive to the
Interrupt mode. Thereby turning on the MPU Clock Output.
The MPU can then resume control of the IC. The “CD Out”
pin must remain low until the MPU changes the operating
mode from Interrupt to Standby, Active, or Rx modes.
Figure 119. Power Saving Application – Option 1
MC13110B
MC13111B
Clk Out
Clk In
Microprocessor
Timer
MPU Clk
Divider
SPI Port
SPI Port
LO2 Out
LO2 In
Mode
“Low Power”
“Sniff”
Standby Mode
Rx Mode
32.8, 128 or 512 kHz
4.0 MHz
MPU Timer
MPU
Clock
Out
MOTOROLA ANALOG IC DEVICE DATA
49
MC13110A/B MC13111A/B
Figure 120. Power Saving Application – Option 2 (MC13110A/MC13111A Only)
MC13110A/
MC13111A
Clk Out
MPU Clk
Divider
Clk In
SPI Port
SPI Port
LO2 Out
Interrupt
LO2 In
Microprocessor
VCC
CD Out/
HW Interrupt
External Timer
Mode
Active/Rx
Inactive
Interrupt
Standby/Rx/Active
MPU Initiates
Mode Change
MPU Initiates
Inactive Mode
EN
External Timer
Pulls Pin Low
CD Out Low
CD Out/Hardware Interrupt
CD Turns Off
Timer Output
Disabled
MPU Clock Out
Delay after MPU selects Inactive Mode to when CD turns off.
“MPU Clock Out” remains active for a minimum of one count of reference
counter after “CD Out/Hardware Interrupt” pin goes high
MPU “Clk Out” Divider Programming
The “Clk Out” signal is derived from the second local
oscillator. It can be used to drive a microprocessor (MPU) clock
input. This will eliminate the need for a separate crystal to drive
the MPU, thus reducing system cost. Figure 121 shows the
relationship between the second LO crystal frequency and the
clock output for each divide value. Figure 122 shows the “Clk
Out” register bit values. With a 10.24 MHz crystal, the divide by
312.5 gives the same clock frequency as a clock crystal and
allows the MPU to display the time on a LCD display without
additional external components.
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Figure 121. Clock Output Values
Clock Output Divider
Crystal
Frequency
2
2.5
3
4
5
20
80
312.5
10.24 MHz
5.120 MHz
4.096 MHz
3.413 MHz
2.560 MHz
2.048 MHz
512 kHz
128 kHz
32.768 kHz
11.15 MHz
5.575 MHz
4.460 MHz
3.717 MHz
2.788 MHz
2.230 MHz
557 kHz
139 kHz
35.680 kHz
12.00 MHz
6.000 MHz
4.800 MHz
4.000 MHz
3.000 MHz
2.400 MHz
600 kHz
150 kHz
38.400 kHz
50
MOTOROLA ANALOG IC DEVICE DATA
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MC13110A/B MC13111A/B
Figure 122. Clock Output Divider
MPU Clk
Bit #2
MPU Clk
Bit #1
MPU Clk
Bit #0
Clk Out
Divider Value
0
0
0
2
0
0
1
3
0
1
0
4
0
1
1
5
1
0
0
2.5
1
0
1
20
1
1
0
80
1
1
1
312.5
MPU “Clk Out” Power–Up Default Divider Value
The power–up default divider value is “divide by 5”. This
provides a MPU clock of about 2.0 MHz after initial
power–up. The reason for choosing a relatively low clock
frequency at initial power–up is because some
microprocessors operate using a 3.0 V power supply and
have a maximum clock frequency of 2.0 MHz. After initial
power–up, the MPU can change the clock divider value and
set the clock to the desired operating frequency. Special care
was taken in the design of the clock divider to insure that the
transition between one clock divider value and another is
“smooth” (i.e. there will be no narrow clock pulses to disturb
the MPU).
MPU “Clk Out” Radiated Noise on Circuit Board
The clock line running between the MC13110A/B or
MC13111A/B and the microprocessor has the potential to
radiate noise. Problems in the system can occur, especially if
the clock is a square wave digital signal with large high
frequency harmonics. In order to minimize the radiated noise,
a 1000 Ω resistor is included on–chip in series with the “Clk
Out” output driver. A small capacitor or inductor with a
capacitor can be connected to the “Clk Out” line on the PCB
to form a one or two pole low pass filter. This filter should
significantly reduce noise radiated by attenuating the high
frequency harmonics on the signal line. The filter can also be
used to attenuate the signal level so that it is only as large as
required by the MPU clock input. To further reduce radiated
noise, the PCB signal trace length should be kept to a
minimum.
Volume Control Programming
The volume control adjustable gain block can be
programmed in 2 dB gain steps from –14 dB to +16 dB. The
power–up default value for the MC13110A/B and
MC13111A/B is 0 dB. (see Figure 123)
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Figure 123. Volume Control
Volume Control
Bit #3
Volume Control
Bit #2
Volume Control
Bit #1
Volume Control
Bit #0
Volume
Control #
Gain/Attenuation
Amount
0
0
0
0
0
–14 dB
0
0
0
1
1
–12 dB
0
0
1
0
2
–10 dB
0
0
1
1
3
– 8 dB
0
1
0
0
4
– 6 dB
0
1
0
1
5
– 4 dB
0
1
1
0
6
– 2 dB
0
1
1
1
7
0 dB
1
0
0
0
8
2 dB
1
0
0
1
9
4 dB
1
0
1
0
10
6 dB
1
0
1
1
11
8 dB
1
1
0
0
12
10 dB
1
1
0
1
13
12 dB
1
1
1
0
14
14 dB
1
1
1
1
15
16 dB
MOTOROLA ANALOG IC DEVICE DATA
51
MC13110A/B MC13111A/B
Gain Control Register
The gain control register contains bits which control the Tx
Voltage Gain, Rx Voltage Gain, and Carrier Detect threshold.
Operation of these latch bits are explained in Figures 124,
125 and 126.
than the nominal power–up default, is desired, it can be
programmed through the MPU interface. Alternately, these
programmable gain blocks can be used during final test of the
telephone to electronically adjust for gain tolerances in the
telephone system (see Figure 125). In this case, the Tx and
Rx gain register values should be stored in ROM during final
test so that they can be reloaded each time the IC is powered
up.
Tx and Rx Gain Programming
The T x and R x audio signal paths each have a
programmable gain block. If a Tx or Rx voltage gain, other
Figure 124. Gain Control Latch Bits
0
5–b Tx Gain Control
5–b Rx Gain Control
5–b CD Threshold Control
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Figure 125. Tx and Rx Gain Control
Gain Control
Bit #4
Gain Control
Bit #3
Gain Control
Bit #2
Gain Control
Bit #1
Gain Control
Bit #0
Gain
Control #
Gain/Attenuation
Amount
–
–
–
–
–
<6
–9 dB
0
0
1
1
0
6
–9 dB
0
0
1
1
1
7
–8 dB
0
1
0
0
0
8
–7 dB
0
1
0
0
1
9
–6 dB
0
1
0
1
0
10
–5 dB
0
1
0
1
1
11
–4 dB
0
1
1
0
0
12
–3 dB
0
1
1
0
1
13
–2 dB
0
1
1
1
0
14
–1 dB
0
1
1
1
1
15
0 dB
1
0
0
0
0
16
1 dB
1
0
0
0
1
17
2 dB
1
0
0
1
0
18
3 dB
1
0
0
1
1
19
4 dB
1
0
1
0
0
20
5 dB
1
0
1
0
1
21
6 dB
1
0
1
1
0
22
7 dB
1
0
1
1
1
23
8 dB
1
1
0
0
0
24
9 dB
1
1
0
0
1
25
10 dB
–
–
–
–
–
>25
10 dB
52
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Carrier Detect Threshold Programming
The “CD Out” pin gives an indication to the microprocessor
if a carrier signal is present on the selected channel. The
nominal value and tolerance of the carrier detect threshold is
given in the carrier detect specification section of this
document. If a different carrier detect threshold value is
desired, it can be programmed through the MPU interface as
shown in Figure 126 below. Alternately, the carrier detect
threshold can be electronically adjusted during final test of
the telephone to reduce the tolerance of the carrier detect
threshold. This is done by measuring the threshold and then
by adjusting the threshold through the MPU interface. In this
case, it is necessary to store the carrier detect register value
in ROM so that the CD register can be reloaded each time the
combo IC is powered up. If a preamp is used before the first
mixer it may be desirable to scale the carrier detect range by
connecting an external resistor from the “RSSI” pin to
ground. The internal resistor is 187 kΩ.
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Figure 126. Carrier Detect Threshold Control
CD
Bit #4
CD
Bit #3
CD
Bit #2
CD
Bit #1
CD
Bit #0
CD
Control #
Carrier Detect
Threshold
0
0
0
0
0
0
– 20 dB
0
0
0
0
1
1
–19 dB
0
0
0
1
0
2
–18 dB
0
0
0
1
1
3
–17 dB
0
0
1
0
0
4
–16 dB
0
0
1
0
1
5
–15 dB
0
0
1
1
0
6
–14 dB
0
0
1
1
1
7
–13 dB
0
1
0
0
0
8
–12 dB
0
1
0
0
1
9
–11 dB
0
1
0
1
0
10
–10 dB
0
1
0
1
1
11
– 9 dB
0
1
1
0
0
12
– 8 dB
0
1
1
0
1
13
–7 dB
0
1
1
1
0
14
– 6 dB
0
1
1
1
1
15
– 5 dB
1
0
0
0
0
16
– 4 dB
1
0
0
0
1
17
– 3 dB
1
0
0
1
0
18
– 2 dB
1
0
0
1
1
19
–1 dB
1
0
1
0
0
20
0 dB
1
0
1
0
1
21
1 dB
1
0
1
1
0
22
2 dB
1
0
1
1
1
23
3 dB
1
1
0
0
0
24
4 dB
1
1
0
0
1
25
5 dB
1
1
0
1
0
26
6 dB
1
1
0
1
1
27
7 dB
1
1
1
0
0
28
8 dB
1
1
1
0
1
29
9 dB
1
1
1
1
0
30
10 dB
1
1
1
1
1
31
11 dB
MOTOROLA ANALOG IC DEVICE DATA
53
MC13110A/B MC13111A/B
Clock Divider/Voltage Adjust Register
This register controls the divider value for the
programmable switched capacitor filter clock divider, the low
battery detect threshold select, the voltage reference adjust,
and the scrambler bypass mode (MC13110A/B only).
Operation is explained in Figures 127 through 134. The Tx
and Rx Audio bits are don’t cares for either the MC13111A or
the MC13111B device. However, for the MC13110A/B, these
bits are defined. Figure 129 describes the operation. Note the
power–up default bit is set to <0>, which is the scrambler
bypass mode.
The non–programmable threshold mode is only available in
the 52 QFP package. In this mode, there are two low battery
detect comparators and the threshold values are set by
external resistor dividers which are connected to the REF1
and REF2 pins. In the programmable threshold mode,
several different threshold levels may be selected through
the “Low Battery Detect Threshold Register” as shown in Figure
128. The power–on default value for this register is <0,0,0> and
is the non–programmable mode. Figure 130 shows equivalent
schematics for the programmable and non–programmable
operating modes.
Low Battery Detect
The low battery detect circuit can be operated in
programmable and non–programmable threshold modes.
Figure 127. Clock Divider/Voltage Adjust Latch Bits
0
3–b Low Battery
Detect Threshold Select
MSB
4–b Voltage
Reference Adjust
LSB
Tx Sbl
Bypass
Rx Sbl
Bypass
MSB
6–b Switched
Capacitor Filter Clock Counter Latch
LSB
0
0
MSB
6–b Switched
Capacitor Filter Clock Counter Latch
LSB
(MC13110A/B)
0
3–b Low Battery
Detect Threshold Select
MSB
4–b Voltage
Reference Adjust
LSB
(MC13111A/B)
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ÁÁ
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ÁÁ
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ÁÁ
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Figure 128. Low Battery Detect Threshold Selection
Low Battery
Detect
Threshold
Select Bit #2
Low Battery
Detect
Threshold
Select Bit #1
Low Battery
Detect
Threshold
Select Bit #0
Select #
0
0
0
0
Non–Programmable
0
0
1
1
Programmable
2.850
0
1
0
2
Programmable
2.938
0
1
1
3
Programmable
3.025
1
0
0
4
Programmable
3.200
1
0
1
5
Programmable
3.288
1
1
0
6
Programmable
3.375
1
1
1
7
Programmable
3.463
Operating Mode
Nominal Low
Battery Detect
Threshold Value (V)
N/A
NOTE: 17. Nominal Threshold Value is before electronic adjustment.
Figure 129. MC13110A/B Bypass Mode Bit Description
(MC13110A/B Only)
54
Tx Scrambler
1
Tx Scrambler Post–Mixer LPF and Mixer Bypassed
Bypass
0
Normal Operation with Tx Scrambler
Rx Scrambler
1
Rx Scrambler Post–Mixer LPF and Mixer Bypassed
Bypass
0
Normal Operation Rx Scrambler
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Figure 130. Low Battery Detect Equivalent Schematics
Ref2
BD2 Out
50
16
Ref 1
BD1 Out
51
VB
14
Vref
52
Non–Programmable Threshold Mode: 52–QFP Package
VB
VCC Audio
VCC Audio
21
23
BD Out
BD2 Out
14
16
Vref
47
Programmable Threshold Mode: 48–LQFP Package
MOTOROLA ANALOG IC DEVICE DATA
VB
Vref
52
Programmable Threshold Mode: 52–QFP Package
55
MC13110A/B MC13111A/B
Voltage Reference Adjustment
An internal 1.5 V bandgap voltage reference provides the
voltage reference for the “BD1 Out” and “BD2 Out” low battery
detect circuits, the “PLL Vref” voltage regulator, the “VB”
reference, and all internal analog ground references. The
initial tolerance of the bandgap voltage reference is ±6%. The
tolerance of the internal reference voltage can be improved to
±1.5% through MPU serial interface programming. During
final test of the telephone, the battery detect threshold is
measured. Then, the internal reference voltage value is
adjusted electronically through the MPU serial interface to
achieve the desired accuracy level. The voltage reference
register value should be stored in ROM during final test so
that it can be reloaded each time the MC13110A/B or
MC13111A/B is powered up (see Figure 131).
Switched Capacitor Filter Clock Programming
A block diagram of the switched capacitor filter clock
divider is show in Figure 132. There is a fixed divide by 2 after
the programmable divider. The switched capacitor filter clock
value is given by the following equation;
Figure 131. Bandgap Voltage Reference Adjustment
Figure 132. SCF Clock Divider Circuit
(SCF Clock) = F(2nd LO) / (SCF Divider Value * 2).
The scrambler modulation clock frequency (SMCF) is
proportional to the SCF clock. The following equation defines
its value:
SMCF = (SCF Clock)/40
The SCF divider should be set to a value which brings the
SCF Clock as close to 165.16 kHz as possible. This is based
on the 2nd LO frequency which is chosen in Figure 114.
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Vref Adj. Vref Adj. Vref Adj. Vref Adj. Vref Adj.
Bit #3
Bit #2
Bit #1
Bit #0
#
Vref Adj.
Amount
0
0
0
0
0
–9.0%
0
0
0
1
1
–7.8%
0
0
1
0
2
–6.6%
0
0
1
1
3
–5.4%
0
1
0
0
4
–4.2%
0
1
0
1
5
–3.0%
0
1
1
0
6
–1.8%
0
1
1
1
7
–0.6%
1
0
0
0
8
+0.6 %
1
0
0
1
9
+1.8 %
1
0
1
0
10
+3.0 %
1
0
1
1
11
+4.2 %
1
1
0
0
12
+5.4 %
1
1
0
1
13
+6.6 %
1
1
1
0
14
+7.8 %
1
1
1
1
15
+9.0 %
LO2 In
6–b
Programmable
SCF Clock Counter
2nd LO
Crystal
Divide
By 2.0
SCF
Clock
LO2 Out
MC13110A/B
only
Divide
By 40
Scrambler
Modulation
Clock
Corner Frequency Programming for MC13110A/B and
MC13111A/B
Four different corner frequencies may be selected by
programming the SCF Clock divider as shown in Figures 133
and 134. It is important to note, that all filter corner
frequencies will change proportionately with the SCF Clock
Frequency and Scrambler Modulation Frequency. The
power–up default SCF Clock divider value is 31.
Figure 133. Corner Frequency Programming for 10.240 MHz 2nd LO
MC13110A/B
MC13111A/B
SCF Clock
Divider
Total
Divide
Value
29
30
31
32
58
60
62
64
SCF Clock
Freq. (kHz)
Rx Upper
Corner
Frequency (kHz)
Tx Upper
Corner
Frequency (kHz)
Scrambler
Modulation
Frequency
(Clk/40) (kHz)
Scrambler
Lower Corner
Frequency (Hz)
Scrambler
Upper Corner
Frequency (kHz)
176.55
170.67
165.16
160 00
160.00
4.147
4.008
3.879
3 758
3.758
3.955
3.823
3.700
3 584
3.584
4.414
4.267
4.129
4 000
4.000
267.2
258.3
250.0
242 2
242.2
3.902
3.772
3.650
3 536
3.536
NOTE: 18. All filter corner frequencies have a tolerance of ±3%.
19. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass
56
MOTOROLA ANALOG IC DEVICE DATA
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MC13110A/B MC13111A/B
Figure 134. Corner Frequency Programming for 11.15 MHz 2nd LO
MC13110A/B
MC13111A/B
SCF Clock
Divider
Total
Divide
Value
32
33
34
35
64
66
68
70
SCF Clock
Freq. (kHz)
Rx Upper
Corner
Frequency (kHz)
Tx Upper
Corner
Frequency (kHz)
Scrambler
Modulation
Frequency
(Clk/40) (kHz)
Scrambler
Lower Corner
Frequency (Hz)
Scrambler
Upper Corner
Frequency (kHz)
174.22
168.94
163.97
159.29
159 29
4.092
3.968
3.851
3.741
3 741
3.903
3.785
3.673
3.568
3 568
4.355
4.223
4.099
3.982
3 982
263.7
255.7
248.2
241.1
241 1
3.850
3.733
3.624
3.520
3 520
NOTES: 20. All filter corner frequencies have a tolerance of ±3%.
21. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass
Figure 135. Auxiliary Register Latch Bits
0
0
0
0
0
0
0
0
0
MSB 3–b Test Mode
LSB
MSB
4–b 1st LO Capacitor
Selection
LSB
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Figure 136. Digital Test Mode Description
Counter Under Test or
Test Mode Option
“Tx VCO”
Input Signal
TM #
TM 2
TM 1
TM 0
0
0
0
0
Normal Operation
1
0
0
1
Rx Counter
0 to 2.5 V
Input Frequency/Rx Counter Value
2
0
1
0
Tx Counter
0 to 2.5 V
Input Frequency/Tx Counter Value
3
0
1
1
Reference Counter + Divide by 4/25
0 to 2.5 V
Input Frequency/Reference Counter Value * 100
4
1
0
0
SC Counter
0 to 2.5 V
Input Frequency/SC Counter Value * 2
5
1
0
1
ALC Gain = 10 Option
N/A
N/A
6
1
1
0
ALC Gain = 25 Option
N/A
N/A
Auxiliary Register
The auxiliary register contains a 4–bit First LO Capacitor
Selection latch and a 3–bit Test Mode latch. Operation of
these latch bits are explained in Figures 135, 136 and 137.
Test Modes
Test modes are be selected through the 3–bit Test Mode
Register. In test mode, the “Tx VCO” input pin is multiplexed
to the input of the counter under test. The output of the
counter under test is multiplexed to the “Clk Out” output pin
so that each counter can be individually tested. Make sure
test mode bits are set to “0’s” for normal operation. Test
mode operation is described in Figure 136. During normal
operation, the “Tx VCO” input can be a minimum of 200 mVpp
at 80 MHz and should be AC coupled. Input signals should be
standard logic levels of 0 to 2.5 V and a maximum frequency of
16 MHz.
First Local Oscillator Programmable Capacitor Selection
There is a very large frequency difference between the
minimum and maximum channel frequencies in the 25
Channel U.S. standard. The internal varactor adjustment
MOTOROLA ANALOG IC DEVICE DATA
>200 mVpp
“Clk Out” Output Expected
–
range is not large enough to accommodate this large
frequency span. An internal capacitor with 15 programmable
capacitor values can be used to cover the 25 channel
frequency span without the need to add external capacitors
and switches. The programmable internal capacitor can also
be used to eliminate the need to use an external variable
capacitor to adjust the 1st LO center frequency during
telephone assembly. Figure 32 shows the schematic of the
1st LO tank circuit. Figure 137 shows the register control bit
values.
The internal programmable capacitor is composed of a
matrix bank of capacitors that are switched in as desired.
Programmable capacitor values between about 0 and 16 pF
can be selected in steps of approximately 1.1 pF. The internal
parallel resistance values in the table can be used to
calculate the quality factor (Q) of the oscillator if the Q of the
external inductor is known. The temperature coefficient of the
varactor is 0.08%/°C. The temperature coefficient of the
internal programmable capacitor is negligible. Tolerance on
the varactor and programmable capacitor values is ±15%.
57
MC13110A/B MC13111A/B
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Figure 137. First Local Oscillator Internal Capacitor Selection
Varactor
Value over
0.3 to 2.5 V (pF)
Equivalent
Internal
Parallel
Resistance
at 40 MHz (kΩ)
Equivalent
Internal
Parallel
Resistance
at 51 MHz (kΩ)
1st LO
Cap.
Bit 3
1st LO
Cap.
Bit 2
1st LO
Cap.
Bit 1
1st LO
Cap.
Bit 0
1st LO
Cap.
Select
Internal
Programmable
Capacitor
Value (pF)
0
0
0
0
0
0.0
9.7 to 5.8
1200
736
0
0
0
1
1
0.6
9.7 to 5.8
79.3
48.8
0
0
1
0
2
1.7
9.7 to 5.8
131
80.8
0
0
1
1
3
2.8
9.7 to 5.8
31.4
19.3
0
1
0
0
4
3.9
9.7 to 5.8
33.8
20.8
0
1
0
1
5
4.9
9.7 to 5.8
66.6
41
0
1
1
0
6
6.0
9.7 to 5.8
49.9
30.7
0
1
1
1
7
7.1
9.7 to 5.8
40.7
25.1
1
0
0
0
8
8.2
9.7 to 5.8
27.1
16.7
1
0
0
1
9
9.4
9.7 to 5.8
21.6
13.3
1
0
1
0
10
10.5
9.7 to 5.8
20.5
12.6
1
0
1
1
11
11.6
9.7 to 5.8
18.6
11.5
1
1
0
0
12
12.7
9.7 to 5.8
17.2
10.6
1
1
0
1
13
13.8
9.7 to 5.8
15.8
9.7
1
1
1
0
14
14.9
9.7 to 5.8
15.3
9.4
1
1
1
1
15
16.0
9.7 to 5.8
14.2
8.7
58
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
OTHER APPLICATIONS INFORMATION
PCB Board Lay–Out Considerations
The ideal printed circuit board (PCB) lay out would be
double–sided with a full ground plane on one side. The
ground plane would be divided into separate sections to
prevent any audio signal from feeding into the first local
oscillator via the ground plane. Leaded components, can
likewise, be inserted on the ground plane side to improve
shielding and isolation from the circuit side of the PCB. The
opposite side of the PCB is typically the circuit side. It has the
interconnect traces and surface mount components. In cases
where cost allows, it may be beneficial to use multi–layer
boards to further improve isolation of components and
sensitive sections (i.e. RF and audio). For the CT–0 band, it
is also permissible to use single–sided PC layouts, but with
continuous full ground fill in and around the components.
The proper placement of certain components specified in
the application circuit may be very critical. In a lay–out
design, these components should be placed before the other
less critical components are inserted. It is also imperative
that all RF paths be kept as short as possible. Finally, the
MC13110A/B and MC13111A/B ground pins should be tied to
ground at the pins and VCC pins should have adequate
decoupling to ground as close to the IC as possible. In mixed
mode systems where digital and RF/Analog circuitry are
present, the VCC and VEE buses need to be ac–decoupled
and isolated from each other. The design must also take
great caution to avoid interference with low level analog
circuits. The receiver can be particularly susceptible to
interference as they respond to signals of only a few
microvolts. Again, be sure to keep the dc supply lines for the
digital and analog portions separate. Avoid ground paths
carrying common digital and analog currents, as well.
Component Selection
The evaluation circuit schematics specify particular
components that were used to achieve the results shown in
the typical curves and tables, but alternate components
should give similar results. The MC13110A/B and
MC13111A /B IC are capable of matching the sensitivity, IMD,
adjacent channel rejection, and other performance criteria of
a multi–chip analog cordless telephone system. For the most
part, the same external components are used as in the
multi–chip solution.
VB and PLL Vref
VB is an internally generated bandgap voltage. It functions
as an ac reference point for the operational amplifiers in the
audio section as well as for the battery detect circuitry. This
pin needs to be sufficiently filtered to reduce noise and
prevent crosstalk between Rx audio to Tx audio signal paths.
A practical capacitor range to choose that will minimize
crosstalk and noise relative to start up time is 0.5 µf to 10 µf.
The start time for a 0.5 µf capacitor is approximately 5.0 ms,
while a 10µf capacitor is about 10 ms.
MOTOROLA ANALOG IC DEVICE DATA
The “PLL Vref” pin is the internal supply voltage for the Rx
and Tx PLL’s. It is regulated to a nominal 2.5 V. The “VCC
Audio” pin is the supply voltage for the internal voltage
regulator. Two capacitors with 10 µF and 0.01 µF values must
be connected to the “PLL Vref” pin to filter and stabilize this
regulated voltage. The “PLL Vref” pin may be used to power
other IC’s as long as the total external load current does not
exceed 1.0 mA. The tolerance of the regulated voltage is
initially ±8.0%, but is improved to ±4.0% after the internal
Bandgap voltage reference is adjusted electronically through
the MPU serial interface. The voltage regulator is turned off in
the Standby and Inactive modes to reduce current drain. In
these modes, the “PLL Vref” pin is internally connected to the
“VCC Audio” pin (i.e., the power supply voltage is maintained
but is now unregulated).
It is important to note that the momentary drop in voltage
below 2.5 V during this transition may affect initial PLL lock
times and also may trigger the reset. To prevent this, the PLL
Vref capacitor described above should be kept the same or
larger than the VB capacitor, say 10 µf as shown in the
evaluation and application diagrams.
DC Coupling
Choosing the right coupling capacitors for the compander
is also critical. The coupling capacitors will have an affect on
the audio distortion, especially at lower audio frequencies. A
useful capacitor range for the compander timing capacitors is
0.1 µf to 1.0 µf. It is advised to keep the compander
capacitors the same value in both the handset and baseset
applications.
All other dc coupling capacitors in the audio section will
form high pass filters. The designer should choose the
overall cut off frequency (–3.0 dB) to be around 200 Hz.
Designing for lower cut off frequencies may add unnecessary
cost and capacitor size to the design, while selecting too high
of a cut off frequency may affect audio quality. It is not
necessary or advised to design each audio coupling
capacitors for the same cut off frequency. Design for the
overall system cut off frequency. (Note: Do not expect the
application, evaluation, nor production test schematics to
necessarily be the correct capacitor selections.) The goals of
these boards may be different than the systems approach a
designer must consider.
For the supply pins (VCC Audio and VCC RF) choose a 10
µf in parallel with a high quality 0.01 µf capacitor. Separation
of the these two supply planes is essential, too. This is to
prevent interference between the RF and audio sections. It is
always a good design practice to add additional coupling on
each supply plane to ground as well.
The IF limiter capacitors are recommended to be 0.1 µf.
Smaller values lower the gain of the limiter stage. The
–3.0 dB limiting sensitivity and SINAD may be adversely
affected.
59
60
BNC
BNC
BNC
Scr Out
E Out
SA Out
Vcap Ctrl
LO 2 In
RF In 2
RF In1
C42a
txt
C52
10 µ
R42b
txt
C42b
txt
R4b
txt
C4
txt
C48 0.47
C47 0.47
C3
0.1
Tx
PD
6
Gnd Tx
PLL VCO
7
8
Data
9
EN
10
Clk
11
29
VCC
RF
R10
10 k
30
Lim
C2
Det Out 25
27
Q
Coil
26
RSSI
C28
txt
L1
txt
Tx Out 17
C Cap 18
C In 19
Amp Out 20
Tx In 21
DA In 22
VCC Audio 23
Rx Audio In 24
28
Lim
Out
R28
txt
Rx PD
C1
txt
XC
txt
C2
txt
52 VB LO2 LO2
In Out
1
2
PLL Vref
Tx PD
C5b
10 µ
C5a
0.01
Tx VCO
Connector
Controllor
R9
10 k
R13
100 k
VCC
Clk Out CD Out
R11
10 k
Clk CD BD1 14
Out Out Out
12
13
DA Out 15
PLL
Vref
5
31
Lim
C1
C30
0.1
51 Ref 1
Rx
PD
4
C31
0.1
32
Lim
In
MC13110A
MC13111A
34
33
Mix 2 SGnd
In
RF
F2
txt
C35
0.01
Mix 2 Out Lim In
BD2 Out 16
Vag
3
35
Mix 2
Out
R34
txt
BNC
50 Ref 2
49 Scr Out
48 E In
47 E Cap
46 E Out
45 SA In
44 SA Out
43 Gnd Audio
42 Vcap Ctrl
36
Gnd
RF
F1
txt
C37
0.01
BNC
R37
txt
39
38
37
Mix 1 Mix 1 Mix 1
In 2 Out
In 1
40
LO1 In
C40
txt
41 LO1 Out
C46 0.1
R4a txt
R50b
100 k
R51b
100 k
R42a txt
R50a
110 k
VCC
VCC
R46
47 k
R45
47 k
T2–L2
txt
R51a
82 k
VCC
C45
220 p
C44
47µ
R44 150
R40
49.9
R39
49.9
C39 0.01
T1
txt
C38
0.01
Mix1 Out Mix 2 In
Figure 138. Evaluation Board Schematic
C19
0.1
R14 100 k
R16 100 k
C18 0.47
R20
47 k
C23a 0.01
C24 0.01
C26 0.047
C53
1000
C55
10 µ
VCC
VCC
VCC
R21 47 k C21 0.1
C23b 10 µ
C20
220 p
C54
0.01
R53 47
txt: see text
BD 1 Out
DA Out
BD 2 Out
Tx Out
Amp Out
Tx In
DA In
BNC
Det Out
RSSI
Gnd
VCC
MC13110A/B MC13111A/B
APPENDIX A
Figure 138.
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
APPENDIX A
Figure 139. Evaluation Board Bill of Materials for U.S. and French Application
USA Application Handset
C
Comp.
N
Number
b
RF
(50 Ω)
RF Matched
M h d
French Application Base
RF Crystal
y
(50 Ω)
RF Ceramic
(50 Ω)
RF Matched
M h d
INPUT MATCHING
T1
n.m.
Toko 1:5
292GNS–765A0
n.m.
n.m.
Toko 1:5
292GNS–765A0
C38
0.01
n.m.
0.01
0.01
n.m.
C39
0.01
n.m.
0.01
0.01
n.m.
Ceramic
Ceramic
Crystal
Ceramic
Ceramic
R37
0
0
1.2 k
0
0
R34
360
360
3.01 k
360
360
4 Element
Murata E
4 Element
Murata E
4 Element
Murata G
4 Element
Murata G
4 Element
Murata G
Q Coil Toko
7MCS–8128Z
Q Coil Toko
7MCS–8128Z
Ceramic Murata
CDBM 450C34
Ceramic Murata
CDBM 450C34
Ceramic Murata
CDBM 450C34
R28
22.1 k
22.1 k
2.7 k
2.7 k
2.7 k
C28
10 p
10 p
390 p
390 p
390 p
Xtal
10.24
C1 = 10 p
10.24
C1 = 10 p
11.15
C1 = 18 p
11.15
C1 = 18 p
11.15
C1 = 18 p
C2
18 p
18 p
33 p
33 p
33 p
C1
5–25 p
5–25 p
15 p + 5–25 p
15 p + 5–25 p
15 p + 5–25 p
0.47
Toko T1370
0.47
Toko T1370
0.22
Toko T1368
0.22
Toko T1368
0.22
Toko T1368
HS: 27 pF
BS: 22 pF
HS: 27 pF
BS: 22 pF
BS: 100 p
HS: 68 pF
BS: 100 p
HS: 68 pF
BS: 100 p
HS: 68 pF
10.7 MHz FILTER
F1
450 kHz FILTER
F2
DEMODULATOR
L1
OSCILLATOR
FIRST LO
L2
C40 HS/BS
LOOP FILTER HANDSET/BASESET
R4a
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
R4b
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
C4
HS: 6800
BS: 8200
HS: 6800
BS: 8200
HS: 8600
BS: 6800
HS: 8600
BS: 6800
HS: 8600
BS: 6800
R42a
HS: 100 k
BS: 100 k
HS: 100 k
BS: 100 k
HS: 100 k
BS: 100 k
HS: 100 k
BS: 100 k
HS: 100 k
BS: 100 k
R42b
HS: 22 k
BS: 18 k
HS: 22 k
BS: 18 k
HS: 18 k
BS: 22 k
HS: 18 k
BS: 22 k
HS: 18 k
BS: 22 k
C42a
HS: 1000
BS: 1000
HS: 1000
BS: 1000
HS: 1000
BS: 1000
HS: 1000
BS: 1000
HS: 1000
BS: 1000
C42b
HS: 0.068
BS: 0.082
HS: 0.068
BS: 0.082
HS: 0.082
BS: 0.068
HS: 0.082
BS: 0.068
HS: 0.082
BS: 0.068
MOTOROLA ANALOG IC DEVICE DATA
61
Speaker
SP1
150–300 Ω
Tx RF–In
R
x
A
n
t
Gnd
+
G
n
d
G
n
d
T
x
3 4 5 6
Gnd
C6
47 µF
1 2
G
n
d
Duplexer
VCC –A
T1
C4
0.01
44
43
42
41
40
Ref 2
Scr Out
E In
Ecap
E Out
SA In
1000
100 k
0.068
18 k
0.1
8200
C18
5.0–25
Gnd
C17
X1
18 10.24
1
Ref 1 L
O
VB 2
I
n
52
C14
10 µF
VB
50
C13 49
C12 48
Gnd Audio
SA Out
FL1
2
1
3
2
1
FL2
3
R36
330
VCC–RF
0.10
C70
10
R34
22 k
Gnd
47
P35
C22
0.01
4
P
D
3
V
a
g
R
x
R
F
G
n
d
2
L
O
2
O
u
t
M
i
x
1
O
u
t
S
G
N
D
R
F
I
n
L
i
m
C
1
L
i
m
5
6
P
D
T
x
7
30
Gnd
+
C
l
k
R
F
V
C
C
O
u
t
C
l
k
O
u
t
L
i
m
CD Out
BD 1 Out
DA Out
BD 2 Out
Tx Out
C Cap
C In
Amp Out
Tx In
DA In
VCC Audio
Rx Audio In
Det Out
Q Coil
RSSI
14
15
16
17
Gnd
R17
1.0 k
+
C25
22 µF
R21
Tx VCO
R18
680
+
R19
18 k
10 k
Gnd
C26
4.7 µF
R22
10 k
100 k
R24
100 k
0.47
19
18
C29
C28
27 k
R28
10 µF
C88
0.15
Tx VT
VCC
R25
100 k
Gnd
C7
10
C33
Gnd
3300
27 k
R29
C84
0.01
C31
Gnd
0.047
VCC–A
R31
47
R26
Gnd
+
Electret
Mic
Gnd
10 µF
VCC
Mic1
C32
R27
1.0 k
3.9 k
Legend:
If ≥1, then capacitor value = pF
If <1, then capacitor value = µ F
Clk Out
Clk
EN
Data
Car–Detect
Low Batt
R x Data
Batt Dead
R30 680 k
1000
C87
47 k
R33
Gnd
VCC –A
Tx Audio
33
0.1
C35
0.01
R32
8.2 k
C86
0.01
RSSI
0.047
C34
21
22
23
24
25
26
10 11 12 13 R23
E
N
9
D
a
t
a
C
2
L
i
m
8
T
x
V
C
O
R16
C27
10
P
L
L
G
n
d
IC1
MC13110A/B
MC13111A/B
M
i
x
2
I
n
+ C23
C24
10 µF 3.3 µF
V
r
e
f
P
L
L
M
i
x
2
O
u
t
C89
10 µF
C71
+
C72
0.01
1000
20
T2
39 38 37 36 35 34 33 32 31 30 29 28 27
Mix 1 In 1 M
i
LO1 In
x
1
LO1 Out
I
n
2
Vcap Ctrl
82 k
C16
0.1
R13
R11
100 k 100 k
VCC –A
0.47
C9 45
R7 47 k 220 46
0.47
47
L3
0.47µH
R4
220
S2
S1
51
C15
47 k
C10
0.1
R8
C5
22
R1
33 k
P2
Q1 8519N
MPSH10
P3
P1
Gnd
R12
R10
110 k
0.1
C2
R2
100 k
VCC–RF
0.1
C3
0.033
C19
R3
220
C74
C73 0.10
R20
8128Z
RF Input
6800
62
10 k
Figure 140.
C30
Figure 140. Basic Cordless Telephone Transceiver Application Circuit
MC13110A/B MC13111A/B
APPENDIX B
APPLICATIONS CIRCUIT
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
APPENDIX B
Figure 140. Basic Cordless Telephone Transceiver Application Circuit (continued)
VCC
+ C57
2.2 µ F
C56
0.1
Batt1
L6
56 µ H
VRx
V+
C54 +
10 µ F
V–
Gnd
VCC –RF
C55
0.22
C53
0.01
Gnd
VCC –A
+
C58
10 µ F
Gnd
Gnd
C59
180
C49
Tx VT
2.0
Tx Audio
U5
C37
C60
0.1 µ F
6800
R51
2
3
4
C38
8.0
R37
22 k
5
6
7
R39
110 k
8
Tx Data
Variable
Reactance
Output
RF Osc
Decoupling
RF Osc
Modulator
Input
Mic Amp
Output
Mic Amp
Input
Gnd
IC2 MC2833D
1
110 k
1
C48
120
R54
100 k
R53
68 k
L4
0.22 µ H
Tr 1
Emitter
Tr 2
Emitter
VCC
Tr 1
Base
Tr 1
Collector
10
R41
MOTOROLA ANALOG IC DEVICE DATA
Tr 2
Base
Tr 2
Collector
C40
27 k
RF
Output
R42
91 k
16
C46
C47
36
15
36
C45
10
Tx VCO
1.5 k
12
R49 100
11
C44
10
2109
VR2
R50
14
13
2
R45
R47
75 k
0.22 µ H
L5
4700
VCC
R46
220 k
Gnd
C50
110
0.022
C43
9
R44
51
P1
Cx P2
7.5 P3
T3
S1
S2
13630
C51
C41
51
51 Ω
110
0.022
R43
Tx RF–In
C52
110
0.022
63
MC13110A/B MC13111A/B
APPENDIX C – MEASUREMENT OF COMPANDER ATTACK/DECAY TIME
This measurement definition is based on EIA/CCITT
recommendations.
Compressor Attack Time
For a 12 dB step up at the input, attack time is defined as
the time for the output to settle to 1.5X of the final steady state
value.
Compressor Decay Time
For a 12 dB step down at the input, decay time is defined
as the time for the input to settle to 0.75X of the final steady
state value.
Expander Attack
For a 6.0 dB step up at the input, attack time is defined as
the time for the output to settle to 0.57X of the final steady
state value.
Expander Decay
For a 6.0 dB step down at the input, decay time is defined
as the time for the output to settle to 1.5X of the final steady
state value.
6.0 dB
Input
12 dB
0 mV
Input
0 mV
Decay Time
Attack Time
Attack Time
Decay Time
0.57X Final Value
1.5X Final Value
1.5X Final Value
Output
Output
0.75X Final Value
0 mV
0 mV
64
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
OUTLINE DIMENSIONS
FB SUFFIX
PLASTIC PACKAGE
CASE 848B–04
(QFP–52)
ISSUE C
B
L
B
39
27
S
D
C A–B
V
F
M
0.20 (0.008)
B
0.20 (0.008)
M
L
–A–, –B–, –D–
DETAIL A
S
S
H A–B
–B–
–A–
0.05 (0.002) A–B
S
DETAIL A
D
26
40
J
N
14
52
1
13
BASE METAL
D
–D–
B
0.20 (0.008) M H A–B
0.02 (0.008)
S
D
S
V
M
C A–B
S
D
S
DETAIL C
M_
C
E
–H–
DATUM
PLANE
0.10 (0.004)
H
–C–
M_
G
U_
R
Q_
K
T
W
X
DETAIL C
MOTOROLA ANALOG IC DEVICE DATA
C A–B
S
D
S
SECTION B–B
0.05 (0.002) A–B
0.20 (0.008)
M
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
Q
R
S
T
U
V
W
X
MILLIMETERS
MIN
MAX
9.90
10.10
9.90
10.10
2.10
2.45
0.22
0.38
2.00
2.10
0.22
0.33
0.65 BSC
–––
0.25
0.13
0.23
0.65
0.95
7.80 REF
5_
10_
0.13
0.17
0_
7_
0.13
0.30
12.95
13.45
0.13
–––
0_
–––
12.95
13.45
0.35
0.45
1.6 REF
INCHES
MIN
MAX
0.390
0.398
0.390
0.398
0.083
0.096
0.009
0.015
0.079
0.083
0.009
0.013
0.026 BSC
–––
0.010
0.005
0.009
0.026
0.037
0.307 REF
5_
10_
0.005
0.007
0_
7_
0.005
0.012
0.510
0.530
0.005
–––
0_
–––
0.510
0.530
0.014
0.018
0.063 REF
65
MC13110A/B MC13111A/B
OUTLINE DIMENSIONS
FTA SUFFIX
PLASTIC PACKAGE
CASE 932–02
(LQFP–48)
ISSUE D
4X
0.200 (0.008) AB T–U Z
9
DETAIL Y
A
P
A1
48
37
1
36
–T–
–U–
B
V
AE
B1
12
25
13
AE
V1
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4 DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5 DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6 DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7 DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014).
8 MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9 EXACT SHAPE OF EACH CORNER IS OPTIONAL.
24
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
–Z–
S1
–T–, –U–, –Z–
S
DETAIL Y
4X
0.200 (0.008) AC T–U Z
0.080 (0.003) AC
G
–AB–
–AC–
AD
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.007
0.011
0.053
0.057
0.007
0.009
0.020 BASIC
0.002
0.006
0.004
0.008
0.020
0.028
12 _REF
0.004
0.006
0.010 BASIC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
M_
BASE METAL
ÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
ÇÇÇÇ
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.170
0.270
1.350
1.450
0.170
0.230
0.500 BASIC
0.050
0.150
0.090
0.200
0.500
0.700
12 _REF
0.090
0.160
0.250 BASIC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
TOP & BOTTOM
N
R
J
GAUGE PLANE
0.250 (0.010)
C
E
F
D
0.080 (0.003)
M
AC T–U
SECTION AE–AE
S
Z
S
W
H
Q_
K
DETAIL AD
X
66
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
MOTOROLA ANALOG IC DEVICE DATA
67
MC13110A/B MC13111A/B
Mfax is a trademark of Motorola, Inc.
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68
◊
MC13110A/D
MOTOROLA ANALOG IC DEVICE
DATA
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