LANSDALE MC145159DW1 Serial-input pll frequency synthesizer with analog phase detector Datasheet

ML145159
Serial-Input PLL Frequency
Synthesizer with Analog Phase
Detector
INTERFACES WITH DUAL–MODULUS PRESCALERS
Legacy Device: Motorola MC145159-1
The ML145159 has a programmable 14–bit reference
counter, as well as fully programmable
divide–by–N/divide–by–A counters. The counters are programmed serially through a common data input and
latched into the appropriate counter latch, according to the
last data bit (control bit) entered.
When combined with a loop filter and VCO, this device can
provide all the remaining functions for a PLL frequency synthesizer operating up to the device's frequency limit. For higher VCO frequency operations, a down mixer or a dual–modulus prescaler can be used between the VCO and the PLL.
• Operating Temperature Range: TA – 40° to 85°C
• Low Power Consumption Through Use of CMOS
Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation
• Compatible with the Serial Peripheral Interface (SPI)
on CMOS MCUs
• ÷ R Range = 3 to 16383
• ÷ N Range = 16 to 1023, P A Range = 0 to 127
• High–Gain Analog Phase Detector
• See Application Note AN969
Page 1 of 10
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Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
Issue A
ML145159
LANSDALE Semiconductor, Inc.
BLOCK DIAGRAM
÷
′
′
÷
÷
* FSO is not and cannot be used as a digital phase detector output.
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
– 0.5 to + 10
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
Supply Current, VDD or VSS Pins
± 30
mA
IDD, ISS
PD
Power Dissipation, per Package
Tstg
Storage Temperature
TL
Lead Temperature (8–Second Soldering)
500
mW
– 65 to + 150
°C
260
°C
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid applications of any voltage higher than maximum rated
voltages to this high–impedance circuit. For
proper operation it is recommended that Vin and
Vout be constrained to the range VSS ≤ (Vin or
Vout) ≤ VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD).
* Maximum Ratings are those values beyond which damage to the device may occur.
Page 2 of 10
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Issue A
ML145159
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS except ICR and IAPD which are referenced to VSS′)
– 40°C
Characteristic
Power Supply Voltage Range
Output Voltage
Vin = 0 V or VDD
Iout = 0 µA
(Except OSCout and APDout)
Output Voltage
OSCout
Vin = 0 V or VDD
Input Voltage* — OSCin
VO = 2.1 V or 0.9 V
VO = 3.5 V or 1.5 V
VO = 6.3 V or 2.7 V
Input Current — Data, CLK, ENB
Max
Min
Max
Unit
3
9
3
9
3
9
V
3
5
9
—
—
—
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
V
1 Level
VOH
3
5
9
2.95
4.95
8.95
—
—
—
2.95
4.95
8.95
—
—
—
2.95
4.95
8.95
—
—
—
0 Level
VOL
3
5
9
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
1 Level
VOH
3
5
9
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
∆V
—
—
—
—
1.05
—
—
V
0 Level
VIL
3
5
9
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
V
1 Level
VIH
3
5
9
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
3
5
9
—
—
—
0
0
0
—
—
—
0
0
0
—
—
—
0
0
0
3
5
9
3.0
5.0
9.0
—
—
—
3.0
5.0
9.0
—
—
—
3.0
5.0
9.0
—
—
—
3
5
9
– 0.60
– 0.90
– 1.50
—
—
—
– 0.50
– 0.75
– 1.25
—
—
—
– 0.30
– 0.50
– 0.80
—
—
—
IOL
3
5
9
1.30
1.90
3.80
—
—
—
1.10
1.70
3.30
—
—
—
0.66
1.08
2.10
—
—
—
ICR
9
—
—
– 90
– 110
—
—
µA
IAPD
9
—
—
170
350
—
—
µA
3
5
9
– 0.44
– 0.64
– 1.30
—
—
—
– 0.35
– 0.51
– 1.00
—
—
—
– 0.22
– 0.36
– 0.70
—
—
—
IOL
3
5
9
0.44
0.64
1.30
—
—
—
0.35
0.51
1.00
—
—
—
0.22
0.36
0.70
—
—
—
Iin
9
—
± 0.3
—
± 0.1
—
± 1.0
µA
0 Level
Source
Sink
Output Current, APDout
RO = 240 k, VCH = 0 V, VAPDout = 4.5 V
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
Min
—
Output Current, CR, VCR = 4.5 V, RR = 240 k
Output Current — Other Outputs
Vout = 2.7 V
Vout = 4.6 V
Vout = 8.5 V
Max
VOL
1 Level
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
Min
VDD
VO = 0.9 V or 2.1 V
VO = 1.5 V or 3.5 V
VO = 2.7 V or 6.3 V
Output Current — MC
Vout = 2.7 V
Vout = 4.6 V
Vout = 8.5 V
VDD
85°C
0 Level
∆Voltage, VCH – VAPDout, IAPDout ≈ 0 µA
Input Voltage
Vout = 0.5 V or VDD – 0.5 V
(All Outputs Except OSCout)
Symbol
25°C
Source
Sink
VIL
VIH
IOH
IOH
V
V
V
mA
mA
Input Current — fin, OSCin
Iin
9
±2
± 50
±2
± 25
±2
± 22
µA
Input Capacitance
Cin
—
—
10
—
10
—
10
pF
Three–State Output Capacitance — FSO
Cout
—
—
10
—
10
—
10
pF
Quiescent Current
Vin = 0 V or VDD
Iout = 0 µA
IDD
3
5
9
—
—
—
800
1200
1600
—
—
—
800
1200
1600
—
—
—
1600
2400
3200
µA
Three–State Leakage Current, Vout = 0 V or 9 V
IOZ
9
—
± 0.3
—
± 0.1
—
± 3.0
µA
* DC coupled square wave.
Page 3 of 10
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Issue A
ML145159
LANSDALE Semiconductor, Inc.
SWITCHING CHARACTERISTICS (TA = 25°C, CL = 50 pF)
Figure
No.
Symbol
VDD
Min
Max
Unit
Output Rise Time — MC
4, 9
tTLH
3
5
9
—
—
—
115
60
40
ns
Output Fall Time — MC
4, 9
tTHL
3
5
9
—
—
—
60
34
30
ns
Output Rise and Fall Time — LD and SRout
4, 9
tTLH,
tTHL
3
5
9
—
—
—
140
80
60
ns
Propagation Delay Time — fin to MC
5, 9
tPLH,
tPHL
3
5
9
—
—
—
125
80
50
ns
6
tsu
3
5
9
30
20
18
—
—
—
ns
3
5
9
70
32
25
—
—
—
Characteristic
Setup Times — Data to CLK
CLK to ENB
Hold Time — CLK to Data
6
th
3
5
9
12
12
15
—
—
—
ns
Recovery Time — ENB to CLK
6
trec
3
5
9
5
10
20
—
—
—
ns
Input Rise and Fall Times — CLK, OSCin, fin
7
tr, tf
3
5
9
—
—
—
5
2
0.5
µs
Input Pulse Width — ENB and CLK
8
tw
3
5
9
40
35
25
—
—
—
ns
NOTE: Refer to the graphs and text in application note AN969 for maximum frequency information.
Page 4 of 10
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Issue A
ML145159
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
COMPONENT PINS
INPUT PINS
OSCin, OSCout
Oscillator Input and Oscillator Output (PDIP, SOG –
Pins 2, 3; SSOP – Pins 7, 8)
These pins form an on–chip reference oscillator when connected to terminals of an external parallel–resonant crystal.
Frequency–setting capacitors of appropriate value must be connected from OSCin to VSS and OSCout toVSS. OSCin may
also serve as input for an externally–generated reference signal. This signal will typically be AC coupled to OSCin, but for
larger amplitude signals (standard CMOS logic levels), DC
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
f in
Frequency Input (PDIP, SOG – Pin 10, SSOP – Pin 15)
Input to the positive edge triggered divide–by–N and divide–by–A counters. f in is typically derived from a dual–modulus prescaler and is AC coupled. This input has an inverter
biased in the linear region to allow use with AC coupled signals as low as 500 mV peak–to–peak or direct coupled signals
swinging from VDD to VSS.
DATA
Serial Data Input (PDIP, SOG – Pin 12, SSOP – Pin 17)
Counter and control information is shifted into this input.
The last data bit entered goes into the one–bit control shift register. A logic 1 allows the reference counter information to be
loaded into its 14–bit latch when ENB goes high. A logic 0
entered as the control bit disables the reference counter latch.
The divide–by–A/divide–by–N counter latch is loaded, regardless of the contents of the control register, when ENB goes
high. The data entry format is shown in Figure 1.
ENB
Transparent Latch Enable (PDIP, SOG – Pin 13,
SSOP – Pin 18)
A logic high on this input allows data to be entered into the
divide–by–A/divide–by–N latch and, if the control bit is high,
into the reference counter latch. Counter programming is unaffected when ENB is low. ENB should be kept normally low
and pulsed high to transfer data to the latches.
CLK
Shift Register Clock (PDIP, SOG – Pin 11, SSOP – Pin 16)
A low–to–high transition on this input shifts data from the
serial data input into the shift registers.
CR
Ramp Capacitor (PDIP, SOG – Pin 15, SSOP – Pin 20)
The capacitor connected from this pin to VSS’ is charged linearly, at a rate determined by RR. The voltage on this capacitor
is proportional to the phase difference of the frequencies present at the internal phase detector inputs. A polystyrene or
mylar capacitor is recommended.
RR
Ramp Current Bias Resistor (PDIP, SOG – Pin 20,
SSOP – Pin 5)
A resistor connected from this pin to VSS’ determines the
rate at which the ramp capacitor is charged, thereby affecting
the phase detector gain (see Figure 2).
CH
Hold Capacitor (PDIP, SOG – Pin 18, SSOP – Pin 3)
The charge stored on the ramp capacitor is transferred to the
capacitor connected from this pin to either VDD’ or VSS’. The
ratio of CR to CH should be large enough to have no effect on
the phase detector gain (CR > 10 CH). A low–leakage capacitor should be used.
RO
Output Bias Current Resistor (PDIP, SOG – Pin 1,
SSOP – Pin 6)
A resistor connected from this pin to VSS’ biases the output
N–Channel transistor, thereby setting a current sink on the analog phase detector output. This resistor adjusts the APDout bias
current (see Figure 3).
OUTPUT PINS
APDout
Analog Phase Detector Output (PDIP, SOG – Pin 17,
SSOP – Pin 2)
This output produces a voltage that controls an external
VCO. The voltage range of this output (VDD = + 9 V) is from
below + 0.5 V to + 8 V or more. The source impedance of this
output is the equivalent of a source follower with an externally
variable source resistor. The source resistor depends upon the
output bias current controlled by the output bias current resistor, RO. The bias current is adjustable from 0.01 mA to 0.5
mA. The output voltage is not more than 1.05 V below the
sampled point on the ramp. With a constant sample of the
ramp voltage at 9 V and the hold capacitor of 50 pF, the instantaneous output ripple is about 5 mV peak–to–peak.
Figure 1. Data Entry Format
Page 5 of 10
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Issue A
ML145159
LANSDALE Semiconductor, Inc.
CHARGE
Ramp Charge Indicator (PDIP, SOG – Pin 4,
SSOP – Pin 9)
This output is high from the time fR goes high to the time
fV goes high (fR and fV are the frequencies at the phase detector inputs). This high voltage indicates that the ramp capacitor,
CR, is being charged.
FSO
Three–State Frequency Steering Output (PDIP,
SOG –Pin 6, SSOP – Pin 11)
If the counted down input frequency on f in is higher than the
counted down reference frequency of OSCin, this output goes
low. If the counted down VCO frequency is lower than that of
the counted down OSCin, this output goes high.
The repetition rate of the frequency steering output pulses is
approximately equal to the difference of the frequencies of the
two counted down inputs from the VCO and OSCin. See
Application Note AN969 for further information.
LD
Lock Detector Indicator (PDIP, SOG – Pin 9,
SSOP – Pin 14)
This output is high during lock and goes low to indicate a
non–lock condition. The frequency and duration of the
non–lock pulses will be the same as either polarity of the frequency steering output.
MC
Dual Modulus Prescaler Control (PDIP, SOG – Pin 8,
SSOP – Pin 13)
The modulus control level is low at the beginning of a count
cycle and remains low until the divide–by–A counter has
counted down from its programmed value. At that time, the
modulus control goes high and remains high until the divide–by–N counter has counted the rest of the way down from
its programmed value (N – A additional counts since both
divide–by–N and divide–by–A are counting down during the
first portion of the cycle). Modulus control is then set back
low, the counters preset to their respective programmed values,
and the above sequence repeated. This provides for a total programmable divide value of NT = N • P + A, where P and P + 1
Page 6 of 10
represent the dual modulus prescaler divide values respectively
for high and low modulus control levels, N is the number programmed into the divide–by–N counter, and A is the number
programmed into the divide–by–A counter.
SRout
Shift Register Output (PDIP, SOG – Pin 14,
SSOP – Pin 19)
This pin is the non–inverted output of the last stage of the
32–bit serial data shift register. It is not latched by the ENB
line. If unused, SRout should be floated.
POWER SUPPLY
VDD
Positive Power Supply (PDIP, SOG – Pin 5, SSOP – Pin 10)
Positive power supply input for all sections of the device
except the analog phase detector. VDD and VDD’ should be
powered up at the same time to avoid damage to the
ML145159. VDD must be tied to the same potential asVDD’.
VSS
Negative Power Supply (PDIP, SOG – Pin 7,
SSOP – Pin 12)
Circuit ground for all sections of the ML145159 except the
analog phase detector. VSS must be tied to the same potential
as VSS’.
VSS’
Analog Phase Detector Circuit Ground (PDIP, SOG –
Pin 16, SSOP – Pin 1)
Separate power supply and ground inputs are provided to
help reduce the effects in the analog section of noise coming
from the digital sections of this device and the surrounding circuitry.
VDD’
Analog Power Supply (PDIP, SOG – Pin 19, SSOP – Pin 4)
Separate power supply and ground inputs are provided to
help reduce the effects in the analog section of noise coming
from the digital sections of this device and the surrounding circuitry.
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Issue A
ML145159
LANSDALE Semiconductor, Inc.
Ω
′
′
′
µ
Ω
Figure 2. Charge Current vs Ramp Resistance
Figure 3. APDout Bias Current vs Output Resistance
DESIGN EQUATION
Kφ =
ICHARGE
2π fRCR
where
Kφ = phase detector gain, ICHARGE is from Figure 2
fR = reference frequency
CR = ramp capacitor (in farads)
SWITCHING WAVEFORMS
Figure 4.
Figure 5.
Figure 7.
Figure 6.
*
* Includes all probe and fixture capacitance.
Figure 8.
Page 7 of 10
Figure 9. Test Circuit
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Issue A
ML145159
LANSDALE Semiconductor, Inc.
DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a reference frequency to Lansdale’s CMOS frequency synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscillators provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 µA at CMOS logic levels
may be direct or DC coupled to OSCin. In general, the highest
frequency capability is obtained utilizing a direct coupled
square wave having a rail–to–rail (VDD to VSS) voltage
swing. If the oscillator does not have CMOS logic levels on the
outputs, capacitive or AC coupling to OSCin may be used.
OSCout, an unbuffered output, should be left floating.
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic Engineers Master Catalog, the Gold Book, or similar publications.
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the ML12061 MECL device. The reference signal from the
MECL device is AC coupled to OSCin. For large amplitude
signals (standard CMOS logic levels), DC coupling is used.
OSCout, an unbuffered output, should be left floating. In general, the highest frequency capability is obtained with a
direct–coupled square wave having rail–to–rail voltage swing.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. A fundamental mode crystal, parallel resonant at the
desired operating frequency, should be connected as shown in
Figure 10.
For VDD = 5 V, the crystal should be specified for a loading
capacitance, CL, which does not exceed 32 pF for frequencies
to approximately 8 MHz, 20 pF for frequencies in the area of 8
to 15 MHz, and 10 pF for higher frequencies. These are guidelines that provide a reasonable compromise between IC capacitance, drive capability, swamping variations in stray and IC
input/output capacitance, and realistic CL values. Assuming
R1 = 0 Ω. the shunt load capacitance, CL, presented across the
crystal can be estimated to be:
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated components must be located as close as possible to the OSCin and
OSCout pins to minimize distortion, stray capacitance, stray
inductance, and start–up stabilization time. Circuit stray capacitance can also be handled by adding the appropriate stray
value to the values for Cin and Cout. For this approach, the
term Cstray becomes zero in the above expression for CL.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 12. The maximum drive level specified
by the crystal manufacturer represents the maximum stress that
a crystal can withstand without damaging or excessive shift in
operating frequency. R1 in Figure 10 limits the drive level. The
use of R1 is not necessary in most cases.
To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a function of
voltage at OSCout. (Care should be taken to minimize loading.) The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in
frequency or become unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1 must
be increased in value if the overdriven condition exists. The
user should note that the oscillator start–up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have developed
expertise in CMOS oscillator design with crystals. Discussions
with such manufacturers can prove very helpful. See Table 1.
CL = CinCout + Ca + Cstray + C1 • C2
C1 + C2
Cin + Cout
where
Cin = 5 pF (see Figure 11)
Cout = 6 pF (see Figure 11)
Ca = 1 pF (see Figure 11)
C1 and C2 = external capacitors (see Figure 10)
Cstray = the total equivalent external circuit stray
capacitance appearing across the
crystal terminals
* May be deleted in certain cases. See text.
Figure 10. Pierce Crystal Oscillator Circuit
Figure 11. Parasitic Capacitances of the
Amplifier and Cstray
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
Figure 12. Equivalent Crystal Networks
Page 8 of 10
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Issue A
ML145159
LANSDALE Semiconductor, Inc.
Table 1. Partial List of Crystal Manufacturers
Name
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Address
3605 McCart Ave., Ft. Worth, TX 76110
2351 Crystal Dr., Ft. Myers, FL 33907
512 N. Main St., Orange, CA 92668
Phone
(817) 921–3013
(813) 936–2109
(714) 639–7810
NOTE: Lansdale cannot recommend one supplier over another and in no way suggests that this is a complete
listing of crystal manufacturers.
RECOMMENDED READING
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2 Feb.,
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June, 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May, 1966.
D. Babin, “Designing Crystal Oscillators”, Machine Design,
March 7, 1985.
D. Babin, “Guidelines for Crystal Oscillator Design”, Machine Design, April 25, 1985.
÷
÷
Figure 13. Timing Diagram for Minimum Divide Value (N = 16)
Page 9 of 10
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Issue A
ML145159
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
PLASTIC DIP 20 = RP
(MC145159RP)
CASE 738-03
-A20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
C
-T-
L
K
SEATING
PLANE
M
E
G
N
F
J 20 PL
0.25 (0.010)
D 20 PL
0.25 (0.010)
M
T
A
M
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
1.070
1.010
0.260
0.240
0.180
0.150
0.022
0.015
0.050 BSC
0.070
0.050
0.100 BSC
0.015
0.008
0.140
0.110
0.300 BSC
15°
0°
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0°
15°
1.01
0.51
MAX
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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Issue A
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