MOTOROLA MC145443P Single-chip 300-baud modem Datasheet

Order this document
by MC145442/D
SEMICONDUCTOR TECHNICAL DATA
The MC145442 and MC145443 silicon–gate CMOS single–chip low–speed
modems contain a complete frequency shift keying (FSK) modulator, demodulator, and filter. These devices are with CCITT V.21 (MC145442) and Bell 103
(MC145443) specifications. Both devices provide full–duplex or half–duplex
300–baud data communication over a pair of telephone lines. They also include
a carrier detect circuit for the demodulator section and a duplexer circuit for
direct operation on a telephone line through a simple transformer.
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•
MC145442 Compatible with CCITT V.21
MC145443 Compatible with Bell 103
Low–Band and High–Band Band–Pass Filters On–Chip
Simplex, Half–Duplex, and Full–Duplex Operation
Originate and Answer Mode
Analog Loopback Configuration for Self Test
Hybrid Network Function On–Chip
Carrier Detect Circuit On–Chip
Adjustable Transmit Level and CD Delay Timing
On–Chip Crystal Oscillator (3.579 MHz)
Single + 5 V Power Supply Operation
Internal Mid–Supply Generator
Power–Down Mode
Pin Compatible with MM74HC943
Capable of Driving – 9 dBm into a 600 Ω Load
P SUFFIX
PLASTIC DIP
CASE 738
20
1
DW SUFFIX
SOG PACKAGE
CASE 751D
20
1
ORDERING INFORMATION
MC145442P
MC145443P
Plastic DIP
Plastic DIP
MC145442DW SOG Package
MC145443DW SOG Package
PIN ASSIGNMENT
DSI
1
20
TLA
LB
2
19
VAG
CD
3
18
Exl
CDT
4
17
TxA
RxD
5
16
RxA1
VDD
6
15
RxA2
CDA
7
14
SQT
Xout
8
13
MODE
Xin
9
12
VSS
FB
10
11
TxD
REV 1
8/95

Motorola, Inc. 1995
MOTOROLA
MC145442•MC145443
1
BLOCK DIAGRAM
RxA2
RxA1
4
7
LOW–BAND
BPF
15
–
+
16
AAF
CARRIER 3
DETECT
S/H
AC AMP
HIGH–BAND
BPF
LB
MODE
SQT
TxD
TLA
Xout
Xin
13
MODE
CONTROL
14
5
10
1
SMOOTHING
FILTER
2
DEMOD
*
–
17
+
18
CDT
CDA
CD
RxD
FB
DSI
TxA
ExI
11
MODULATOR
20
8
9
OSCILLATOR
INTERNAL
VAG
CLOCK
DIVIDER
SAMPLING CLOCK: 77.82 kHz
SAMPLING CLOCK: 19.46 kHz
ANALOG
GROUND
GENERATOR
19
6
12
VAG
VDD
VSS
* Refer to the FB pin description.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS)
Rating
Symbol
Supply Voltage
Value
Unit
VDD
– 0.5 to + 7.0
V
DC Input Voltage
Vin
– 0.5 to VDD + 0.5
V
DC Output Voltage
Vout
– 0.5 to VDD + 0.5
V
IIK, IOK
± 20
mA
DC Output Current, per Pin
Iout
± 28
mA
Power Dissipation
PD
500
mW
TA
– 40 to + 85
°C
Tstg
– 65 to + 150
°C
Clamp Diode Current, per Pin
Operating Temperature Range
Storage Temperature Range
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application
of any voltage higher than maximum rated
voltages to this high impedance circuit. For
proper operation it is recommended that Vin and
Vout be constrained to the range VSS ≤ (Vin or
Vout) ≤ VDD).
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD).
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
DC Input or Output Voltage
Input Rise or Fall Time
Crystal Frequency*
Symbol
Min
Max
Unit
VDD
4.5
5.5
V
Vin, Vout
0
VDD
V
tr, tf
—
500
ns
fcrystal
3.2
5.0
MHz
* Changing the crystal frequency from 3.579 MHz will change the output frequencies. The
change in output frequency will be proportional to the change in crystal frequency.
MC145442•MC145443
2
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (VDD = 5.0 V ± 10%, TA = – 40 to + 85°C)
Characteristic
Symbol
Min
Typ
Max
Unit
High–Level Input Voltage
LB
Xin, TxD, Mode, SQT
VIH
VDD – 0.8
3.15
—
—
—
—
V
Low–Level Input Voltage
LB
Xin, TxD, Mode, SQT
VIL
—
—
—
—
0.8
1.1
V
VDD – 0.1
3.7
—
—
—
VDD – 0.05
—
—
—
—
—
—
—
—
0.05
0.1
0.4
—
Iin
—
—
—
—
10
—
± 1.0
± 12
± 10
µA
IDD
—
7
10
mA
High–Level Output Voltage
IOH = 20 µA
IOH = 2 mA
IOH = 20 µA
CD, RxD
CD, RxD
Xout
VOH
Low–Level Output Voltage
IOL = 20 µA
IOL = 2 mA
IOL = 20 µA
CD, RxD
CD, RxD
Xout
V
VOL
Input Current
LB, TxD, Mode, SQT
RxA1, RxA2
Xin
Quiesent Supply Current (Xin or fcrystal = 3.579 MHz)
V
—
200
300
µA
Cin
—
—
10
—
—
10
pF
VAG Output Voltage (IO = ± 10 µA)
VAG
2.4
2.5
2.6
V
CDA Output Voltage (IO = ± 10 µA)
VCDA
1.1
1.2
1.3
V
Rf
10
20
30
kΩ
Unit
Power–Down Supply Current
Input Capacitance
Xin
All Other Inputs
Line Driver Feedback Resistor
AC ELECTRICAL CHARACTERISTICS
(VDD = 5.0 V ± 10%, TA = – 40 to + 85°C, Crystal Frequency = 3.579 MHz ± 0.1%; See Figure 1)
Characteristic
Min
Typ
Max
– 13
– 10
– 12
–9
– 11
–8
—
– 56
—
dBm
40
50
—
kΩ
TRANSMITTER
Power Output on TxA
RL = 1.2 kΩ, RTLA = ∞
RL = 1.2 kΩ, RTLA = 5.5 kΩ
dBm
Second Harmonic Power
RL = 1.2 kΩ
RECEIVE FILTER AND HYBRID
Hybrid Input Impedance RxA1, RxA2
FB Output Impedance
—
16
—
kΩ
– 48
—
—
dBm
– 48
—
– 12
dBm
Dynamic Range
—
36
—
dB
Bit Jitter (S/N = 30 dB, Input = – 38 dBm, Bit Rate = 300 baud)
—
100
—
µs
Bit Bias
—
5
—
%
—
—
– 44
– 47
—
—
dBm
Adjacent Channel Rejection
DEMODULATOR
Receive Carrier Amplitude
Carrier Detect Threshold
(CDA = 1.2 V or CDA grounded through a 0.1 µF capacitor)
MOTOROLA
On to Off
Off to On
MC145442•MC145443
3
3.579 MHz ± 0.1%
RTLA
VDD
600 Ω
600 Ω
TEST
INPUT
8
9
Xout
Xin
20
TLA
TxD
17
TxA
15
RxA2
MC145442
MC145443
16
Table 1. Bell 103 and CCITT V.21
Frequency Characteristics
Originate Mode
11
5
RxD
FB
10
0.1 µF
RxA1
TEST
CDT
OUTPUT 4
0.1 µF
CCDT
Data
Din
Receive
Transmit
Receive
Bell 103 (MC145443)
Space
1070 Hz
2025 Hz
2025 Hz
1070 Hz
Mark
1270 Hz
2225 Hz
2225 Hz
1270 Hz
CCITT V.21 (MC145442)
Dout
CFB
VDD
Positive Power Supply (Pin 6)
This pin is normally tied to 5.0 V.
VSS
Negative Power Supply (Pin 12)
This pin is normally tied to 0 V.
VAG
Analog Ground (Pin 19)
Analog ground is internally biased to (VDD – VSS) / 2. This
pin must be decoupled by a capacitor from VAG to VSS and a
capacitor from VAG to VDD. Analog ground is the common
bias line used in the switched capacitor filters, limiter, and
slicer in the demodulation circuitry.
TLA
Transmit Level Adjust (Pin 20)
This pin is used to adjust the transmit level. Transmit level
adjustment range is typically from – 12 dBm to – 9 dBm. (See
Applications Information.)
TxD
Transmit Data (Pin 11)
Binary information is input to the transmit data pin. Data
entered for transmission is modulated using FSK techniques.
A logic high input level represents a mark and a logic low represents a space (see Table 1).
TxA
Transmit Carrier (Pin 17)
This is the output of the line driver amplifier. The transmit
carrier is the digitally synthesized sine wave output of the
modulator derived from a crystal oscillator reference. When a
3.579 MHz crystal is used the frequency outputs shown in
Table 1 apply. (See Applications Information.)
1180 Hz
1850 Hz
1850 Hz
1180 Hz
Mark
980 Hz
1650 Hz
1850 Hz
980 Hz
MAXIMUM LEVEL OF OUT–OF–BAND ENERGY
RELATIVE TO THE TRANSMIT CARRIER LEVEL INTO 600 Ω (kHz)
TRANSMIT CARRIER LEVEL (dBm)
PIN DESCRIPTIONS
Space
NOTE: Actual frequencies may be ± 5 Hz assuming 3.579545 MHz
crystal is used.
Figure 1. AC Characteristics Evaluation Circuit
MC145442•MC145443
4
Transmit
Answer Mode
0
2 3.4 4
16
64
256
0
– 20
– 25
15 dB/OCTAVE
– 55
– 60
Figure 2. Out–of–Band Energy
ExI
External Input (Pin 18)
The external input is the non–inverting input to the line
driver. It is provided to combine an auxiliary audio signal or
speech signal to the phone line using the line driver. This pin
should be connected to VAG if not used. The average level
must be the same as VAG to maintain proper operation. (See
Applications Information.)
DSI
Driver Summing Input (Pin 1)
The driver summing input may be used to connect an external signal, such as a DTMF dialer, to the phone line. A
series resistor, RDSI, is needed to define the voltage gain
AV (see Applications Information and Figure 6). When applying a signal to do DSI pin, the modulator should be
squelched by bringing SQT (Pin 14) to a logic high level. The
voltage gain, AV, is calculated by the formula AV = – Rf/RDSI
(where Rf ≈ 20 kΩ). For example, a 20 kΩ resistor for RDSI
will provide unity gain (AV = – 20 kΩ/20 kΩ = – 1). This pin
must be left open if not used.
RxD
Receive Data (Pin 6)
The receive data output pin presents the digital binary data
resulting from the demodulation of the receive carrier. If no
carrier is present, CD high, the receive data output (RxD) is
clamped high.
MOTOROLA
RxA2, RxA1
Receive Carrier (Pins 15, 16)
The receive carrier is the FSK input to the demodulator
through the receive band–pass filter. RxA1 is the non–inverting input and RxA2 is the inverting input of the receive hybrid
(duplexer) operational amplifier.
LB
Analog Loopback (Pin 2)
When a high level is applied to this pin (SQT must be low),
the analog loopback test is enabled. The analog loopback
test connects the TxA pin to the RxA2 pin and the RxA1 to
analog ground. In loopback, the demodulator frequencies
are switched to the modulation frequencies for the selected
mode. (See Tables 1 and 2 and Figures 4c and 4d.)
When LB is connected to analog ground (VAG), the modulator generates an echo cancellation tone of 2100 Hz for
MC145442 CCITT V.21 and 2225 Hz for MC145443 Bell 103
systems. For normal operation, this pin should be at a logic
low level (VSS).
The power–down mode is enabled when both LB and SQT
are connected to a logic high level (see Table 2).
Table 2. Functional Table
MODE
Pin 13
SQT
Pin 14
LB
Pin 2
1
0
0
Originate Mode
Answer Mode
Operating Mode
0
0
0
X
0
VAG (VDD/2)
X
0
1
Analog Loopback
X
1
0
Squelch Mode
X
1
VAG (VDD/2)
Squelch Mode
X
1
1
Echo Tone
Power Down
MODE
Mode (Pin 13)
This input selects the pair of transmit and frequencies
used during modulation and demodulation. When a logic
high level is placed on this input, originate (Bell) or channel 1
(CCITT) is selected. When a low level is placed on this input,
answer (Bell) or channel 2 (CCITT) is selected. (See
Tables 1 and 2 and Figure 4.)
by CDT, Pin 4). This pin is held at the logic low level until the
signal falls below the maximum threshold level for longer
than the turn off time. (See Applications Information and
Figure 5.)
CDA
Carrier Detect Adjust (Pin 7)
An external voltage may be applied to this pin to adjust the
carrier detect threshold. The threshold hysteresis is internally
fixed at 3 dB (see Applications Information).
Xout, Xin
Crystal Oscillator (Pins 8, 9)
A crystal reference oscillator is formed when a 3.579 MHz
crystal is connected between these two pins. Xout (Pin 8) is
the output of the oscillator circuit, and Xin (Pin 9) is the input
to the oscillator circuit. When using an external clock, apply
the clock to the Xin (Pin 9) pin and leave Xout (Pin 8) open. An
internal 10 MΩ resistor and internal capacitors, typically
10 pF on Xin and 16 pF on Xout, allow the crystal to be connected without any other external components. Printed circuit board layout should keep external stray capacitance to a
minimum.
FB
Filter Bias (Pin 10)
This is the negative input to the ac amplifier. In normal operation, this pin is connected to analog ground through a
0.1 µF bypass capacitor in order to cancel the input offset
voltage of the limiter. It has a nominal input impedance of
16 kΩ. (see Figure 3).
SQT
Transmit Squelch (Pin 14)
When this input pin is at a logic high level, the modulator is
disabled. The line driver remains active if LB is at a logic low
level (see Table 2) .
When both LB and SQT are connected to a logic high
level, see Table 2, the entire chip is in a power down state
and all circuitry except the crystal oscillator is disabled. Total
power supply current decreases from 10 mA (Max) to 300 µA
(Max).
FROM
BAND–PASS
FILTER
–
CDT
Carrier Detect Timing (Pin 4)
490 kΩ
A capacitor on this pin to VSS sets the amount of time the
carrier must be present before CD goes low (see Applications Information for the capacitor values).
CD
Carrier Detect Output (Pin 3)
This output is used to indicate when a carrier has been
sensed by the carrier detect circuit. This output goes to a
logic low level when a valid signal above the maximum
threshold level (defined by CDA, Pin 7) is maintained on the
input to the hybrid circuit longer then the response (defined
MOTOROLA
TO
CARRIER DETECT CIRCUIT
AND DEMODULATOR
+
16 kΩ
10
FB
0.1 µF
Figure 3. ac Amplifier Circuit
MC145442•MC145443
5
GENERAL DESCRIPTION
The MC145442 and MC145443 are full–duplex low–speed
modems. They provide a 300–baud FSK signal for bidirectional data transmission over the telephone network. They
can be operated in one of four basic configurations as determined by the state of MODE (Pin 13) and LB (Pin 2). The
normal (non–loopback) and self test (loopback) modes in
both answer and originate modes will be discussed.
For an originate or channel 1 mode, a logic high level is
placed on MODE (Pin 13) and a logic low level is placed on
LB (Pin 2). In this mode, transmit data is input on TxD, where
it is converted to a FSK signal and routed through a low–
band band–pass filter. The filtered output signal is then buffered by the Tx op–amp line driver, which is capable of driving
– 9 dBm onto a 600 Ω line. The receive signal is connected
through a hybrid duplexer circuit on Pins 15 and 16, RxA2
and RxA1. The signal then passes through the anti–aliasing
filter, the sample–and–hold circuit, is switched into the high–
band band–pass filter, and then switched into the ac amplifier
circuit. The output of the ac amplifier circuit is routed to the
demodulator circuit and demodulated. The resulting digital
data is then output through RxD (Pin 5). The carrier detect
circuit receives its signal from the output of the ac amplifier
circuit and goes low when the incoming signal is detected
(see Figure 4a).
MC145442•MC145443
6
In the answer or channel 2 mode, a logic low level is
placed on MODE (Pin 13) and on LB (Pin 2). In this mode,
the data follows the same path except the FSK signal is
routed to the high–band band–pass filter and the sample–
and–hold signal is routed through the low–band band–pass
filter. (See Figure 4b.)
In the analog loopback originate or channel 1 mode, a logic
high level is placed on MODE (Pin 13) and on LB (Pin 2).
This mode is used for a self check of the modulator, demodulator, and low–band pass–band filter circuit. The modulator
side is configured exactly like the originate mode above except the line driver output (TxA, Pin 17) is switched to the
negative input of the hybrid op–amp. The RxA2 input pin is
open in this mode and the non–inverting input of the hybrid
circuit is connected to VAG. The sample–and–hold output bypasses the filter so that the demodulator receives the modulated Tx data (see Figure 4c). This test checks all internal
device components except the high–band band–pass filter,
which can be checked in the answer or channel 2 mode test.
In the analog loopback or channel 2 mode, a logic low level
is placed on MODE (Pin 13) and a logic high level on LB
(Pin 2). This mode is used for a self check of the modulator,
demodulator, and high–band pass–band filter circuit. This
configuration is exactly like the originate loopback mode
above, except the signal is routed through the high–band
pass–band filter (see Figure 4d).
MOTOROLA
RxA2
15
–
RxA1
16
AAF
+
AC
AMP
LOW–BAND
BPF
S/H
3
CARRIER
DETECT
5
DEMOD
1
TxD
11
SMOOTHING
FILTER
HIGH–BAND
BPF
MODULATOR
–
17
+
18
CD
RxD
DSI
TxA
Exl
(a) Originate/Channel 1 Mode (MODE = High, LB = Low)
RxA2
15
–
RxA1
16
AAF
+
LOW–BAND
BPF
S/H
CARRIER
DETECT
AC
AMP
3
5
DEMOD
1
TxD
11
HIGH–BAND
BPF
MODULATOR
SMOOTHING
FILTER
–
17
+
18
CD
RxD
DSI
TxA
Exl
(b) Answer/Channel 2 Mode (MODE = Low, LB = Low)
RxA2
15
–
RxA1 16
+
AAF
S/H
LOW–BAND
BPF
AC
AMP
CARRIER
DETECT
DEMOD
3
5
1
TxD
11
MODULATOR
HIGH–BAND
BPF
SMOOTHING
FILTER
–
17
+
18
CD
RxD
DSI
TxA
Exl
(c) Originate/Channel 1 Mode and Analog Loopback State (MODE = High, LB = Low)
RxA2
15
–
RxA1
16
+
AAF
S/H
LOW–BAND
BPF
AC
AMP
CARRIER
DETECT
DEMOD
3
5
1
TxD
11
MODULATOR
HIGH–BAND
BPF
SMOOTHING
FILTER
–
17
+
18
CD
RxD
DSI
TxA
Exl
(d) Answer/Channel 2 Mode and Analog Loopback State (MODE = Low, LB = Low)
Figure 4. Basic Operating Modes
MOTOROLA
MC145442•MC145443
7
APPLICATIONS INFORMATION
CARRIER DETECT TIMING ADJUSTMENT
The value of a capacitor, CCDT at CDT (Pin 4) determines
how long a received modem signal must be present above
the minimum threshold level before CD (Pin 3) goes low. The
CCDT capacitor also determines how long the CD pin stays
low after the received modem signal goes below the minimum threshold. The CD pin is used to distinguish a strong
modem signal from random noise. The following equations
show the relationship between tCDL, the time in seconds required for CD to go low; tCDH, the time in seconds required
for CD to go high; and CCDT, the capacitor value in µF.
Valid signal to CD response time: tCDL ≈ 6.4 × CCDT
Invalid signal to CD off time:
tCDH ≈ 0.54 × CCDT
Example: tCDL ≈ 6.4 × 0.1 µF ≈ 0.64 seconds
tCDH ≈ 0.54 × 0.1 µF ≈ 0.054 seconds
20) to V DD (Pin 6). Table 3 shows the RTLA values and the
corresponding power output for a 600 Ω load. The voltage at
TxA is twice the value of that at ring and tip because TxA
feeds the signal through a 600 Ω resistor RTx to a 600 Ω line
transformer (see Figure 7). When choosing resistor RTLA,
keep in mind that – 9 dBm is the maximum output level allowed from a modem onto the telephone line (in the U.S.). In
addition, keep in mind that maximizing the power output from
the modem optimizes the signal–to–noise ratio, improving
accurate data transmission.
Table 3. Transmit Level Adjust
Output Transmit Level
(Typical into 600 Ω)
RTLA
– 12 dBm
– 11 dBm
– 10 dBm
– 9 dBm
∞
19.8 kΩ
9.2 kΩ
5.5 kΩ
CARRIER DETECT THRESHOLD ADJUSTMENT
The carrier detect threshold is set by internal resistors to
activate CD with a typical – 44 dBm (into 600 Ω) signal and
deactivate CD with a typical – 47 dBm signal applied to the
input of the hybrid circuit. The carrier detect threshold level
can be adjusted by applying an external voltage on CDA
(Pin 7). The following equations may be used to find the CDA
voltage required for a given threshold voltage. (Von and Voff
are in Vrms.)
VCDA = 244 × Von
VCDA = 345 × Voff
Example (Internally Set)
Von = 4.9 mV ≈ – 44 dBm: VCDA = 244 × 4.9 mV = 1.2 V
Voff = 3.5 mV ≈ – 47 dBm: VCDA = 345 × 3.5 mV = 1.2 V
Example (Externally Set)
Von = 7.7 mV ≈ – 40 dBm: VCDA = 244 × 7.7 mV = 1.9 V
Voff = 5.4 mV ≈ – 43 dBm: VCDA = 345 × 5.4 mV = 1.9 V
The CDA pin has an approximate Thevenin equivalent
voltage of 1.2 V and an output impedance of 100 kΩ. When
using the internal 1.2 V reference a 0.1 µF capacitor should
be connected between this pin and VSS (see Figure 5).
TRANSMIT LEVEL ADJUSTMENT
The power output at TxA (Pin 17) is determined by the
value of resistor RTLA that is connected between TLA (Pin
MC145442•MC145443
8
THE LINE DRIVER
The line driver is a power amplifier used for driving the
telephone line. Both the inverting and noninverting input to
the line driver are available for transmitting externally generated tones.
Exl (Pin 18) is the noninverting input to the line driver and
gives a fixed gain of 2 (Ri = 50 kΩ). The average signal level
must be the same as VAG to maintain proper operation. This
pin should be connected to VAG if not used.
The driver summing input (DSI, Pin 1) may be used to connect an external signal, such as a DTMF dialer, to the phone
line. When applying a signal to the DSI pin, the modulator
should be squelched by bringing SQT (Pin 14) to a logic high
level. DSI must be left open if not used.
In addition, the DSI pin is the inverting side of the line driver and allows adjustable gain with a series resistor RDSI (see
Figure 6). The voltage gain, AV, is determined by the
equation:
AV = –
Rf
RDSI
where Rf ≈ 20 kΩ.
Example: A resistor value of 20 kΩ for RDSI will provide
unity gain.
AV = – (20 kΩ/20 kΩ) = – 1
MOTOROLA
VDD
HYBRID
ac
AMP
16
AUTO–NULLED
COMPARATOR
6 ms
RETRIGGERABLE
ONE–SHOT
RxA1
3
CD
Vref
7
CDA
VCDA ≈ 1.2 V
SAMPLING
CLOCK
THRESHOLD
CONTROL
4
CCDA
0.1 µF
CDT
CCDT
0.1 µF
Figure 5. Carrier Detect Circuit
MODULATOR
OUTPUT
R0 = Rf
RDSI
DSI
1
R0
Rf
ExI
18
VAG
19
–
TxA
17
+
Ri
Figure 6. Line Driver Using the DSI Input
MOTOROLA
MC145442•MC145443
9
+5V
0.1 µF
6
VDD
Xin
20
RDSI
DTMF
INPUT
20 kΩ
10 Ω
TIP
TLA
RTLA
1
DSI
17
0.1 µF
TxA
15
RxA2
RTx
MC145442/3
10 µF 600 Ω
+
16
RxA1
CDSI
Xout
9
1
3.58
MHz
8
CD
TxD
RxD
15
10 kΩ
VDD
0.1 µF
18
CFB
10
0.1 µF 19
Exl
LB
FB
VAG
CDT
0.1 µF
4
CCDT
0.1 µF
13
17
VDD
19
VCC
C1+
C1+
C1–
C1–
GND
18
EIA–232–D
DB–25
CONNECTOR
MMBZ15VDLT1 X 3
DI2
Tx2
2
Rx1
DI1
8
10
DO1 MC145407
TxEN
Tx1
STBY
Rx2
10 kΩ
Rx3
MODE
12
20
6
3
10 kΩ
RING
3
11
SQT
*
0.1 µF
0.1 µF
CDA
GND
VSS
7
2
4
8
7
7
9
CCDA
0.1 µF
* Line Protection Circuit
Figure 7. Typical MC145442/MC145443 Applications Circuit
MC145442•MC145443
10
MOTOROLA
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP
CASE 738–03
-A20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
C
-T-
L
K
SEATING
PLANE
M
E
N
G
F
J 20 PL
0.25 (0.010)
D 20 PL
0.25 (0.010)
M
T A
M
M
T
B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010 1.070
0.240 0.260
0.150 0.180
0.015 0.022
0.050 BSC
0.050 0.070
0.100 BSC
0.008 0.015
0.110 0.140
0.300 BSC
15°
0°
0.020 0.040
MILLIMETERS
MIN
MAX
25.66 27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0°
15°
1.01
0.51
DW SUFFIX
SOG PACKAGE
CASE 751D–04
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
20
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R
C
–T–
18X
MOTOROLA
G
K
SEATING
PLANE
X 45 _
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
M
MC145442•MC145443
11
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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MC145442•MC145443
12
◊
*MC145442/D*
MC145442/D
MOTOROLA
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