LANSDALE MC145503DW Pcm codec-filter mono-circuit Datasheet

ML145502
ML145503
ML145505
PCM Codec–Filter Mono–Circuit
Legacy Device: Motorola MC145502, MC145503, MC145505
The ML145502, ML145503, and ML145505 are all per channel PCM
Codec–Filter mono–circuits. These devices perform the voice digitization
and reconstruction as well as the band limiting and smoothing required
for PCM systems. The ML145503 is a general purpose device that is
offered in a 16–pin package. These are designed to operate in both synchronous and asynchronous applications and contain an on–chip precision reference voltage. The ML145505 is a synchronous device offered in
a 16–pin DIP and wide body SOIC package intended for instrument use.
The ML145502 is the full–featured device which presents all of the
options of the chip. This device is packaged in a 22–pin DIP and a
28–pin chip carrier package
These devices are pin–for–pin replacements for Motorola’s first generation of MC14400/01/02/03/05 PCM mono–circuits and are upwardly
compatible with the MC14404/06/07 codecs and other industry standard
codecs. They also maintain compatibility with Motorola’s family of
MC33120 and MC3419 SLIC products.
The ML1455xx family of PCM Codec–Filter mono–circuits utilizes
CMOS due to its reliable low–power performance and proven capability
for complex analog/digital VLSI functions.
ML145502
• 22 Pin and 28 Pin Packages
• Transmit Bandpass and Receive Low–Pass Filter On–Chip
• Pin Selectable Mu–Law/A–Law Companding with Corresponding
Data Format
• On–Chip Precision Reference Voltage (3.15 V)
• Power Dissipation of 50 mW, Power–Down of 0.1 mW at ±5 V
• Automatic Prescaler Accepts 128 kHz, 1.536, 1.544, 2.048, and 2.56
MHz for Internal Sequencing
• Selectable Peak Overload Voltages (2.5, 3.15, 3.78 V)
• Access to the Inverting Input of the TxI Input Operational Amplifier
• Variable Data Clock Rates (64 kHz to 4.1 MHz)
• Complete Access to the Three Terminal Transmit Input Operational
Amplifiers
• An External Precision Reference May Be Used
P DIP 16 = EP
PLASTIC DIP
CASE 648
16
1
22
1
P DIP 22 = WP
PLASTIC DIP
CASE 708
SOG 16 = -5P
SOG PACKAGE
CASE 751G
16
1
PLCC 28 = -4P
PLCC PACKAGE
CASE 776
28 1
CROSS REFERENCE/ORDERING INFORMATION
LANSDALE
PACKAGE
MOTOROLA
P DIP 22
PLCC 28
P DIP 16
SO 16W
P DIP 16
SO 16W
MC145502P
MC145502FN
MC145503P
MC145503DW
MC145505P
MC145505DW
ML145502WP
ML145502-4P
ML145503EP
ML145503-5P
ML145505EP
ML145505-5P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
ML145503— Similar to the ML145502 Plus:
• 16–Pin Dip and SOIC 16 Packages
• Complete Access to the Three Terminal Transmit Input Operational
Amplifiers
ML145505 — Somewhat Similar To ML145503 Except:
• Common 64 kHz to 4.1 MHz Transmit/Receive Data Clock
Page 1 of 26
www.lansdale.com
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ML145502/03/05 PCM CODEC–FILTER MONO–CIRCUIT BLOCK DIAGRAM
RDD
1
RxO
D/A
FREQUENCY
Rx
RECEIVE SHIFT
REGISTER
RCE
÷ 1, 12, 16, 20
CCI PRESCALER
CCI
RDC
RxG
Rx
–
VDD
SHARED
DAC
400 µA
RxO
+
VDD
VSS
VAG
+
2.5 V
REF
–
VSS
Vref
RSI
TxI
– Tx
–
NOTES:
Page 2 of 26
+
SEQUENCE
AND
CONTROL
VLS
TRANSMIT SHIFT
REGISTER
TDD
PDI
RSI
CIRCUITRY
A/D
+ Tx
MSI
FREQUENCY
FREQUENCY
TDE
TDC
Controlled by VLS
Rx ≈ 100 kΩ (internal resistors)
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Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
PIN ASSIGNMENTS
(DRAWINGS DO NOT REFLECT RELATIVE SIZE)
ML145505EP
VAG
1
16
VDD
VAG
1
16
VDD
RxO
2
15
RDD
RxO
2
15
RDD
+ Tx
3
14
RCE
+ Tx
3
14
RCE
TxI
4
13
RDC
TxI
4
13
DCLK
12
CCI
– Tx
5
12
TDC
– Tx
5
Mu/A
6
11
TDD
Mu/A
6
11
TDD
PDI
7
10
TDE
PDI
7
10
TDE
VSS
8
9
VLS
VSS
8
9
VLS
ML145505-5P
ML145502-4P
Vref
1
22
RSI
VAG
1
16
VDD
VAG
1
16
VDD
VAG
2
21
VDD
RxO
2
15
RDD
RxO
2
15
RDD
RxO
3
20
RDD
+ Tx
3
14
RCE
+ Tx
3
14
RCE
RxG
4
19
RCE
TxI
4
13
RDC
TxI
4
13
DCLK
RxO
5
18
RDC
– Tx
5
12
TDC
– Tx
5
12
CCI
+ Tx
6
17
TDC
Mu/A
6
11
TDD
Mu/A
6
11
TDD
TxI
7
16
CCI
PDI
7
10
TDE
PDI
7
10
TDE
VSS
8
9
VSS
8
9
VLS
– Tx
8
15
TDD
Mu/A
9
14
TDE
PDI
10
13
MSI
VSS
11
12
VLS
Page 3 of 26
VLS
RxO
VAG
Vref
NC
RSI
VDD
RDD
ML145503-5P
ML145502WP
RxG
RxO
+ Tx
NC
NC
TxI
– Tx
4 3 2 1 28 27 26
5
25
24
6
7
23
22
8 28–PIN PQLCC
(TOP VIEW)
9
21
20
10
11
19
12 13 14 15 16 17 18
RCE
RDC
TDC
NC
NC
CCI
TDD
Mu/A
PDI
VSS
NC
V LS
MSI
TDE
ML145503EP
NC = NO CONNECTION
www.lansdale.com
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to VSS)
Rating
Symbol
Value
Unit
VDD, VSS
– 0.5 to 13
V
Voltage, Any Pin to VSS
V
– 0.5 to VDD + 0.5
V
DC Drain Per Pin (Excluding VDD, VSS)
I
10
mA
TA
– 40 to + 85
°C
Tstg
– 85 to + 150
°C
DC Supply Voltage
Operating Temperature Range
Storage Temperature Range
RECOMMENDED OPERATING CONDITIONS (TA = – 40 to + 85°C)
This device contains circuitry to protect
against damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit. For
proper operation it is recommended that Vin
and Vout be constrained to the range VSS (Vin
or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., VSS, VDD,
VLS, or VAG).
Min
Typ
Max
4.75
5.0
6.3
8.5
—
12.6
7.0
9.5
4.75
—
—
—
12.6
12.6
12.6
Power Dissipation
CMOS Logic Mode (VDD to VSS = 10 V, VLS = VDD)
TTL Logic Mode (VDD = + 5 V, VSS = – 5 V, VLS = VAG = 0 V)
—
—
40
50
70
90
Power Down Dissipation
—
0.1
1.0
mW
Frame Rate Transmit and Receive
7.5
8.0
8.5
kHz
Data Rate
ML145503
Must Use One of These Frequencies, Relative to MSI Frequency of 8 kHz
—
—
—
—
—
128
1536
1544
2048
2560
—
—
—
—
—
kHz
Data Rate for ML145502, ML145505
64
—
4096
kHz
—
—
—
—
—
—
—
3.15
3.78
3.15
2.5
1.51 x Vref
1.26 x Vref
Vref
—
—
—
—
—
—
—
Characteristic
DC Supply Voltage
Dual Supplies: VDD = – VSS, (VAG = VLS = 0 V)
Single Supply: VDD to VSS (VAG is an Output, VLS = VDD or VSS)
ML145502, ML145503, ML145505 (Using Internal 3.15 V Reference)
V
ML145502 Using Internal 2.5 V Reference
ML145502 Using Internal 3.78 V Reference
ML145502 Using External 1.5 V Reference, Referenced to V AG
Full Scale Analog Input and Output Level
ML145503, ML145505
ML145502 (Vref = VSS )
Unit
mW
Vp
ML145502 Using an External Reference V oltage Applied at Vref Pin
RSI = VDD
RSI = VSS
RSI = VAG
RSI = VDD
RSI = VSS
RSI = VAG
DIGITAL LEVELS (VSS to VDD = 4.75 V to 12.6 V, TA = – 40 to + 85°C)
Characteristic
Input Voltage Levels (TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI, PDI)
CMOS Mode (VLS = VDD, VSS is Digital Ground)
TTL Mode (VLS ≤ VDD – 4.0 V, VLS is Digital Ground)
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Min
Max
VIL
VIH
VIL
VIH
—
0.7 x VDD
—
VLS + 2.0 V
0.3 x VDD
—
VLS + 0.8 V
—
Unit
V
“0”
“1”
“0”
“1”
Output Current for TDD (Transmit Digital Data)
CMOS Mode (VLS = VDD, VSS = 0 V and is Digital Ground)
(VDD = 5 V, Vout = 0.4 V)
(VDD = 10 V, Vout = 0.5 V)
(VDD = 5 V, Vout = 4.5 V)
(VDD = 10 V, Vout = 9.5 V)
TTL Mode (VLS ≤ VDD – 4.75 V, VLS = 0 V and is Digital Ground)
(VOL = 0.4 V)
(VOH = 2.4 V)
Page 4 of 26
Symbol
mA
IOL
IOH
IOL
IOH
1.0
3.0
– 1.0
– 3.0
1.6
– 0.2
—
—
—
—
—
—
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ANALOG TRANSMISSION PERFORMANCE
(VDD = + 5 V ± 5%, VSS = – 5 V ± 5%, VLS = VAG = 0 V, Vref = RSI = VSS (Internal 3.15 V Reference), 0 dBm0 = 1.546 Vrms = + 6 dBm @
600 Ω, TA = – 40 to + 85°C, TDC = RDC = CC = 2.048 MHz, TDE = RCE = MSI = 8 kHz, Unless Otherwise Noted)
End–to–End
A/D
D/A
Characteristic
Min
Max
Min
Max
Min
Max
Unit
Absolute Gain (0 dBm0 @ 1.02 kHz, TA = 25°C, VDD = 5 V, VSS = – 5 V)
—
—
– 0.30
+ 0.30
– 0.30
+ 0.30
dB
Absolute Gain Variation with Temperature 0 to + 70°C
—
—
—
± 0.03
—
± 0.03
dB
Absolute Gain Variation with Temperature – 40 to +85°C
—
—
—
± 0.1
—
± 0.1
dB
—
—
—
± 0.02
—
± 0.02
dB
– 0.4
– 0.8
– 1.6
+ 0.4
+ 0.8
+ 1.6
– 0.2
– 0.4
– 0.8
+ 0.2
+ 0.4
+ 0.8
– 0.2
– 0.4
– 0.8
+ 0.2
+ 0.4
+ 0.8
dB
—
—
—
—
—
—
– 0.25
– 0.30
– 0.45
+ 0.25
+ 0.30
+ 0.45
– 0.25
– 0.30
– 0.45
+ 0.25
+ 0.30
+ 0.45
35
29
24
—
—
—
36
29
24
—
—
—
36
30
25
—
—
—
dBC
27.5
35
33.1
28.2
13.2
—
—
—
—
—
28
35.5
33.5
28.5
13.5
—
—
—
—
—
28.5
36
34.2
30.0
15.0
—
—
—
—
—
dB
—
—
15
– 69
—
—
15
– 69
—
—
9
– 78
dBrnC0
dBm0p
—
– 0.3
– 1.6
—
—
– 23
+ 0.3
0
– 28
– 60
—
– 0.15
– 0.8
—
—
– 23
+ 0.15
0
– 14
– 32
—
– 0.15
– 0.8
—
—
0.15
+ 0.15
0
– 14
– 30
dB
—
—
—
– 43
—
– 43
dBm0
Out–of–Band Spurious at RxO (300 – 3400 Hz @ 0 dBm0 In)
4600 to 7600 Hz
7600 to 8400 Hz
8400 to 100,000 Hz
—
—
—
– 30
– 40
– 30
—
—
—
—
—
—
—
—
—
– 30
– 40
– 30
Idle Channel Noise Selective @ 8 kHz, Input = VAG, 30 Hz Bandwidth
—
– 70
—
—
—
– 70
dBm0
Absolute Delay @ 1600 Hz (TDC = 2.048 MHz, TDE = 8 kHz)
—
—
—
310
—
180
µs
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
200
140
70
40
75
110
170
– 40
– 40
– 30
– 20
—
—
—
—
—
—
—
90
120
160
Crosstalk of 1020 Hz @ 0 dBm0 From A/D or D/A (Note 2)
—
—
—
– 75
—
– 80
dB
Intermodulation Distortion of Two Frequencies of Amplitudes – 4 to
– 21 dBm0 from the Range 300 to 3400 Hz
—
—
—
– 41
—
– 41
dB
Absolute Gain Variation with Power Supply (VDD = 5 V, VSS = – 5 V, 5%)
Gain vs Level Tone (Relative to – 10 dBm0, 1.02 kHz)
+ 3 to – 40 dBm0
– 40 to – 50 dBm0
– 50 to – 55 dBm0
Gain vs Level Pseudo Noise (A–Law Relative to – 10 dBm0)
CCITT G.714
– 10 to – 40 dBm0
– 40 to – 50 dBm0
– 50 to – 55 dBm0
Total Distortion – 1.02 kHz Tone (C–Message)
Total Distortion With Pseudo Noise (A–Law)
CCITT G.714
0 to – 30 dBm0
– 40 dBm0
– 45 dBm0
– 3 dBm0
– 6 to – 27 dBm0
– 34 dBm0
– 40 dBm0
– 55 dBm0
Idle Channel Noise (For End–End and A/D, See Note 1)
Mu–Law, C–Message Weighted
A–Law, Psophometric Weighted
Frequency Response (Relative to 1.02 kHz @ 0 dBm0)
15 to 60 Hz
300 to 3000 Hz
3400 Hz
4000 Hz
4600 Hz
Inband Spurious (1.02 kHz @ 0 dBm0, Transmit and RxO)
dB
300 to 3000 Hz
Group Delay Referenced to 1600 Hz (TDC = 2048 kHz,
TDE = 8 kHz)
dB
µs
500 to 600 Hz
600 to 800 Hz
800 to 1000 Hz
1000 to 1600 Hz
1600 to 2600 Hz
2600 to 2800 Hz
2800 to 3000 Hz
NOTES:
1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement.
2. Selectively measured while the A/D is stimulated with 2667 Hz @ – 50 dBm0.
Page 5 of 26
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Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ANALOG ELECTRICAL CHARACTERISTICS (VDD = – VSS = 5 V to 6 V 5%, TA = – 40 to + 85°C)
Characteristic
Symbol
Min
Typ
Max
Unit
Input Current
+Tx, –Tx
Iin
—
± 0.01
± 0.2
µA
AC Input Impedance to VAG (1 kHz)
+Tx, –Tx
Zin
5
10
—
—
MΩ
Input Capacitance
+Tx, –Tx
—
—
10
pF
—
< ± 30
—
mV
Input Offset Voltage of Txl Op Amp
Input Common Mode Voltage Range
+Tx, –Tx
VICR
VSS + 1.0
—
VDD – 2.0
V
Input Common Mode Rejection Ratio
+Tx, –Tx
CMRR
—
70
—
dB
1000
—
kHz
Txl Unity Gain Bandwidth
RL ≥ 10 kΩ
BWp
—
Txl Open Loop Gain
RL ≥ 10 kΩ
AVOL
—
75
—
dB
Equivalent Input Noise (C–Message) Between +Tx and –Tx, at Txl
—
– 20
—
dBrnC0
Output Load Capacitance for Txl Op Amp
0
—
100
pF
VSS + 0.8
VSS + 1.5
—
—
VDD – 1.0
VDD – 1.5
± 5.5
—
—
mA
—
3
—
Ω
0
—
200
pF
—
—
—
—
± 100
± 150
mV
Internal Gainsetting Resistors for RxG to RxO and RxO
62
100
225
kΩ
External Reference Voltage Applied to Vref (Referenced to VAG)
0.5
—
VDD – 1.0
V
Vref Input Current
—
—
20
µA
VAG Output Bias Voltage
—
0.53 VDD +
0.47 VSS
—
V
0.4
10.0
—
—
0.8
—
mA
Output Leakage Current During Power Down for the Txl Op Amp, VAG,
RxO, and RxO
—
—
± 30
µA
Positive Power Supply Rejection Ratio,
0 – 100 kHz @ 250 mV, C–Message Weighting
Transmit
Receive
45
55
50
65
—
—
dBC
Negative Power Supply Rejection Ratio,
0 – 100 kHz @ 250 mV, C–Message Weighting
Transmit
Receive
50
50
55
60
—
—
dBC
Output Voltage Range Txl Op Amp, RxO or RxO
RL = 10 kΩ to VAG
RL = 600 Ω to VAG
Vout
Output Current Txl, RxO, RxO
VSS + 1.5 V ≤ Vout ≤ VDD – 1.5 V
Output Impedance RxO, RxO*
0 to 3.4 kHz
Zout
Output Load Capacitance for RxO and RxO*
Output dc Offset Voltage Referenced to VAG Pin
VAG Output Current
RxO
RxO*
Source
Sink
IVAG
V
* Assumes that RxG is not connected for gain modifications to RxO.
Page 6 of 26
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Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
MODE CONTROL LOGIC (VSS to VDD = 4.75 V to 12.6 V, TA = – 40 to + 85°C)
Characteristic
Min
Typ
Max
Unit
VSS
—
VDD – 4.0
V
VLS Voltage for CMOS Mode (CMOS Logic Levels of VSS to VDD)
VDD – 0.5
—
VDD
V
Mu/A Select Voltage
Mu–Law Mode
Sign Magnitude Mode
A–Law Mode
VDD – 0.5
VAG – 0.5
VSS
—
—
—
VDD
VAG + 0.5
VSS + 0.5
3.78 V Mode
2.5 V Mode
3.15 V Mode
VDD – 0.5
VAG – 0.5
VSS
—
—
—
VDD
VAG + 0.5
VSS + 0.5
Vref Voltage for Internal or External Reference (ML145502 Only)
Internal Reference Mode
External Reference Mode
VSS
VAG + 0.5
—
—
VSS + 0.5
VDD – 1.0
—
128
—
VLS Voltage for TTL Mode (TTL Logic Levels Referenced to VLS)
V
RSI Voltage for Reference Select Input (ML145502)
Analog Test Mode Frequency, MS = CCI (ML145502 Only)
See Pin Description; Test Modes
V
V
kHz
SWITCHING CHARACTERISTICS (VSS to VDD = 9.5 V to 12.6 V, TA = – 40 to + 85°C, CL = 150 pF, CMOS or TTL Mode)
Characteristic
Symbol
Min
Typ
Max
Unit
TDD
tTLH
tTHL
—
—
30
30
80
80
ns
TDE, TDC, RCE, RDC, DC, MSI, CCI
tTLH
tTHL
—
—
—
—
4
4
µs
tw
100
—
—
ns
TDC, RDC, DC
fCL
64
—
4096
kHz
CCI Clock Pulse Frequency (MSI = 8 kHz)
CCI is internally tied to TDC on the ML145503, therefore, the
transmit data clock must be one of these frequencies. This pin will accept
one of these discrete clock frequencies and will compensate to produce
internal sequencing.
fCL1
fCL2
fCL3
fCL4
fCL5
—
—
—
—
—
128
1536
1544
2048
2560
—
—
—
—
—
kHz
tP1
—
—
—
—
—
—
—
—
90
90
—
—
90
90
90
90
180
150
55
40
180
150
180
150
Output Rise Time
Output Fall Time
Input Rise Time
Input Fall Time
Pulse Width
TDE Low, TDC, RCE, RDC, DC, MSI, CCI
DCLK Pulse Frequency (ML145502/05 Only)
Propagation Delay Time
TDE Rising to TDD Low Impedance
ns
TTL
CMOS
TTL
CMOS
TTL
CMOS
TTL
CMOS
TDE Falling to TDD High Impedance
TDC Rising Edge to TDD Data, During TDE High
TDE Rising Edge to TDD Data, During TDC High
tP2
tP3
tP4
TDC Falling Edge to TDE Rising Edge Setup Time
tsu1
20
—
—
ns
TDE Rising Edge to TDC Falling Edge Setup Time
tsu2
100
—
—
ns
TDE Falling Edge to TDC Rising Edge to Preserve the Next TDD Data
tsu8
20
—
—
ns
RDC Falling Edge to RCE Rising Edge Setup Time
tsu3
20
—
—
ns
RCE Rising Edge to RDC Falling Edge Setup Time
tsu4
100
—
—
ns
RDD Valid to RDC Falling Edge Setup Time
tsu5
60
—
—
ns
CCI Falling Edge to MSI Rising Edge Setup Time
tsu6
20
—
—
ns
MSI Rising Edge to CCI Falling Edge Setup Time
tsu7
100
—
—
ns
th
100
—
—
ns
RDD Hold Time from RDC Falling Edge
TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI Input Capacitance
—
—
10
pF
TDE,TDC, RCE, RDC, RDD, DC, MSI, CCI Input Current
—
± 0.01
± 10
µA
TDD Capacitance During High Impedance (TDE Low)
—
12
15
pF
TDD Input Current During High Impedance (TDE Low)
—
± 0.1
± 10.0
µA
Page 7 of 26
www.lansdale.com
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
DEVICE DESCRIPTIONS
A codec–filter is a device which is used for digitizing and reconstructing the human voice. These devices were developed primarily
for the telephone network to facilitate voice switching and transmission. Once the voice is digitized, it may be switched by digital
switching methods or transmitted long distance (T1, microwave,
satellites, etc.) without degradation. The name codec is an acronym
from “Coder” for the A/D used to digitize voice, and “Decoder” for
the D/A used for reconstructing voice. A codec is a single device
that does both the A/D and D/A conversions.
To digitize intelligible voice requires a signal to distortion of
about 30 dB for a dynamic range of about 40 dB. This may be
accomplished with a linear 13–bit A/D and D/A, but will far
exceed the required signal to distortion at amplitudes greater than
40 dB below the peak amplitude. This excess performance is at the
expense of data per sample. Two methods of data reduction are
implemented by compressing the 13–bit linear scheme to companded 8–bit schemes. These companding schemes follow a segmented
or “piecewise–linear”curve formatted as sign bit, three chord bits,
and four stepbits. For a given chord, all 16 of the steps have the
same voltage weighting. As the voltage of the analog input increases, the four step bits increment and carry to the three chord bits
which increment. With the chord bits incremented, the step bits
double their voltage weighting. This results in an effective resolution of 6–bits (sign + chord + four step bits) across a 42 dB dynamic range (7 chords above zero, by 6 dB per chord). There are two
companding schemes used; Mu–255 Law specifically in North
America, and A–Law specifically in Europe. These companding
schemes are accepted worldwide. The tables show the linear quantization levels to PCM words for the two companding schemes.
In a sampling environment, Nyquist theory says that to properly
sample a continuous signal, it must be sampled at a frequency higher than twice the signal’s highest frequency component. Voice contains spectral energy above 3 kHz, but its absence is not detrimental
to intelligibility. To reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 kHz was adopted, consistent with a band-width of 3 kHz. This sampling requires a low–pass
filter to limit the high frequency energy above 3 kHz from distorting the inband signal. The telephone line is also subject to 50/60 Hz
power line coupling which must be attenuated from the signal by a
high–pass filter before the A/D converter. The D/A process recon-
Page 8 of 26
structs a staircase version of the desired inband signal which has
spectral images of the in-band signal modulated about the sample
frequency and its harmonics. These spectral images are called aliasing components which need to be attenuated to obtain the desired
signal. The low–pass filter used to attenuate filter aliasing components is typically called a reconstruction or smoothing filter.
The ML1455XX series PCM Codec–Filters have the codec, both
presampling and reconstruction filters, a precision voltage reference on chip, and require no external components. There are three
distinct versions of the Lansdale ML1455XX Series.
ML145502
The ML145502 PCM Codec–Filter is the full feature 22–pin
device. It is intended for use in applications requiring maximum
flexibility. The ML145502 is intended for bit interleaved or byte
interleaved applications with data clock frequencies which are nonstandard or time varying. One of the five standard frequencies (see
ML145503 below) is applied to the CCI input, and the data clock
inputs can be any frequency between 64 kHz and 4.096 MHz. The
Vref pin allows for use of an external shared reference or selection
of the internal reference. The RxG pin accommodates gain adjustments for the inverted analog output. All three pins of the input
gain–setting operational amplifier are present, providing maximum
flexibility for the analog interface.
ML145503
The ML145503 PCM Codec–Filter is intended for standard byte
interleaved synchronous or asynchronous applications. TDC can be
one of five discrete frequencies. These are 128 kHz (40 to 60%
duty cycle), 1.536, 1.544, 2.048, or 2.56 MHz. (For other data
clock frequencies, see ML145502 or ML145505.) The internal reference is set for 3.15 V peak full scale, and the full scale input level
at Txl and output level at RxO is 6.3 V peak–to–peak. This is the +
3 dBm0 level of the PCM Codec–Filter. The +Tx and –Tx inputs
provide maximum flexibility for analog interface. All other functions are described in the pin description.
ML145505
The ML145505 PCM Codec–Filter is intended for byte interleaved synchronous applications. The ML145505 has all the features of the ML145503 but internally connects TDC and RDC (see
pin description) to the DC pin. One of the five standard frequencies
(listed above) should be applied to CCI. The data clock input
(DC) can be any frequency between 64 kHz and 4.096 MHz.
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PIN DESCRIPTIONS
DIGITAL
VLS
Logic Level Select input and TTL Digital Ground
VLS controls the logic levels and digital ground reference
for all digital inputs and the digital output. These devices can
operate with logic levels from full supply (VSS to VDD) or
with TTL logic levels using VLS as digital ground. For VLS =
VDD, all I/O is full supply (VSS to VDD swing) with CMOS
switch points. For VSS < VLS < (VDD – 4 V), all inputs and
outputs are TTL compatible with VLS being the digital
ground. The pins controlled by V are inputs MSI, CCI, TDE,
TDC, RCE, RDC, RDD, PDI, and output TDD.
MSI
Master Synchronization Input
MSI is used for determining the sample rate of the transmit
side and as a time base for selecting the internal prescale
divider for the convert clock input (CCI) pin. The MSI pin
should be tied to an 8 kHz clock which may be a frame sync
or system sync signal. MSI has no relation to transmit or
receive data timing, except for determining the internal transmit strobe as described under the TDE pin description. MSI
should be derived from the transmit timing in asynchronous
applications. In many applications MSI can be tied to TDE.
(MSI is tied internally to TDE in ML145503/05.)
CCI
Convert Clock Input
CCI is designed to accept five discrete clock frequencies.
These are 128 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or
2.56 MHz. The frequency at this input is compared with MSI
and prescale divided to produce the internal sequencing clock
at 128 kHz (or 16 times the sampling rate). The duty cycle of
CCI is dictated by the minimum pulse width except for 128
kHz, which is used directly for internal sequencing and must
have a 40 to 60% duty cycle. In asynchronous applications,
CCI should be derived from transmit timing. (CCI is tied
internally to TDC in ML145503.)
TDC
Transmit Data Clock Input
TDC can be any frequency from 64 kHz to 4.096 MHz, and
is often tied to CCI if the data rate is equal to one of the five
discrete frequencies. This clock is the shift clock for the transmit shift register and its rising edges produce successive data
bits at TDD. TDE should be derived from this clock. (TDC
and RDC are tied together internally in the ML145505 and are
called DC.) CCI is internally tied to TDC on the ML145503.
Therefore, TDC must satisfy CCI timing requirements also.
TDE
Transmit Data Enable Input
TDE serves three major functions. The first TDE rising
edge following an MSI rising edge generates the internal
transmit strobe which initiates an A/D conversion. The internal transmit strobe also transfers a new PCM data word into
the transmit shift register (sign bit first) ready to be output at
TDD. The TDE pin is the high impedance control for the
transmit digital data (TDD) output. As long as this pin is high,
the TDD output stays low impedance. This pin also enables
Page 9 of 26
the output shift register for clocking out the 8–bit serial PCM
word. The logical AND of the TDE pin with the TDC pinclocks out a new data bit at TDD. TDE should be held high
for eight consecutive TDC cycles to clock out a complete
PCM word for byte interleaved applications. The transmit shift
register feeds back on itself to allow multiple reads of the
transmit data. If the PCM word is clocked out once per frame
in a byte interleaved system, the MSI pin function is transparent and may be connected to TDE.
The TDE pin may be cycled during a PCM word for bit
interleaved applications. TDE controls both the high impedance state of the TDD output and the internal shift clock. TDE
must fall before TDC rises (tsu8) to ensure integrity of the
next data bit. There must be at least two TDC falling edges
between the last TDE rising edge of one frame and the first
TDE rising edge of the next frame. MSI must be available
separate from TDE for bit interleaved applications.
TDD
Transmit Digital Data Output
The output levels at this pin are controlled by the VLS pin.
For VLS connected to VDD, the output levels are from VSS to
VDD. For a voltage of VLS between VDD – 4 V and VSS, the
output levels are TTL compatible with VLS being the digital
ground supply. The TDD pin is a three–state output controlled
by the TDE pin. The timing of this pin is controlled by TDC
and TDE. When in TTL mode, this output may be made
high–speed CMOS compatible using a pull–up resistor. The
data format (Mu–Law, A–Law, or sign magnitude) is controlled by the Mu/A pin.
RDC
Receive Data Clock Input
RDC can be any frequency from 64 kHz to 4.096 MHz.
This pin is often tied to the TDC pin for applications that can
use a common clock for both transmit and receive data transfers. The receive shift register is controlled by the receive
clock enable (RCE) pin to clock data into the receive digital
data (RDD) pin on falling RDC edges. These three signals can
be asynchronous with all other digital pins. The RDC input is
internally tied to the TDC input on the ML145505 and called
DC.
RCE
Receive Clock Enable Input
The rising edge of RCE should identify the sign bit of a receive PCM word on RDD. The next falling edge of RDC, after
a rising RCE, loads the first bit of the PCM word into the receive register. The next seven falling edges enter the remainder of the PCM word. On the ninth rising edge, the receive
PCM word is transferred to the receive buffer register and the
A/D sequence is interrupted to commence the decode process.
In asynchronous applications with an 8 kHz transmit sample
rate, the receive sample rate should be between 7.5 and 8.5
kHz. Two receive PCM words may be decoded and analog
summed each transmit frame to allow on–chip conferencing.
The two PCM words should be clocked in as two single PCM
words, a minimum of 31.25 µs apart, with a receive data clock
of 512 kHz or faster.
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RDD
Receive Digital Data Input
RDD is the receive digital data input. The timing for this pin is
controlled by RDC and RCE. The data format is determined by the
Mu/A pin.
Mu/A
Select
This pin selects the companding law and the data format at TDD
and RDD.
Mu/A = VDD; Mu–255 Companding D3 Data Format with Zero
Code Suppress
Mu/A = VAG; Mu–255 Companding with Sign Magnitude
Data Format
Mu/A = VSS; A–Law Companding with CCITT Data Format
Bit Inversions
Code
Sign/
Magnitude
+ Full Scale
+ Zero
– Zero
– Full Scale
1111 1111
1000 0000
0000 0000
0111 1111
SIGN
BIT
0
1000
1111
0111
0000
CHORD BITS
1
2
A–Law
(CCITT)
Mu–Law
0000
1111
1111
0010
1010
1101
0101
0010
1010
0101
0101
1010
STEP BITS
3
4
5
6
7
NOTE: Starting from sign magnitude, to change format:
To Mu–Law —
MSB is unchanged (sign)
Invert remaining seven bits
If code is 0000 0000, change to 0000 0010 (for zero
code suppression)
To A–Law —
MSB is unchanged (sign)
Invert odd numbered bits
Ignore zero code suppression
PDI
Power Down Input
The power down input disables the bias circuitry and gates off all
clock inputs. This puts the VAG, Txl, RxO, RxO, and TDD outputs
into a high–impedance state. The power dissipation is reduced to 0.1
mW when PDI is a low logic level. The circuit operates normally
with PDI = VDD or with a logic high as defined by connection at
VLS. TDD will not come out of high impedance for two MSI cycles
after PDI goes high.
DCLK
Data Clock Input
In the ML145505, TDC and RDC are internally connected to
DCLK.
ANALOG
VAG
Analog Ground input/Output Pin
Page 10 of 26
VAG is the analog ground power supply input/output. All analog
signals into and out of the device use this as their ground reference.
Each version of the ML1455xx PCM Codec–Filter family can provide its own analog ground supply internally. The DC voltage of this
internal supply is 6% positive of the midway between VDD and
VSS. This supply can sink more than 8 mA but has a current source
limited to 400 µA.The output of this supply is internally connected
to the analog ground input of the part. The node where this supply
and the analog ground are connected is brought out to the VAG pin.
In symmetric dual supply systems (±5, ±6, etc.), VAG may be externally tied to the system analog ground supply. When RxO or RxO
drive low impedance loads tied to VAG, a pull–up resistor to VDD
will be required to boost the source current capability if VAG is not
tied to the supply ground. All analog signals for the part are referenced to VAG, including noise; therefore, decoupling capacitors (0.1
µF) should be used from VDD to VAG and VSS to VAG.
Vref
Positive Voltage Reference Input (ML145502 Only)
The Vref pin allows an external reference voltage to be used for
the A/D and D/A conversions. If Vref is tied to VSS, the internal reference is selected. If Vref > VAG, then the external mode is selected
and the voltage applied to Vref is used for generating the internal
converter reference voltage. In either internal or external reference
mode, the actual voltage used for conversion is multiplied by the
ratio selected by the RSI pin. The RSI pin circuitry is explained
under its pin description below. Both the internal and external references are inverted within the PCM Codec–Filter for negative input
voltages such that only one reference is required.
External Mode — In the external reference mode (Vref >VAG),
a 2.5 V reference like the MC1403 may be connected from Vref to
VAG. A single external reference may be shared by tying together a
number of Vref pins and VAG pins from different codec–filters. In
special applications, the external reference voltage may be between
0.5 and 5 V. However, the reference voltage gain selection circuitry
associated with RSI must be considered to arrive at the desired
codec–filter gain.
Internal Mode — In the internal reference mode (Vref =VSS),
an internal 2.5 V reference supplies the reference voltage for the RSI
circuitry. The Vref pin is functionally connected to VSS for the
ML145503,and ML145505 pinouts.
RSI
Reference Select Input (ML145502 Only)
The RSI input allows the selection of three different overload or
full–scale A/D and D/A converter reference voltages independent of
the internal or external reference mode. The RSI pin is a digital
input that senses three different logic states: VSS, VAG, and VDD.
For RSI = VAG, the reference voltage is used directly for the converters. The internal reference is 2.5 V. For RSI = VSS, the reference
voltage is multiplied by the ratio of 1.26, which results in an internal
converter reference of 3.15 V. For RSI = VDD, the reference voltage
is multiplied by 1.51, which results in an internal converter reference
of 3.78 V. The device requires a minimum of 1.0 V of headroom
between the internal converter reference to VDD. VSS has this same
absolute valued minimum, also measured from VAG pin. The various modes of operation are summarized in Table 2. The RSI pin is
functionally connected to VSS for the ML145503, and ML145505
pinouts.
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RxO, RxO
Receive Analog Outputs
These two complimentary outputs are generated from the output of the receive filter. They are equal in magnitude and out of
phase. The maximum signal output of each is equal to the maximum peak–to–peak signal described with the reference. If a
3.15 V reference is used with RSI tied to VAG and a + 3 dBm0
sine wave is decoded, the RxO output will be a 6.3 V
peak–to–peak signal. RxO will also have an inverted signal output of 6.3 V peak–to–peak. External loads may be connected
from RxO to RxO for a 6 dB push–pull signal gain or from
either RxO or RxO to VAG. With a 3.15 V reference each output
will drive 600 Ω to + 9 dBm. With RSI tied to VDD, each output will drive 900 Ω to + 9 dBm.
RxG
Receive Output Gain Adjust (ML145502 Only)
The purpose of the RxG pin is to allow external gain adjustment for the RxO pin. If RxG is left open, then the output signal
at RxO will be inverted and output at RxO. Thus the push–pull
gain to a load from RxO to RxO is two times the output level at
RxO. If external resistors are applied from RxO to RxG (RI)
and from RxG to RxO (RG), the gain of RxO can be set differently from inverting unity. These resistors should be in the range
of 10 kΩ. The RxO output level is unchanged by the resistors
and the RxO gain is approximately equal to minus RG/RI. The
actual gain is determined by taking into account the internal
resistors which will be in parallel to these external resistors. The
internal resistors have a large tolerance, but they match each
other very closely. This matching tends to minimize the effects
of their tolerance on external gain configurations. The circuit for
RxG and RxO is shown in the block diagram.
Txl
Transmit Analog Input
TxI is the input to the transmit filter. It is also the output of
the transmit gain amplifiers of the ML145502/03/05. The TxI
input has an internal gain of 1.0, such that a +3 dBm0 signal at
TxI corresponds to the peak converter reference voltage as
described in the Vref and RSI pin descriptions. For 3.15 V reference, the + 3 dBm0 input should be 6.3 V peak–to–peak.
Page 11 of 26
+Tx/–Tx
Positive Tx Amplifier Input
Negative Tx Amplifier Input
The Txl pin is the input to the transmit band–pass filter. If
+Tx or –Tx is available, then there is an internal amplifier preceding the filter whose pins are +Tx, –Tx, and TxI. These pins
allow access to the amplifier terminals to tailor the input gain
with external resistors. The resistors should be in the range of
10 kΩ. If +Tx is not available, it is internally tied to VAG. If
–Tx and +Tx are not available, the TxI is a unity gain
high–impedance input.
POWER SUPPLIES
VDD
Most Positive Power Supply
VDD is typically 5 to 12 V.
VSS
Most Negative Power Supply
VSS is typically 10 to 12 V negative of VDD.
For a ±5 V dual–supply system, the typical power supply configuration is VDD = + 5 V, VSS = – 5 V, VLS = 0 V (digital
ground accommodating TTL logic levels), and VAG = 0 V being
tied to system analog ground.
For single–supply applications, typical power supply configurations include:
VDD = 10 V to 12 V
VSS = 0 V
VAG generates a mid supply voltage for referencing all analog
signals.
VLS controls the logic levels. This pin should be connected to
VDD for CMOS logic levels from VSS to VDD. This pin should
be connected to digital ground for true TTL logic levels referenced to VLS.
TESTING CONSIDERATIONS (ML145502 ONLY)
An analog test mode is activated by connecting MSI and CCI
to 128 kHz. In this mode, the input of the A/D (the output of the
Tx filter) is available at the PDI pin. This input is direct coupled
to the A/D side of the codec. The A/D is a differential design.
This results in the gain of this input being effectively attenuated
by half. If monitored with a high–impedance buffer, the output
of the Tx low–pass filter can also be measured at the PDI pin.
This test mode allows independent evaluation of the transmit
low–pass filter and A/D side of the codec. The transmit and
receive channels of these devices are tested with the codec–filter
fully functional.
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ML145503
VAG
1
600 Ω
VAG
VDD
RxO
RDD
+ Tx
RCE
TxI
RDC
– Tx
TDC
Mu/A
TDD
PDI
8 V
SS
TDE
2
Rx
3
5 kΩ
10 kΩ
4
Tx
5
681
6
7
VLS
16
5V
51 kΩ*
0.1 µF
15
14
ENABLE
13
CLOCK
12
11
10
9
0.1 µF
–5V
* To define RDD when TDD is high Z.
Figure 1. Test Circuit
Table 1. Options Available by Pin Selection
RSI*
Pin Level
Vref*
Pin Level
Peak–to–Peak Overload Voltage
(Txl, RxO)
VDD
VSS
7.56 V p–p
VDD
VAG + VEXT
(3.02 x VEXT) V p–p
VAG
VSS
5 V p–p
VAG
VAG + VEXT
(2 x VEXT) V p–p
VSS
VSS
6.3 V p–p
VSS
VAG + VEXT
(2.52 x VEXT) V p–p
* On ML145503/05, RSI and Vref tied internally to V SS .
Table 2. Summary of Operation Conditions User Programmed Through Pins VDD, VAG, and VSS
Pin
Programmed
Logic
Level
Page 12 of 26
Mu/A
RSI
Peak Overload
Voltage
VLS
VDD
Mu–Law Companding Curve and D3/D4 Digital
Formats with Zero Code Suppress
3.78
CMOS
Logic Levels
VAG
Mu–Law Companding Curve and Sign
Magnitude Data Format
2.50
TTL Levels
VAG Up
VSS
A–Law Companding Curve and CCITT Digital
Format
3.15
TTL Levels
VSS Up
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LANSDALE Semiconductor, Inc.
TDE
tsu2
tP4
tsu8
tw
tsu1
TDC
1
2
*
4
3
5
6
7
8
tP3
tP3
tP1
TDD
tw
fCL
9
10
11
tP2
tP2
MSB
LSB
PCM WORD REPEATED
* Data output during this time will vary depending on TDC rate and TDE timing.
Figure 2. Transmit Timing Diagram
tw
RCE
tsu4
RDD
tw
1
RDC
tw
fCL
tsu3
2
3
4
5
6
7
8
9
10
11
th
tsu5
DON’T
CARE
MSB
DON’T
CARE
LSB
Figure 3. Receive Timing Diagram
tw
MSI
tsu7
tw
tw
tsu6
CCI
1
2
3
4
5
6
7
8
9
10
11
Figure 4. MSI/CCI Timing Diagram
Page 13 of 26
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1.00
0.40
TYPICAL
PEFORMANCE
0.60
GUARANTEED
PERFORMANCE
0
– 0.20
– 0.40
0.20
– 0.40
– 0.80
– 40
– 30
– 20
– 10
INPUT LEVEL AT 1.02 kHz
– 1.00
– 60
0
C–MESSAGE WEIGHTED
VDD = + 5 V
VSS = – 5 V
2048 kHz CLOCK
25.0
20.0
QUANTIZTION DISTORTION (dB)
TYPICAL
PEFORMANCE
30.0
GUARANTEED
PERFORMANCE
15.0
– 50
– 40
– 30
– 20
– 10
INPUT LEVEL AT 1.02 kHz
40.0
25.0
20.0
GUARANTEED
PERFORMANCE
15.0
– 50
– 40
– 30
– 20
– 10
INPUT LEVEL AT 1.02 kHz
0
Figure 8. ML145502 Quantization
Distortion Mu–Law Receive
0.8
VDD = + 5 V
VSS = – 5 V
2048 kHz CLOCK
0.4
0.2
TYPICAL PEFORMANCE
0
– 0.2
– 0.4
GUARANTEED
PERFORMANCE
– 0.6
– 50
– 40
– 30
VDD = + 5 V
VSS = – 5 V
2048 kHz CLOCK
0.6
0.4
GAIN ERROR (dB)
0.6
GAIN ERROR (dB)
0
C–MESSAGE WEIGHTED
VDD = + 5 V
VSS = – 5 V
2048 kHz CLOCK
30.0
10.0
– 60
0
0.8
0.2
0
– 0.2
TYPICAL PEFORMANCE
GUARANTEED
PERFORMANCE
– 0.4
– 0.6
– 20
– 10
– 0.8
– 60
INPUT LEVEL PSEUDO NOISE (dBm0)
– 50
– 40
– 30
– 20
– 10
INPUT LEVEL PSEUDO NOISE (dBm0)
Figure 9. ML145502 Gain vs Level A–Law Transmit
Page 14 of 26
– 10
TYPICAL
PEFORMANCE
35.0
Figure 7. ML145502 Quantization
Distortion Mu–Law Transmit
– 0.8
– 60
– 40
– 30
– 20
INPUT LEVEL AT 1.02 kHz
45.0
40.0
10.0
– 60
– 50
Figure 6. ML145502 Gain vs Level Mu–Law Receive
45.0
35.0
GUARANTEED
PERFORMANCE
– 0.20
– 0.60
– 50
TYPICAL
PEFORMANCE
0
– 0.80
Figure 5. ML145502 Gain vs Level Mu–Law Transmit
QUANTIZTION DISTORTION (dB)
0.40
– 0.60
– 1.00
– 60
VDD = + 5 V
VSS = – 5 V
2048 kHz CLOCK
0.80
GAIN ERROR (dB)
GAIN ERROR (dB)
0.60
0.20
1.00
VDD = + 5 V
VSS = – 5 V
2048 kHz CLOCK
0.80
Figure 10. ML145502 Gain vs Level A–Law Receive
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40.0
TYPICAL
PERFORMANCE
35.0
GUARANTEED
PERFORMANCE
30.0
25.0
PSOPHOMETRIC
WEIGHTED
VDD = + 5 V
VSS = – 5 V
2048 kHz
20.0
15.0
10.0
– 60
– 50
– 40
– 30
– 20
40.0
QUANTIZATION DISTORTION (dB)
QUANTIZATION DISTORTION (dB)
ML145502, ML145503, ML145505
– 10
TYPICAL
PERFORMANCE
35.0
30.0
25.0
PSOPHOMETRIC
WEIGHTED
VDD = + 5 V
VSS = – 5 V
2048 kHz
20.0
15.0
10.0
– 60
0
– 50
INPUT LEVEL PSEUDO NOISE (dBm0)
TYPICAL PERFORMANCE
60
50
40
30
20
10
0
– 20
– 10
0
70
TYPICAL PERFORMANCE
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90
0
100
10
20
30
POWER SUPPLY REJECTION (dB)
70
TYPICAL PERFORMANCE
60
50
40
30
20
10
0
10
20
30
40
50
60
60
70
80
90
100
70
80
90
100
70
TYPICAL PERFORMANCE
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 15. ML145502 Power Supply Rejection
Ratio Positive Receive VAC = 250 mVrms,
C–Message Weighted
Page 15 of 26
50
Figure 14. ML145502 Power Supply Rejection
Ratio Negative Transmit VAC = 250 mVrms,
C–Message Weighted
Figure 13. ML145502 Power Supply Rejection
Ratio Positive Transmit VAC = 250 mVrms,
C–Message Weighted
0
40
FREQUENCY (kHz)
FREQUENCY (kHz)
POWER SUPPLY REJECTION (dB)
– 30
Figure 12. ML145502 Quantization Distortion
A–Law Receive
POWER SUPPLY REJECTION (dB)
POWER SUPPLY REJECTION (dB)
– 40
INPUT LEVEL PSEUDO NOISE (dBm0)
Figure 11. ML145502 Quantization Distortion
A–Law Transmit
70
GUARANTEED
PERFORMANCE
www.lansdale.com
Figure 16. ML145502 Power Supply Rejection
Ratio Negative Receive VAC = 250 mVrms,
C–Message Weighted
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
0.2
2.0
0.1
0
0
– 2.0
TYPICAL
PERFORMANCE
– 0.2
– 4.0
GAIN (dB)
GAIN (dB)
– 0.1
GUARANTEED
PERFORMANCE
– 0.3
– 0.4
– 6.0
– 8.0
– 0.5
– 12.0
– 0.6
– 14.0
– 0.7
– 16.0
– 0.8
TYPICAL
PERFORMANCE
– 10.0
GUARANTEED
PERFORMANCE
– 18.0
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
3.0 3.1
3.2
3.3 3.4 3.5 3.6
FREQUENCY (kHz)
0.2
– 2.0
0.1
TYPICAL
PERFORMANCE
0
– 6.0
– 0.1
GAIN (dB)
TYPICAL
PERFORMANCE
– 14.0
GUARANTEED
PERFORMANCE
– 18.0
3.9 4.0 4.1 4.2
Figure 18. ML145502 Low–Pass Filter
Response Transmit
2.0
– 10.0
3.7 3.8
FREQUENCY (kHz)
Figure 17. ML145502 Pass–Band
Filter Response Transmit
GAIN (dB)
GUARANTEED
PERFORMANCE
– 0.2
GUARANTEED
PERFORMANCE
– 0.3
– 0.4
– 0.5
– 22.0
– 0.6
– 26.0
– 0.7
– 30.0
– 0.8
0
0.04
0.08
0.12
0.16
FREQUENCY (kHz)
0.20
0.24
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
FREQUENCY (kHz)
Figure 19. ML145502 High–Pass Filter
Response Transmit
Figure 20. ML145502 Pass–Band
Filter Response Receive
2.0
0
GUARANTEED
PERFORMANCE
– 2.0
GAIN (dB)
– 4.0
– 6.0
– 8.0
TYPICAL
PERFORMANCE
– 10.0
– 12.0
– 14.0
– 16.0
GUARANTEED
PERFORMANCE
– 18.0
3.0 3.1
3.2
3.3 3.4 3.5 3.6
3.7 3.8
3.9 4.0 4.1 4.2
FREQUENCY (kHz)
Figure 21. ML145502 Low–Pass Filter Response Receive
Page 16 of 26
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Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
2.048 MHz
18 pF
18 pF
10 MΩ
300 Ω
+5V
VCC
R
0.1 µF
OSC
IN
OSC
OUT 1
2.048 MHz
(TDC, RDC, CCI)
OSC
OUT 2
8 kHz
(TDE, RCE, MSI)
MC74HC4060
GND Q8
Q4
+5V
J
VCC
1/2
MC74HC73
K
GND
Q
J
Q
K
R
1/2
MC74HC73
Q
Q
R
+5V
255
256
1
2
3
4
5
6
7
8
9
10
2.048 MHz
8 kHz
Figure 22. Simple Clock Circuit for Driving ML145502/03/05 Codec–Filters
Page 17 of 26
www.lansdale.com
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
N=1
R0
VAG
VDD
RxO
RDD
+ Tx
RCE
TxI
RDC
– Tx
TDC
Mu/A
TDD
PDI
TDE
VSS
VLS
R0
N=2
– 48 V
10 kΩ
N=1
10 kΩ
MC145503
23a. Simplified Transformer Hybrid Using ML145503
N=1
R0
VAG
VDD
RxO
RDD
+ Tx
RCE
TxI
RDC
– Tx
TDC
Mu/A
TDD
PDI
TDE
VSS
VLS
R3
N=2
R5
R4
– 48 V
R6
N=1
R1
R2
R0 = R3 R4 (R2 + R1) ≅ R3 R4
AV out =
R0 R4 (R2 + R1)
R3 + R0 R4 (R2 + R1)
≅
R0 R4
R3 + R0 R4
AV in = – R1
R2
MC145503
NOTE: Hybrid Balance by R5 and R6 to equate the RxO signal gain at Txl through the
inverting and non–inverting signal paths.
23b. Universal Transformer Hybrid Using ML145503
Figure 23. Hybrid Interfaces to the ML145503 PCM Codec–Filter Mono–Circuit
Page 18 of 26
www.lansdale.com
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
R0 = 600 Ω
VSS
+ Vref
RSI
VAG
VDD
RxO
RDD
RxG
RCE
RxO
RDC
+ Tx
TDC
TxI
CCI
– Tx
TDD
Mu/A
TDE
PDI
MSI
VSS
VLS
R0 = 900 Ω
N=1
R0
R5
R4
R6
R3
N=2
– 48
N=1
R0
R2
R1
NOTE: Balance by R5 and R6 to equate the Txl gains through the inverting
and non–inverting input signal paths, respectively, is given by:
R1
R3
1–
2 × R2
R4
=
1+
R1
R2
R6
R3
–
R5 + R6
R4
R5
R5 + R6
Tx Gain = R1/R2
Rx Gain = 1 + R3/R4
R5, R6 ≈ 10 kΩ
Adjust Rx Gain with R3
Adjust Tx Gain with R1
ML145502
24a. Universal Transformer Hybrid Using ML145502
R0 = 600
R0 = 900
T
N=1
VSS
10 kΩ
N=2
R0
+ Vref
RSI
VAG
VDD
RxO
20 kΩ
RxG
– 48
N=1
R0
RxO
R
+ Tx
RDD
RCE
RDC
TDC
TxI
CCI
20 kΩ
– Tx
10 kΩ
TDD
Mu/A
TDE
PDI
MSI
VSS
VLS
ML145502
24b. Single–Ended Hybrid Using ML145502
Figure 24. Hybrid Interfaces to the ML145502 PCM Codec–Filter Mono–Circuit
Page 19 of 26
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Issue A
Page 20 of 26
RING
TIP
0.0047
– 48 V
75 Ω
75 Ω
47 k
www.lansdale.com
1N4002
0.1
– 48 V
9
8
7
6
4
3
19.6 kΩ
TIP111
TIP125
5
0.0047
0.0047
2
VEE
EN
BN
RS I
CC
TSI
BP
EP
VCC
1 kΩ
1
19.6 kΩ
1N4002
15
16
17
18
10 µF
+ 50 V
VQB
HST
10
11
RS O 1 2
TSO 13
HSO 14
PDI
TxO
RxI
VAG
MC3419–1L
R7
270 k Ω
+5V
R3
42.2 k Ω
R4
19.6 k Ω
R1
30.1 k Ω
R5
126 k Ω
(A0)
10 kΩ
10 k Ω
0.47 (A1)
R2
143 k Ω
0.47
–5V
0.1
8
7
6
5
4
3
2
1
VSS
PDI
Mu/A
–Tx
TxI
+Tx
RxO
VAG
16
V LS
9
TDE 10
TDD 11
TDC 12
RDC 13
RCE 14
RDD 15
VDD
ML 145503
+5V
0. 1
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
Figure 25. A Complete Single Party Channel Unit Using
MC3419 SLIC and ML145503 PCM Mono–Circuit
Issue Aj
Page 21 of 26
www.lansdale.com
Refer to AN968 for more information.
C5
Tx–
µ /A
TxI
VDD
RxO
Tx+
VAG
V LS
C4
ML145503
HANDSET
R1
5
6
4
16
2
3
1
9
MC145412
R2
R5
R6
R9
OSC
C4
OSC
MS
MO
VSS
OH
OPL
VDD
1
PDI
TDC
RDC
RCE
RDD
TDD
TDE
VSS
7
12
13
14
15
11
10
8
2
NC
8
10
11
6
12
17
9
R10
SW2
X2
R36
–5V
R3 5
Q5
R34
LED
C1
Q2
R15
R13
C13
SYNC TO
POWER SUPPLY
SW1
R14
R11
4
V in
1
CD
3
FC1
2
FC 2
Q1
R12
C14
R24
+5V
C10
C12
D5
VCC
T x3
Rx3
Rx2
Tx2
Tx1
Rx1
G ND
9
16
7
6
4
5
3
2
9
8
7
6
17
13
14
18
19
12
SO2
SI2
SO1
SI1
CLK
TE1
Tx
Rx
RE 1
TE
VSS
VDD
X2
PD
X1
µ /A
LO2
LB
LO1
LI
VD
Vref
2
C9
22
16
11
15
10
20
4
21
3
5
–5V
+5V
1
20
TxS
VDD
17
4
DOE BRCLK
14
3
DL
DIE
2
9
SB
TxD
11
6
BR1
RxD
12
7
B R2
RxS
19
8
RST
BR3 5
15
DCLK BCLK
18
16
CM
DCO
13
10
VSS
DCI
VDD
DI3
DO3
DO2
DI2
DI1
DO1
VSS
ML145428
R4
C2
C3
R3
R7
R8
+5V
1 2 3
4 5 6
7 8 9
* 0 #
5
16
15
14
13
18
7
C1
C2
C3
R1
R2
R3
R4
DTMF OUT
TSO
MC34119
4
+5V
5
VO1
8
V
6 O2
VCC
7
GND
R25
1
10
11
13
12
14
15
8
ML145406
3
SW1: CLOSED = ON-HOOK
OPEN = OFF-HOOK
SPEAKER
R23
C15
+5V
C11
X1
C8
R16
C6
C7
TIP
RING
TO POWER
SUPPLY V in
SW3 – SW7
+5V
+5V
R37 – R41
FEMALE
DB–25
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
MC145426
Figure 26. Digital Telephone Schematic
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
Table 3. Mu–Law Encode–Decode Characteristics
Chord
Number
Number
of Steps
Step
Size
Normalized
Encode
Decision
Levels
Digital Code
1
2
3
4
5
6
7
8
Sign
Chord
Chord
Chord
Step
Step
Step
Step
Normalized
Decode
Levels
1
0
0
0
0
0
0
0
8031
1
0
0
0
1
1
1
1
4191
1
0
0
1
1
1
1
1
2079
1
0
1
0
1
1
1
1
1023
1
0
1
1
1
1
1
1
495
1
1
0
0
1
1
1
1
231
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
2
1
1
1
1
1
1
1
1
0
8159
256
…
16
…
8
…
7903
4319
7
16
128
…
…
…
4063
2143
6
16
64
…
…
…
2015
1055
5
16
32
…
…
…
991
511
4
16
16
…
…
…
479
239
3
16
8
…
…
…
223
103
99
2
16
4
…
…
…
95
35
33
1
15
2
…
…
…
31
3
1
1
1
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inversion of all magnitude bits.
Page 22 of 26
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Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
Table 4. A–Law Encode–Decode Characteristics
Chord
Number
Number
of Steps
Step
Size
Normalized
Encode
Decision
Levels
Digital Code
1
2
3
4
5
6
7
8
Sign
Chord
Chord
Chord
Step
Step
Step
Step
Normalized
Decode
Levels
1
0
1
0
1
0
1
0
4032
1
0
1
0
0
1
0
1
2112
1
0
1
1
0
1
0
1
1056
1
0
0
0
0
1
0
1
528
1
0
0
1
0
1
0
1
264
1
1
1
0
0
1
0
1
132
1
1
1
1
0
1
0
1
1
1
0
1
0
1
0
1
4096
128
…
16
…
7
…
3968
2176
6
16
64
…
…
…
2048
1088
5
16
32
…
…
…
1024
544
4
16
16
…
…
…
512
272
3
16
8
…
…
…
256
136
2
16
4
…
…
…
128
68
66
1
32
2
…
…
…
64
2
1
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes alternate bit inversion, as specified by CCITT.
Page 23 of 26
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Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 16 = EP
(ML145503EP, ML145505EP)
PLASTIC DIP
CASE 648–08
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
10
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
10
0.51
1.01
P DIP 22 = WP
(ML145502WP)
PLASTIC DIP
CASE 708–04
22
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
12
B
1
11
L
A
N
C
K
H
Page 24 of 26
G
F
D
SEATING
PLANE
M
J
www.lansdale.com
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
27.56 28.32
8.64
9.14
3.94
5.08
0.36
0.56
1.27
1.78
2.54 BSC
1.02
1.52
0.20
0.38
2.92
3.43
10.16 BSC
15°
0°
1.02
0.51
INCHES
MIN
MAX
1.085
1.115
0.340 0.360
0.155 0.200
0.014 0.022
0.050 0.070
0.100 BSC
0.040 0.060
0.008 0.015
0.115 0.135
0.400 BSC
15°
0°
0.020 0.040
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
PLCC 28 = -4P
(ML145502-4P)
PLCC PACKAGE
CASE 776–02
0.007 (0.180)
B
T L–M
M
N
S
T L–M
S
S
Y BRK
–N–
0.007 (0.180)
U
M
N
S
D
Z
–M–
–L–
W
28
D
X
G1
0.010 (0.250)
T L–M
S
N
S
S
V
1
VIEW D–D
A
0.007 (0.180)
R
0.007 (0.180)
M
T L–M
S
N
S
C
M
T L–M
N
S
T L–M
N
S
S
K1
0.004 (0.100)
J
–T–
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
M
S
E
G
T L–M
S
N
S
0.007 (0.180)
M
T L–M
S
N
S
VIEW S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
Page 25 of 26
S
0.007 (0.180)
H
Z
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
www.lansdale.com
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2
10
0.410
0.430
0.040
–––
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
–––
0.64
–––
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
–––
0.50
2
10
10.42
10.92
1.02
–––
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SO 16 = -5P
(ML145503-5P, ML145505-5P)
SOG PACKAGE
CASE 751G–02
–A–
16
9
–B–
8X
P
0.010 (0.25)
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45
C
–T–
14X
G
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0
7
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0
7
0.395
0.415
0.010
0.029
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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