MOTOROLA MC14XXXBDW 4x4 multiport register Datasheet

SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 623
The MC14580B is a 4 by 4 multiport register useful in small scratch pad
memories, arithmetic operations when coupled with an adder, and other data
storage applications. It allows independent reading of any two words (or the
same word at both outputs) while writing into any one of four words.
Address changing and data entry occur on the rising edge of the clock.
When the write enable input is low, the contents of any word may be
accessed but not altered.
•
•
•
•
•
No Restrictions on Clock Input Rise or Fall Times
3–State Outputs
Single Phase Clocking
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or one Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin Compatible with CD40108
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Parameter
Symbol
VDD
DC Supply Voltage
Value
Unit
– 0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package†
Tstg
Storage Temperature
TL
Lead Temperature (8–Second Soldering)
16
DW SUFFIX
SOIC
CASE 751E
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
Q3B
1
24
VDD
2
23
Q1B
500
mW
Q2B
– 65 to + 150
_C
3–STATE A
3
22
Q0B
260
_C
Q0A
4
21
3–STATE B
Q1A
5
20
D0
Q2A
6
19
D1
Q3A
7
18
D2
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
CLOCK
P SUFFIX
PLASTIC
CASE 709
WRITE 0
8
17
D3
BLOCK DIAGRAM
WRITE 1
9
16
CLOCK
W0 W1 R0A R1A R0B R1B
8 9 13 14 11 10
READ 1B
10
15
WE
READ 0B
11
14
READ 1A
VSS
12
13
READ 0A
DECODER
3–STATE A
3
WE
DATA
INPUT
15
20
D0
19
D1
18
D2
17
D3
4X4
MEMORY
VDD = PIN 24
VSS = PIN 12
Q0A
Q1A
Q2A
Q3A
4
5
6
7
22
Q0B
23
Q1B
2
Q2B
1
Q3B
WORD A
OUTPUT
WORD B
OUTPUT
21
3–STATE B
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14580B
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
Three–State Leakage Current
ITL
15
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc
IT = (1.18 µA/kHz) f + IDD
IT = (1.91 µA/kHz) f + IDD
IT = (2.67 µA/kHz) f + IDD
—
± 0.1
—
± 0.0001
± 0.1
µAdc
—
± 3.0
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MC14580B
2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Min
Typ #
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
tPLH, tPHL
(Figures 3 and 6)
5.0
10
15
—
—
—
650
250
170
1300
500
340
ns
Write Enable Setup Time
(Enabling a Write or Read)
tsu
(Figure 5)
5.0
10
15
800
300
200
400
150
100
—
—
—
ns
Write Enable Removal Time
(Disabling a Write or Read)
trem
(Figure 5)
5.0
10
15
0
0
0
– 100
– 50
– 35
—
—
—
ns
Setup Time**
Address, Data to Clock
tsu
(Figure 3)
5.0
10
15
50
30
25
20
0
0
—
—
—
ns
Hold Time**
Clock to Address, Data
th
(Figure 3)
5.0
10
15
480
195
150
160
65
50
—
—
—
ns
tPHZ, tPLZ
tPZH, tPZL
(Figures 4 and 7)
5.0
10
15
—
—
—
130
60
45
260
120
90
ns
tw
(Figure 3)
5.0
10
15
820
330
220
410
165
110
—
—
—
ns
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
(Figures 3 and 6)
Propagation Delay Time
Clock to Output
3–State Enable/Disable Delay Time
Clock Pulse Width
Unit
tTLH, tTHL
ns
** When loading repetitive highs, the output may glitch low momentarily after the rising edge of Clock. However, data integrity remains unaffected
and data is valid after the propagation delays listed in the Switching Characteristics Table.
VDD
PULSE
GENERATOR
VDD
VSS
1
2
S1
WE
W0
W1
R0A
R1A
R0B
R1B
C
D0
D1
D2
D3
Vout
Q0A
Q1A
IDS
Q2A
Q3A
Q0B
Q1B
Sink Current
EXTERNAL
POWER
SUPPLY
Source Current
Position of S1
2
1
VGS =
VDS =
VDD
Vout
– VDD
Vout – VDD
Q2B
Q3B
VSS
Figure 1. Output Drive Current Test Circuit
MOTOROLA CMOS LOGIC DATA
MC14580B
3
VDD
IDD
WE
W0
W1
R0A
R1A
R0B
R1B
C
D0
D1
D2
D3
PULSE
GENERATOR
1
PULSE
GENERATOR
2
PULSE
GENERATOR
3
Q0A
REPETITIVE WAVEFORMS
CL
Q1A
CL
Q2A
P.G. 1
CL
Q3A
CL
Q0B
P.G. 2
CL
Q1B
CL
Q2B
P.G. 3
OUTPUT
Qn A, B
CL
Q3B
CL
VSS
Figure 2. Power Dissipation Test Circuit and Waveforms (3–State Inputs are High)
tw(H)
tw(L)
CLOCK
VDD
50%
tsu
th
VSS
3–STATE
A OR B
VDD
tPHZ
50%
ADDRESS DATA
VSS
tPLH, tPHL
Q
50%
VOH
90%
QA
VDD
50%
50%
VSS
tPZH
90%
VOH
10%
tPZL
VOH
90%
10%
VOL
tTLH, tTHL
QB
Figure 3.
VOL
tPZL
10%
VOL
Figure 4.
VDD
50%
CLOCK
50%
Q
VSS
tsu
WE
trem
50%
DEVICE
UNDER
TEST
VDD
CL
50%
VSS
Figure 5.
Figure 6. Test Circuit
1 kΩ
Q
DEVICE
UNDER
TEST
CONNECT TO VCC WHEN TESTING tPLZ AND tPZL
CONNECT TO GND WHEN TESTING tPHZ AND tPZH
CL
Figure 7. Test Circuit
MC14580B
4
MOTOROLA CMOS LOGIC DATA
LOGIC DIAGRAM
CLOCK
WE
R0A
13
R1A
14
16
15
R1B
10
R0B
11
3–STATE A
3
C
Q
C
Q
C
Q
C
Q
D
Q
D
Q
D
Q
D
Q
Q
C
D
3–STATE
Q
C
D
3–STATE
D3
D2
17
18
C
D
Q
C
D
3–STATE
Q
Q
C
D
3–STATE
C
D
Q
Q
C
D
3–STATE
D1
D0
W1
W0
19
20
9
8
C
D
Q
C
D
3–STATE
Q
Q
Q
C
D
3–STATE
C
Q
Q
C
D
3–STATE
D
Q
C
Q
Q
C
D
D
7
6
5
4
1
2
Q3A
Q2A
Q1A
Q0A
Q3B
Q2B
23
Q1B
22
Q0B
21
3–STATE B
TRUTH TABLE
Clock
WE
Write 1
Write 0
Read 1A
Read 0A
Read 1B
Read 0B
3–State A
3–State B
Dn
QnA
QnB
1
1
X
0
0
X
1
1
X
0
0
X
1
1
X
0
0
X
1
1
X
1
1
1
1
1
1
1
0
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
X
X
1
X
X
X
X
X
X
X
1
1
X
1
0
0
0
1
1
0
1
1
Dn to
word 0
0
0
0
0
1
1
0
1
1
Word 0
not
altered
1
0
No
Change
Z
No
Change
No
Change
Contents
of word 1
displayed
Contents
of word 1
displayed
1
0
No
Change
Z
No
Change
No
Change
Contents
of word 2
displayed
Contents
of word 2
displayed
Z = High Impedance
X = Don’t Care
MOTOROLA CMOS LOGIC DATA
MC14580B
5
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 623–05
ISSUE M
24
NOTES:
1. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
13
B
1
12
DIM
A
B
C
D
F
G
J
K
L
M
N
A
F
SEATING
PLANE
C
L
N
D
G
INCHES
MIN
MAX
1.230
1.290
0.500
0.610
0.160
0.220
0.016
0.020
0.050
0.060
0.100 BSC
0.008
0.012
0.125
0.160
0.600 BSC
0_
15_
0.020
0.050
J
M
K
MILLIMETERS
MIN
MAX
31.24
32.77
12.70
15.49
4.06
5.59
0.41
0.51
1.27
1.52
2.54 BSC
0.20
0.30
3.18
4.06
15.24 BSC
0_
15 _
0.51
1.27
P SUFFIX
PLASTIC DIP PACKAGE
CASE 709–02
ISSUE C
24
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
13
B
1
12
A
L
C
N
K
H
F
G
MC14580B
6
D
SEATING
PLANE
M
J
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
31.37
32.13
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.03
0.20
0.38
2.92
3.43
15.24 BSC
0_
15_
0.51
1.02
INCHES
MIN
MAX
1.235
1.265
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.080
0.008
0.015
0.115
0.135
0.600 BSC
0_
15_
0.020
0.040
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
–A–
24
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
–B–
12X
P
0.010 (0.25)
1
M
B
M
12
24X
D
J
0.010 (0.25)
M
T A
S
B
S
F
R
C
–T–
SEATING
PLANE
M
22X
G
K
X 45 _
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0_
8_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0_
8_
0.395
0.415
0.010
0.029
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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MOTOROLA CMOS LOGIC DATA
◊
*MC14580B/D*
MC14580B
MC14580B/D
7
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