ON MC34065P-H High performance dual channel current mode controller Datasheet

MC34065−H, L
MC33065−H, L
High Performance
Dual Channel Current
Mode Controllers
The MC34065−H,L series are high performance, fixed frequency,
dual current mode controllers. They are specifically designed for
off−line and dc−to−dc converter applications offering the designer a
cost effective solution with minimal external components. These
integrated circuits feature a unique oscillator for precise duty cycle
limit and frequency control, a temperature compensated reference,
two high gain error amplifiers, two current sensing comparators, Drive
Output 2 Enable pin, and two high current totem pole outputs ideally
suited for driving power MOSFETs.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, and a latch for single pulse metering of each output.
These devices are available in dual−in−line and surface mount
packages.
The MC34065−H has UVLO thresholds of 14 V (on) and 10 V (off),
ideally suited for off−line converters. The MC34065−L is tailored for
lower voltage applications having UVLO thresholds of 8.4 V (on) and
7.8 V (off).
• Unique Oscillator for Precise Duty Cycle Limit and Frequency Control
• Current Mode Operation to 500 kHz
• Automatic Feed Forward Compensation
• Separate Latching PWMs for Cycle−By−Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• Drive Output 2 Enable Pin
• Two High Current Totem Pole Outputs
• Input Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
VCC
Vref
5.0V
Reference
1
5
R
Sync Input
HIGH PERFORMANCE
DUAL CHANNEL CURRENT
MODE CONTROLLERS
SEMICONDUCTOR
TECHNICAL DATA
P SUFFIX
PLASTIC PACKAGE
16
CASE 648
1
DW SUFFIX
PLASTIC PACKAGE
CASE 751G
(SO−16L)
16
1
PIN CONNECTIONS
1
16 VCC
CT
2
15 Vref
RT
3
14 Drive Output 2 Enable
Voltage Feedback 1
4
Sync Input
Compensation 1
5
Current Sense 1
6
Drive Output 1
7
13 Voltage Feedback
2
12 Compensation
2
11 Current Sense
2
10 Drive Output 2
Gnd
8
9
3
Oscillator
Drive Output 1
2
Voltage
Feedback 1
VCC
Undervoltage
Lockout
Vref
Undervoltage
Lockout
R
1
RT
CT
16
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Compensation 1
Latching
PWM 1
+
−
Error
Amp 1
Drive
Gnd
(Top View)
7
ORDERING INFORMATION
Current Sense
6 1
5
Device
Operating
Temperature Range
MC34065DW−H
Drive Output
2
Enable 14
Voltage
Feedback 2 13
Drive Output 2
Latching
PWM 2
+
−
Error
Amp 2
10
MC34065P−H
SO−16L
TA = 0° to +70°C
Plastic DIP
MC34065P−L
Current Sense
11 2
Compensation 2
12
Gnd
8
Drive Gnd
9
© Semiconductor Components Industries, LLC, 2006
MC33065DW−H
MC33065DW−L
MC33065P−H
MC33065P−L
Representative Block Diagram
July, 2006 − Rev. 2
MC34065DW−L
Package
1
SO−16L
TA = −40° to +85°C
Plastic DIP
Publication Order Number:
MC34065−H/D
MC34065−H, L
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
20
V
Output Current, Source or Sink (Note 1)
IO
400
mA
Output Energy (Capacitive Load per Cycle)
W
5.0
μJ
Current Sense, Enable, and Voltage Feedback Inputs
Vin
− 0.3 to +5.5
V
Sync Input
High State (Voltage)
Low State (Reverse Current)
VIH
IIL
+5.5
− 5.0
V
mA
Error Amp Output Sink Current
IO
10
mA
Power Dissipation and Thermal Characteristics
DW Suffix, Plastic Package Case 751G
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
PD
RθJA
862
145
mW
°C/W
P Suffix, Plastic Package Case 648
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
PD
RθJA
1.25
100
mW
°C/W
Operating Junction Temperature
TJ
+150
°C
Operating Ambient Temperature (Note 3)
MC34065
MC33065
TA
Storage Temperature Range
Tstg
Power Supply Voltage
0 to +70
− 40 to +85
− 65 to +150
°C
°C
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 8.2 kΩ, CT = 3.3 nF, for typical values TA = 25°C, for min/max
values
TA is the operating ambient temperature range that applies to [Note 3].)
Characteristics
Symbol
Min
Typ
Max
Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C)
Vref
4.85
5.0
5.13
V
Line Regulation (VCC = 11 V to 20 V)
Regline
−
2.0
20
mV
Load Regulation (IO = 1.0 mA to 10 mA, VCC = 20 V)
Regload
−
3.0
25
mV
Total Output Variation over Line, Load, and Temperature
Vref
4.8
−
5.15
V
Output Short Circuit Current
ISC
30
100
−
mA
OSCILLATOR AND PWM SECTIONS
Total Frequency Variation over Line and Temperature
VCC = 11 V to 20 V, TA = Tlow to Thigh
MC34065
MC33065
fosc
Frequency Change with Voltage (VCC = 11 V to 20 V)
kHz
46.5
45
49
49
51.5
53
Δfosc/ΔV
−
0.2
1.0
Duty Cycle at each Output
Maximum
Minimum
DCmax
DCmin
46
−
49.5
−
52
0
Sync Input Current
High State (Vin = 2.4 V)
Low State (Vin = 0.8 V)
IIH
IIL
−
−
170
80
250
160
VFB
2.45
2.5
2.55
V
%
%
μA
ERROR AMPLIFIERS
Voltage Feedback Input (VO = 2.5 V)
Input Bias Current (VFB = 5.0 V)
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V)
Unity Gain Bandwidth (TJ = 25°C)
Power Supply Rejection Ratio (VCC = 11 V to 20 V)
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IIB
−
− 0.1
− 1.0
μA
AVOL
65
100
−
dB
BW
0.7
1.0
−
MHz
PSRR
60
90
−
dB
MC34065−H, L
ERROR AMPLIFIERS
Output Current
Source (VO = 3.0 V, VFB = 2.3 V)
Sink (VO = 1.2 V, VFB = 2.7 V)
Output Voltage Swing
High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to Vref, VFB = 2.7 V)
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Isource
Isink
0.45
2.0
1.0
12
−
−
VOH
VOL
5.0
−
6.2
0.8
−
1.1
mA
V
MC34065−H, L
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 8.2 kΩ, CT = 3.3 nF, for typical values TA = 25°C, for min/max
values
TA is the operating ambient temperature range that applies to [Note 3].)
Symbol
Min
Typ
Max
Unit
Current Sense Input Voltage Gain (Notes 4 and 5)
AV
2.75
3.0
3.25
V/V
Maximum Current Sense Input Threshold (Note 4)
Vth
0.9
1.0
1.1
V
Input Bias Current
IIB
−
− 2.0
− 10
μA
tPLN(In/Out)
−
150
300
ns
Enable Pin Voltage − High State (Output 2 Enabled)
Enable Pin Voltage − Low State (Output 2 Disabled)
VIH
VIL
3.5
0
−
−
Vref
1.5
V
Low State Input Current (VIL = 0 V)
IIB
100
250
400
μA
VOL
−
1.6
12.8
10
0.3
2.4
13.3
11.2
0.5
3.0
−
12.3
V
VOL(UVLO)
−
0.1
1.1
V
Output Voltage Rise Time (CL = 1.0 nF)
tr
−
50
150
ns
Output Voltage Fall Time (CL = 1.0 nF)
tf
−
50
150
ns
7.8
13
8.4
14
9.0
15
7.2
9.0
7.8
10
8.4
11
Characteristics
CURRENT SENSE SECTION
Propagation Delay (Current Sense Input to Output)
DRIVE OUTPUT 2 ENABLE PIN
DRIVE OUTPUTS
Output Voltage − Low State (Isink = 20 mA)
Output Voltage − Low State (Isink = 200 mA)
Output Voltage − High State (Isource = 20 mA)
Output Voltage − High State (Isource = 200 mA)
VOH
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA)
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (VCC Increasing)
−L Suffix
−H Suffix
Vth
Minimum Operating Voltage After Turn−On (VCC Decreasing)
−L Suffix
−H Suffix
VCC(min)
V
V
TOTAL DEVICE
ICC
Power Supply Current
Startup
−L Suffix (VCC = 6.0 V)
−H Suffix (VCC = 12 V)
Operating (Note 2)
mA
−
−
−
0.4
0.6
20
0.8
1.0
25
4. This parameter is measured at the latch trip point with VFB = 0 V
NOTES: 1. Maximum package power dissipation limits must be observed.
NOTES: 2. Adjust VCC above the startup threshold before setting to 15 V.
ΔV Compensation
NOTES: 3. Low duty cycle pulse techniques are used during test to maintain junction
5. Comparator gain is defined as AV =
ΔV Current Sense
NOTES: 3. temperature as close to ambient as possible:
Thigh = +70°C for MC34065
Tlow = 0°C for the MC34065
Thigh = +85°C for MC33065
Tlow = −40°C for the MC33065
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MC34065−H, L
50
14
100pF
3.3nF
500pF
1.0nF
12
220pF
10
330pF
5.0nF
2.2nF
8.0
6.0
4.0
DC max , DUTY CYCLE MAXIMUM (%)
R T, TIMING RESISTOR (k Ω )
16
CT=
10nF
VCC=15V
TA=25°C
10k
48
46
Output2
44
Output1
VCC=15V
RT=4.0 k to 16k
TA = 25°
CL=15pF
42
40
38
30k 50k
100k
300k 500k
fOSC, OSCILLATOR FREQUENCY (Hz)
1.0 M
10k
Figure 1. Timing Resistor versus
Oscillator Frequency
30k 50k
100k
300k 500k
fOSC, OSCILLATOR FREQUENCY (Hz)
Figure 2. Maximum Output Duty Cycle
versus Oscillator Frequency
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1.0 M
MC34065−H, L
VCC=15V
AV=−1.0
TA=25°C
2.50V
2.0V
1.0 μs/DIV
Figure 3. Error Amp Small−Signal
Transient Response
Figure 4. Error Amp Large−Signal
Transient Response
100
0
80
VCC=15V
VO=1.5 V to 2.5V
RL=100 k
TA=25°C
Gain
60
40
30
60
90
20
Phase 120
0
150
100
1.0 k
10 k
100 k
180
10 M
1.0 M
1.2
VCC = 15 V
1.0
TA = 125°C
0.8
TA = 25°C
0.6
0.4
TA = −55°C
0.2
0
0
1.0
2.0
3.0
4.0
5.0
6.0
f, FREQUENCY (Hz)
VO, ERROR AMP OUTPUT VOLTAGE (V)
Figure 5. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 6. Current Sense Input Threshold
versus Error Amp Output Voltage
ISC , REFERENCE SHORT CIRCUIT CURRENT (mA)
ΔVref, REFERENCE VOLTAGE CHANGE (mV)
Vth, CURRENT SENSE INPUT THRESHOLD (V)
1.0 μs/DIV
φ , EXCESS PHASE (DEGREES)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
2.45V
0
VCC = 15 V
−4.0
−8.0
TA = −55°C
−12
TA = 25°C
−16
TA = 125°C
−20
−24
0
200 mV/DIV
2.50V
−20
10
VCC=15V
AV=−1.0
TA=25°C
3.0V
20 mV/DIV
2.55V
20
40
60
80
100
120
120
VCC=15V
RL≤0.1Ω
100
80
60
−55
Iref, REFERENCE SOURCE CURRENT (mA)
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
Figure 7. Reference Voltage Change
versus Source Current
Figure 8. Reference Short Circuit Current
versus Temperature
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7.0
−25
100
125
ΔVO, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
ΔVO , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
MC34065−H, L
VCC=15V
IO=1.0 mA to 10mA
TA=25°C
1.0 ms/DIV
VCC=11 V to 15V
TA=25°C
1.0 ms/DIV
Vsat , OUTPUT SATURATION VOLTAGE (V)
Figure 9. Reference Load Regulation
Figure 10. Reference Line Regulation
0
−2.0
−4.0
VCC
Source Saturation
VCC=15V
(Load to Ground) 80μs Pulsed Load
120 Hz Rate
TA=25°C
TA=−55°C
VCC=15V
CL=1.0nF
TA=25°C
90% −
−6.0
4.0
2.0
0
0
TA=−55°C
TA=25°C
Gnd
Sink Saturation
(Load to VCC)
100
200
300
IO, OUTPUT LOAD CURRENT (mA)
10% −
400
100 ns/DIV
VO2, OUTPUT VOLTAGE 2; VO1, OUTPUT VOLTAGE 1
ICC, SUPPLY CURRENT
Figure 11. Output Saturation Voltage
versus Load Current
Figure 12. Output Waveform
ICC , SUPPLY CURRENT (mA)
VCC=15V
CL=15pF
TA=25°C
10 V/DIV 50 mA/DIV 10 V/DIV
32
24
16
−L Suffix
−H Suffix
8.0
0
0
100 ns/DIV
RT=10k
CT=3.3nF
VFB=0V
Current Sense=0V
TA=25°C
4.0
8.0
12
16
VCC, SUPPLY VOLTAGE (V)
Figure 13. Output Cross Conduction Current
Figure 14. Supply Current versus Supply
Voltage
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20
MC34065−H, L
OPERATING DESCRIPTION
(Figure 5). The noninverting input is internally biased at 2.5
V and is not pinned out. The converter output voltage is
typically divided down and monitored by the inverting input
through a resistor divider. The maximum input bias current
is −1.0 μA which will cause an output voltage error that is
equal to the product of the input bias current and the
equivalent input divider source resistance.
The Error Amp output (Pin 5, 12) is provided for external
loop compensation. The output voltage is offset by two
diode drops (≈1.4 V) and divided by three before it connects
to the inverting input of the Current Sense Comparator. This
guarantees that no pulses appear at the Drive Output (Pin 7,
10) when the error amplifier output is at its lowest state
(VOL). This occurs when the power supply is operating and
the load is removed, or at the beginning of a soft−start
interval (Figures 20, 21).
The minimum allowable Error Amp feedback resistance
is limited by the amplifier’s source current (0.5 mA) and the
output voltage (VOH) required to reach the comparator’s
1.0 V clamp level with the inverting input at ground. This
condition happens during initial system startup or when the
sensed output is shorted:
The MC34065−H,L series are high performance, fixed
frequency, dual channel current mode controllers
specifically designed for Off−Line and dc−to−dc converter
applications. These devices offer the designer a cost
effective solution with minimal external components where
independent regulation of two power converters is required.
The Representative Block Diagram is shown in Figure 15.
Each channel contains a high gain error amplifier, current
sensing comparator, pulse width modulator latch, and totem
pole output driver. The oscillator, reference regulator, and
undervoltage lock−out circuits are common to both
channels.
Oscillator
The unique oscillator configuration employed features
precise frequency and duty cycle control. The frequency is
programmed by the values selected for the timing
components RT and CT. Capacitor CT is charged and
discharged by an equal magnitude internal current source
and sink, generating a symmetrical 50 percent duty cycle
waveform at Pin 2. The oscillator peak and valley thresholds
are 3.5 V and 1.6 V respectively. The source/sink current
magnitude is controlled by resistor RT. For proper operation
over temperature it must be in the range of 4.0 kΩ to 16 kΩ
as shown in Figure 1.
As CT charges and discharges, an internal blanking pulse
is generated that alternately drives the center inputs of the
upper and lower NOR gates high. This, in conjunction with
a precise amount of delay time introduced into each channel,
produces well defined non−overlapping output duty cycles.
Output 2 is enabled while CT is charging, and Output 1 is
enabled during the discharge. Figure 2 shows the Maximum
Output Duty Cycle versus Oscillator Frequency. Note that
even at 500 kHz, each output is capable of approximately
44% on−time, making this controller suitable for high
frequency power conversion applications.
In many noise sensitive applications it may be desirable to
frequency−lock the converter to an external system clock.
This can be accomplished by applying a clock signal as
shown in Figure 17. For reliable locking, the free−running
oscillator frequency should be set about 10% less than the
clock frequency. Referring to the timing diagram shown in
Figure 16, the rising edge of the clock signal applied to the
Sync input, terminates charging of CT and Drive Output 2
conduction. By tailoring the clock waveform symmetry,
accurate duty cycle clamping of either output can be
achieved. A circuit method for this, and multi−unit
synchronization, is shown in Figure 18.
Rf(min) ≈
3.0 (1.0 V) ) 1.4 V
= 8800
0.5 mA
Ω
Current Sense Comparator and PWM Latch
The MC34065 operates as a current mode controller,
whereby output switch conduction is initiated by the
oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier output. Thus the error signal controls the peak
inductor current on a cycle−by−cycle basis. The Current
Sense Comparator−PWM Latch configuration used ensures
that only a single pulse appears at the Drive Output during
any given oscillator cycle. The inductor current is converted
to a voltage by inserting a ground−referenced sense resistor
RS in series with the source of output switch Q1. This
voltage is monitored by the Current Sense Input (Pin 6, 11)
and compared to a level derived from the Error Amp output.
The peak inductor current under normal operating
conditions is controlled by the voltage at Pin 5, 12 where:
Ipk =
V(Pin 5, 12) − 1.4 V
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Error Amplifier
Each channel contains a fully−compensated Error
Amplifier with access to the inverting input and output. The
amplifier features a typical dc voltage gain of 100 dB, and
a unity gain bandwidth of 1.0 MHz with 71° of phase margin
Ipk(max) =
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1.0
RVS
MC34065−H, L
When designing a high power switching regulator it may
be desirable to reduce the internal clamp voltage in order to
keep the power dissipation of RS to a reasonable level. A
simple method to adjust this voltage is shown in Figure 19.
The two external diodes are used to compensate the internal
diodes, yielding a constant clamp voltage over temperature.
Erratic operation due to noise pickup can result if there is an
excessive reduction of the Ipk(max) clamp voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense input with
a time constant that approximates the spike duration will
usually eliminate the instability, refer to Figure 24.
hysteresis and low startup current of the −H suffix version
makes it ideally suited in off−line converter applications
where efficient bootstrap startup techniques are required
(Figure 28). The −L suffix version is intended for lower
voltage dc−to−dc converter applications. The minimum
operating voltage for the −H suffix is 11 V and 8.2 V for the
−L suffix.
Drive Outputs and Drive Ground
Each section contains a single totem−pole output stage
that is specifically designed for direct drive of power
MOSFETs. The Drive Outputs are capable of up to ±400 mA
peak current with a typical rise and fall time of 50 ns with a
1.0 nF load. Additional internal circuitry has been added to
keep the outputs in a sinking mode whenever an
Undervoltage Lockout is active. This characteristic
eliminates the need for an external pull−down resistor. The
totem−pole output has been optimized to minimize
cross−conduction current in high speed operation. The
addition of two 10 Ω resistors, one in series with the source
output transistor and one in series with the sink output
transistor, reduces the cross−conduction current to minimal
levels, as shown in Figure 13.
Although the Drive Outputs were optimized for
MOSFETs, they can easily supply the negative base current
required by bipolar NPN transistors for enhanced turn−off
(Figure 25).
Undervoltage Lockout
Two Undervoltage Lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stages are enabled. The positive power
supply terminal (VCC) and the reference output (Vref) are
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 14 V/10 V for −H suffix, and
8.4 V/7.6 V for −L suffix. The Vref comparator upper and
lower thresholds are 3.6 V/3.4 V respectively. The large
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MC34065−H, L
Vin=15V
VCC
15
Internal
Bias
R
+
−
20k
+
Sync
Input 1
3.6V
−
Vref
UVLO
−
10
Drive Output 1
PWM
Latch 1
2
1.0mA
Current Sense
Comparator 1
Error
Amp 1
Compensation
1 5
Q
−
+
4
1.0V
10
R
Current Sense 1
R
6
RS
Vref
10
250μA
Drive Output 2
Enable
Input 14
Voltage Feedback 2
13
Error
Amp 2
Current Sense
Comparator 2
2R
10
S
R
R
−
+
1.0V
Q2
10
PWM
Latch 2
1.0mA
+
−
Q1
7
S
2R
+
−
Voltage Feedback 1
+
Oscillator
3
CT
VCC
UVLO
R
2.5V
RT
+
−
Reference
Regulator
Vref
16
Q
Current Sense 2
R
11
Compensation
2 12
RS
Gnd
8
Drive Gnd
9
+
−
=
Sink Only
Positive True Logic
Figure 15. Representative Block Diagram
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MC34065−H, L
Sync
Input
Capacitor CT
Latch 1
Set" Input
Compensation
1
Current Sense
1
Latch 1
Reset" Input
Drive Output 1
Drive Output
2
Enable
Latch 2
Set" Input
Compensation
2
Current Sense
2
Latch 2
Reset" Input
Drive Output 2
Figure 16. Timing
Diagram
The outputs do not contain internal current limiting,
therefore an external series resistor may be required to
prevent the peak output current from exceeding the ±400
mA maximum rating. The sink saturation (VOL) is less than
0.75 V at 50 mA.
A separate Drive Ground pin is provided and, with proper
implementation, will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level. Figure 23 shows the proper ground connections
required for current sensing power MOSFET applications.
protection and is capable of providing in excess of 30 mA for
powering any additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse−width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low current signal and high
current switch and output grounds returning on separate
paths back to the input filter capacitor. Ceramic bypass
capacitors (0.1 μF) connected directly to VCC and Vref may
be required depending upon circuit layout. This provides a
low impedance path for filtering the high frequency noise.
All high current loops should be kept as short as possible
using heavy copper runs to minimize radiated EMI. The
Error Amp compensation circuitry and the converter output
voltage−divider should be located close to the IC and as far
as possible from the power switch and other noise generating
components.
Drive Output 2 Enable Pin
This input is used to enable Drive Output 2. Drive
Output 1 can be used to control circuitry that must run
continuously such as volatile memory and the system clock,
or a remote controlled receiver, while Drive Output 2
controls the high power circuitry that is occasionally turned
off.
Reference
The 5.0 V bandgap reference is trimmed to ±2.0%
tolerance at TJ = 25°C. The reference has short circuit
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MC34065−H, L
Vref
1
5
R
15
R
Bias
8
R
External
Sync
Input
220p
F
1
6
20k
CT
4
5.0k
7
+
−
2
3
S
4
−
RB
1
EA1
Osc.
2
MC1455
5.0k
+
4
2R
1.0V
5
5
R
C
Dmax Drive Output 1 =
Figure 17. External Clock Synchronization
+
−
2R
EA1
1.0V
R
1.08
f=
The external diode clamp is required if the negative Sync current
is greater than −5.0 mA.
20k
3
Q
+
−
2
1
R
5.0k
Osc
.
Bias
R
5
3
RT
RA
(RA + RB)C
RB
RA + RB
To additional MC34065s
Dmax Drive Output 2 =
RA
RA + RB
Figure 18. External Duty Cycle Clamp and
Multi−Unit Synchronization
PIN FUNCTION DESCRIPTION
Pin
Function
Description
1
Sync Input
A narrow rectangular waveform applied to this input will synchronize the oscillator. A dc voltage
within the range of 2.4 V to 5.5 V will inhibit the oscillator.
2
CT
Timing capacitor CT connects from this pin to ground setting the free−running oscillator frequency
range.
3
RT
Resistor RT connects from this pin to ground precisely setting the charge current for CT. RT must
be between 4.0 k and 16 k.
4
Voltage Feedback 1
This pin is the inverting input of Error Amplifier 1. It is normally connected to the switching power
supply output through a resistor divider.
5
Compensation 1
This pin is the output of Error Amplifier 1 and is made available for loop compensation.
6
Current Sense 1
A voltage proportional to the inductor current is connected to this input. PWM 1 uses this
information to terminate conduction of output switch Q1.
7
Drive Output 1
This pin directly drives the gate of a power MOSFET Q1. Peak currents up to 400 mA are sourced
and sunk by this pin.
8
Gnd
This pin is the control circuitry ground return and is connected back to the source ground.
9
Drive Gnd
This pin is a separate power ground return that is connected back to the power source. It is used
to reduce the effects of switching transient noise on the control circuitry.
10
Drive Output 2
This pin directly drives the gate of a power MOSFET Q2. Peak currents up to 400 mA are sourced
and sunk by this pin.
11
Current Sense 2
A voltage proportional to inductor current is connected to this input. PWM 2 uses this information
to terminate conduction of output switch Q2.
12
Compensation 2
This pin is the output of Error Amplifier 2 and is made available for loop compensation.
13
Voltage Feedback 2
This pin is the inverting input of Error Amplifier 2. It is normally connected to the switching power
supply output through a resistor divider.
14
Drive Output 2 Enable
A logic low at this input disables Drive Output 2.
15
Vref
This is the 5.0 V reference output. It can provide bias for any additional system circuitry.
16
VCC
This pin is the positive supply of the control IC. The minimum operating voltage range after startup
is 11 V to 15.5 V for the −H suffix, 8.2 V to 9.5 V for the −L suffix.
http://onsemi.com
12
MC34065−H, L
VCC
Vin
16
Vref
+
5.0Vref
1
5
−
+
_
R
Bias
1
Vref
+
R
15
+ −
_
20k
R
Bias
R
3
2
−
3
Osc.
2
Q
−
R
1.0V
1.67
+ 0.33 x 10−3 (R1)
R2
) 1
R1
Ǔ
C
Where: 0 ≤ VClamp ≤ 1.0 V
tSoft−Start ≈ 2100 C in μF
Figure 19. Adjustable Reduction of Clamp Level
Figure 20. Soft−Start Circuit
VCC
16
+
5.0Vref
Bias
+
−
R
1
20k
+
_
3
+
VClamp
−
EA1
R2
C
5
R1
PWM
Latch 1
S
Q
R
−
7
−
+
ǒ
Ǔ
1−
VCC
C
+
_
VC
−
RS
R 1 ) R 2
3 VClamp
Figure 22. MOSFET Parasitic Oscillations
Vin
VCC
Vin
16
+
_
D
PWM
Latch 1
S
Q
R
7
M
SENSEFET
S
Power Ground to
Input Source Return
K
Drive Ground
to Pin 9
6
Control Circuitry Ground
to Pin 8
+
_
5.0Vref
+
_
G
+
1N5819
Series gate resistor Rg may be needed to damp high frequency parasitic
oscillations caused by the MOSFET input capacitance and any series
wiring inductance in the gate−source circuit. Rg will decrease the MOSFET
switching speed. Schottky diode D1 is required if circuit ringing drives the
output pin below ground.
R 1R 2
16
+
_
D1
6
Figure 21. Adjustable Reduction of Clamp Level
with Soft−Start
5.0Vref
Q1
7
RS
RS
1
tSoft−Start = In
R2
) 1
R1
6
VClamp
Ipk(max) ≈
MPSA63
VClamp ≈
Rg
PWM
Latch 1
S
Q
R
R
Where: 0 ≤ VClamp ≤ 1.0 V
1.67
−
Q1
+
2R
1.0V
+
_
−
2
+
−
+
Osc
4
+
5.0Vref
− +
_
R
Vin
VCC
Vin
16
15
R
5
RS
Vref
2R
1.0V
EA1
RS
VClamp
Ipk(max) ≈
−
1.0M
6
ǒ
+
4
5
VClamp ≈
1.0mA
R
+
2R
EA1
20k
S
VClamp
+
4
7
PWM
Latch 1
1.0mA
R2
R1
1
Q1
Osc.
RS
1/4W
VPin6 ≈
+
_
+
_
+
_
Q1
RS Ipk rDS(on)
rDM(on) + RS
−
+
If: SENSEFET = MTP10N10M
RS = 200
Then: VPin6 = 0.075 Ipk
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over current conditions, a reduction
of the Ipk(max) clamp level must be implemented. Refer to Figures 19 and 21.
PWM
Latch 1
S
Q
R
7
R
6
C
RS
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
Figure 23. Current Sensing Power MOSFET
Figure 24. Current Waveform Spike Suppression
http://onsemi.com
13
MC34065−H, L
IB
Vin
+
VCC
Vin
0
16
Base Charge
Removal
−
+
5.0Vref
C1
−
+
+
_
Isolation
Boundary
+ −
−
−
RS
+
Q1
PWM
Latch 1
S
Q
R
7
D1
6
R
The totem−pole outputs can furnish negative base current for enhanced
transistor turn−off, with the addition of capacitor C1.
ǒǓ
Figure 25. Bipolar Transistor Drive
NS
C
* 1.4 N
(Pin 6)
P
I pk +
N
3R
S
S
V
Figure 26. Isolated MOSFET Drive
VCC=15V
+
16
15
+
5.0Vref
−
R
2.5V
Bias
R
47
+
_
+
20k
1
+ −
_
3
27
10
12k
1.0nF
PWM
Latch 1
2
1.0mA
4
+
−
+
EA1
1.0V
250μA
13
ǒ
27
10
PWM
Latch 2
+
R2
R1
6
1.0mA
47
R
R
14
+
Connect to Pin 4 for
closed−loop regulation.
Q
−
1N5819
+
7
S
2R
5
10
10
+VO≈2.0VCC
Osc.
10
Ǔ
R2
) V + 2.5
) 1
O
R1
10
1N5819
+
10
47
−VO≈−VCC
+
S
2R
−
−
+
EA2
1.0V
R Q
R
Output Load Regulation
R
11
12
8
9
IO (mA)
+VO (V)
−VO (V)
0
1.0
5.0
10
50
28.43
27.72
27.04
26.20
20.52
−13.89
−12.90
−12.25
−11.44
−5.80
The capacitor’s equivalent series resistance must limit the Drive Output current to 400 mA. An additional series resistor may be required
when using tantalum or other low ESR capacitors. The positive output can provide excellent line and load regulation by connecting the R2/R1
resistor divider as shown.
Figure 27. Dual Charge Pump Converter
http://onsemi.com
14
NP
MC34065−H, L
10 Cold
<1 Hot
T
92Vac to
138Vac
MDA
970G5
T1
+
270
56k
0.05
0.22
3.0A
MUR110
100
16
T2
L1
MUR110
+
220
+
+
9.0V
0.1A
10
1N4148
75k
RTN
+
5.0Vref
15
−
R
Bias
R
1
20k
+
_
3
5.6k
4.7
nF
Osc.
2
4
+
2R
−
+
−
16.2k
1.0M
+
−
EA1
100
pF
1.0V
10k
T3
+
_
MUR415
10
PWM
Latch 1
S
Q
R
10
7
1N
4937
6
R
MUR
440
1.0 k
470
pF
10
1000
1/2
4N35
10
68k
51k
0.01
100
12V
1.0A
+
100
+
−12V
1.0A
L4
L2
MPS
+ A20
100V
1.0A
0.01
3.3k
TL
43A
3.3
+
1.3k
RTN
10k
10
1/2
4N35
14
13
+
2R
−
−
47k
330
MUR415
3300
pF
MTD
2N50
+
1000
RTN
10
12k
22
0.001
0.001
4.7k
330
+
330
pF
5
47k
L3
180
pF
EA2
R
1.0V
+
S
R Q
R
10
PWM
Latch 2
10
22
11
1.0k
MC34065−H
12
8
470pF
MTH
8N45
Output 2
Shutdown
0.082
9
Test
Line Regulation
100 V Output
±12 V Outputs
9.0 V Output
Conditions
Vin = 92 Vac to 138 Vac
IO = 1.0 A
IO = ±1.0 A
IO = 0.1 A
Results
Δ = 40 mV or ±0.02%
Δ = 32 mV or ±0.13%
Δ = 55 mV or ±0.31%
Load Regulation
100 V Output
±12 V Outputs
9.0 V Output
Vin = 115 Vac
IO = 0.25 A to 1.0 A
IO = ±0.25 A to ±1.0 A
IO = 0.08 A to 0.1 A
Δ = 50 mV or ±0.025%
Δ = 320 mV or ±1.2%
Δ = 234 mV or ±1.3%
Output Ripple
100 V Output
±12 V Outputs
9.0 V Output
Vin = 115 Vac
IO = 1.0 A
IO = ±1.0 A
IO = 0.1 A
Short Circuit Current
100 V Output
±12 V Outputs
9.0 V Output
Vin = 115 Vac, RL = 0.1 Ω
Efficiency
Vin = 115 Vac, PO = 125 W
T1 −
468 μH per section at 2.5 A,
Coilcraft E3496A.
T2 −
Primary: 156 Turns, #34 AWG
Primary Feedback: 19 Turns, #34 AWG
Secondary: 17 Turns, #28 AWG
Core: TDK PC30 EE22−Z
Bobbin: BE22−118CP
Gap: ≈0.001″ for a primary
inductance of 6.8 mH
Primary: 56 Turns, #23 AWG
(2 strands) Bifiliar Wound
Secondary: ±12 V, 4 Turns, #23 AWG
(4 strands) Quadfiliar Wound
Secondary 100 V: 32 Turns, #23 AWG (2
strands) Bifiliar Wound
Core: TDK PC30 EER40 G0.76
Bobbin: BEER40−1112CP
Gap: ≈0.030″ for a primary
inductance of 212 μH
T3 −
40 mVpp
100 mVpp
60 mVpp
4.3 A
17 A
Output Hiccups
L1, L3, L4 −
86
%
Figure 28. 125 Watt Off−Line Converter
http://onsemi.com
15
L2 −
25 μH at 1.0 A, Coilcraft Z7157.
10 μH at 3.0 A, Coilcraft
PCV−0−010−03.
MC34065−H, L
5 11/16″
4 1/2″
(CIRCUIT VIEW)
AC INPUT
9V
*
100V
12V −12V
(COMPONENT VIEW)
*100 V and ±12 V Shutdown
Figure 29. PC Board Circuit Side and Component View
http://onsemi.com
16
MC34065−H, L
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 648−08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
S
−T−
H
SEATING
PLANE
K
G
D
M
J
16 PL
0.25 (0.010)
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
DW SUFFIX
PLASTIC PACKAGE
CASE 751G−03
(SOP−8+8L)
ISSUE B
A
D
9
1
8
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16X
M
T A
S
B
h X 45 _
S
14X
e
L
A
0.25
B
B
A1
H
E
0.25
8X
M
B
M
16
q
SEATING
PLANE
T
C
http://onsemi.com
17
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
10.15
10.45
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC34065−H, L
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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