MOTOROLA MC54/74HC533A Octal 3-state inverting transparent latch high-performance silicon-gate cmo Datasheet

 SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC54/74HC533A is identical in pinout to the LS533. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The Data appears at the
outputs in inverted form. When Latch Enable goes low, data meeting the
setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high-impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC533A is identical in function to the HC563 but has the data inputs
on the opposite side of the package from the outputs to facilitate PC board
layout.
This device is similar in function to the HC373A, which has noninverting
outputs.
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
20
1
1
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 256 FETs or 64 Equivalent Gates
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
2
4
5
7
6
8
9
OUTPUT
ENABLE
Q0
13
12
14
15
17
16
18
19
LATCH ENABLE 11
1
OUTPUT ENABLE
Q0
Q1
Q2
Q3
Q4
1
20
VCC
2
19
Q7
D0
3
18
D7
D1
4
17
D6
Q1
5
16
Q6
Q2
6
15
Q5
D2
7
14
D5
D3
8
13
D4
Q3
9
12
10
11
Q4
LATCH
ENABLE
GND
INVERTING
OUTPUTS
Q5
FUNCTION TABLE
Q6
Inputs
Q7
PIN 20 = VCC
PIN 10 = GND
3/97
1
REV 3
Output
Output
Enable
Latch
Enable
D
Q
L
L
L
H
H
H
L
X
H
L
X
X
L
H
No Change
Z
X = Don’t Care
Z = High Impedance
 Motorola, Inc. 1997
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
3
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
•
•
•
•
•
•
D0
MC54/74HC533A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = VCC – 0.1 V
|Iout|
20 µA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V
|Iout|
20 µA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
Minimum High–Level Output
Voltage
Vin = VIH
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
Vin = VIH
VOL
Maximum Low–Level Output
Voltage
2.4 mA
6.0 mA
7.8 mA
Vin = VIL
|Iout|
20 µA
Vin = VIL
MOTOROLA
|Iout|
|Iout|
|Iout|
|Iout|
|Iout|
|Iout|
2
2.4 mA
6.0 mA
7.8 mA
V
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC533A
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
Iin
Maximum Input Leakage Current
IOZ
Maximum Three–State Leakage
Current
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
Vin = VCC or GND
Iout = 0 µA
VCC
V
– 55 to
25_C
6.0
± 0.1
± 1.0
± 1.0
µA
6.0
± 0.5
± 5.0
± 10
µA
6.0
4.0
40
160
µA
85_C
125_C
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
S b l
Symbol
P
Parameter
Fi
Fig.
VCC
V
– 55 to
25_C
85_C
125_C
U i
Unit
tPLH
tPHL
Maximum Propagation Delay, Input D to Q
1, 5
2.0
3.0
4.5
6.0
125
80
25
21
155
110
31
26
190
130
38
32
ns
tPLH
tPHL
Maximum Propagation Delay, Latch Enable to Q
2, 5
2.0
3.0
4.5
6.0
125
80
25
21
155
110
31
26
190
130
38
32
ns
tPLZ
tPHZ
Maximum Propagation Delay, Output Enable to Q
3, 6
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL
tPZH
Maximum Propagation Delay, Output Enable to Q
3, 6
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tTLH
tTHL
Maximum Output Transition Time, Any Output
1, 5
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Maximum Input Capacitance
10
10
10
pF
Maximum Tri–State Output Capacitance (Output in Hi–Impedance State)
15
15
15
pF
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Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
P
Power
Di
Dissipation
i i C
Capacitance
i
(P
(Per E
Enabled
bl d O
Output)*
)*
36
pF
F
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC54/74HC533A
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TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
S b l
Parameter
P
Fig.
Fi
VCC
Volts
– 55 to 25_C
Min
85_C
Max
Min
125_C
Max
Min
Max
Unit
U i
tsu
Minimum Setup Time, Input D to Latch Enable
4
2.0
3.0
4.5
6.0
25
20
5.0
5.0
30
25
6.0
6.0
40
30
8.0
7.0
ns
th
Minimum Hold Time, Latch Enable to Input D
4
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Latch Enable
2
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
tr, tf
Maximum Input Rise and Fall Times
1
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
SWITCHING WAVEFORMS
tr
INPUT D
tf
VCC
VCC
90%
LATCH
ENABLE
50%
50%
10%
tPHL
GND
tw
GND
tPLH
tPLH
tPHL
90%
Q
50%
Q
50%
10%
tTHL
tTLH
Figure 1.
Figure 2.
OUTPUT
ENABLE
VCC
50%
VALID
VCC
GND
tPZL
tPLZ
INPUT D
HIGH
IMPEDANCE
Q
50%
tsu
50%
tPZH
10%
VOL
90%
VOH
tPHZ
LATCH
ENABLE
th
GND
VCC
50%
GND
1.3 V
HIGH
IMPEDANCE
Q
Figure 3.
MOTOROLA
Figure 4.
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC533A
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH
1 kΩ
OUTPUT
CL*
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 5.
Figure 6.
EXPANDED LOGIC DIAGRAM
D0
3
D1
4
D
Q
D
LE
LATCH
ENABLE
OUTPUT
ENABLE
D2
7
Q
D3
8
D
LE
Q
D4
13
D
LE
Q
D5
14
D
LE
Q
D6
17
D
LE
Q
D7
18
D
LE
Q
D
LE
Q
LE
11
1
2
Q0
High–Speed CMOS Logic Data
DL129 — Rev 6
5
Q1
6
9
Q2
Q3
5
12
Q4
15
Q5
16
Q6
19
Q7
MOTOROLA
MC54/74HC533A
OUTLINE DIMENSIONS
20
11
1
10
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
A
L
C
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
N
H
G
D
J
K
M
MILLIMETERS
MIN
MAX
23.88
25.15
6.60
7.49
3.81
5.08
0.38
0.56
1.40
1.65
2.54 BSC
0.51
1.27
0.20
0.30
3.18
4.06
7.62 BSC
0_
15 _
0.25
1.02
INCHES
MIN
MAX
0.940
0.990
0.260
0.295
0.150
0.200
0.015
0.022
0.055
0.065
0.100 BSC
0.020
0.050
0.008
0.012
0.125
0.160
0.300 BSC
0_
15_
0.010
0.040
SEATING
PLANE
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
M
T A
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R X 45 _
C
–T–
18X
G
K
SEATING
PLANE
M
T B
M
M
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
–A–
20
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
MOTOROLA
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
M
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC533A
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
7
MC74HC533A/D
MOTOROLA
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