MOTOROLA MC54HC4538AJ Dual precision monostable multivibrator (retriggerable, resettable) Datasheet

SEMICONDUCTOR TECHNICAL DATA
! ! " The MC54/74HC4538A is identical in pinout to the MC14538B. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This dual monostable multivibrator may be triggered by either the positive
or the negative edge of an input pulse, and produces a precision output
pulse over a wide range of pulse widths. Because the device has conditioned
trigger inputs, there are no trigger–input rise and fall time restrictions. The
output pulse width is determined by the external timing components, Rx and
Cx. The device has a reset function which forces the Q output low and the Q
output high, regardless of the state of the output pulse circuitry.
• Unlimited Rise and Fall Times Allowed on the Trigger Inputs
• Output Pulse is Independent of the Trigger Pulse Width
• ± 10% Guaranteed Pulse Width Variation from Part to Part (Using the
Same Test Jig)
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 145 FETs or 36 Equivalent Gates
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
1
ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
GND
1
16
VCC
CX1/RX1
2
15
GND
RESET 1
3
14
CX2/RX2
A1
4
13
RESET 2
B1
5
12
A2
Q1
6
11
B2
Q1
7
10
Q2
GND
8
9
Q2
RX1
VCC
1
2
6
4
TRIGGER A1
INPUTS B1 5
RESET 1
7
Q1
Q1
CX2
RX2
VCC
3
15
TRIGGER
INPUTS
A2
B2
RESET 2
FUNCTION TABLE
Inputs
14
12
10
11
9
13
PIN 16 = VCC
PIN 8 = GND
RX AND CX ARE EXTERNAL COMPONENTS
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND
Reset
Q2
Q2
3–1
A
Outputs
B
Q
Q
H
H
L
H
H
X
H
L
X
Not Triggered
Not Triggered
H
H
L,H,
L
H
L,H,
Not Triggered
Not Triggered
L
X
X
X
X
L
H
Not Triggered
10/95
 Motorola, Inc. 1995
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
CX1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
REV 6
H
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MC54/74HC4538A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Vin
DC Input Voltage (Referenced to GND)
Vout
DC Output Voltage (Referenced to GND)
Iin
DC Input Current, per Pin
Value
Unit
– 0.5 to + 7.0
V
– 1.5 to VCC + 1.5
V
– 0.5 to VCC + 0.5
A, B, Reset
Cx, Rx
± 20
± 30
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 7)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
A or B (Figure 5)
Rx
External Timing Resistor
Cx
External Timing Capacitor
VCC < 4.5 V
VCC ≥ 4.5 V
Max
Unit
3.0**
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
—
No Limit
1.0
2.0
*
*
kΩ
0
*
µF
* The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx, the leakage of the HC4538A, and leakage due to
board layout and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10 µF/1.0 MΩ. Values of Cx > 1.0 µF
may cause a problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may occur for
Rx > 1.0 MΩ.
** The HC4538A will function at 2.0 V but for optimum pulse width stability, VCC should be above 3.0 V.
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
3–2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HC4538A
DC CHARACTERISTICS FOR THE MC54/74HC4538A
Guaranteed Limits
Symbol
Parameter
Test Conditions
– 55 to
25_C
VCC
Volts
Min
1.5
3.15
4.2
Max
85_C
Min
Max
Max
VIH
Minimum High–Level
Input Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
VIL
Maximum Low–Level
Input Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
VOH
Minimum High–Level
Output Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
Vin = VIH or VIL
|Iout|
– 4.0 mA
|Iout|
– 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout|
4.0 mA
|Iout|
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VOL
Maximum Low–Level
Output Voltage
1.5
3.15
4.2
125_C
Min
0.5
1.35
1.8
1.5
3.15
4.2
0.5
1.35
1.8
Unit
V
0.5
1.35
1.8
V
V
V
Iin
Maximum Input
Leakage Current
(A, B, Reset)
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Iin
Maximum Input
Leakage Current
(Rx, Cx)
Vin = VCC or GND
6.0
± 50
± 500
± 500
nA
ICC
Maximum Quiescent
Supply Current
(per package)
Standby State
Vin = VCC or GND
Q1 and Q2 = Low
Iout = 0 µA
6.0
130
220
350
µA
ICC
Maximum Supply Current
(per package)
Active State
Vin = VCC or GND
Q1 and Q2 = High
Iout = 0 µA
Pins 2 and 14 = 0.5 VCC
High–Speed CMOS Logic Data
DL129 — Rev 6
25_C
6.0
3–3
400
– 45_C to
85_C
600
– 55_C to
125_C
800
µA
MOTOROLA
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MC54/74HC4538A
AC CHARACTERISTICS FOR THE MC54/74HC4538A (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limits
Symbol
VCC
Volts
Parameter
– 55 to
25_C
Min
Max
85_C
Min
Max
125_C
Min
Max
Unit
tPLH
Maximum Propagation Delay
Input A or B to Q
(Figures 6 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPHL
Maximum Propagation Delay
Input A or B to NQ
(Figures 6 and 8)
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
ns
tPHL
Maximum Propagation Delay
Reset to Q
(Figures 7 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH
Maximum Propagation Delay
Reset to NQ
(Figures 7 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 7 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
—
10
25
10
25
10
25
pF
Cin
Maximum Input Capacitance
(A. B, Reset)
(Cx, Rx)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CPD
Power Dissipation Capacitance (Per Multivibrator)*
pF
150
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING CHARACTERISTICS FOR THE MC54/74HC4538A (Input tr = tf = 6.0 ns)
Guaranteed Limits
– 55 to
25_C
85_C
125_C
VCC
Volts
Min
Minimum Recovery Time, Inactive to A or B
(Figure 7)
2.0
4.5
6.0
0
0
0
0
0
0
0
0
0
ns
tw
Minimum Pulse Width, Input A or B
(Figure 6)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tw
Minimum Pulse Width, Reset
(Figure 7)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
Maximum Input Rise and Fall Times, Reset
(Figure 7)
2.0
4.5
6.0
A or B
(Figure 7)
2.0
4.5
6.0
Symbol
trec
tr, tf
Parameter
MOTOROLA
3–4
Max
1000
500
400
Min
Max
1000
500
400
Min
Max
1000
500
400
Unit
ns
No Limit
High–Speed CMOS Logic Data
DL129 — Rev 6
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
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ÎÎÎ
ÎÎÎ
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ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
v ÎÎÎ
v ÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC54/74HC4538A
OUTPUT PULSE WIDTH CHARACTERISTICS (CL = 50 pF)t
Conditions
Symbol
Guaranteed Limits
– 55 to
25_C
85_C
125_C
Timing Components
VCC
Volts
Min
Max
Min
Max
Min
Max
Unit
Rx = 10 kΩ, Cx = 0.1 µF
5.0
0.63
0.77
0.6
0.8
0.59
0.81
ms
Parameter
τ
Output Pulse Width*
(Figures 6 and 8)
—
Pulse Width Match
Between Circuits in the
same Package
—
—
± 5.0
%
—
Pulse Width Match
Variation (Part to Part)
—
—
± 10
%
10 s
0.8
TA = 25°C
1s
0.7
OUTPUT PULSE WIDTH (τ )
k, OUTPUT PULSE WIDTH CONSTANT (TYPICAL)
* For output pulse widths greater than 100 µs, typically τ = kRxCx, where the value of k may be found in Figure 1.
0.6
0.5
0.4
100 ms
10 ms
1 ms
100 µs
1
2
3
4
5
6
VCC, POWER SUPPLY VOLTAGE (VOLTS)
1 MΩ
10 µs 100 kΩ
1 µs
0.3
VCC = 5 V, TA = 25°C
10 kΩ
1 kΩ
100 ns
0.00001 0.0001
7
0.001
0.01
0.1
CAPACITANCE (µF)
1
10
100
Figure 2. Output Pulse Width versus
Timing Capacitance
Figure 1. Typical Output Pulse Width Constant, k,
versus Supply Voltage
(For output pulse widths > 100 µs: τ = kRxCx)
OUTPUT PULSE WIDTH (t)
(NORMALIZED TO 5 V NUMBER)
1.1
TA = 25°C
Rx = 100 kΩ
Cx = 1000 pF
1
0.9
0.8
Rx = 1 MΩ
Cx = 0.1 µF
0.7
0.6
0.5
1
2
3
4
5
6
VCC, POWER SUPPLY VOLTAGE (VOLTS)
7
Figure 3. Normalized Output Pulse Width
versus Power Supply Voltage
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
MC54/74HC4538A
OUTPUT PULSE WIDTH (τ )
(NORMALIZED TO 25 °C NUMBER)
1.1
1.05
1
VCC = 6 V
0.95
Rx = 10 kΩ
Cx = 0.1 µF
0.9
0.85
VCC = 3 V
0.8
– 75
– 50
– 25
0
25
50
75
100
125
150
125
150
TA, AMBIENT TEMPERATURE (°C)
Figure 4. Normalized Output Pulse Width
versus Power Supply Voltage
OUTPUT PULSE WIDTH (τ )
(NORMALIZED TO 25 °C NUMBER)
1.03
Rx = 10 kΩ
Cx = 0.1 µF
1.02
1.01
1
VCC = 5.5 V
0.99
VCC = 5 V
0.98
VCC = 4.5 V
0.97
– 75
– 50
– 25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (°C)
Figure 5. Normalized Output Pulse Width
versus Power Supply Voltage
MOTOROLA
3–6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC4538A
SWITCHING WAVEFORMS
tw(H)
VCC
50%
GND
A
tw(L)
VCC
B
50%
GND
τ
tPLH
τ
tPLH
50%
Q
τ
tPHL
τ
tPHL
Q
50%
tr
Figure 6.
tf
VCC
90%
10%
A
GND
trr
VCC
50%
GND
B
tf
tf
10%
tw(L)
tTLH
GND
trec
τ + trr
tPHL
90%
50%
50%
(RETRIGGERED PULSE)
10%
Q
tTHL
Q
VCC
90%
50%
RESET
tPLH
90%
10%
50%
Figure 7.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
Figure 8. Test Circuit
High–Speed CMOS Logic Data
DL129 — Rev 6
3–7
MOTOROLA
MC54/74HC4538A
PIN DESCRIPTIONS
INPUTS
tors (see the Block Diagram). Polystyrene capacitors are
recommended for optimum pulse width control. Electrolytic
capacitors are not recommended due to high leakages
associated with these type capacitors.
A1, A2 (Pins 4, 12)
Positive–edge trigger inputs. A rising–edge signal on
either of these pins triggers the corresponding multivibrator
when there is a high level on the B1 or B2 input.
GND (Pins 1 and 15)
External ground. The external timing capacitors discharge
to ground through these pins.
B1, B2 (Pins 5, 11)
Negative–edge trigger inputs. A falling–edge signal on
either of these pins triggers the corresponding multivibrator
when there is a low level on the A1 or A2 input.
OUTPUTS
Q1, Q2 (Pins 6, 10)
Noninverted monostable outputs. These pins (normally
low) pulse high when the multivibrator is triggered at either
the A or the B input. The width of the pulse is determined by
the external timing components, RX and CX.
Reset 1, Reset 2 (Pins 3, 13)
Reset inputs (active low). When a low level is applied to
one of these pins, the Q output of the corresponding multivibrator is reset to a low level and the Q output is set to a high
level.
Q1, Q2 (Pins 7, 9)
Inverted monostable outputs. These pins (normally high)
pulse low when the multivibrator is triggered at either the A or
the B input. These outputs are the inverse of Q1 and Q2.
CX1/RX1 and CX2/RX2 (Pins 2 and 14)
External timing components. These pins are tied to the
common points of the external timing resistors and capaci-
LOGIC DETAIL
(1/2 THE DEVICE)
RxCx
UPPER
REFERENCE
CIRCUIT
–
+
Vre, UPPER
VCC
VCC
OUTPUT
LATCH
LOWER
REFERENCE
CIRCUIT
M1
2 kΩ
–
+
M2
Q
Vre, LOWER
M3
Q
TRIGGER CONTROL
CIRCUIT
A
C
Q
TRIGGER CONTROL
RESET CIRCUIT
CB R
B
RESET
POWER
ON
RESET
RESET LATCH
Figure 9.
MOTOROLA
3–8
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC4538A
CIRCUIT OPERATION
Figure 12 shows the HC4538A configured in the retriggerable mode. Briefly, the device operates as follows (refer to
Figure 10): In the quiescent state, the external timing capacitor, Cx, is charged to V CC. When a trigger occurs, the Q output goes high and C x discharges quickly to the lower
reference voltage (Vref Lower 1/3 V CC). Cx then charges,
through Rx, back up to the upper reference voltage (Vref Upper
2/3 V CC), at which point the one–shot has timed out
and the Q output goes low.
The following, more detailed description of the circuit operation refers to both the logic detail (Figure 9) and the timing
diagram (Figure 10).
TRIGGER OPERATION
The HC4538A is triggered by either a rising–edge signal at
input A (#7) or a falling–edge signal at input B (#8), with the
unused trigger input and the Reset input held at the voltage
levels shown in the Function Table. Either trigger signal will
cause the output of the trigger–control circuit to go high (#9).
The trigger–control circuit going high simultaneously initiates two events. First, the output latch goes low, thus taking
the Q output of the HC4538A to a high state (#10). Second,
transistor M3 is turned on, which allows the external timing
capacitor, Cx, to rapidly discharge toward ground (#11).
(Note that the voltage across Cx appears at the input of both
the upper and lower reference circuit comparator).
When Cx discharges to the reference voltage of the lower
reference circuit (#12), the outputs of both reference circuits
will be high (#13). The trigger–control reset circuit goes high,
resetting the trigger–control circuit flip–flop to a low state
(#14). This turns transistor M3 off again, allowing Cx to begin
to charge back up toward VCC, with a time constant t = RxCx
(#15). Once the voltage across Cx charges to above the lower reference voltage, the lower reference circuit will go low
allowing the monostable multivibrator to be retriggered.
[
[
QUIESCENT STATE
In the quiescent state, before an input trigger appears, the
output latch is high and the reset latch is high (#1 in Figure 10). Thus the Q output (pin 6 or 10) of the monostable
multivibrator is low (#2, Figure 10).
The output of the trigger–control circuit is low (#3), and
transistors M1, M2, and M3 are turned off. The external timing capacitor, Cx, is charged to VCC (#4), and both the upper
and lower reference circuit has a low output (#5).
In addition, the output of the trigger–control reset circuit is
low.
QUIESCENT
STATE
TRIGGER CYCLE
(A INPUT)
TRIGGER CYCLE
(B INPUT)
RESET
RETRIGGER
trr
7
TRIGGER INPUT A
(PIN 4 OR 12)
TRIGGER INPUT B
(PIN 5 OR 11)
8
24
9
TRIGGER-CONTROL
CIRCUIT OUTPUT
3
14
11
4
RX/CX INPUT
(PIN 2 OR 14)
15
21
17
23
12
Vref LOWER
5
UPPER REFERENCE
CIRCUIT
Vref UPPER
13
25
18
13
LOWER REFERENCE
CIRCUIT
6
16
RESET INPUT
(PIN 3 OR 13)
20
1
RESET LATCH
22
10
Q OUTPUT
(PIN 6 OR 10)
2
19
τ
τ
τ + trr
Figure 10. Timing Diagram
High–Speed CMOS Logic Data
DL129 — Rev 6
3–9
MOTOROLA
MC54/74HC4538A
When Cx charges up to the reference voltage of the upper
reference circuit (#17), the output of the upper reference circuit goes low (#18). This causes the output latch to toggle,
taking the Q output of the HC4538A to a low state (#19), and
completing the time–out cycle.
occurs, the output of the reset latch goes low (#22), turning
on transistor M1. Thus Cx is allowed to quickly charge up to
VCC (#23) to await the next trigger signal.
On power up of the HC4538A the power–on reset circuit
will be high causing a reset condition. This will prevent the
trigger–control circuit from accepting a trigger input during
this state. The HC4538A’s Q outputs are low and the Q not
outputs are high.
POWER–DOWN CONSIDERATIONS
Large values of Cx may cause problems when powering
down the HC4538A because of the amount of energy stored
in the capacitor. When a system containing this device is
powered down, the capacitor may discharge from V CC
through the input protection diodes at pin 2 or pin 14. Current
through the protection diodes must be limited to 30 mA;
therefore, the turn–off time of the VCC power supply must not
be faster than t = V C C C x / (30 mA). For example, if
V CC = 5.0 V and Cx = 15 µF, the VCC supply must turn off no
faster than t = (5.0 V)(15 µF)/30 mA = 2.5 ms. This is usually
not a problem because power supplies are heavily filtered
and cannot discharge at this rate.
When a more rapid decrease of VCC to zero volts occurs,
the HC4538A may sustain damage. To avoid this possibility,
use an external damping diode, D x, connected as shown in
Figure 11. Best results can be achieved if diode Dx is chosen
to be a germanium or Schottky type diode able to withstand
large current surges.
RETRIGGER OPERATION
When used in the retriggerable mode (Figure 12), the
HC4538A may be retriggered during timing out of the output
pulse at any time after the trigger–control circuit flip–flop has
been reset (#24), and the voltage across Cx is above the lower reference voltage. As long as the Cx voltage is below the
lower reference voltage, the reset of the flip–flop is high, disabling any trigger pulse. This prevents M3 from turning on
during this period resulting in an output pulse width that is
predictable.
The amount of undershoot voltage on RxCx during the
trigger mode is a function of loop delay, M3 conductivity, and
V DD. Minimum retrigger time, trr (Figure 7), is a function of
1) time to discharge R x C x from V DD to lower reference
voltage (T discharge); 2) loop delay (T delay); 3) time to charge
R x C x from the undershoot voltage back to the lower reference voltage (Tcharge).
Figure 13 shows the device configured in the non–retriggerable mode.
An Application Note (AN1558/D) titled Characterization of
Retrigger Time in the HC4538A Dual Precision Monstable
Multivibrator is being prepared. Please consult the factory for
its availability.
RESET AND POWER ON RESET OPERATION
A low voltage applied to the Reset pin always forces the Q
output of the HC4538A to a low state.
The timing diagram illustrates the case in which reset occurs (#20) while Cx is charging up toward the reference voltage of the upper reference circuit (#21). When a reset
DX
CX
VCC
RX
Q
A
B
Q
RESET
Figure 11. Discharge Protection During Power Down
MOTOROLA
3–10
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC4538A
TYPICAL APPLICATIONS
CX
RX
RISING–EDGE
TRIGGER
RISING–EDGE
TRIGGER
VCC
VCC
Q
A
B
RX
CX
Q
A
Q
B
Q
B = VCC
RESET = VCC
CX
RESET = VCC
RX
CX
VCC
A = GND
VCC
Q
Q
B
FALLING–EDGE
TRIGGER
RX
A
B
Q
Q
FALLING–EDGE
TRIGGER
RESET = VCC
Figure 12. Retriggerable Monostable Circuitry
RESET = VCC
Figure 13. Non–retriggerable Monostable Circuitry
ONE–SHOT SELECTION GUIDE
100 ns
MC14528B
MC14536B
MC14538B
MC14541B
HC4538A*
1 µs
10 µs 100 µs 1 ms 10 ms 100 ms
1s
10 s
23 HR
5 MIN
* Limited operating voltage (2 – 6 V)
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
High–Speed CMOS Logic Data
DL129 — Rev 6
3–11
MOTOROLA
MC54/74HC4538A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
–B
–
L
C
DIM
A
B
C
D
E
F
G
J
K
L
M
N
–T
K
N
SEATING
–
PLANE
E
M
F
J 16 PL
0.25 (0.010)
G
D 16 PL
0.25 (0.010)
T A
M
9
1
8
T B
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
M
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
1
P 8 PL
0.25 (0.010)
8
B
M
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
MOTOROLA
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
3–12
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
MILLIMETERS
MIN
MAX
19.05 19.93
6.10
7.49
—
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
15°
0°
1.01
0.51
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
S
S
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
—
0.200
0.015 0.020
0.050 BSC
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
15°
0°
0.020 0.040
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC4538A
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High–Speed CMOS Logic Data
DL129 — Rev 6
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CODELINE
*MC54/74HC4538A/D*
3–13
MC54/74HC4538A/D
MOTOROLA
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