ON MC74AC253 Dual 4-input multiplexer with 3-state output Datasheet

MC74AC253, MC74ACT253
Dual 4-Input Multiplexer
with 3-State Outputs
The MC74AC253/74ACT253 is a dual 4−input multiplexer with
3−state outputs. It can select two bits of data from four sources using
common select inputs. The outputs may be individually switched to a
high impedance state with a HIGH on the respective Output Enable
(OE) inputs, allowing the outputs to interface directly with bus
oriented systems.
•
•
•
•
•
Multifunctional Capability
Noninverting 3−State Outputs
Outputs Source/Sink 24 mA
′ACT253 Has TTL Compatible Inputs
These are Pb−Free Devices
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MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
16
1
xxx253G
AWLYWW
1
16
VCC
OEb
S0
I3b
I2b
I1b
I0b
Zb
16
15
14
13
12
11
10
9
16
1
xxx
253
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
1
1
2
3
4
5
6
7
8
OEa
S1
I3a
I2a
I1a
I0a
Za
GND
xxx
= AC or ACT
A
= Assembly Location
WL or L = Wafer Lot
Y
= Year
WW or W = Work Week
G or G
= Pb−Free Package
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
(Note: Microdot may be in either location)
ORDERING INFORMATION
PIN NAME
PIN
FUNCTION
I0a−I3a
Side A Data Inputs
I0b−I3b
Side B Data Inputs
S0, S1
Common Select Inputs
OEa
Side A Output Enable Input
OEb
Side B Output Enable Input
Za, Zb
3−State Outputs
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 7
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1
Publication Order Number:
MC74AC253/D
MC74AC253, MC74ACT253
TRUTH TABLE
Select
Inputs
Data Inputs
Output
Enable
Outputs
S0
S1
I0
I1
I2
I3
OE
Z
X
L
L
H
H
L
L
H
H
X
L
L
L
L
H
H
H
H
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
H
L
L
L
L
L
L
L
L
Z
L
H
L
H
L
H
L
H
OEa I0a I1a I2a I3a I0b I1b I2b I3b OEb
S0
S1
Za
Zb
Figure 2. Logic Symbol
Address inputs S0 and S1 are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
FUNCTIONAL DESCRIPTION
supplied to the two select inputs. The logic equations for the
outputs are shown:
The MC74AC253/74ACT253 contains two identical
4−input multiplexers with 3−state outputs. They select two
bits from four sources selected by common Select inputs (S0,
S1). The 4−input multiplexers have individual Output
Enable (OEa, OEb) inputs which, when HIGH, force the
outputs to a high impedance (High Z) state. This device is the
logic implementation of a 2−pole, 4−position switch, where
the position of the switch is determined by the logic levels
OEb
I3b
I2b
I1b
I0b
Za = OEa•(I0a•S1•S0+I1a•S1•S0+
I2a•S1•S0+I3a•S1•S0)
Zb = OEb•(I0b•S1•S0+I1b•S1•S0+
I2b•S1•S0+I3b•S1•S0)
If the outputs of 3−state devices are tied together, all but
one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3−state devices
whose outputs are tied together are designed so that there is
no overlap.
S0
S1
I3a
Zb
NOTE:
I2a
I1a
I0a
Za
This diagram is provided only for the understanding of logic operations
and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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2
OEa
MC74AC253, MC74ACT253
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
−0.5 to +7.0
V
DC Input Voltage
*0.5 ≤ VCC +0.5
V
VO
DC Output Voltage (Note 1)
*0.5 ≤ VCC +0.5
V
IIK
DC Input Diode Current
±20
mA
IOK
DC Output Diode Current
±50
mA
IO
DC Output Sink/Source Current
±50
mA
ICC
DC Supply Current per Output Pin
±50
mA
IGND
DC Ground Current per Output Pin
±50
mA
TSTG
Storage Temperature Range
−65 to +150
°C
TL
Lead temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction temperature under Bias
+150
°C
qJA
Thermal Resistance (Note 2)
SOIC
TSSOP
69.1
103.8
°C/W
PD
Power Dissipation in Still Air at 65°C (Note 3)
SOIC
TSSOP
500
500
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ESD Withstand Voltage
Human Body Model (Note 4)
Machine Model (Note 5)
Charged Device Model (Note 6)
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 85°C (Note 7)
VCC
DC Supply Voltage
VI
Level 1
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
> 2000
> 200
> 1000
V
±100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD51−7.
3. 500 mW at 65°C; derate to 300 mW by 10 mW/ from 65°C to 85°C.
4. Tested to EIA/JESD22−A114−A.
5. Tested to EIA/JESD22−A115−A.
6. Tested to JESD22−C101−A.
7. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
VIN, VOUT
DC Input Voltage, Output Voltage (Ref. to GND)
tr, tf
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
Min
Typ
Max
Unit
′AC
2.0
5.0
6.0
′ACT
4.5
5.0
5.5
0
−
VCC
VCC @ 3.0 V
−
150
−
VCC @ 4.5 V
−
40
−
VCC @ 5.5 V
−
25
−
VCC @ 4.5 V
−
10
−
VCC @ 5.5 V
−
8.0
−
−40
25
85
°C
V
V
ns/V
tr, tf
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
TA
Operating Ambient Temperature Range
IOH
Output Current − High
−
−
−24
mA
IOL
Output Current − Low
−
−
24
mA
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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3
MC74AC253, MC74ACT253
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74AC
74AC
TA = +25°C
TA =
−40°C to
+85°C
Typ
VIH
VIL
VOH
VOL
Unit
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1 V
or VCC − 0.1 V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1 V
or VCC − 0.1 V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
Maximum Low Level
Output Voltage
IOUT = −50 μA
V
*VIN = VIL or VIH
−12 mA
IOH
−24 mA
−24 mA
IOUT = 50 μA
V
V
*VIN = VIL or VIH
12 mA
IOL
24 mA
24 mA
IIN
Maximum Input
Leakage Current
5.5
−
±0.1
±1.0
μA
VI = VCC, GND
IOZ
Maximum
3−State
Current
5.5
−
±0.5
±5.0
μA
VI (OE) = VIL, VIH
VI = VCC, GND
VO = VCC, GND
5.5
−
−
75
mA
VOLD = 1.65 V Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
5.5
−
8.0
80
μA
VIN = VCC or GND
IOLD
IOHD
ICC
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
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4
MC74AC253, MC74ACT253
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
VCC*
(V)
Parameter
Symbol
74AC
74AC
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
tPLH
Propagation Delay
Sn to Zn
3.3
5.0
2.0
2.0
−
−
15.5
11.0
2.0
1.5
17.5
12.5
ns
3−6
tPHL
Propagation Delay
Sn to Zn
3.3
5.0
2.5
2.0
−
−
16.0
11.5
2.0
1.5
18.0
13.0
ns
3−6
tPLH
Propagation Delay
In to Zn
3.3
5.0
1.5
1.5
−
−
14.5
10.0
1.5
1.5
17.0
11.5
ns
3−5
tPHL
Propagation Delay
In to Zn
3.3
5.0
2.0
1.5
−
−
13.0
9.5
1.5
1.5
15.0
11.0
ns
3−5
tPZH
Output Enable Time
3.3
5.0
1.5
1.5
−
−
8.0
6.0
1.0
1.0
8.5
6.5
ns
3−7
tPZL
Output Enable Time
3.3
5.0
1.5
1.5
−
−
8.0
6.0
1.0
1.0
9.0
7.0
ns
3−8
tPHZ
Output Disable Time
3.3
5.0
2.0
2.0
−
−
9.5
8.0
1.5
1.5
10.0
8.5
ns
3−7
tPLZ
Output Disable Time
3.3
5.0
1.5
1.5
−
−
8.0
7.0
1.0
1.0
9.0
7.5
ns
3−8
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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5
MC74AC253, MC74ACT253
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74ACT
74ACT
TA = +25°C
TA =
−40°C to
+85°C
Typ
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
4.5
5.5
−
−
3.86
4.86
3.76
4.76
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
4.5
5.5
−
−
0.36
0.36
0.44
0.44
V
*VIN = VIL or VIH
24 mA
IOL
24 mA
VOL
Maximum Low Level
Output Voltage
V
V
IOUT = −50 μA
*VIN = VIL or VIH
−24 mA
IOH
−24 mA
IOUT = 50 μA
IIN
Maximum Input
Leakage Current
5.5
−
±0.1
±1.0
μA
VI = VCC, GND
ΔICCT
Additional Max. ICC/Input
5.5
0.6
−
1.5
mA
VI = VCC − 2.1 V
IOZ
Maximum
3−State
Current
5.5
−
±0.5
±5.0
μA
VI (OE) = VIL, VIH
VI = VCC, GND
VO = VCC, GND
5.5
−
−
75
mA
VOLD = 1.65 V Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
5.5
−
8.0
80
μA
VIN = VCC or GND
IOLD
IOHD
ICC
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
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6
MC74AC253, MC74ACT253
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
VCC*
(V)
Parameter
Symbol
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
tPLH
Propagation Delay
Sn to Zn
5.0
2.0
−
11.5
2.0
13.0
ns
3−6
tPHL
Propagation Delay
Sn to Zn
5.0
3.0
−
13.0
2.5
14.5
ns
3−6
tPLH
Propagation Delay
In to Zn
5.0
2.5
−
10.0
2.0
11.0
ns
3−5
tPHL
Propagation Delay
In to Zn
5.0
3.5
−
11.0
3.0
12.5
ns
3−5
tPZH
Output Enable Time
5.0
2.0
−
7.5
1.5
8.5
ns
3−7
tPZL
Output Enable Time
5.0
2.0
−
8.0
1.5
9.0
ns
3−8
tPHZ
Output Disable Time
5.0
3.0
−
9.5
2.5
10.0
ns
3−7
tPLZ
Output Disable Time
5.0
2.5
−
7.5
2.0
8.5
ns
3−8
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
50
pF
VCC = 5.0 V
ORDERING INFORMATION
Package
Shipping†
MC74AC253DG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74AC253DR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74AC253DTR2G
TSSOP−16
(Pb−Free)
2500 Tape & Reel
MC74ACT253DG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74ACT253DR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74ACT253DTR2G
TSSOP−16
(Pb−Free)
2500 Tape & Reel
Device Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MC74AC253, MC74ACT253
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
0.25 (0.010)
8
1
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
D
DETAIL E
G
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74AC253, MC74ACT253
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
B
M
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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MC74AC253/D
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