ON MC74AC377MEL Octal d flip-flop with clock enable Datasheet

MC74AC377, MC74ACT377
Octal D Flip-Flop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s Q
output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
•
•
•
•
•
•
•
•
•
•
•
Ideal for Addressable Register Applications
http://onsemi.com
PDIP–20
N SUFFIX
CASE 738
20
Clock Enable for Address and Data Synchronization Applications
1
SO–20
DW SUFFIX
CASE 751
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
20
Outputs Source/Sink 24 mA
1
See MC74AC273 for Master Reset Version
See MC74AC373 for Transparent Latch Version
20
See MC74AC374 for 3-State Version
1
TSSOP–20
DT SUFFIX
CASE 948E
ACT377 Has TTL Compatible Inputs
EIAJ–20
M SUFFIX
CASE 967
MSL = 1 for all Surface Mount
Chip Complexity: 292 FETS or 73 Gates
20
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 8 of this data sheet.
 Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev.6
1
Publication Order Number:
MC74AC377/D
MC74AC377, MC74ACT377
VCC
20
O7
D7
D6
O6
O5
D5
D4
O4
CP
19
18
17
16
15
14
13
12
11
D0 D1 D2 D3 D4 D5 D6 D7
CP
CE
O0 O1 O2 O3 O4 O5 O6 O7
1
2
3
4
5
6
7
8
9
10
CE
O0
D0
D1
O1
O2
D2
D3
O3
GND
Figure 2. LOGIC SYMBOL
Figure 1. Pinout: 20–Lead Packages Conductors
(Top View)
PIN NAMES
PIN
MODE SELECT-FUNCTION TABLE
FUNCTION
Inputs
Outputs
Operating Mode
D0–D7
CP
Data Inputs
CE
Clock Enable (Active LOW)
Q0–Q7
Data Outputs
CP
Clock Pulse Input
Load ′1′
CE
Dn
Qn
L
H
H
Load ′0′
L
L
L
Hold (Do Nothing)
H
H
X
X
No Change
No Change
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
D0
D1
D2
D3
D4
D5
D6
D7
CE
D
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
CP
CP
O0
O1
O2
O3
O4
O5
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. LOGIC DIAGRAM
http://onsemi.com
2
O6
O7
MC74AC377, MC74ACT377
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
–0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
–0.5 to VCC +0.5
V
Vout
DC Output Voltage (Referenced to GND)
–0.5 to VCC +0.5
V
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC VCC or GND Current per Output Pin
Tstg
Storage Temperature
θJA
Thermal Resistance (Junction to Ambient)
VESD
ESD Withstand Voltage
ILatch–Up
Latch–Up Performance
VCC
DC Supply Voltage (Referenced to GND)
Vin
±50
mA
–65 to +150
°C
97
129
69
°C/W
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 2000
> 200
> 1000
V
VCC = 5.5 V; TA = 125°C (Note 4)
> 100
mA
SOIC, DW
TSSOP, DT
PDIP, N
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
1. Tested to EIA/JESD22–A114–A
2. Tested to EIA/JESD22–A115–A
3. Tested to JESD22–C101–A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
Vin, Vout
DC Input Voltage, Output Voltage (Ref. to GND)
tr, tf
In ut Rise and Fall Time (Note 6)
Input
′ACT Devices except Schmitt Inputs
TJ
Junction Temperature (PDIP)
TA
Operating Ambient Temperature Range
IOH
Output Current — High
Typ
Max
′AC
2.0
5.0
6.0
′ACT
4.5
5.0
5.5
0
IInputt Rise
Ri and
d Fall
F ll Time
Ti
(Note
(N t 5)
′AC
AC Devices except
exce t Schmitt Inputs
In uts
tr, tf
Min
VCC
VCC @ 3.0 V
150
VCC @ 4.5 V
40
VCC @ 5.5 V
25
VCC @ 4.5 V
10
VCC @ 5.5 V
8.0
Unit
V
V
ns/V
ns/V
140
°C
85
°C
–24
mA
IOL
Output Current — Low
24
5. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
6. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
mA
–40
http://onsemi.com
3
25
MC74AC377, MC74ACT377
74AC – DC CHARACTERISTICS
TA = +25°C
+25 C
Symbol
Parameter
VCC (V)
Typ
TA =
–40°C to +85°C
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level Input Voltage
3.0
4.5
5.5
1.50
2.25
2.75
2.10
3.15
3.85
2.10
3.15
3.85
V
V
V
VOUT = 0.1 V
or
VCC – 0.1 V
VIL
Maximum Low Level Input Voltage
3.0
4.5
5.5
1.50
2.25
2.75
0.90
1.35
1.65
0.90
1.35
1.65
V
V
V
VOUT = 0.1 V
or
VCC – 0.1 V
VOH
Minimum High Level Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
V
V
IOUT = –50 µA
2.56
3.86
4.86
2.46
3.76
4.76
V
V
V
*VIN = VIL or VIH
IOH
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
IOUT = 50 µA
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
V
V
V
*VIN = VIL or VIH
IOH
Maximum Input Leakage Current
5.5
±0.1
±1.0
µA
VI = VCC, GND
Maximum Input Leakage Current
5.5
5.5
75
–75
mA
mA
VOLD = 1.65 V Max
VOHD = 3.85 V Min
3.0
4.5
5.5
VOL
IIN
IOLD
IOHD
Maximum Low Level Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
–12 mA
–24 mA
–24 mA
–12 mA
–24 mA
–24 mA
ICC
Maximum Quiescent Supply Current
5.5
8.0
80
µA
VIN = VCC or GND
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
74AC – AC CHARACTERISTICS For Figures and Waveforms, See Figures 4, 5, and 6.
Symbol
Parameter
VCC* (V)
Min
3.3
5.0
90
140
TA = +25°C
+25 C
CL = 50 pF
Typ
TA = –40°C
40 C to +85°C
+85 C
CL = 50 pF
Max
Min
Max
75
125
Unit
fmax
Maximum Clock Frequency
MHz
tPLH
Propagation Delay
CP to Qn
3.3
5.0
3.0
2.0
13.0
9.0
1.5
1.5
14.0
10.0
ns
tPHL
Propagation Delay
CP to Qn
3.3
5.0
3.5
2.5
13.0
10.0
2.0
1.5
14.5
11.0
ns
* Voltage Range 3.3 V is 3.3 V ±0.3 V; Voltage Range 5.0 V is 5.0 V ±0.5 V.
74AC – AC OPERATING REQUIREMENTS
TA = +25°C
+25 C
CL = 50 pF
Symbol
Parameter
VCC* (V)
Typ
TA = –40°C
40 C to +85°C
+85 C
Guaranteed Minimum
Unit
ts
Setup Time, HIGH or LOW
Dn to CP
3.3
5.0
5.5
4.0
6.0
4.5
ns
th
Hold Time, HIGH or LOW
Dn to CP
3.3
5.0
0
1.0
0
1.0
ns
ts
Setup Time, HIGH or LOW
CE to CP
3.3
5.0
6.0
4.0
7.5
4.5
ns
th
Hold Time, HIGH or LOW
CE to CP
3.3
5.0
0
1.0
0
1.0
ns
tw
CP Pulse Width
HIGH or LOW
3.3
5.0
5.5
4.0
6.0
4.5
* Voltage Range 3.3 V is 3.3 V ±0.3 V; Voltage Range 5.0 V is 5.0 V ±0.5 V.
http://onsemi.com
4
ns
MC74AC377, MC74ACT377
74ACT – DC CHARACTERISTICS
TA =
–40C to +85C
TA = +25C
Symbol
Parameter
VCC (V)
Typ
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT = 0.1 V
or
VCC – 0.1 V
VIL
Maximum Low Level Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT = 0.1 V
or
VCC – 0.1 V
VOH
Minimum High Level Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
IOUT = –50 µA
3.86
4.86
3.76
4.76
V
*VIN = VIL or VIH
IOH
0.1
0.1
0.1
0.1
V
IOUT = 50 µA
4.5
5.5
0.36
0.36
0.44
0.44
V
*VIN = VIL or VIH
IOH
±0.1
±1.0
µA
VI = VCC, GND
1.5
mA
VI = VCC – 2.1 V
75
–75
mA
VOLD = 1.65 V Max
VOHD = 3.85 V Min
80
µA
VIN = VCC or GND
4.5
5.5
VOL
Maximum Low Level Output Voltage
4.5
5.5
IIN
Maximum Input Leakage Current
5.5
∆ICCT
Additional Max. ICC/Input
5.5
IOLD
IOHD
†Minimum Dynamic Output Current
5.5
0.001
0.001
0.6
ICC
Maximum Quiescent Supply Current
5.5
8.0
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
–24 mA
–24 mA
–24 mA
–24 mA
74ACT – AC CHARACTERISTICS For Figures and Waveforms — See Figures 4, 5, and 6.
TA = +25°C
+25 C
CL = 50 pF
Symbol
Parameter
fmax
Maximum Clock Frequency
tPLH
Propagation Delay
tPHL
Propagation Delay
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
TA = –40°C
40 C to +85°C
+85 C
CL = 50 pF
VCC* (V)
Min
5.0
140
CP to Qn
5.0
3.0
9.0
2.5
10
ns
CP to Qn
5.0
3.5
10
2.5
11
ns
Typ
Max
Min
Max
125
Unit
MHz
74ACT – AC OPERATING REQUIREMENTS
TA = +25°C
+25 C
CL = 50 pF
Symbol
Parameter
VCC* (V)
Typ
TA = –40°C
–40 C to +85°C
+85 C
CL = 50 pF
Guaranteed Minimum
Unit
ts
Setup Time, HIGH or LOW
Dn to CP
5.0
4.5
5.5
ns
th
Hold Time, HIGH or LOW
Dn to CP
5.0
1.0
1.0
ns
ts
Setup Time, HIGH or LOW
CE to CP
5.0
4.5
5.5
ns
th
Hold Time, HIGH or LOW
CE to CP
5.0
1.0
1.0
ns
tw
CP Pulse Width
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
HIGH or LOW
5.0
4.0
4.5
ns
http://onsemi.com
5
MC74AC377, MC74ACT377
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
90
pF
VCC = 5.0 V
SWITCHING WAVEFORMS
tr
tf
VCC
CLOCK
50%
tw
VCC
CE
GND
50%
tsu
1/fmax
tPLH
th
VCC
tPHL
CLOCK
50%
GND
Q
50%
Figure 4.
Figure 5.
VALID
VCC
DATA
50%
GND
tsu
th
VCC
CLOCK
50%
GND
Figure 6.
450 OUTPUT
DEVICE
UNDER
TEST
50 SCOPE
TEST POINT
CL*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
http://onsemi.com
6
MC74AC377, MC74ACT377
ORDERING INFORMATION
Device
Package
Shipping
MC74AC377N
PDIP–20
18 Units/Rail
MC74ACT377N
PDIP–20
18 Units/Rail
MC74AC377DW
SOIC–20
38 Units/Rail
MC74AC377DWR2
SOIC–20
1000 Tape & Reel
MC74ACT377DW
SOIC–20
38 Units/Rail
MC74ACT377DWR2
SOIC–20
1000 Tape & Reel
MC74AC377DT
TSSOP–20
75 Units/Rail
MC74AC377DTR2
TSSOP–20
2500 Tape & Reel
MC74ACT377DT
TSSOP–20
75 Units/Rail
MC74ACT377DTR2
TSSOP–20
2500 Tape & Reel
MC74AC377M
EIAJ–20
40 Units/Rail
MC74AC377MEL
EIAJ–20
2000 Tape & Reel
MC74ACT377M
EIAJ–20
40 Units/Rail
MC74ACT377MEL
EIAJ–20
2000 Tape & Reel
http://onsemi.com
7
MC74AC377, MC74ACT377
MARKING DIAGRAMS
PDIP–20
SO–20
MC74AC377N
AWLYYWW
AC377
AWLYYWW
MC74ACT377N
AWLYYWW
ACT377
AWLYYWW
A
WL, L
YY, Y
WW, W
TSSOP–20
EIAJ–20
AC
377
ALYW
74AC377
AWLYWW
ACT
377
ALYW
74ACT377
AWLYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
http://onsemi.com
8
MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
20 PIN PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0
15 0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0
15
0.51
1.01
SO–20
DW SUFFIX
20 PIN PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
A
20
X 45 h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
C
T
http://onsemi.com
9
DIM
A
A1
B
C
D
E
e
H
h
L
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
K REF
20X
0.15 (0.006) T U
2X
0.10 (0.004)
S
20
L/2
M
T U
V
S
K
K1
11
J J1
B
L
–U–
PIN 1
IDENT
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
S
S
M
A
–V–
N
F
DETAIL E
–W–
C
G
D
H
DETAIL E
0.100 (0.004)
–T– SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
PLANE
EIAJ–20
M SUFFIX
20 PIN PLASTIC EIAJ PACKAGE
CASE 967–01
ISSUE O
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M
L
10
DETAIL P
Z
D
VIEW P
e
A
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
http://onsemi.com
10
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 0
0.70
0.90
--0.81
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 0
0.028
0.035
--0.032
MC74AC377, MC74ACT377
Notes
http://onsemi.com
11
MC74AC377, MC74ACT377
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: [email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
http://onsemi.com
12
MC74AC377/D
Similar pages