ON MC74HCT374ADWR2G Octal 3-state noninverting d flip-flop with lsttl-compatible input Datasheet

MC74HCT374A
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
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The MC74HCT374A may be used as a level converter for
interfacing TTL or NMOS outputs to High−Speed CMOS inputs.
The HCT374A is identical in pinout to the LS374.
Data meeting the setup and hold time is clocked to the outputs with
the rising edge of Clock. The Output Enable does not affect the state of
the flip−flops, but when Output Enable is high, the outputs are forced
to the high−impedance state. Thus, data may be stored even when the
outputs are not enabled.
The HCT374A is identical in function to the HCT574A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT534A, which has
inverting outputs.
Features
•
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance With the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 276 FETs or 69 Equivalent Gates
Improvements over HCT374
♦ Improved Propagation Delays
♦ 50% Lower Quiescent Power
♦ Improved Input Noise and Latchup Immunity
These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
3
2
4
5
7
6
8
9
13
12
14
15
17
16
18
19
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 12
PIN ASSIGNMENT
OUTPUT ENABLE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CLOCK
MARKING DIAGRAMS
20
HCT
374A
ALYWG
G
HCT374A
AWLYYWWG
1
1
TSSOP−20
SOIC−20
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
FUNCTION TABLE
Q2
Q4
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20
Q1
Q3
TSSOP−20
DT SUFFIX
CASE 948E
(Note: Microdot may be in either location)
Q0
Inputs
NONINVERTING
OUTPUTS
Output
Enable
L
L
L
H
Q5
Q6
Q7
Output
Clock
D
Q
L,H,
X
H
L
X
X
H
L
No Change
Z
X = don’t care
Z = high impedance
11
1
SOIC−20
DW SUFFIX
CASE 751D
PIN 20 = VCC
PIN 10 = GND
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
1
Publication Order Number:
MC74HCT374A/D
MC74HCT374A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Design Criteria
Value
Units
Internal Gate Count*
69
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
mW
.0075
pJ
Speed Power Product
*Equivalent to a two−input NAND gate.
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
–0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
–0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
–65 to +150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
SOIC Package†
TSSOP Package†
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
Max
Unit
4.5
5.5
V
0
VCC
V
–55
+125
_C
0
500
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MC74HCT374A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
−55 to
25_C
≤ 85_C
≤ 125_C
Unit
VIH
Minimum High−Level Input Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| ≤ 20 mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low−Level Input Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| ≤ 20 mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOH
Minimum High−Level Output Voltage
Vin = VIH or VIL
|Iout| ≤ 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout| ≤ 6.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout| ≤ 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout| ≤ 6.0 mA
4.5
0.26
0.33
0.4
VOL
Maximum Low−Level Output Voltage
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
±0.1
±1.0
±1.0
mA
IOZ
Maximum Three−State Leakage
Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
5.5
±0.5
±5.0
±10
mA
ICC
Maximum Quiescent Supply Current
(per Package)
Vin = VCC or GND
Iout = 0 mA
5.5
4.0
40
160
mA
DICC
Additional Quiescent Supply Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 mA
≥ −55_C
25_C to 125_C
2.9
2.4
mA
5.5
1. Total Supply Current = ICC + ΣDICC.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
−55 to 25_C
≤ 85_C
≤ 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
31
39
47
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
30
38
45
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
30
38
45
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
12
15
18
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
15
15
15
pF
CPD
Power Dissipation Capacitance (Per Flip−Flop)*
Typical @ 25°C, VCC = 5.0 V
65
* Used to determine the no−load dynamic power consumption: P D = CPD VCC
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3
2f
+ ICC VCC .
pF
MC74HCT374A
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, Input tr = tf = 6.0 ns)
Guaranteed Limit
−55 to 25_C
≤ 85_C
≤ 125_C
Unit
tsu
Minimum Setup Time, Data to Clock
(Figure 3)
12
15
18
ns
th
Minimum Hold Time, Clock to Data
(Figure 3)
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
12
15
18
ns
Maximum Input Rise and Fall Times
(Figure 1)
500
500
500
ns
Symbol
tr, tf
Parameter
SWITCHING WAVEFORMS
tr
CLOCK
tf
3V
OUTPUT
ENABLE
VCC
2.7 V
1.3 V
0.3 V
tw
GND
GND
Q
1/fmax
tPZL
tPLZ
tPZH
tPHZ
90%
1.3 V
10%
Q
HIGH
IMPEDANCE
1.3 V
tPHL
tPLH
Q
1.3 V
10%
VOL
90%
VOH
1.3 V
HIGH
IMPEDANCE
tTHL
tTLH
Figure 1.
Figure 2.
VALID
DATA
3V
1.3 V
GND
tsu
th
3V
CLOCK
1.3 V
GND
Figure 3.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH
*Includes all probe and jig capacitance
Figure 4.
Figure 5.
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4
MC74HCT374A
EXPANDED LOGIC DIAGRAM
D0
3
D1
4
D
D
Q
C
CLOCK
D2
7
Q
D3
8
D
C
Q
D4
13
D
C
Q
D5
14
D
C
Q
D6
17
D
C
Q
D7
18
D
C
Q
D
C
Q
C
11
OUTPUT 1
ENABLE
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
ORDERING INFORMATION
Package
Shipping†
MC74HCT374ADWG
SOIC−20
(Pb−Free)
38 Units / Rail
MC74HCT374ADWR2G
SOIC−20
(Pb−Free)
1000 Units / Reel
MC74HCT374ADTR2G
TSSOP−20
(Pb−Free)
2500 Units / Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MC74HCT374A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
−U−
L
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
N
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
1.20
--0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
0.047
--0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74HCT374A
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
20
11
X 45 _
h
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
SEATING
PLANE
C
T
ON Semiconductor and the
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Sales Representative
MC74HCT374A/D
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