MOTOROLA MC74LCX573SD Low-voltage cmos octal transparent latch Datasheet

SEMICONDUCTOR TECHNICAL DATA
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The MC74LCX573 is a high performance, non–inverting octal
transparent latch operating from a 2.7 to 3.6V supply. High impedance
TTL compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5V allows MC74LCX573 inputs to be
safely driven from 5V devices.
The MC74LCX573 contains 8 D–type latches with 3–state standard
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs
enters the latches. In this condition, the latches are transparent, i.e., a
latch output will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on the D inputs a
setup time preceding the HIGH–to–LOW transition of LE. The 3–state
standard outputs are controlled by the Output Enable (OE) input. When
OE is LOW, the standard outputs are enabled. When OE is HIGH, the
standard outputs are in the high impedance state, but this does not
interfere with new data entering into the latches. The LCX573 flow
through design facilitates easy PC board layout.
•
•
•
•
•
•
•
•
LOW–VOLTAGE
CMOS OCTAL
TRANSPARENT LATCH
DW SUFFIX
PLASTIC SOIC
CASE 751D–04
20
1
M SUFFIX
PLASTIC SOIC EIAJ
CASE 967–01
20
Designed for 2.7 to 3.6V VCC Operation
5V Tolerant — Interface Capability With 5V TTL Logic
1
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0V
LVTTL Compatible
20
LVCMOS Compatible
1
24mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
20
• ESD Performance: Human Body Model >2000V; Machine Model >200V
1
SD SUFFIX
PLASTIC SSOP
CASE 940C–03
DT SUFFIX
PLASTIC TSSOP
CASE 948E–02
Pinout: 20–Lead (Top View)
VCC
O0
O1
O2
O3
O4
O5
O6
O7
LE
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
PIN NAMES
Pins
Function
OE
LE
D0–D7
O0–O7
Output Enable Input
Latch Enable Input
Data Inputs
3–State Latch Outputs
11/96
 Motorola, Inc. 1996
1
REV 3
MC74LCX573
LOGIC DIAGRAM
OE
LE
1
11
O0
Q
D0
D
18
nLE
3
O1
Q
D1
D
17
nLE
4
O2
Q
D2
D
16
nLE
5
O3
Q
D3
D
15
nLE
6
O4
Q
D4
D
14
nLE
7
O5
Q
D5
D
13
nLE
8
O6
Q
D6
D
12
nLE
9
Q
D7
INPUTS
19
nLE
2
O7
D
OUTPUTS
OE
LE
Dn
On
OPERATING MODE
L
L
H
H
H
L
H
L
Transparent (Latch Disabled); Read Latch
L
L
L
L
h
l
H
L
Latched (Latch Enabled) Read Latch
L
L
X
NC
Hold; Read Latch
H
L
X
Z
Hold; Disabled Outputs
H
H
H
H
H
L
Z
Z
Transparent (Latch Disabled); Disabled Outputs
H
H
L
L
h
l
Z
Z
Latched (Latch Enabled); Disabled Outputs
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable High–to–Low Transition;
L = Low Voltage Level; l = Low Voltage Level One Setup Time Prior to the Latch Enable High–to–Low Transition;
NC = No Change, State Prior to the Latch Enable High–to–Low Transition; X = High or Low Voltage Level or Transitions
are Acceptable; Z = High Impedance State; For ICC Reasons DO NOT FLOAT Inputs
MOTOROLA
2
LCX DATA
BR1339 — REV 3
MC74LCX573
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
VCC
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
Value
Condition
Unit
–0.5 to +7.0
V
–0.5 ≤ VI ≤ +7.0
V
–0.5 ≤ VO ≤ +7.0
Output in 3–State
V
–0.5 ≤ VO ≤ VCC + 0.5
Note 1.
V
IIK
DC Input Diode Current
–50
VI < GND
mA
IOK
DC Output Diode Current
–50
VO < GND
mA
+50
VO > VCC
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
–65 to +150
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
1. Output in HIGH or LOW State. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Operating
Data Retention Only
Min
Typ
Max
Unit
2.0
1.5
3.3
3.3
3.6
3.6
V
0
5.5
V
0
0
VCC
5.5
V
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH
HIGH Level Output Current, VCC = 3.0V – 3.6V
–24
mA
IOL
LOW Level Output Current, VCC = 3.0V – 3.6V
24
mA
IOH
HIGH Level Output Current, VCC = 2.7V – 3.0V
–12
mA
IOL
LOW Level Output Current, VCC = 2.7V – 3.0V
12
mA
TA
Operating Free–Air Temperature
∆t/∆V
Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V,
VCC = 3.0V
(HIGH or LOW State)
(3–State)
–40
+85
°C
0
10
ns/V
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C
Symbol
Characteristic
VIH
HIGH Level Input Voltage (Note 2.)
VIL
LOW Level Input Voltage (Note 2.)
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
Condition
Min
2.7V ≤ VCC ≤ 3.6V
2.0
2.7V ≤ VCC ≤ 3.6V
Max
V
0.8
2.7V ≤ VCC ≤ 3.6V; IOH = –100µA
VCC – 0.2
VCC = 2.7V; IOH = –12mA
2.2
VCC = 3.0V; IOH = –18mA
2.4
VCC = 3.0V; IOH = –24mA
2.2
Unit
V
V
2.7V ≤ VCC ≤ 3.6V; IOL = 100µA
0.2
VCC = 2.7V; IOL= 12mA
0.4
VCC = 3.0V; IOL = 16mA
0.4
VCC = 3.0V; IOL = 24mA
0.55
V
2. These values of VI are used to test DC electrical characteristics only.
LCX DATA
BR1339 — REV 3
3
MOTOROLA
MC74LCX573
DC ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to +85°C
Symbol
Characteristic
Condition
Min
Max
Unit
II
Input Leakage Current
2.7V ≤ VCC ≤ 3.6V; 0V ≤ VI ≤ 5.5V
±5.0
µA
IOZ
3–State Output Current
2.7 ≤ VCC ≤ 3.6V; 0V ≤ VO ≤ 5.5V;
VI = VIH or V IL
±5.0
µA
IOFF
Power–Off Leakage Current
VCC = 0V; VI or VO = 5.5V
10
µA
ICC
Quiescent Supply Current
2.7 ≤ VCC ≤ 3.6V; VI = GND or VCC
10
µA
2.7 ≤ VCC ≤ 3.6V; 3.6 ≤ VI or VO ≤ 5.5V
±10
µA
2.7 ≤ VCC ≤ 3.6V; VIH = VCC – 0.6V
500
µA
∆ICC
Increase in ICC per Input
AC CHARACTERISTICS (tR = tF = 2.5ns; CL = 50pF; RL = 500Ω)
Limits
TA = –40°C to +85°C
VCC = 3.0V to 3.6V
Symbol
Parameter
VCC = 2.7V
Waveform
Min
Max
Min
Max
Unit
tPLH
tPHL
Propagation Delay
Dn to On
1
1.5
1.5
8.0
8.0
1.5
1.5
9.0
9.0
ns
tPLH
tPHL
Propagation Delay
LE to On
3
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
ns
tPZH
tPZL
Output Enable Time to HIGH and
LOW Level
2
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
ns
tPHZ
tPLZ
Output Disable Time from HIGH and
LOW Level
2
1.5
1.5
6.5
6.5
1.5
1.5
7.0
7.0
ns
ts
Setup TIme, HIGH or LOW Dn to LE
3
2.5
2.5
ns
th
Hold TIme, HIGH or LOW Dn to LE
3
1.5
1.5
ns
tw
LE Pulse Width, HIGH
3
3.3
3.3
ns
tOSHL
tOSLH
Output–to–Output Skew
(Note 3.)
1.0
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter
guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Condition
VOLP
Dynamic LOW Peak Voltage (Note 4.)
VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V
Min
Typ
0.8
Max
Unit
V
VOLV
Dynamic LOW Valley Voltage (Note 4.)
VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V
0.8
V
4. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
CPD
Power Dissipation Capacitance
MOTOROLA
Condition
Typical
Unit
VCC = 3.3V, VI = 0V or VCC
7
pF
VCC = 3.3V, VI = 0V or VCC
8
pF
10MHz, VCC = 3.3V, VI = 0V or VCC
25
pF
4
LCX DATA
BR1339 — REV 3
MC74LCX573
2.7V
1.5V
Dn
1.5V
0V
tPLH
tPHL
VOH
1.5V
On
1.5V
VOL
WAVEFORM 1 – PROPAGATION DELAYS
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
2.7V
1.5V
OE
2.7V
Dn
1.5V
1.5V
0V
tPZH
0V
ts
tPHZ
VCC
VOH – 0.3V
2.7V
LE
1.5V
On
th
tw
1.5V
1.5V
≈ 0V
0V
tPLH, tPHL
tPZL
tPLZ
≈ 3.0V
VOH
On
1.5V
1.5V
On
VOL
VOL + 0.3V
GND
WAVEFORM 3 – LE to On PROPAGATION DELAYS, LE MINIMUM
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted
WAVEFORM 2 – OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
Figure 1. AC Waveforms
VCC
PULSE
GENERATOR
R1
DUT
CL
RT
TEST
6V
OPEN
GND
RL
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V
Open Collector/Drain tPLH and tPHL
6V
tPZH, tPHZ
GND
CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 2. Test Circuit
LCX DATA
BR1339 — REV 3
5
MOTOROLA
MC74LCX573
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
–A
–
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
11
1
–B
–
P 10 PL
A
B
0.010 (0.25)
B
M
M
10
D
20 PL
J
0.010 (0.25)
M
T
S
S
DIM
A
B
C
D
F
G
J
K
M
P
R
F
R X 45°
C
–T
G
18 PL
M
SEATING
–
PLANE
K
MILLIMETERS
MIN
MAX
12.65 12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0°
7°
10.05 10.55
0.25
0.75
INCHES
MIN
MAX
0.499 0.510
0.292 0.299
0.093 0.104
0.014 0.019
0.020 0.035
0.050 BSC
0.010 0.012
0.004 0.009
0°
7°
0.395 0.415
0.010 0.029
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 967–01
ISSUE O
20
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5 THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
M_
L
10
1
DETAIL P
Z
D
e
VIEW P
A
c
A1
b
0.13 (0.005)
MOTOROLA
M
0.10 (0.004)
6
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.81
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.032
LCX DATA
BR1339 — REV 3
MC74LCX573
OUTLINE DIMENSIONS
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C–03
ISSUE B
20X
K REF
0.12 (0.005)
T U
M
V
S
S
0.25 (0.010)
N
20
L/2
11
M
N
B
L
F
PIN 1
IDENT
1
10
DETAIL E
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K
–U–
A
–V–
0.20 (0.008)
M
J
T U
S
NOTES:
13 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 CONTROLLING DIMENSION: MILLIMETER.
15 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
16 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
17 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR INTRUSION
SHALL NOT REDUCE DIMENSION K BY MORE
THAN 0.07 (0.002) AT LEAST MATERIAL
CONDITION.
18 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
19 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
K1
SECTION N–N
0.076 (0.003)
–T–
–W–
C
SEATING
PLANE
D
G
DETAIL E
H
20X
0.15 (0.006) T U
K REF
M
T U
S
V
S
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
2X
L/2
20
11
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
NOTES:
6 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
7 CONTROLLING DIMENSION: MILLIMETER.
8 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
9 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
10 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
11 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
12 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
M
A
–V–
N
F
DETAIL E
–W–
C
D
G
INCHES
MIN
MAX
0.278
0.288
0.205
0.212
0.068
0.078
0.002
0.008
0.024
0.037
0.026 BSC
0.023
0.030
0.003
0.008
0.003
0.006
0.010
0.015
0.010
0.013
0.301
0.311
0_
8_
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
0.10 (0.004)
S
MILLIMETERS
MIN
MAX
7.07
7.33
5.20
5.38
1.73
1.99
0.05
0.21
0.63
0.95
0.65 BSC
0.59
0.75
0.09
0.20
0.09
0.16
0.25
0.38
0.25
0.33
7.65
7.90
0_
8_
H
DETAIL E
0.100 (0.004)
–T– SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
PLANE
LCX DATA
BR1339 — REV 3
7
MOTOROLA
MC74LCX573
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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◊
MOTOROLA
8
MC74LCX573/D
LCX DATA
BR1339 — REV 3
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