ON MC74LVX373DWR2G Octal d-type latch with 3-state output Datasheet

MC74LVX373
Octal D-Type Latch
with 3-State Outputs
With 5V−Tolerant Inputs
The MC74LVX373 is an advanced high speed CMOS octal latch
with 3−state outputs. The inputs tolerate voltages up to 7.0 V, allowing
the interface of 5.0 V systems to 3.0 V systems.
This 8−bit D−type latch is controlled by a latch enable input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
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SOIC−20
DW SUFFIX
CASE 751D
Features
•
•
•
•
•
•
•
•
•
High Speed: tPD = 5.8 ns (Typ) at VCC = 3.3 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
These Devices are Pb−Free and are RoHS Compliant
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
VCC O7 D7
D6 O6 O5 D5
D4 O4
LE
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
OE O0 D0
D1 O1 O2 D2
D3 O3 GND
20−Lead (Top View)
MARKING DIAGRAMS
20
20
LVX
373
ALYWG
G
LVX373
AWLYYWWG
1
1
SOIC−20
LVX373
A
WL, L
Y
WW, W
G or G
TSSOP−20
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN NAMES
Pins
Function
OE
LE
D0−D7
O0−O7
Output Enable Input
Latch Enable Input
Data Inputs
3−State Latch Outputs
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 4
1
Publication Order Number:
MC74LVX373/D
MC74LVX373
OE
LE
1
11
3
D0
2
nLE
O0
Q
D
4
D1
5
nLE
O1
Q
D
7
D2
6
nLE
O2
Q
D
8
D3
9
nLE
O3
Q
D
13
D4
12
nLE
O4
Q
D
14
D5
15
nLE
O5
Q
D
17
D6
16
nLE
O6
Q
D
18
D7
19
nLE
O7
Q
D
Figure 1. Logic Diagram
INPUTS
OUTPUTS
OE
LE
Dn
On
OPERATING MODE
L
L
H
H
H
L
H
L
Transparent (Latch Disabled); Read Latch
L
L
L
L
h
l
H
L
Latched (Latch Enabled) Read Latch
L
L
X
NC
Hold; Read Latch
H
L
X
Z
Hold; Disabled Outputs
H
H
H
H
H
L
Z
Z
Transparent (Latch Disabled); Disabled Outputs
H
H
L
L
h
l
Z
Z
Latched (Latch Enabled); Disabled Outputs
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable High−to−Low
Transition; L = Low Voltage Level; l = Low Voltage Level One Setup Time Prior to the Latch Enable
High−to−Low Transition; NC = No Change, State Prior to the Latch Enable High−to−Low Transition; X = High
or Low Voltage Level or Transitions are Acceptable; Z = High Impedance State; For ICC Reasons DO NOT
FLOAT Inputs
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2
MC74LVX373
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
–0.5 to +7.0
V
Vin
DC Input Voltage
–0.5 to +7.0
V
Vout
DC Output Voltage
–0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation
180
mW
Tstg
Storage Temperature
–65 to +150
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
3.6
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
−40
+85
_C
0
100
ns/V
TA
Dt/DV
Operating Temperature, All Package Types
Input Rise and Fall Time
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
TA = 25°C
VCC
V
Min
1.5
2.0
2.4
VIH
High−Level Input Voltage
2.0
3.0
3.6
VIL
Low−Level Input Voltage
2.0
3.0
3.6
VOH
High−Level Output Voltage
(Vin = VIH or VIL)
IOH = −50 mA
IOH = −50 mA
IOH = −4 mA
2.0
3.0
3.0
VOL
Low−Level Output Voltage
(Vin = VIH or VIL)
IOL = 50 mA
IOL = 50 mA
IOL = 4 mA
2.0
3.0
3.0
Iin
Input Leakage Current
Vin = 5.5 V or GND
IOZ
Maximum 3−State Leakage Current
ICC
Quiescent Supply Current
Typ
TA = −40 to 85°C
Max
Min
0.5
0.8
0.8
1.9
2.9
2.58
Max
1.5
2.0
2.4
2.0
3.0
0.0
0.0
Unit
V
0.5
0.8
0.8
1.9
2.9
2.48
V
V
0.1
0.1
0.36
0.1
0.1
0.44
V
3.6
±0.1
±1.0
mA
Vin = VIL or VIH
Vout = VCC or GND
3.6
±0.2
5
±2.5
mA
Vin = VCC or GND
3.6
4.0
40.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
MC74LVX373
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
tPLH,
tPHL
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSHL
tOSLH
Parameter
Propagation Delay
D to O
Propagation Delay
LE to O
Output Enable Time
OE to O
Output Disable Time
OE to O
Output−to−Output Skew
(Note 1)
Test Conditions
Min
TA = −40 to 85°C
Typ
Max
Min
Max
Unit
ns
VCC = 2.7 V
CL = 15 pF
CL = 50 pF
7.5
10.0
14.5
18.0
1.0
1.0
17.5
21.0
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
5.8
8.3
9.3
12.8
1.0
1.0
11.0
14.5
VCC = 2.7 V
CL = 15 pF
CL = 50 pF
7.7
10.2
15.0
18.5
1.0
1.0
18.5
22.0
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
6.0
8.5
9.7
13.2
1.0
1.0
11.5
15.0
VCC = 2.7 V
RL = 1 kW
CL = 15 pF
CL = 50 pF
7.7
10.2
15.0
18.5
1.0
1.0
18.5
22.0
VCC = 3.3 ± 0.3 V
RL = 1 kW
CL = 15 pF
CL = 50 pF
6.0
8.5
9.7
13.2
1.0
1.0
11.5
15.0
VCC = 2.7 V
RL = 1 kW
CL = 50 pF
9.8
18.0
1.0
21.0
VCC = 3.3 ± 0.3 V
RL = 1 kW
CL = 50 pF
8.2
12.8
1.0
14.5
VCC = 2.7 V
VCC = 3.3 ±0.3 V
CL = 50 pF
CL = 50 pF
1.5
1.5
1.5
1.5
ns
ns
ns
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
TA = 25°C
Symbol
Min
Parameter
TA = −40 to 85°C
Typ
Max
4
10
Min
Max
Unit
10
pF
Cin
Input Capacitance
Cout
Maximum Three−State Output Capacitance
6
pF
CPD
Power Dissipation Capacitance (Note 2)
27
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per latch). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
TA = 25°C
Typ
Characteristic
Symbol
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.5
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.5
−0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
tw(h)
Parameter
Test Conditions
Typ
TA = −40 to 85°C
Limit
Limit
Unit
Minimum Pulse Width, LE
VCC = 2.7 V
VCC = 3.3 ± 0.3 V
6.5
5.0
7.5
5.0
ns
tsu
Minimum Setup Time, D to LE
VCC = 2.7V
VCC = 3.3 ± 0.3 V
6.0
4.0
6.0
4.0
ns
th
Minimum Hold Time, D to LE
VCC = 2.7 V
VCC = 3.3 ± 0.3 V
1.0
1.0
1.0
1.0
ns
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4
MC74LVX373
SWITCHING WAVEFORMS
tw
VCC
D
LE
50%
VCC
50%
GND
tPLH
O
GND
tPHL
tPHL
tPLH
50% VCC
O
50% VCC
Figure 2.
Figure 3.
OE
VCC
50%
GND
tPZL
O
tPLZ
VALID
VCC
HIGH
IMPEDANCE
50% VCC
D
50%
tPZH
tPHZ
50% VCC
VCC
50%
GND
HIGH
IMPEDANCE
Figure 4.
th
LE
VOL -0.3V
O
GND
tsu
VOL +0.3V
Figure 5.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Propagation Delay Test Circuit
Figure 7. Three−State Test Circuit
ORDERING INFORMATION
Package
Shipping†
MC74LVX373DWR2G
SOIC−20
(Pb−Free)
1000 Tape & Reel
MC74LVX373DTR2G
TSSOP−20
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MC74LVX373
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
L
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
N
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74LVX373
PACKAGE DIMENSIONS
SOIC−20
CASE 751D−05
ISSUE G
20
11
X 45 _
h
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
SEATING
PLANE
C
T
ON Semiconductor and the
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MC74LVX373/D
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