ON MC74VHC373DWR2G Octal d-type latch with 3-state output Datasheet

MC74VHC373
Octal D−Type Latch
with 3−State Output
The MC74VHC373 is an advanced high speed CMOS octal latch
with 3−state output fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
This 8−bit D−type latch is controlled by a latch enable input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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MARKING
DIAGRAMS
20
20
1
SOIC−20 WIDE
DW SUFFIX
CASE 751D
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
VHC373
AWLYYWW
High Speed: tPD = 5.0 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4.0 A (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.9 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 186 FETs or 46.5 Equivalent Gates
Pb−Free Packages are Available*
20
VHC
373
ALYW
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
20
SOEIAJ−20
M SUFFIX
CASE 967
20
1
74VHC373
AWLYYWW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
OE
1
20
VCC
Q0
2
19
Q7
D0
3
18
D7
D1
4
17
D6
Q1
5
16
Q6
Q2
6
15
Q5
D2
7
14
D5
D3
8
13
D4
Q3
9
12
Q4
10
11
LE
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2005
January, 2005 − Rev. 6
1
Publication Order Number:
MC74VHC373/D
MC74VHC373
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
LE
OE
3
2
4
5
7
6
8
9
13
12
14
15
17
16
18
19
Q0
Q1
Q2
Q3
Q4
FUNCTION TABLE
INPUTS
NONINVERTING
OUTPUTS
Q5
Q6
Q7
OUTPUT
OE
LE
D
Q
L
L
L
H
H
H
L
X
H
L
X
X
H
L
No Change
Z
11
1
Figure 1. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — SOIC Packages: – 7 mW/C from 65 to 125C
TSSOP Package: − 6.1 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage
Vin
DC Input Voltage
Vout
DC Output Voltage
TA
Operating Temperature
tr, tf
Input Rise and Fall Time
VCC = 3.3 V
VCC = 5.0 V
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2
Min
Max
Unit
2.0
5.5
V
0
5.5
V
0
VCC
V
− 40
+ 85
C
0
0
100
20
ns/V
MC74VHC373
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VCC
V
Test Conditions
VIH
Minimum High−Level
Input Voltage
2.0
3.0 to
5.5
VIL
Maximum Low−Level
Input Voltage
2.0
3.0 to
5.5
VOH
Minimum High−Level
Output Voltage
Vin = VIH or VIL
IOH = − 50 A
Vin = VIH or VIL
IOH = − 4 mA
IOH = − 8 mA
VOL
Maximum Low−Level
Output Voltage
Vin = VIH or VIL
IOL = 50 A
TA = 25°C
Min
Typ
Max
Min
1.50
VCC x 0.7
2.0
3.0
4.5
1.9
2.9
4.4
3.0
4.5
2.58
3.94
Max
1.50
VCC x 0.7
0.50
VCC x 0.3
2.0
3.0
4.5
Unit
V
0.50
VCC x 0.3
V
V
1.9
2.9
4.4
2.48
3.80
2.0
3.0
4.5
Vin = VIH or VIL
IOL = 4 mA
IOL = 8 mA
TA = − 40 to 85°C
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
V
Iin
Maximum Input
Leakage Current
Vin = 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
A
IOZ
Maximum
Three−State Leakage
Current
Vin = VIL or VIH
Vout = VCC or GND
5.5
± 0.25
± 2.5
A
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
4.0
40.0
A
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
tPLH,
tPHL
Maximum Propagation Delay,
D to Q
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSLH,
tOSHL
Maximum Propagation Delay,
LE to Q
Output Enable Time,
OE to Q
Output Disable Time,
OE to Q
Output to Output Skew
Typ
Max
Min
Max
Unit
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
7.3
9.8
11.4
14.9
1.0
1.0
13.5
17.0
ns
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
4.9
6.4
7.2
9.2
1.0
1.0
8.5
10.5
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
7.0
9.5
11.0
14.5
1.0
1.0
13.0
16.5
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
5.0
6.5
7.2
9.2
1.0
1.0
8.5
10.5
VCC = 3.3 ± 0.3 V
RL = 1 k
CL = 15 pF
CL = 50 pF
7.3
9.8
11.4
14.9
1.0
1.0
13.5
17.0
VCC = 5.0 ± 0.5 V
RL = 1 k
CL = 15 pF
CL = 50 pF
5.5
7.0
8.1
10.1
1.0
1.0
9.5
11.5
VCC = 3.3 ± 0.3 V
RL = 1 k
CL = 50 pF
9.5
13.2
1.0
15.0
VCC = 5.0 ± 0.5V
RL = 1 k
CL = 50 pF
6.5
9.2
1.0
10.5
VCC = 3.3 ± 0.3 V
(Note 1)
CL = 50 pF
1.5
1.5
ns
VCC = 5.5 ± 0.5 V
(Note 1)
CL = 50 pF
1.0
1.0
ns
Test Conditions
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3
Min
TA = − 40 to 85°C
ns
ns
ns
MC74VHC373
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
Test Conditions
Min
TA = − 40 to 85°C
Typ
Max
10
Cin
Maximum Input Capacitance
4
Cout
Maximum Three−State Output
Capacitance (Output in
High−Impedance State)
6
Min
Max
Unit
10
pF
pF
Typical @ 25°C, VCC = 5.0 V
CPD
27
Power Dissipation Capacitance (Note 2)
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per latch). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0V)
TA = 25°C
Symbol
Parameter
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.6
0.9
V
VOLV
Quiet Output Minimum Dynamic VOL
− 0.6
− 0.9
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
TIMING REQUIREMENTS (Input tr = tf = 3.0 ns)
TA = − 40
to 85°C
TA = 25°C
Symbol
Parameter
Test Conditions
Typ
Limit
Limit
Unit
Minimum Pulse Width, LE
VCC = 3.3 ± 0.3 V
VCC = 5.0 ±0.5 V
5.0
5.0
5.0
5.0
ns
tsu
Minimum Setup Time, D to LE
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
4.0
4.0
4.0
4.0
ns
th
Minimum Hold Time, D to LE
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
1.0
1.0
1.0
1.0
ns
tw(h)
ORDERING INFORMATION
Package
Shipping†
MC74VHC373DWR2
SOIC−20
1000 Tape & Reel
MC74VHC373DWR2G
SOIC−20
(Pb−Free)
1000 Tape & Reel
MC74VHC373DTR2
TSSOP−20*
2500 Tape & Reel
MC74VHC373MEL
SOEIAJ−20
2000 Tape & Reel
MC74VHC373MELG
SOEIAJ−20
(Pb−Free)
2000 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
MC74VHC373
SWITCHING WAVEFORMS
D
tw
VCC
50%
tPHL
tPLH
LE
GND
GND
tPHL
tPLH
50% VCC
Q
Q
50% VCC
Figure 2.
OE
VCC
50%
Figure 3.
VCC
50%
tPZL
GND
tPLZ
50% VCC
Q
tPZH
D
tsu
tPHZ
LE
VOL −0.3V
VCC
50%
VOL +0.3V
50% VCC
Q
VALID
HIGH
IMPEDANCE
th
50%
HIGH
IMPEDANCE
Figure 4.
Figure 5.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 k
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 6.
Figure 7.
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5
GND
VCC
GND
MC74VHC373
D0
3
D1
4
D
Q
D
LE
LE
OE
D2
7
Q
D3
8
D
LE
Q
D4
13
D
LE
Q
D5
14
D
LE
Q
D6
17
D
LE
Q
D7
18
D
LE
Q
D
LE
Q
LE
11
1
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
Figure 8. EXPANDED LOGIC DIAGRAM
INPUT
Figure 9. INPUT EQUIVALENT CIRCUIT
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6
15
Q5
16
Q6
19
Q7
MC74VHC373
OUTLINE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
A
20
X 45 h
1
10
20X
B
B
0.25
M
T A
B
S
DIM
A
A1
B
C
D
E
e
H
h
L
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
e
18X
SEATING
PLANE
A1
C
T
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE B
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
S
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
−U−
L
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
D
G
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
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7
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
MC74VHC373
OUTLINE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE O
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M
L
10
DETAIL P
Z
D
VIEW P
e
A
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 0
0.70
0.90
−−−
0.81
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 0
0.028
0.035
−−−
0.032
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your
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MC74VHC373/D
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