MOTOROLA Order this document by MCM64PC32T/D SEMICONDUCTOR TECHNICAL DATA Advance Information 256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium MCM64PC32T MCM64PC64T 160–LEAD CARD EDGE CASE TBD, TOP VIEW 1 The MCM64PC32T (256K) and MCM64PC64T (512K) are designed to provide a burstable, high performance, L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton II chip set. The MCM64PC32T is configured as 32K x 64 bits and the MCM64PC64T is configured as 64K x 64 bits. Both are packaged in a 160 pin card edge memory module. Each module uses Motorola’s 3.3 V 32K x 32 BurstRAMs and one Motorola 3.3 V 32K x 8 FSRAM for the tag RAM. Bursts can be initiated with either address status processor (ADSP) or cache address status (CADS). Subsequent burst addresses are generated internal to the BurstRAM by the cache burst advance (CADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLK0) input. Eight write enables are provided for byte write control. PD0 – PD3 map into the Triton II chip set for auto–configuration of the cache control. • • • • • • • • • • • • • • • • 42 43 Pentium–Style Burst Counter on Chip Pipelined Data Out 160 Pin Card Edge Module Address Pipeline Supported by ADSP Disabled with Ex All Cache Data and Tag I/Os are TTL Compatible Three State Outputs Byte Write Capability Fast Module Clock Rate: 66 MHz Fast SRAM Access Times:15 ns for Tag RAM 8 ns for Data RAMs 1.5 Cycle Deselect Data RAMs Decoupling Capacitors for Each Fast Static RAM High Quality Multi–Layer FR4 PWB with Separate Power and Ground Planes Single 3.3 V +10%, – 5% Power Supply Burndy Connector, Part Number: CELP2X80SC3Z48 Intel COAST 3.0 Option III Compliant Burst Order Select (BOSEL) Option 80 BurstRAM is a trademark of Motorola. Pentium is a trademark of Intel Corp. This document contains information on a new product. Specifications and information herein are subject to change without notice. 1/22/97 Motorola, Inc. 1997 MOTOROLA FAST SRAM MCM64PC32T•MCM64PC64T 1 MCM64PC32T BLOCK DIAGRAM 32K x 8 TIO0 – TIO7 TWE A3 – A18 DQ0 – DQ7 W 13 A0 – A12 A13 A14 ECS2 ECS1 E G 32K x 32 15 SA0 – SA14 ADSP ADSC ADV K G ADSP CADS CADV CLK0 CG BWE GWE SW SE1 SE2 SE3 LBO 4.7 kΩ CCS VDD VDD BOSEL ZZ SGW SBa – SBd CWE0 – CWE3 DQ0 – DQ31 DQ0 – DQ31 32K x 32 15 SA0 – SA14 ADSP ADSC ADV K G SW SGW CWE4 – CWE7 SE1 SE2 SE3 LBO ZZ SBa – SBd DQ0 – DQ31 MCM64PC32T•MCM64PC64T 2 DQ32 – DQ63 MOTOROLA FAST SRAM MCM64PC64T BLOCK DIAGRAM 32K x 8 TIO0 – TIO7 DQ0 – DQ7 TWE W 13 A3 – A17 A18 A0 – A12 A13 A14 15 E G CCS 32K x 32 ADSP CADS CADV CLK0 CG BWE GWE CWE0 – CWE3 SA0 – SA14 ADSP ADSC ADV K G SW SGW 32K x 32 SE1 SE2 SE3 LBO ZZ SBa – SBd 15 SA0 – SA14 ADSP ADSC ADV K G SW SGW SE1 SE2 SE3 VDD LBO ZZ SBa – SBd DQ0 – DQ31 DQ0 – DQ31 DQ0 – DQ31 VDD 4.7 kΩ CLK1 BOSEL 32K x 32 SA0 – SA14 ADSP ADSC ADV K G SW SGW CWE4 – CWE7 MOTOROLA FAST SRAM 32K x 32 SE1 SE2 SE3 LBO ZZ SBa – SBd DQ0 – DQ31 SA0 – SA14 ADSP ADSC ADV K G SW SGW SE1 SE2 SE3 VDD LBO ZZ SBa – SBd DQ0 – DQ31 DQ32 – DQ63 MCM64PC32T•MCM64PC64T 3 PIN ASSIGNMENT 160–LEAD CARD EDGE MODULE (DIMM) TOP VIEW PRESENCE DETECT TABLE Cache Size and Functionality PD0 PD1 PD2 PD3 256K Pipe Burst NC NC VSS NC 512K Pipe Burst VSS VSS NC VSS MCM64PC32T•MCM64PC64T 4 VSS TIO1 TIO7 TIO5 TIO3 NC VDD5 NC CADV VSS CG CWE5 CWE7 CWE1 VDD5 CWE3 NC NC VSS RSVD A4 A6 A8 A10 VDD5 A17 VSS A9 A14 A15 RSVD PD0 PD2 BOSEL VSS CLK0 VSS DQ63 VDD5 DQ61 DQ59 DQ57 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 TWE CADS VSS CWE4 CWE6 CWE0 CWE2 VDD3 CCS GWE BWE VSS A3 A7 A5 A11 A16 VDD3 A18 VSS A12 A13 ADSP ECS1 ECS2 PD1 PD3 VSS CLK1 VSS DQ62 VDD3 DQ60 DQ58 DQ56 VSS DQ55 DQ53 DQ51 DQ49 VSS DQ47 DQ45 DQ43 VDD5 DQ41 DQ39 DQ37 VSS DQ35 DQ33 DQ31 VDD5 DQ29 DQ27 DQ25 VSS DQ23 DQ21 DQ19 VDD5 DQ17 DQ15 DQ13 VSS DQ11 DQ9 DQ7 VDD5 DQ5 DQ3 DQ1 VSS 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VSS DQ54 DQ52 DQ50 DQ48 VSS DQ46 DQ44 DQ42 VDD3 DQ40 DQ38 DQ36 VSS DQ34 DQ32 DQ30 VDD3 DQ28 DQ26 DQ24 VSS DQ22 DQ20 DQ18 VDD3 DQ16 DQ14 DQ12 VSS DQ10 DQ8 DQ6 VDD3 DQ4 DQ2 DQ0 VSS VSS TIO0 TIO2 TIO6 TIO4 NC VDD3 MOTOROLA FAST SRAM PIN DESCRIPTIONS 160–Lead Card Edge Pin Locations Symbol Type Description 20, 21, 22, 23, 24, 26, 28, 29, 101, 102, 103, 104, 106, 108, 109, 110 A3 – A18 Input Address Inputs: These inputs are registered into data RAMs and must meet setup and hold times. The tag RAM addresses are not registered. 30 ADSP Input Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (Exception–chip deselect does not occur when ADSP is asserted and CCS is high. 114 BOSEL Input Burst Order Select: NC for interleaved burst counter. Tie to ground for linear burst counter. 18 BWE Input Byte Write Enable: To be used in future modules. 9 CADS Input Cache Address Status: Initiates READ, WRITE, or chip deselect cycle. 89 CADV Input Cache Burst Advance: Increments address count in accordance with interleaved count style. 16 CCS Input Chip Select: Active low chip enable for data RAMs. 91 CG Input Cache Output Enable: Active low asynchronous input. Low–enables output buffers (DQ pins) High–DQx pins are high impedance. 36, 116 CLK0, CLK1 Input Clock: This signal registers the address, data in, and all control signals except CG. 11, 12, 13, 14, 92, 93, 94, 96 CWE0 – CWE7 Input Cache Data Byte Write Enable: Active low write signal for data RAMs. 38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51, 53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66, 67, 69, 70, 71, 73, 74, 75, 77, 78, 79, 118, 120, 121, 122, 124, 125, 126, 127, 129, 130, 131, 133, 134, 135, 137, 138, 139, 141, 142, 143, 145, 146, 147, 149, 150, 151, 153, 154, 155, 157, 158, 159 DQ0 – DQ63 I/O 31, 32 ECS1, ECS2 Input Expansion Chip Select 17 GWE Input Global Write Enable: To be used in future modules. 33, 34, 112, 113 PD0 – PD3 — Presence Detect: See Presence Detect Table 100, 111 RSVD — No Connection: Reserved for future use. 2, 3, 4, 5, 82, 83, 84, 85 TIO0 – TIO7 I/O Tag RAM I/O: Drives data out during tag compare cycles. Stores data to tag RAM during tag WRITE cycles. 8 TWE Input 7, 15, 25, 39, 52, 60, 68, 76 VDD3 Supply Power Supply: 3.3 V + 10%, – 5%. 87, 95, 105, 119, 132, 140, 148, 156 VDD5 Supply Power Supply: 5.0 V ± 5%. 1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72, 80, 81, 90, 99, 107, 115, 117, 123, 128, 136, 144, 152, 160 VSS Supply Ground 6, 86, 88, 97, 98 NC — MOTOROLA FAST SRAM Synchronous Data I/O: Drives data out of data RAMs during READ cycles. Stores data to data RAMs during WRITE cycles. Tag Write Enable: Active low write signal for tag RAMs. No Connection: There is no connection to the module. MCM64PC32T•MCM64PC64T 5 SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3) CCS ADSP CADS CADV CWEx CLK0 Address Used Operation H X L X X L–H N/A Deselected L L X X X L–H External Address Read Cycle, Begin Burst L H L X L L–H External Address Write Cycle, Begin Burst L H L X H L–H External Address Read Cycle, Begin Burst X H H L L L–H Next Address Write Cycle, Continue Burst X H H L H L–H Next Address Read Cycle, Continue Burst X H H H L L–H Current Address Write Cycle, Suspend Burst X H H H H L–H Current Address Read Cycle, Suspend Burst H X H L L L–H Next Address Write Cycle, Continue Burst H X H L H L–H Next Address Read Cycle, Continue Burst H X H H L L–H Current Address Write Cycle, Suspend Burst H X H H H L–H Current Address Read Cycle, Suspend Burst NOTES: 1. X means Don’t Care. 2. All inputs except CG must meet setup and hold times for the low–to–high transition of clock (CLK0/1). 3. Wait states are inserted by suspending burst. ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2) Operation CG I/O Status Read L Data Out Read H High–Z Write X High–Z — Data In Deselected X High–Z NOTES: 1. X means Don’t Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time. DC ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Rating Symbol Value Unit VDD3 – 0.5 to + 4.6 V Voltage Relative to VSS Vin, Vout VSS – 0.5 to VDD3 + 0.5 V Output Current (per I/O) Iout ± 20 mA Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TJ 20 to +110 °C Power Supply Voltage Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Storage Temperature MCM64PC32T•MCM64PC64T 6 This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TJ = 20 to + 110°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V) Symbol Min Max Unit Notes Supply Voltage (Operating Voltage Range) VDD 3.135 3.6 V 1 Input High Voltage VIH 2.0 VDD + 0.3 V 2 Input Low Voltage VIL – 0.5 0.8 V 3 Notes Parameter NOTES: 1. JEDEC specification 8–1A specifies ± 0.3 V tolerance for VDD. 2. VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 1.4 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. 3. VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. DC CHARACTERISTICS Parameter Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VDD3) Ilkg(I) — ± 1.0 µA Output Leakage Current (CG = VIH) Ilkg(O) — ± 1.0 µA TTL Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V 1 TTL Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V 1 NOTES: 1. Champing diodes exist to VSS and VDD. POWER SUPPLY CURRENTS Parameter Symbol Max Unit AC Supply Current (CG = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min) MCM64PC32T MCM64PC64T IDDA 495 705 mA AC Standby Current (CG = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min) MCM64PC32T MCM64PC64T ISB1 230 505 mA Symbol Max Unit CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TJ = 20 to 110°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance MCM64PC32T MCM64PC64T Cin 21 31 pF Input/Output Capacitance (DQ0 – DQ63) MCM64PC32T MCM64PC64T CI/O 8 16 pF MOTOROLA FAST SRAM MCM64PC32T•MCM64PC64T 7 DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5% TJ = 20 to + 110°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 3 Unless Otherwise Noted OUTPUT LOAD OUTPUT BUFFER TEST POINT (UNLOADED OUTPUT) UNLOADED RISE AND FALL TIME MEASUREMENT INPUT WAVEFORM 2.4 OUTPUT WAVEFORM 2.4 0.4 tr 0.4 tf NOTES: 1. Input waveform should have a slew rate of 1 V/ns. 2. Rise time is measure from 0.4 V to 2.4 V unloaded. 3. Fall time is measure from 2.4 V to 0.4 V unloaded. Figure 1. Unloaded Rise and Fall time Characterization MCM64PC32T•MCM64PC64T 8 MOTOROLA FAST SRAM DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3) MCM64PC32T–66 MCM64PC32T–66 Parameter Symbol Min Max Unit Cycle Time tKHKH 15 — ns Clock Access Time tKHQV — 8 ns Output Enable to Output Valid Notes 5 tGLQV — 6 ns 5 Clock High to Output Active tKHQX1 0 — ns 5, 7 Clock High to Output Change tKHQX2 2 — ns 5, 7 Output Enable to Output Active tGLQX 0 — ns 5, 7 Output Disable to Q High–Z tGHQZ — 8 ns 6, 7 Clock High to Q High–Z tKHQZ 2 8 ns 6, 7 Clock High Pulse Width tKHKL 5 — ns Clock Low Pulse Width tKLKH 5 — ns Setup Times: Address Address Status Data In Write Address Advance Chip Enable tAVKH tADSVKH tDVKH tWVKH tADVVKH tEVKH 2.5 — ns 4 Hold Times: Address Address Status Data In Write Address Advance Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHEX 0.5 — ns 4 NOTES: 1. Write applies to all SBx, SW, and SGW signals when the chip is selected and ADSP high. 2. Chip Enable applies to all SE1, SE2 and SE3 signals whenever ADSP or ADSC is asserted. 3. All read and write cycle timings are referenced from K or G. 4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle. 5. Tested per AC Test Load. 6. Measured at ± 200 mV from steady state. Tested per High–Z Test Load. 7. This parameter is sampled and is not 100% tested. MOTOROLA FAST SRAM MCM64PC32T•MCM64PC64T 9 3.6 PULL–UP I (mA) Min I (mA) Max – 0.5 – 40 – 120 0 – 40 – 120 1.4 – 40 – 120 1.65 – 37 – 104 2 – 28 – 81 3.135 0 – 20 3.6 0 0 3.135 2.8 VOLTAGE (V) VOLTAGE (V) TEST POINT DC DRIVE POINT 1.65 1.4 AC DRIVE POINT 0 – 80 0–5 – 40 NOTES: CURRENT (mA) 1. Driver impedance @ 1.65 V = 15.9 to 44.6 Ω. 2. Meets the temperature and voltage range specified in DC Characteristics tables. 3. This drawing is not to scale. Comparisons should be made to the table in Figure 2a. – 120 2a. Pull–Up PULL–DOWN I (mA) Min – 0.5 – 34 VDD I (mA) Max AC DRIVE POINT – 126 0 0 0 0.5 17 47 1 35 90 1.65 45 114 1.8 46 120 3.6 46 120 4 46 120 VOLTAGE (V) VOLTAGE (V) 1.8 1.65 DC DRIVE POINT TEST POINT 0.3 0 0 5 46 80 CURRENT (mA) NOTES: 1. Driver impedance @ 1.65 V = 15.9 to 44.6 Ω. 2. Meets the temperature and voltage range specified in DC Characteristics tables. 3. This drawing is not to scale. Comparisons should be made to the table in Figure 2b. 120 2b. Pull–Down Figure 2. Output Buffer Characteristics MCM64PC32T•MCM64PC64T 10 MOTOROLA FAST SRAM MOTOROLA FAST SRAM MCM64PC32T•MCM64PC64T 11 Q(n–1) DESELECTED tKHQZ t KLQZ B SINGLE READ tKHQX1 A Q(A) Q(B) tKHQX2 t KHQV tKHKL Note: W low = GWE low and/or BWE and CWEx low. DQx CG W ESC1 CCS CADV CADS ADSP Ax (ADDRESS) CLK0, CLK1 tKHKH Q(B+2) BURST READ Q(B+1) Q(B) tGHQZ Q(B+3) BURST WRAPS AROUND tKLKH C ADSP, Ax ESC1 IGNORED D(C) DATA RAMs READ/WRITE CYCLES D(C+2) BURST WRITE D(C+1) D(C+3) tGLQX D SINGLE READ Q(D) t KHQV TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 0.3 V, TJ = 20 to + 110°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . Figure 3 Unless Otherwise Noted TAG RAM READ CYCLE (See Notes 1 and 2) – 15 Parameter Symbol Min Max Unit Notes Read Cycle Time tAVAV 15 — ns 3 Address Access Time tAVQV — 15 ns Output Hold from Address Change tAXQX 4 — ns 4, 5 NOTES: 1. CWE is high for read cycle. 2. Device is continuously selected (CG = VIL). 3. All timings are referenced from the last valid address to the first address transition. 4. Transition is measured ±500 mV from steady–state voltage with load of Figure 3b. 5. This parameter is sampled and not 100% tested. TAG RAM READ CYCLE (See Note 5) tAVAV Ax (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV 3.3 V 317 Ω Z0 = 50 Ω OUTPUT OUTPUT 50 Ω 351 Ω 5 pF VL = 1.5 V (a) (b) TIMING LIMITS The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 3. Test Loads MCM64PC32T•MCM64PC64T 12 MOTOROLA FAST SRAM TAG RAM WRITE CYCLE (See Notes 1 and 2) – 15 Parameter Symbol Min Max Unit Notes Write Cycle Time tAVAV 15 — ns 3 Address Setup Time tAVWL 0 — ns Address Valid to End of Write tAVWH 12 — ns Data Valid to End of Write tDVWH 7 — ns Data Hold Time tWHDX 0 — ns Write Low to Output High–Z tWLQZ 0 7 ns 5,6,7 Write High to Output Active tWHQX 4 — ns 5,6,7 Write Recovery Time tWHAX 0 — ns NOTES: 1. A write occurs when CWE is low. 2. If CG goes low coincident with or after CWE goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first address transition. 4. If CG ≥ VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 3b. 7. This parameter is sampled and not 100% tested. TAG RAM WRITE CYCLE (See Notes 1 and 2) tAVAV AX (ADDRESS) tAVWH tWHAX tWLWH TWE tAVWL tDVWH D (DATA IN) DATA VALID tWLQZ Q (DATA OUT) MOTOROLA FAST SRAM tWHDX HIGH Z tWHQX HIGH Z MCM64PC32T•MCM64PC64T 13 ORDERING INFORMATION (Order by Full Part Number) MCM 64PC32T 64PC64T XX XX Motorola Memory Prefix Speed (66 = 66 MHz) Part Number Package (SG = Gold Pad SIMM) Full Part Number — MCM64PC32TSG66 MCM64PC32T•MCM64PC64T 14 MCM64PC64TSG66 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 160–LEAD CARD EDGE MODULE CASE TBD A C NOTE 4 E COMPONENT AREA B MIN .285 inches, MAX .305 inches ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉ 80 –Y– VIEW AA 43 2X 42 V P NOTE 4 1 F AC –X– L M AB NOTE 5 J –T– FRONT VIEW NOTE 6 0.012 (0.3) M SIDE VIEW 160X R R D 0.004 (0.1) ÉÉÉ É É É ÉÉ ÉÉÉ É W 160X 156X L T Y X S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS C AND V DEFINE A DOUBLE–SIDED MODULE. 5. DIMENSION AB DEFINES OPTIONAL SINGLE–SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. H 160X K G (N) VIEW AA ÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉ ÉÉ 160 123 122 81 COMPONENT AREA BACK VIEW DIM A B C D E F G H J K L M N P R V W AB AC INCHES MIN MAX 4.330 4.350 1.120 1.140 ––– 0.454 0.033 0.037 2.265 2.275 0.075 BSC 0.050 BSC ––– 0.030 0.055 0.069 0.210 ––– 1.955 1.965 2.155 2.165 0.110 REF 0.300 ––– 0.492 0.512 0.300 ––– 0.040 0.060 ––– 0.262 0.072 0.076 MILLIMETERS MIN MAX 109.98 110.49 28.45 28.96 ––– 11.53 0.84 0.94 57.53 57.79 1.91 BSC 1.27 BSC ––– 0.51 1.40 1.75 5.33 ––– 49.66 49.91 54.74 54.99 2.79 REF 7.62 ––– 7.24 7.75 7.62 ––– 1.02 1.52 ––– 6.66 1.83 1.93 NOTE: Case Outline number to be determined. MOTOROLA FAST SRAM MCM64PC32T•MCM64PC64T 15 Motorola reserves the right to make changes without further notice to any products herein. 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