MOTOROLA MCM69P818ZP4 256k x 18 bit pipelined burstram synchronous fast static ram Datasheet

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
256K x 18 Bit Pipelined
BurstRAM Synchronous
Fast Static RAM
The MCM69P818 is a 4M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the PowerPC and other
high performance microprocessors. It is organized as 256K words of 18 bits
each. This device integrates input registers, an output register, a 2–bit address
counter, and a high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and linear burst order (LBO) are clock (K) controlled through positive–
edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69P818 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and
SBb controls DQb. Individual bytes are written if the selected byte writes SBx are
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM69P818 operates from a 3.3 V core power supply and all outputs
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible.
Order this document
by MCM69P818/D
MCM69P818
ZP PACKAGE
PBGA
CASE 999–02
• MCM69P818–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)
MCM69P818–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)
MCM69P818–4: 4 ns Access/7.5 ns Cycle (133 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• 2–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA Package
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
REV 2
11/7/97

Motorola, Inc. 1997
MOTOROLA
FAST SRAM
MCM69P818
1
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K
ADSC
BURST
COUNTER
K2
2
18
256K x 18 ARRAY
CLR
ADSP
2
SA
SA1
SA0
ADDRESS
REGISTER
18
16
SGW
SW
SBa
18
18
WRITE
REGISTER
a
2
SBb
K2
SE1
SE2
SE3
G
MCM69P818
2
DATA–IN
REGISTER
WRITE
REGISTER
b
ENABLE
REGISTER
DATA–OUT
REGISTER
K
K
ENABLE
REGISTER
DQa – DQb
MOTOROLA FAST SRAM
PIN ASSIGNMENT
A
B
C
D
1
2
3
4
5
6
7
VDDQ
SA
SA
ADSP
SA
SA
VDDQ
NC
SE2
SA
ADSC
SA
SE3
NC
NC
SA
SA
VDD
SA
SA
NC
DQb
NC
VSS
NC
VSS
DQa
NC
NC
DQb
VSS
SE1
VSS
NC
DQa
VDDQ
NC
VSS
G
VSS
DQa VDDQ
NC
DQb
SBb
ADV
VSS
NC
DQa
DQb
NC
VSS
SGW
VSS
DQa
NC
VDDQ VDD
NC
VDD
NC
VDD VDDQ
E
F
G
H
J
K
L
NC
DQb
VSS
K
VSS
NC
DQa
DQb
NC
VSS
NC
SBa
DQa
NC
VDDQ DQb
VSS
SW
VSS
NC
VDDQ
M
N
P
R
DQb
NC
VSS
SA1
VSS
DQa
NC
NC
DQb
VSS
SA0
VSS
NC
DQa
NC
SA
LBO
VDD
NC
SA
NC
NC
SA
SA
NC
SA
SA
NC
VDDQ
NC
NC
NC
NC
NC VDDQ
T
U
TOP VIEW 119 BUMP PBGA
Not to Scale
MOTOROLA FAST SRAM
MCM69P818
3
PBGA PIN DESCRIPTIONS
Pin Locations
Symbol
Type
4B
ADSC
Input
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
4A
ADSP
Input
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
4G
ADV
Input
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
DQx
I/O
4F
G
Input
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
4K
K
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
3R
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
4N, 4P
SA1, SA0
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
5L, 3G
(a) (b)
SBx
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b). SGW overrides SBx.
4E
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
2B
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
6B
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
4H
SGW
Input
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
4M
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
4C, 2J, 4J, 6J, 4R
VDD
Supply
Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
VDDQ
Supply
I/O Power Supply.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P
VSS
Supply
Ground.
1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,
2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K,
2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R,
5R, 7R, 1T, 4T, 7T, 2U, 3U, 4U, 5U, 6U
NC
—
MCM69P818
4
Description
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
No Connection: There is no connection to the chip.
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 Through 5)
Address
Used
SE1
SE2
SE3
ADSP
Deselect
None
1
X
X
Deselect
None
0
X
1
Deselect
None
0
0
Deselect
None
X
X
Next Cycle
Deselect
ADSC
ADV
G3
DQx
Write 2, 4
X
0
X
X
High–Z
X
0
X
X
X
High–Z
X
X
0
X
X
X
High–Z
X
1
1
0
X
X
High–Z
X
None
X
0
X
1
0
X
X
High–Z
X
Begin Read
External
0
1
0
0
X
X
X
High–Z
X5
Begin Read
External
0
1
0
1
0
X
X
High–Z
READ5
Continue Read
Next
X
X
X
1
1
0
1
High–Z
READ
Continue Read
Next
X
X
X
1
1
0
0
DQ
READ
Continue Read
Next
1
X
X
X
1
0
1
High–Z
READ
Continue Read
Next
1
X
X
X
1
0
0
DQ
READ
Suspend Read
Current
X
X
X
1
1
1
1
High–Z
READ
Suspend Read
Current
X
X
X
1
1
1
0
DQ
READ
Suspend Read
Current
1
X
X
X
1
1
1
High–Z
READ
Suspend Read
Current
1
X
X
X
1
1
0
DQ
READ
Begin Write
External
0
1
0
1
0
X
X
High–Z
WRITE
Next
X
X
X
1
1
0
X
High–Z
WRITE
Continue Write
Continue Write
Next
1
X
X
X
1
0
X
High–Z
WRITE
Suspend Write
Current
X
X
X
1
1
1
X
High–Z
WRITE
Suspend Write
Current
1
X
X
X
1
1
X
High–Z
WRITE
NOTES:
1. X = don’t care. 1 = logic high. 0 = logic low.
2. Write is defined as either (a) any SBx and SW low or (b) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This read assumes the RAM was previously deselected.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
WRITE TRUTH TABLE
SGW
SW
SBa
SBb
Read
Cycle Type
H
H
X
X
Read
H
L
H
H
Write Byte a
H
L
L
H
Write Byte b
H
L
H
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
MOTOROLA FAST SRAM
MCM69P818
5
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating
Symbol
Value
Unit
VDD
VSS – 0.5 to + 4.6
V
VDDQ
VSS – 0.5 to VDD
V
2
Vin, Vout
VSS – 0.5 to
VDD + 0.5
V
2
Input Voltage (Three–State I/O)
VIT
VSS – 0.5 to
VDDQ + 0.5
V
2
Output Current (per I/O)
Iout
± 20
mA
Package Power Dissipation
PD
1.6
W
Ambient Temperature
TA
0 to 70
°C
Power Supply Voltage
I/O Supply Voltage
Input Voltage Relative to VSS for
Any Pin Except VDD
Die Temperature
Temperature Under Bias
Storage Temperature
TJ
110
°C
Tbias
– 10 to 85
°C
Tstg
– 55 to 125
°C
Notes
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
3
3
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing can not be controlled and
is not allowed.
3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS — PBGA
Rating
Symbol
Max
Unit
Notes
RθJA
41
19
°C/W
1, 2
Junction to Board (Bottom)
RθJB
11
°C/W
3
Junction to Case (Top)
RθJC
9
°C/W
4
Junction to Ambient (@ 200 lfm)
Single Layer Board
Four Layer Board
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
MCM69P818
6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O Supply (Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
VDD
3.135
3.3
3.6
V
I/O Supply Voltage
VDDQ
2.375
2.5
2.9
V
Input Low Voltage
VIL
– 0.3
—
0.7
V
Input High Voltage
VIH
1.7
—
VDD + 0.3
V
Input High Voltage (I/O Pins)
VIH2
1.7
—
VDDQ + 0.3
V
Max
Unit
Supply Voltage
RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O Supply (Voltages Referenced to VSS = 0 V)
Parameter
Supply Voltage
Symbol
Min
Typ
VDD
3.135
3.3
3.6
V
I/O Supply Voltage
VDDQ
3.135
3.3
VDD
V
Input Low Voltage
VIL
– 0.5
—
0.8
V
Input High Voltage
VIH
2
—
VDD + 0.5
V
Input High Voltage (I/O Pins)
VIH2
2
—
VDDQ + 0.5
V
VIH
VSS
VSS – 1.0 V
20% tKHKH (MIN)
Figure 1. Undershoot Voltage
MOTOROLA FAST SRAM
MCM69P818
7
DC CHARACTERISTICS AND SUPPLY CURRENTS
Symbol
Min
Typ
Max
Unit
Input Leakage Current (0 V ≤ Vin ≤ VDD)
Parameter
Ilkg(I)
—
—
±1
µA
Output Leakage Current (0 V ≤ Vin ≤ VDD)
Ilkg(O)
—
—
±1
µA
IDDA
—
—
—
—
—
—
425
400
375
mA
1, 2, 3
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at CMOS Levels)
ISB2
—
—
45
mA
4, 5
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at TTL Levels)
ISB3
—
—
50
mA
4, 6
Clock Running (Device Deselected,
Freq = Max, VDD = Max,
All Inputs Toggling at CMOS Levels)
ISB4
—
—
—
—
—
—
190
180
165
mA
4, 5
Static Clock Running (Device Deselected, Freq = Max,
VDD = Max, All Inputs Static at TTL Levels)
ISB5
—
—
95
mA
4, 6
Output Low Voltage (IOL = 2 mA), VDDQ = 2.5 V
VOL
—
—
0.7
V
Output High Voltage (IOH = – 2 mA), VDDQ = 2.5 V
VOH
1.7
—
—
V
Output Low Voltage (IOL = 8 mA), VDDQ = 3.3 V
VOL2
—
—
0.4
V
Output High Voltage (IOH = – 4 mA), VDDQ = 3.3 V
VOH2
2.4
—
—
V
AC Supply Current (Device Selected,
All Outputs Open, Freq = Max) MCM69P818
MCM69P818
Includes VDD Only
MCM69P818–3.5
–3.8
MCM69P818–4
MCM69P818–3.5
MCM69P818MCM69P818–3.8
–3.8
MCM69P818–4
Notes
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing.
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
4. Device in deselected mode as defined by the Truth Table.
5. CMOS levels for I/O’s are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.
6. TTL levels for I/O’s are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
—
4
5
pF
Input/Output Capacitance
CI/O
—
7
8
pF
MCM69P818
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V
Input Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20 to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V
Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM69P818–3.5
166 MHz
Parameter
P
MCM69P818–3.8
150 MHz
MCM69P818–4
133 MHz
Symbol
S b l
Min
Max
Min
Max
Min
Max
Unit
U i
Notes
N
Cycle Time
tKHKH
6
—
6.7
—
7.5
—
ns
Clock High Pulse Width
tKHKL
2.4
—
2.6
—
3
—
ns
3
Clock Low Pulse Width
tKLKH
2.4
—
2.6
—
3
—
ns
3
Clock Access Time
tKHQV
—
3.5
—
3.8
—
4
ns
Output Enable to Output Valid
tGLQV
—
3.5
—
3.5
—
3.8
ns
Clock High to Output Active
tKHQX1
0
—
0
—
0
—
ns
4, 5
Clock High to Output Change
tKHQX2
1.5
—
1.5
—
1.5
—
ns
4
Output Enable to Output Active
tGLQX
0
—
0
—
0
—
ns
4, 5
Output Disable to Q High–Z
tGHQZ
—
3.5
—
3.5
—
3.8
ns
4, 5
Clock High to Q High–Z
tKHQZ
1.5
6
1.5
6.7
1.5
7.5
ns
4, 5
Setup Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tADKH
tADSKH
tDVKH
tWVKH
tEVKH
1.5
—
1.5
—
1.5
—
ns
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
0.5
—
0.5
—
0.5
—
ns
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
1.25 V
Figure 2. AC Test Load
MOTOROLA FAST SRAM
MCM69P818
9
CLOCK ACCESS TIME DELAY (ns)
5
OUTPUT
CL
4
3
2
1
0
0
20
40
60
80
100
LUMPED CAPACITANCE, CL (pF)
Figure 3. Lumped Capacitive Load and Typical Derating Curve
OUTPUT LOAD
OUTPUT
BUFFER
TEST POINT
UNLOADED RISE AND FALL TIME MEASUREMENT
INPUT
WAVEFORM
OUTPUT
WAVEFORM
2.0
2.0
0.5
0.5
2.0
2.0
0.5
tr
0.5
tf
NOTES:
1. Input waveform has a slew rate of 1 V/ns.
2. Rise time is measured from 0.5 to 2.0 V unloaded.
3. Fall time is measured from 2.0 to 0.5 V unloaded.
Figure 4. Unloaded Rise and Fall Time Characterization
MCM69P818
10
MOTOROLA FAST SRAM
2.9
2.5
2.3
PULL–UP
I (mA) MIN
I (mA) MAX
– 0.5
– 38
– 105
0
– 38
– 105
0.8
– 38
– 105
1.25
– 26
– 83
1.5
– 20
– 70
2.3
0
– 30
2.7
0
– 10
2.9
0
0
2.1
VOLTAGE (V)
VOLTAGE (V)
1.25
0.8
0
0
– 38
CURRENT (mA)
– 105
– 100
– 50
CURRENT (mA)
– 150
(a) Pull–Up for 2.5 V I/O Supply
3.6
3.135
2.8
PULL–UP
I (mA) MIN
I (mA) MAX
– 0.5
– 50
– 150
0
– 50
– 150
1.4
– 50
– 150
1.65
– 46
– 130
2.0
– 35
– 101
3.135
0
– 25
3.6
0
0
VOLTAGE (V)
VOLTAGE (V)
1.65
1.4
0
0
(b) Pull–Up for 3.3 V I/O Supply
VDD
PULL–DOWN
I (mA) MIN
I (mA) MAX
– 0.5
0
0
0
0
0
0.4
10
20
0.8
20
40
1.25
31
63
1.6
40
80
2.8
40
80
3.2
40
80
3.4
40
80
3.6
46
120
1.6
VOLTAGE (V)
VOLTAGE (V)
1.25
0.3
0
0
40
CURRENT (mA)
80
(c) Pull–Down
Figure 5. Typical Output Buffer Characteristics
MOTOROLA FAST SRAM
MCM69P818
11
MCM69P818
12
MOTOROLA FAST SRAM
DESELECTED
tKHQZ
Q(n)
B
SINGLE READ
tKHQX1
A
Q(A)
Q(B)
tKHQX2
t KHQV
tKHKL
NOTE: E low = SE2 high and SE3 low.
W low = SGW low and/or SW and SBx low.
DQx
G
W
E
SE1
ADV
ADSC
ADSP
SA
K
tKHKH
Q(B+2)
BURST READ
Q(B+1)
tGHQZ
Q(B+3)
BURST WRAPS AROUND
tKLKH
Q(B)
C
D(C)
ADSP, SA
SE2, SE3
IGNORED
READ/WRITE CYCLES
D(C+2)
BURST WRITE
D(C+1)
D(C+3)
tGLQX
D
SINGLE READ
Q(D)
t KHQV
APPLICATION INFORMATION
STOP CLOCK OPERATION
In the stop clock mode of operation, the SRAM will hold all
state and data values even though the clock is not running
(full static operation). The SRAM design allows the clock to
start with ADSP and ADSC, and stops the clock after the last
write data is latched, or the last read data is driven out.
When starting and stopping the clock, the AC clock timing
and parametrics must be strictly maintained. For example,
clock pulse width and edge rates must be guaranteed when
starting and stopping the clocks.
To achieve the lowest power operation for all three stop
clock modes, stop read, stop write, and stop deselect:
• Force the clock to a low state.
• Force the control signals to an inactive state (this guarantees any potential source of noise on the clock input will not
start an unplanned on activity).
• Force the address inputs to a low state.
STOP CLOCK WITH READ TIMING
K
ADSP
ADDRESS
A1
A2
ADV
Q(A1)
DQx
ADSP
(INITIATES
BURST READ)
CLOCK STOP
(CONTINUE
BURST READ)
Q(A1+1)
Q(A2)
WAKE UP ADSP
(INITIATES BURST READ)
NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL).
Best results are obtained if VIL < 0.2 V.
MOTOROLA FAST SRAM
MCM69P818
13
STOP CLOCK WITH WRITE TIMING
K
ADSC
ADDRESS
A1
A2
WRITE
ADV
DATA IN
D(A1)
D(A1+1)
VIH OR VIL FIXED (SEE NOTE)
D(A2)
HIGH–Z
DQx
ADSC
(INITIATES
BURST WRITE)
CLOCK STOP
(CONTINUE
BURST WRITE)
WAKE UP ADSC
(INITIATES BURST WRITE)
NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the
input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control
lines held in an inactive state.
MCM69P818
14
MOTOROLA FAST SRAM
CONTROL PIN TIE VALUES (H ≥ VIH, L ≤ VIL)
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC–
based and other high end MPU–based systems, these
SRAMs can be used in other high speed L2 cache or
memory applications that do not require the burst address
feature. Most L2 caches designed with a synchronous interface can make use of the MCM69P818. The burst counter
feature of the BurstRAM can be disabled, and the SRAM can
be configured to act upon a continuous stream of addresses.
See Figure 6.
Non–Burst
ADSP
ADSC
ADV
SE1
LBO
H
L
H
L
X
Sync Non–Burst,
Pipelined SRAM
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
K
ADDR
A
B
C
D
E
F
G
H
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
READS
D(F)
D(G)
D(H)
WRITES
Figure 6. Configured as Non–Burst Synchronous SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM
69P818
XX
X
X
Motorola Memory Prefix
Blank = Trays, R = Tape and Reel
Part Number
Speed (3.5 = 3.5 ns, 3.8 = 3.8 ns, 4 = 4.0 ns)
Package (ZP = PBGA)
Full Part Numbers — MCM69P818ZP3.5
MCM69P818ZP3.5R
MOTOROLA FAST SRAM
MCM69P818ZP3.8
MCM69P818ZP3.8R
MCM69P818ZP4
MCM69P818ZP4R
MCM69P818
15
PACKAGE DIMENSIONS
ZP PACKAGE
7 x 17 BUMP PBGA
CASE 999–02
0.20
4X
119X
E
C
B
D
e
6X
E2
M
A B C
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
D1
16X
M
0.15
7 6 5 4 3 2 1
D2
b
0.3
DIM
A
A1
A2
A3
D
D1
D2
E
E1
E2
b
e
e
E1
TOP VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. ALL DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
BOTTOM VIEW
MILLIMETERS
MIN
MAX
–––
2.40
0.50
0.70
1.30
1.70
0.80
1.00
22.00 BSC
20.32 BSC
19.40
19.60
14.00 BSC
7.62 BSC
11.90
12.10
0.60
0.90
1.27 BSC
0.25 A
A3
0.35 A
0.20 A
A
A1
A2
SIDE VIEW
SEATING
PLANE
A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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MCM69P818
16
◊
MCM69P818/D
MOTOROLA FAST
SRAM
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